DESCRIPTION 1(16)

Prepared Subject responsible No.

WIPRO/Shahnaz Fathima 1551-ROJ 208 316/1 Uen
Doc.respons./Approved Checked Date Rev. File
ERI/Rocco Mecoli 2007-05-07 F

INCOMING REFERENCES BOARD

(IRB)

TABLE OF CONTENTS
1 GENERAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2 FUNCTION OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 IRB BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 CPLD FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 INTERFACES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 CLREF - 2.048 MHZ UNBALANCED (75 OHM) . . . . . . . . . . 9
3.2 CLREF - 2.048 MHZ BALANCED (120 OHM) . . . . . . . . . . . . 9
3.3 CLREF - 1.544 MB/S FRAMED ONES (100 OHM) . . . . . . . . 9
3.4 CLREF - 64 + 8 KHZ (110 OHM) . . . . . . . . . . . . . . . . . . . . . . . 9
3.5 CLREF - 64 + 8 KHZ COMPOSITE CLOCK (135 OHM) . . . 10
3.6 CLREF - 8 KHZ (100 OHM) . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.7 8KS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.8 MAINTENANCE BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.9 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . 12
4.1 POWER SUPPLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2 MAINTENANCE BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5 EXTERNAL SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1 INCOMING SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.2 OUTGOING SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6 MECHANICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
 DESCRIPTION 2(16)
Prepared Subject responsible No.
WIPRO/Shahnaz Fathima 1551-ROJ 208 316/1 Uen
Doc.respons./Approved Checked Date Rev. File
ERI/Rocco Mecoli 2007-05-07 F

6.1 FRONT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

7 ABBREVIATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
 DESCRIPTION 3(16)
Prepared Subject responsible No.
WIPRO/Shahnaz Fathima 1551-ROJ 208 316/1 Uen
Doc.respons./Approved Checked Date Rev. File
ERI/Rocco Mecoli 2007-05-07 F

1 GENERAL

This document describes the functions of the Incoming References Board

(IRB) and its interfaces.

From revision R2F onwards, the board is lead free and compliant to European
RoHS regulation
 DESCRIPTION 4(16)
Prepared Subject responsible No.
WIPRO/Shahnaz Fathima 1551-ROJ 208 316/1 Uen
Doc.respons./Approved Checked Date Rev. File
ERI/Rocco Mecoli 2007-05-07 F

1.1 INTRODUCTION

IRB is hosted in the GEM and CDM subracks according to CLM variants
(variant 10: 2 IRB’s in a single GEM, variant 11: 1 IRB in each GEM, variant
12: 1 IRB in each CDM). Up to two IRB’s can be housed in a fully equipped
configuration.

GEM
XDB-B
ET155W STM-1
XDB-A

ET155W STM-1

DLEB-B
DLEB-A GDM-H

DLEB-B
ET155-7
DLEB-A
DL34
DL3

CGB-1 CBC
CGB-0 ISI

SYCL IRB-1
IRB-0 ISI

8kS LRB

Figure 1-1 Place in the System (GEM)

In the CDM magazine only the clock boards are hosted.

 DESCRIPTION 5(16)
Prepared Subject responsible No.
WIPRO/Shahnaz Fathima 1551-ROJ 208 316/1 Uen
Doc.respons./Approved Checked Date Rev. File
ERI/Rocco Mecoli 2007-05-07 F

1.2 FUNCTION OVERVIEW

IRB is the unit that converts external signals called ISI to 8kHz signals
distributed to both CLM’s for NS purposes.

The connections from IRB to CGB’s can be made either via backplane or
cable; via backplane if both CGB’s are housed in the same GEM (variant 10),
otherwise via backplane to the CGB housed in the same GEM/CDM and via
cable to the CGB housed in another GEM/CDM (variant 11 and 12).

Each 8kS signal is the result of the conversion of an external Clock Reference,
received on a PBA’s front connector, which can be any of six different types of
signals:
o 2.048 MHz (75 Ω, coaxial cable);
o 2.048 MHz (120 Ω, twisted pair cable);
o 1544 Mb/s framed ones(100 Ω, twisted pair cable);
o 64 + 8 kHz (110 Ω, twisted pair cable);
o 64 + 8 kHz composite clock (135 Ω, twisted pair cable);
o 8 kHz (100 Ω, twisted pair cable).

These CLREF’s are terminated on the board and divided down to 8kHz by
counters implemented in a CPLD (GEN8K). Only one CLREF can be present
on each couple of front connectors (see Figure 2-1). The presence of more than
one CLREF connected to a single couple of front connectors is treated as a
fault and no signal is generated in this case. To each CLREF an Alarm signal
is associated. When active (high) the related CLREF is switched off and no
8kS is generated by the IRB.

Moreover, in the CPLD is done a frequency measurement on the outgoing

signals in order to detect wrong cable connections on the board and to avoid
transmission of signals with wrong frequency towards CGB’s.

The 8kS signals generated by CPLD must be distributed to the two CGB’s.
Three identical groups, three 8kS signals each, are available from CPLD. One
group is transmitted to an LVDS driver which performs the translation from
Low Voltage CMOS to LVDS level and is conveyed to one front connector.
The other two groups from the CPLD are transmitted to LVDS drivers which
perform the translation from Low Voltage CMOS to LVDS level and are
conveyed to back connectors.
 DESCRIPTION 6(16)
Prepared Subject responsible No.
WIPRO/Shahnaz Fathima 1551-ROJ 208 316/1 Uen
Doc.respons./Approved Checked Date Rev. File
ERI/Rocco Mecoli 2007-05-07 F

It is important to highlight once again that each 8kS, related to a specific

CLREF, is present on all the three outputs. When three CLREF’s are
connected, three 8kS signals are present at the same time on the output front
connector.

In total seven front connectors are used: six of them are used as input
connectors, for termination of three separate CLREF’s; the last one of them is
used as output connector for distribution of 8kS via cable.

Furthermore the IRB is equipped with an EEPROM that contains the inventory
information readable by the SCB-RP.

A yellow LED, controlled by the SCB-RP through an I/O Expander, is

provided on the PBA’s front to be used as fault indicator.
 DESCRIPTION 7(16)
Prepared Subject responsible No.
WIPRO/Shahnaz Fathima 1551-ROJ 208 316/1 Uen
Doc.respons./Approved Checked Date Rev. File
ERI/Rocco Mecoli 2007-05-07 F

2 FUNCTIONAL DESCRIPTION

2.1 IRB BLOCK DIAGRAM

The IRB block diagram is shown in Figure 2-1.

BACK
from SCB-RP to CGB-0 to CGB-1 to/from SCB-RP

2 2 2 2 2 2

3.3V
POWER

-48V

3 8kS_2,8kS_1,8kS_0

3 8kS_2,8kS_1,8kS_0
GEN8K 3 8kS_2,8kS_1,8kS_0

EEPROM

RX
CLREF 6 6
BLOCK
Terminations
& Conversion
RX RX
**2048kHz
#64+8kHz
*2048kHz

1544kHz
8kHz
##64+8kHz

BLOCK BLOCK
MB

2 2 2

3 3 3 3

CLREF-0 CLREF-1 CLREF-2 3-8kS LED

*: 75 ohm impedance #: 110 ohm impedance FRONT
**: 120 ohm impedance ##: 135 ohm impedance

Figure 2-1 IRB block diagram

 DESCRIPTION 8(16)
Prepared Subject responsible No.
WIPRO/Shahnaz Fathima 1551-ROJ 208 316/1 Uen
Doc.respons./Approved Checked Date Rev. File
ERI/Rocco Mecoli 2007-05-07 F

2.2 CPLD FUNCTIONS

GEN8K component is mainly devoted to the conversion from external clock

references to 8kHz synchronization signals used for NS. Three groups of three
identical 8kHz signals are generated by GEN8K. Each of them is the result of
the conversion from one external clock reference (CLREF), which can be any
of the following types:

o 2.048 MHz (unbalanced 2.048 MHz 75 Ω impedance CLREF);

o 2.048 MHz (balanced 2.048 MHz 120 Ω impedance CLREF);
o 1544 Mb/s framed ones;
o 64 + 8 kHz (110 Ω impedance CLREF);
o 64 + 8 kHz composite clock (135 Ω impedance CLREF);
o 8 kHz (100 Ω impedance CLREF).

Toggle Detectors check which signal is present, detecting the activity of the
generated 8 kHz signal (or a 4 kHz signal in the case of the 8 kHz CLREF). In
doing this, they make use of a 64 kHz clock internally generated by division
of an external 16.384 MHz clock generated by a quartz oscillator. This 64 kHz
clock is sent out and then looped back into the FPGA.
The result of each toggle detection is available on separate output pins,
twentyone in total.

Moreover, in the CPLD a frequency measurement is done on the outgoing

signals in order to detect wrong cable connections on the board and to avoid
transmission of signals with wrong frequency towards CGB’s. In doing this,
it’s used a 1 MHz clock internally generated by division of an external
16.384 MHz clock generated by a quartz oscillator. This 1 MHz clock is sent
out and then looped back into the CPLD.
The result of each frequency measure is available on separate output pins,
three in total.

Finally a JTAG interface is implemented.

 DESCRIPTION 9(16)
Prepared Subject responsible No.
WIPRO/Shahnaz Fathima 1551-ROJ 208 316/1 Uen
Doc.respons./Approved Checked Date Rev. File
ERI/Rocco Mecoli 2007-05-07 F

3 INTERFACES

3.1 CLREF - 2.048 MHz Unbalanced (75 Ohm)

This interface allows the connection of the 2 MHz (75 Ohm) CLREF from
external equipment to the IRB. The characteristics of this reference are
specified in ITU-T G.703 (10/98) sec. 13.

A shielded coaxial cable is used to carry this CLREF.

3.2 CLREF - 2.048 MHz Balanced (120 Ohm)

This interface allows the connection of the 2 MHz (120 Ohm) CLREF from
external equipment to the IRB. The characteristics of this reference are
specified in ITU-T G.703 (10/98) sec. 13.

A shielded twisted pair cable is used to carry this CLREF.

3.3 CLREF - 1.544 Mb/s framed ones (100 Ohm)

This interface allows the connection of the 1.544 Mb/s framed ones
(100 Ohm) CLREF from external equipment to the IRB. The characteristics of
this reference are specified in the ANSI technical report T1X1/2001-013R1
sec. 7.2.

A shielded twisted pair cable is used to carry this CLREF.

3.4 CLREF - 64 + 8 kHz (110 Ohm)

This interface allows the connection of the 64 + 8 kHz (110 Ohm) CLREF
from external equipment to the IRB. The characteristics of this reference are
specified in ITU-T G.703 (10/98) sec. 4.2.2.

A shielded twisted pair cable is used to carry this CLREF.

 DESCRIPTION 10(16)
Prepared Subject responsible No.
WIPRO/Shahnaz Fathima 1551-ROJ 208 316/1 Uen
Doc.respons./Approved Checked Date Rev. File
ERI/Rocco Mecoli 2007-05-07 F

3.5 CLREF - 64 + 8 kHz composite clock (135 Ohm)

This interface allows the connection of the 64 + 8 kHz composite clock

(135 Ohm) CLREF from external equipment to the IRB. The characteristics of
this reference are specified in the ANSI technical report T1X1/2001-013R1
sec. 7.1.

A shielded twisted pair cable is used to carry this CLREF.

3.6 CLREF - 8 kHz (100 Ohm)

This interface allows the connection of the 8 kHz (RS-422, 100 Ohm) CLREF
from other equipments (ETC5, ET155-1 or ET155-7) to the IRB.

A shielded twisted pair cable is used to carry this CLREF.

3.7 8kS

The interface allows the distribution of the 8kHz signals (LVDS) from the IRB
to the two CGB’s.

A shielded twisted pair cable is used to carry the 8kS.

3.8 MAINTENANCE BUS

The PBA is connected to the Inter IC (I2C) control bus used as the
Maintenance Bus (MB). It is a simple bidirectional 2-wire bus located in the
backplane.
The bus is controlled by the SCB-RP.

The Maintenance Bus works even if the rest of the board is faulty because a
separate system supplies the I2C component with voltage and control signals.
 DESCRIPTION 11(16)
Prepared Subject responsible No.
WIPRO/Shahnaz Fathima 1551-ROJ 208 316/1 Uen
Doc.respons./Approved Checked Date Rev. File
ERI/Rocco Mecoli 2007-05-07 F

3.8.1 Product Identification

Through the Maintenance Bus the SCB-RP can read a small EEPROM that
stores the unique serial number, product number, revision state and
manufacturing date of the board. Operators can fetch and read this information
by command (on site or remotely).

3.8.2 Visual Indication

The PBA contains a Light Emitting Diode (LED) on the front. The LED helps
the operator in maintenance situation, e.g. when locating a board that needs to
be removed for repair or upgrade.

The indicator is surface mounted yellow LED, complete with a light guide.
The indicator is controlled by the SCB-RP.

3.9 JTAG

The FPGA is provided with the standard JTAG interface. It consists of 4

signals: TDI, TMS, TCK and TDO.
 DESCRIPTION 12(16)
Prepared Subject responsible No.
WIPRO/Shahnaz Fathima 1551-ROJ 208 316/1 Uen
Doc.respons./Approved Checked Date Rev. File
ERI/Rocco Mecoli 2007-05-07 F

4 ELECTRICAL CHARACTERISTICS

4.1 POWER SUPPLY

The IRB is fed from the backplane by two -48 Volt input power supply
branches. The duplication is needed to improve reliability so that the PBA
works even if one branch is missing.
A DC/DC converter is devoted to convert the -48 V supply voltage into +3.3 V,
to feed all the circuitry, except the MB circuitry that is completely remote fed
and driven by the SCB-RP board.

A fuse resistance is provided for each -48 Volt input for protective purposes.

4.1.1 POWER CONSUMPTION

The PBA’s power consumption is typically 1 W and max 1.2 W.

4.2 MAINTENANCE BUS

Bit Rate: 100 kbit/s

Impedance: N.A.

Logic Family: LVCMOS I2C

4.3 JTAG
Bit Rate: N.A.

Impedance: N.A.

Logic Family: TTL

 DESCRIPTION 13(16)
Prepared Subject responsible No.
WIPRO/Shahnaz Fathima 1551-ROJ 208 316/1 Uen
Doc.respons./Approved Checked Date Rev. File
ERI/Rocco Mecoli 2007-05-07 F

5 EXTERNAL SIGNALS

5.1 INCOMING SIGNALS

-48VA -48 V Power Supply A
-48VB -48 V Power Supply B
BOARDPOS 0-4 Board Position in the subrack
DATA_MB Data on MB
CLK_MB CLocK on MB
3V_MB +3.3 V Power Supply on MB
WC Write Control for EEPROM on MB
TDI TDI on JTAG of FPGA
TDO TDO on JTAG of FPGA
TCK TCK on JTAG of FPGA
TMS TMS on JTAG of FPGA
2M_0 2 MHz CLREF 75 Ohm (group 0)
2M_1 2 MHz CLREF, 75 Ohm (group 1)
2M_2 2 MHz CLREF, 75 Ohm (group 2)
2M_0_P/N 2 MHz CLREF, 120 Ohm (group 0)
2M_1_P/N 2 MHz CLREF, 120 Ohm (group 1)
2M_2_P/N 2 MHz CLREF, 120 Ohm (group 2
1544K_0_P/N 1.544 MHz CLREF (group 0)
1544K_1_P/N 1.544 MHz CLREF (group 1)
1544K_2_P/N 1.544 MHz CLREF (group 2)
64_8_0_P/N 64 + 8 kHz CLREF (group 0)
64_8_1_P/N 64 + 8 kHz CLREF (group 1)
64_8_2_P/N 64 + 8 kHz CLREF (group 2)
64K_8_CC_0_P/N 64 + 8 kHz composite clock (group 0)
64K_8_CC_1_P/N 64 + 8 kHz composite clock (group 1)
 DESCRIPTION 14(16)
Prepared Subject responsible No.
WIPRO/Shahnaz Fathima 1551-ROJ 208 316/1 Uen
Doc.respons./Approved Checked Date Rev. File
ERI/Rocco Mecoli 2007-05-07 F

64K_2_P/N 64 + 8 kHz composite clock (group 2)

8K_0_P/N 8 kHz CLREF (group 0)
8K_1_P/N 8 kHz CLREF (group 1)
8K_2_P/N 8 kHz CLREF (group 2)
ALARM_0 Alarm (group 0)
ALARM_1 Alarm (group 1)
ALARM_2 Alarm (group 2)

5.2 OUTGOING SIGNALS

8kS-0_A 8kHz to CGB 0 from CLREF_2
8kS-1_A 8kHz to CGB 0 from CLREF_1
8kS-2_A 8kHz to CGB 0 from CLREF_0
8kS-0_B 8kHz to CGB 1 from CLREF_2
8kS-1_B 8kHz to CGB 1 from CLREF_1
8kS-2_B 8kHz to CGB 1 from CLREF_0
8kS-0_C 8kHz to CGB x from CLREF_2
8kS-1_C 8kHz to CGB x from CLREF_1
8kS-2_C 8kHz to CGB x from CLREF_0
 DESCRIPTION 15(16)
Prepared Subject responsible No.
WIPRO/Shahnaz Fathima 1551-ROJ 208 316/1 Uen
Doc.respons./Approved Checked Date Rev. File
ERI/Rocco Mecoli 2007-05-07 F

6 MECHANICS

6.1 FRONT

The Front Panel of the IRB is shown in Figure 6-1

Yellow Light Emitting Diode

8kS

CLREF_2

CLREF_1

CLREF_0

Figure 6-1 IRB Front Panel

 DESCRIPTION 16(16)
Prepared Subject responsible No.
WIPRO/Shahnaz Fathima 1551-ROJ 208 316/1 Uen
Doc.respons./Approved Checked Date Rev. File
ERI/Rocco Mecoli 2007-05-07 F

7 ABBREVIATIONS

AMI Alternate Mask Inversion

CGB Clock Generation Board

CPLD Complex Programmable Logic Device

GS Group Switch

IRB Incoming References Board

ISI Incoming Synchronization Interface

I2C Inter Integrated Circuit

JTAG Joint Test Action Group

LED Light Emitting Diode

LVCMOS Low Voltage Complementary MOS

LVDS Low Voltage Differential Signal

MB Maintenance Bus

NS Network Synchronization

PBA Printed Board Assembly

RoHS Restriction of Hazardous Substances

SCB-RP Support and Control Board - with RP