Utrm SVC Tel Fnf5660a Rev D

Unit Test Requirement, Manufacturing
Rev.
Rev Date
2006-08-17
Document ID
15205-891763 (NG-IFU\BASIC\00173)
Prepared by
Subject Resp.
Approved by
StSo
StSo
JSk
EOW_Service Telephone Auxiliary Unit, FNF5660A

Evolution Series IFU
INTERNAL
Table of Contents
1.
1.1
1.2
1.3
INTRODUCTION.............................................................................................................. 4
Purpose and scope........................................................................................................... 4
References....................................................................................................................... 4
Terminology and abbreviations.........................................................................................5
2.
2.1
2.1.1
2.1.2
2.1.3
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
UNIT DESCRIPTION........................................................................................................6
Hardware overview........................................................................................................... 8
Service Telephone Auxiliary Unit.......................................................................................8
Front Connection, J200.....................................................................................................9
Rear Connection, J500...................................................................................................10
Software overview........................................................................................................... 11
Download of Application SW to the Svc Tel.....................................................................11
Download of FPGA SW to the Svc Tel.............................................................................11
Download of Application SW to the AUT and PIUT Test Jigs...........................................11
Download of FPGA SW to the PIUT Test Jig, K-7295 (ET-5157A)...................................11
Download of FPGA SW to the AUT Test Jig, K-7346 (ET-5189A)....................................11
3.
3.1
3.2
3.3
3.3.1
3.3.2
3.3.3
3.4
3.5
3.5.1
3.5.2
3.5.3
3.5.4
3.5.5
3.6
3.6.1
3.6.2
3.6.3
3.6.4
TEST STATION DESCRIPTION.....................................................................................12

Test Station overview......................................................................................................12
Test Jig overview............................................................................................................12
PIUT Test Jig, K-7295.....................................................................................................13
Test Board, ET5157A......................................................................................................13
Connection Board, ET5162.............................................................................................13
Mechanical enclosure, VJTE-7328.................................................................................13
AUT Test Jig, K-7346......................................................................................................14
Test Station Equipment...................................................................................................15
Nera Equipment.............................................................................................................. 15
Instruments..................................................................................................................... 15
JTAG Equipment.............................................................................................................15
General Equipment......................................................................................................... 15
Cables & Connectors......................................................................................................15
Test Station Software......................................................................................................16
BSDL-Files used for Boundary Scan Testing..................................................................16
Common TCL Scripts used during Functional Tests........................................................16
First time Set-up of Test Station......................................................................................17
Set-up for each test.........................................................................................................17
4.
4.1
4.2
4.3
4.3.1
4.3.2
4.4
4.4.1
4.5
4.5.1
TEST DESCRIPTIONS...................................................................................................18
Test Overview.................................................................................................................18
Test Coverage................................................................................................................. 19
Initial Process tests.........................................................................................................20
Automatic Optical Inspection (AOI).................................................................................20
In-Circuit Testing (ICT)....................................................................................................20
Power-On tests............................................................................................................... 20
Current Limit test............................................................................................................ 20
Boundary Scan Test........................................................................................................21
General Information........................................................................................................21
Internal
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Nera Company Standards on Notes, FS0170-M30, Rev. A
Page 1(58)

Document ID
Rev.
Rev Date
D
15205-891763 (NG-IFU\BASIC\00173)
2006-08-17
Internal
4.5.2
4.5.3
4.6
4.6.1
4.6.2
4.6.3
4.6.4
4.6.5
4.6.6
4.6.7
4.6.8
4.6.9
4.6.10
4.6.11
4.6.12
4.6.13
4.6.14
4.6.15
4.6.16
4.6.17
4.6.18
4.6.19
4.6.20
4.6.21
4.6.22
Tests to be developed.....................................................................................................21
General Quality Requirements........................................................................................21
Functional Tests.............................................................................................................. 22
Power consumption........................................................................................................ 22
SBC Software Download................................................................................................23
Ethernet Testing.............................................................................................................. 24
SBC Address Detection..................................................................................................25
Front LED Test................................................................................................................ 26
Hot Swap Test................................................................................................................. 27
Voltage Measurements...................................................................................................28
FPGA Software Download and Configuration.................................................................29
Power consumption after SW Download.........................................................................30
Other Equipment 1 Input Test.........................................................................................31
Other Equipment 2 Input Test.........................................................................................32
4Wire Input Test.............................................................................................................. 33
Telephone Input Test (Tip/Ring)......................................................................................34
DTMF Detector and Ringing Test....................................................................................35
Call In / Call Out Test......................................................................................................36
DTMF Generator Input Test (Send Star from EOW FPGA).............................................37
500 Hz Generator Test....................................................................................................38
64 kb/s Channel 1 Test...................................................................................................39
64 kb/s Channel 2 Test...................................................................................................39
Set Inventory................................................................................................................... 40
Get EOW SvcTel SW Info...............................................................................................41
Verify All Inventory.......................................................................................................... 42
5.
5.1
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
5.1.7
5.1.8
5.1.9
5.1.10
5.1.11
5.1.12
5.1.13
5.1.14
5.1.15
5.1.16
5.1.17
5.1.18
5.1.19
5.1.20
5.1.21
5.1.22
FAULT SEEKING............................................................................................................ 43
General........................................................................................................................... 43
Test 4.6.1 Power consumption........................................................................................43
Test 4.6.2 SBC Software Download................................................................................43
Test 4.6.3 Ethernet Testing..............................................................................................43
Test 4.6.4 SBC Address Detection..................................................................................43
Test 4.6.5 Front LED Test................................................................................................44
Test 4.6.6 Hot Swap Test................................................................................................44
Test 4.6.7 Voltage Measurements...................................................................................45
Test 4.6.8 Download of FPGA SW using ActiveTCL environment...................................46
Test 4.6.9 Power consumption after SW Download........................................................46
Test 4.6.10 Other Equipment 1 Input..............................................................................47
Test 4.6.11 Other Equipment 2 Input...............................................................................48
Test 4.6.12 4Wire Input...................................................................................................48
Test 4.6.13 Telephone Input (Tip/Ring)............................................................................49
Test 4.6.14 DTMF Detector and Ringing.........................................................................50
Test 4.6.15 Call In / Call Out Function.............................................................................51
Test 4.6.16 DTMF Generator..........................................................................................52
Test 4.6.17 500 Hz Generator.........................................................................................52
Test 4.6.18 64 kb/s Channel 1.........................................................................................53
Test 4.6.19 64 kb/s Channel 2.........................................................................................53
Test 4.6.20 Set Inventory................................................................................................53
Test 4.6.21 Get EOW SvcTel SW Info.............................................................................53
Test 4.6.22 Verify All Inventory........................................................................................53
6.
TEST STATION MAINTENANCE....................................................................................54
Internal
Nera Networks AS
Page 2(58)

Rev Date
2006-08-17
Rev.
D
Document ID
15205-891763 (NG-IFU\BASIC\00173)
Internal
6.1
6.2
6.3
General........................................................................................................................... 54
Maintenance schedule for the PIUT (K-7295) Test Jig....................................................54
Maintenance schedule for the AUT (K-7346) Test Jig.....................................................54
7.
7.1
7.2
7.3
APPENDIX...................................................................................................................... 55
Boot Screen.................................................................................................................... 55
JTAG overview................................................................................................................56
Configuration of Secondary Network Card in Test PC.....................................................57
Internal
Nera Networks AS
Page 3(58)

Document ID
Rev.
Rev Date
D
15205-891763 (NG-IFU\BASIC\00173)
2006-08-17
Internal
1.
INTRODUCTION
1.1
Purpose and scope
This Unit Test Requirement for Manufacturing describes the tests for the Service Telephone Auxiliary Unit
(Svc Tel), FNF5660, built on the UBN6398-R1A PCB.
The purpose of this document is to:
Define test requirements for the Svc Tel. Auxiliary Unit.
Describe (in some detail) how the tests shall be performed.
Describe necessary equipment, instruments and software to perform the tests.
Describe the process of downloading code.
Be a reference and input for test development and documentation (Test-Instructions/-Results, etc.).
1.2
References
Nera specifications
Ref. No. / Document code
[1] NG-IFU\BASIC\00073
[2] NGP\00106
[3] CaliberRM\NG-IFU
[4] In e-Matrix, object FKF5660A
[5] In e-Matrix, object K-7295
Title / description
FNF5660A HW Design Specification
IFU-System Design Specification
Database for requirements for NG IFU
EOW / Svc Tel schematics and drawings
PIUT Test Jig (Based on ET5157A)
[6] In e-Matrix, object K-7346
AUT Test Jig (Based on ET5189A)
Table 1-1: References
Microcontroller:
Phillips LPC2114
The MC data sheets and User Manual can be found here:
V:\projects\NG_ePD_lib\dataSheets\cpu\LPC2114_2124-02.pdf
V:\projects\NG_ePD_lib\dataSheets\cpu\UM_LPC2114_2124_2212_2214_2.pdf
FPGA:
V:\projects\NG_ePD_lib\dataSheets\fpga\Spartan-3.pdf
Internal
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Page 4(58)

Rev Date
2006-08-17
Rev.
D
Document ID
15205-891763 (NG-IFU\BASIC\00173)
Internal
1.3
Terminology and abbreviations
Abbreviations
ACU
ADC
AUT
BGA
BST
DAC
DXC
DTMF
EOW
FCT
FP
FPGA
IEEE
IFU
I/O
JTAG
LIU
MODEM
MSOH
NC
NROP
OE
OHC Bus
PCB
PIU
PIUT
POD
RCVR
RIU
RPS
RSOH
SBC
SDH
SOH
SLIC
SvcTel
TCK
TDI
TDO
TMS
TRST
TIP
UBN
UUT
XCVR
Descriptions
Alarm & Control Auxiliary Unit, FKN5674A
Analogue to Digital Converter
Auxiliary Units Test (Test Jig for all Auxiliary Boards) K-7346
Ball Grid Array
Boundary Scan Test
Digital to Analogue Converter
Digital Xross Connect
Dual Tone Multi Frequency
Engineering Order Wire (another name for Service Telephone)
Functional Test
Frame Pulse
Field Programming Gate Array
Institute of Electrical and Electronics Engineers
InterFace Unit
Input/Output
Joint Test Action Group
Line Interface Unit
MOdulatorDEModulator
Multiplex Section OverHead
No Connection
Nera Radio Overhead Processor
Other Equipment
OverHead Connection Bus
Printed Circuit Board
Plug In Unit
Plug In Unit Test (Test Jig for Plug-In Units) K-7295 based on ET5157A board.
Connection Box used with JTAG Boundary Scan controller
ReCeiVeR
Radio Interface Unit
Radio Protection Switching
Regenerator Section OverHead
Su Bus Controller
Synchronous Digital Hierarchy
Section OverHead
Subscriber Line Interface Circuit (IC260 on UUT)
Service Telephone, also referred to as EOW and UUT
Test Clock
Test Data In
Test Data Out
Test Mode Select
Test Reset
Contact (jack)
Nera Networks PCB
Unit Under Test
Transceiver
Table 1-2: Terminology and abbreviations

Internal
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Document ID
Rev.
Rev Date
D
15205-891763 (NG-IFU\BASIC\00173)
2006-08-17
Internal
2.
UNIT DESCRIPTION
The Service Telephone Auxiliary unit is a part of the Evolution-IFU product family. The unit is designed to
facilitate handling of telephone function with selective call number and with 300-3400Hz analogue- or
64kb/s digital- connection to other IFU enclosures.
The main functions of the unit are:
Hot swap circuit for the incoming +3.35V and DC/DC converters for the different voltages needed.
Interface towards a standard telephone line by use of a SLIC (Tip and Ring) with line length
0..100meters
Interface towards Radio by use of a standard 64kb/s PCM-Codec, A-law coding. The channel is
inserted to and extracted from the OHC-bus
Two balanced Analogue interfaces toward other Service Telephone Boards with nom. -6dBm signal
level
One 4Wire transformer isolated interface with nom. signal level -6dBm but with possibility to adapt
to other in/out levels
Two 64kb/s channels with G.703 Co-dir. Timing. 2 Modes of operation
o Direct interconnection of the service telephone to a 64kb/s channel
o Customer 64kb/s channel connected to LIU or Radio using OHC bus.
Calling is based on DTMF with selective call number (00...99) or collective call by use of *-button.
It means that the board must have a DTMF-transceiver.
Optional Call in / call out signal connected via opto-couplers for collective call to / from equipment
with different call system than DTMF signaling.
A FPGA circuit for handling the OHC-bus, the Codec interfaces, the 64kb/s channel interfaces, the
SLIC interface and the signaling interface.
LEDs including heartbeat and FPGA test connector will be mounted for test purposes.
A SU-bus controller module contains a micro controller and an Ethernet port for interfacing the SUbus. The micro controller interfaces the FPGA circuit for configuration and alarm reporting
A four port RJ45 connector will be used for the external connections and a 95pins Hard Metric type
AB connector will interface the Motherboard via Vertical Board.
See figure 2-1 on next page for a Block schematic of the Service Telephone Auxiliary Unit.
Internal
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Rev Date
2006-08-17
Rev.
D
Document ID
15205-891763 (NG-IFU\BASIC\00173)
Internal
Figure 2-1: Block schematic
Internal
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Page 7(58)

Document ID
Rev.
Rev Date
D
15205-891763 (NG-IFU\BASIC\00173)
2006-08-17
Internal
2.1
Hardware overview
2.1.1 Service Telephone Auxiliary Unit

Connections on rear edge of board:
HM95AB Port
J500 95-pin connector
For connecting Svc Tel to IFU
Basic Frame or PIUT Test Jig.
PCB description:
PCB thickness : 1.6mm10%
PCB dimensions : 124 x 74mm
Figure 2-2: Service Telephone Board Component Layout
Connections on front edge of

board:
Port 1 J200-A 8-pin connector
Telephone Interface (TIP,
RING) to SLIC
Port 2 J200-B 8-pin connector
Other Equipment 1 In/Out,
64kb/s Co-dir In/Out
Port 3 J200-C 8-pin connector
Other Equipment 2 In/Out,
64kb/s Co-dir In/Out
Port 4 J200-D 8-pin connector
Call Input/Output, 4Wire
Input/Output
Internal
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Page 8(58)

Rev Date
2006-08-17
Rev.
D
Document ID
15205-891763 (NG-IFU\BASIC\00173)
Internal
2.1.2 Front Connection, J200
A RJ45 connector with four ports is used for connection at front.
Figure 2-3: Auxiliary Units front view
Pin no.
1
2
3
4
5
6
7
8
PORT1
NC
NC
NC
Tel_Ring
Tel_Tip
NC
NC
NC
PORT2
64kb/s_ codir_OutA
64kb/s_ codir_OutB
64kb/s_ codir_InpA
OE1- OutA
OE1- OutA
64kb/s_ codir_InpB
OE1- InpA
OE1- InpB
PORT3
64kb/s- codir_OutA
64kb/s- codir_OutB
64kb/s- codir_InpA
OE2- OutA
OE2- OutB
64kb/s- codir_InpB
OE2- InpA
OE2- InpB
PORT4
Call_Out
NC
Call_Inp
4Wire- OutA
4Wire- OutB
NC
4Wire- InpA
4Wire- InpB
Table 2-3 Pinning of Svc Tel 4 x 8-Pin connector J200
Pinning enables use of standard crossed Ethernet twisted pair cables for interconnection between equipment.
Internal
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Page 9(58)

Document ID
Rev.
Rev Date
D
15205-891763 (NG-IFU\BASIC\00173)
2006-08-17
Internal
2.1.3 Rear Connection, J500

A
1
2
3
4
5
6
7
8
9
10
GND
TDO
TRST_L
TCK
TMS
TDI
NC (+5V/GND2)
DIAG_OUT
DIAG_IN
GND
SU_OUT+
SU_OUTSADR0
SU_IN+
SU_IN GND
-48V1
GND
NC (SU_RA_OUT+)
NC (SU_RA_OUT-)
NC (SU_RB_OUT+)
NC (SU_RB_OUT-)
SADR2
NC (SU_RB_IN+)
NC (SU_RB_IN-)
NC (SYNC1)
IFU_ADDR1
-48V2
GND
NC (-48V_INVALID)
SADR1
GND
SADR3
IFU_ADDR0
GND
NC (MAIN1_IN0)
-48V3
GND
NC (SU_B_OUT+)
NC (SU_B_OUT-)
GND
NC (SU_B_IN+)
NC (SU_B_IN-)
GND
NC (MAIN1_OUT0)
RESET_L
NC (SYNC2)
+5V (HSWAP)
NC
(MODEM_IN_CLK)
NC (MAIN1_OUT1)
11
12
NC (+5V/GND3)
NC (SU_RA_IN+)
GND
NC (MAIN1_IN1)
NC (MAIN1_OUT2)
NC (MODEM_IN0)
NC (SU_RA_IN-)
NC (MODEM_OUT_0)
NC (MAIN1_IN2)
NC
(MODEM_OUT_CLK)
13
14
15
16
17
18
19
NC (MAIN1_IN_CLK)
NC (MODEM_IN1)
NC (MODEM_IN2)
NC (MODEM_IN3)
GND
GND
+3.3V1
IFU_ADDR2
ISP_EN_L
RTCK
GND
NC (RIU_CLK+)
NC (RIU_CLK-)
+3.3V2
NC (MAIN1_OUT_CLK)
NC (MODEM_OUT1)
NC (MODEM_OUT2)
NC (MODEM_OUT3)
GND
GND
+3.3V3
NC (MAIN1_IN3)
GND
NC (RES0)
OHC_TIMING
OHC_SPARE
OHC_DATA_UPPER
+3.3V4
NC (MAIN1_OUT3)
GND
OHC_DATA_LOWER
GND
NC (SYNC0)
GND
REF_10MCLK
Table 2-2 Pinning of SvcTel 95-Pin connector J500
Yellow shaded cells

Green shaded cells
Light Green shaded cells
Pale Blue shaded cells
White shaded cells
Grey shaded cells
Pink shaded cells
Blue shaded cells
Tan shaded cells
Orange shaded cells
Lavender shaded cells
Total No. of Nets = 95
Possible BST test coverage:
Possible FCT test coverage:
5
3
41
1
20
2
8
4
7
1
3
=> BST
=> BST
=> BST
=> BST
=> GND
=> NC
=> FCT
=> FCT
=> FCT
=> FCT
=> FCT
Infra Test
Boundary Scan TAP Signals
Inter Test
Including ADP test.
Inter Test
(ADP NC test).
Inter Test
(ADP test) Partially Tested
No Test
No Test
No FPGA connection on PIUT
Test 4.6.2 SBC Software Download.
Test 4.6.3 Ethernet Testing
Test 4.6.4 SBC Address Detection (+ Partial BST)
Test 4.6.6 Hot Swap Test
Test 4.6.7 Voltage Measurements
GND nets = 20
50/ 95 = 53%
23 / 95 = 24%
BST Nets=50 (Incl. 39 NC)

FCT Nets = 23
Total Test coverage:
77%
Note: Some nets are tested both by BST and FCT.
The physical pin layout of connector J500 seen from the rear side of the Svc Tel is shown below.
E
D
C
B
A
19
Figure 2-4 J500 Physical Pin Layout

Internal
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Page 10(58)

Rev Date
2006-08-17
Rev.
D
Document ID
15205-891763 (NG-IFU\BASIC\00173)
Internal
2.2
Software overview
For detailed description of programming and download refer to SW build descriptions in eMatrix.
2.2.1 Download of Application SW to the Svc Tel

New versions of the application software may be downloaded to the EOW / SvcTel. The software is loaded
into the Phillips LPC2114 micro-controller, IC120. The software is often referred to as SBC Code.
File to be downloaded:
SW-SBC-APP-<revision>.hex
Description:
SBC code
Type:
(.Hex file)
Visual control of Application software using LEDs:

Application software loaded: LED H1 blinking green.
2.2.2 Download of FPGA SW to the Svc Tel

FPGA SW shall be downloaded by using the ActiveTCL environment (Ethernet).
SW-FNF5660A-FPGA46-<rev>.nff
Description:
FGPA Code
Type:
(.NFF file)
Visual control of FPGA software using LED:

FPGA Code loaded:
LED H600 blinking approx. 1-2 Hz
2.2.3 Download of Application SW to the AUT and PIUT Test Jigs

The procedure is the same as for loading code to the Svc Tel. The same software is used.
SW-SBC-APP-<revision>.hex
Description:
SBC code
Type:
(.Hex file)
Visual control of Application software using LEDs:

Application software loaded: AUT: H400 Blinking green.
PIUT: H301
Blinking green.
2.2.4 Download of FPGA SW to the PIUT Test Jig, K-7295 (ET-5157A)

FPGA29-<revision>.nff
Description:
FGPA Code
Type:
(.NFF file)
Visual control of PIUT FPGA software using LED:

FPGA Code loaded:
LED H302 blinking slowly, approx. 0.5 Hz.
2.2.5 Download of FPGA SW to the AUT Test Jig, K-7346 (ET-5189A)

FPGA54-<revision>.nff
Description:
FGPA Code
Type:
(.NFF file)
Visual control of AUT FPGA software using LED:

FPGA Code loaded:
LED H401 blinking slowly, approx. 0.5 Hz.
Internal
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Page 11(58)

Document ID
Rev.
Rev Date
D
15205-891763 (NG-IFU\BASIC\00173)
2006-08-17
Internal
3.
TEST STATION DESCRIPTION
3.1
Test Station overview

Service Telephone (EOW) Test Station Overview
AUTO-TIMS III
Signal Generator, Level Detector
1kHz Sine, 600 Ohm
Generator A, B
Level_Det A, B
Power
Supply
70V DC
0.5A
FAN_ALM1
FAN_ALM2
FAN_ALM3
FAN_CTRL1
FAN_CTRL2
FAN_CTRL3
GND1
GND2
GND3
GREEN_LED
RED_LED
FAN_ALM0
J271
FAN
Freq.
BNC
Connector
J272
2-Pin D-Sub
70V Connector
P550
Ethernet
AUT
Port A
P4
2-Pin D-Sub
48V Connector
Debug LEDs
Port B
J1
95-Pin
P1
H401
H402
H403
H404
ALM
LED
H400
J1
95-Pin
P2
3M
20-Pin
P1
3M
10-Pin
3M
20-Pin
P8
3M
10-Pin
P7
P5B
P5A
Port D
Port C
Debug LEDs
H600
H601
H602
P300
H603
Port A
Port D
BNC
Connector
J252
64kb/s
Freq.
Port B
P11
9-Pin D-Sub
DIAG-RS232PIUT
P9
3M
20-Pin
Debug PIUT
P3
3M
20-Pin
Debug UUT
P10
USB-PIU
Type B
P12
USB-PIU
Type A
Port A
J251
J2
55-Pin
Port A
Port B
Port C
Port D
J202
Telephone
Port D
Port D
Port C
Port C
Port B
Port B
Port A
Port A
J201
J200
AUT K-7346
(ET5189A)
ALM
LED
H1
Ethernet
PIUT
P6
Port C
48V Power Supply

Controllable
Agilent E3645A
GPIB
TAP1 (UUT)
TAP2 (PIUT)
USB
GPIB-USB
Controller
JTAG POD
JT2137/12
JT2147
Ethernet
PIU (UUT)
9-Pin D-Sub
DIAG-RS232PIU (UUT)
Port B
-48V
RS-232
Ethernet 2
RS232
Ethernet 1
JTAG Cable
Boundary Scan
Controller
JT3727/TSI
Switch
PIUT Test Jig K-7295

(ET5157A)
UUT FNF5660A
Windows XP PC
Two LAN
Office
LAN
WATS
Test Data
Collection
Test
Requirements
StSo 08.04.2006
Figure 3-3 Svc Tel Test Station overview
3.2
Test Jig overview
Two test jigs will be used to test the UUT:

PIUT
(Plug-In Unit Test)
K-7295
AUT
(Auxiliary Unit Test) K-7346.
The UUT board will be placed inside the PIUT test jig, where the rear connector mates with the PIUT.
A set of cables from the AUT test jig will then be connected to the front connectors of the UUT.
Internal
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Rev Date
2006-08-17
Rev.
D
Document ID
15205-891763 (NG-IFU\BASIC\00173)
Internal
3.3
PIUT Test Jig, K-7295
The UUT will be placed in a Test Jig (Fixture), K-7295.

It is often referred to as the PIUT (Plug-In Unit Test).
The Test Jig will consist of a dedicated Test Board, a connection board and a mechanical enclosure.
3.3.1 Test Board, ET5157A

The Test Board (ET5157A) is normally referred to as the PIUT board.
The UUT connects to the PIUT via a connection board named ET5162A.
The PIUT has several connectors for various test equipment. See Figure 3-1 above.
The PIUT connectors are:
P4 2-Pin D-Sub connector
P1 3M 10-Pin connector
P5-B 8-Pin RJ45 connector
P5-A 8-Pin RJ45 connector
P10 USB Type B connector
P12 USB Type A connector
-48DC In
TAP1 UUT
TAP1 UUT
TAP2 PIUT
TAP2 PIUT
Ethernet-PIU
Ethernet-PIUT
RS-232-PIU
RS-232-PIUT
USB-PIU 1
USB-PIU 2
Straps on PIUT
P301 Short between
P302 Short between
P303 Short between
BST
Pin 3 - 4
Pin 3 - 4
Pin 1 - 2
FCT
Pin 3 - 4*
Pin 3 - 4*
Pin 3 - 4
P304
P305
P306
P501
P502
P41
P42
P43
P44
P45
Short between
Short between
Short between
Short between
Short between
Short between
Short between
Short between
Short between
Short between
Pin 1 - 2
Pin 3 - 4
Pin 1 - 2
Pin 1 - 2
Pin 1 - 2
Pin 1 - 2
Pin 1 - 2
Pin 1 - 2
Pin 1 - 2
Pin 2 - 4
Pin 1 - 2*
Pin 3 - 4
Pin 1 - 2*
Pin 1 - 2*
Pin 1 - 2
Pin 1 - 2
Pin 1 - 2
Pin 1 - 2
Pin 1 - 2
Pin 1 - 2
P13
Short between Pin 1 - 2
Pin 1 - 2
For use with JTAG PM3705 controller

For use with JTAG JT 3710/37x7 controller
For use with JTAG PM3705 controller
For use with JTAG JT 3710/37x7 controller
LAN Connector for communicating with UUT
LAN Connector for communicating with the test jig.
For serial communication with UUT
For serial communication with PIUT
For USB Test of Supervisory Unit.
For USB Test of Supervisory Unit.
Comment
For NC test of +5V/GND2, J1 Pin 7A
For NC test of +5V/GND3, J1 Pin 11A
BST: Disconnect RESET#
FCT: Connect RESET# to download SBC SW
Bypass SBC, LPC2114
Disconnect ISP_EN_L to SBC
1 k Ohm Pull-Up on HSWAP
RES1 for Auto-Write during Flash programming
RES2/RTCK Default setting
+3.3V Supply to PIU
+3.3V Supply to PIU
+3.3V Supply to PIU
+3.3V Supply to PIU
BST: Disconnect -48V to PIU
FCT: Connect -48V to PIU (SvcTel only)
Enable +5V_VBUS to USB A
* Dont care, either position works.
3.3.2 Connection Board, ET5162

The connection board consists of two 95-pin male connectors and two 55-pin male connectors.
3.3.3 Mechanical enclosure, VJTE-7328

The mechanical enclosure for the test jig is documented in eMatrix as VJTE-7328.
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3.4
AUT Test Jig, K-7346
The AUT Test Jig is based on the ET5189A board.

The UUT connects to the AUT via 4 RJ-45 connectors. See Figure 3-1 SvcTel Test Station Overview.
AUT Connectors used for SvcTel (EOW) Test:
P550
D-Sub connector
-70V DC In
P404
4-Pin Berg connector
For RS-232 communication with the AUT (Download of SBC-SW).
P1A 8-Pin RJ45 connector Ethernet for local SBC on AUT

P1B 8-Pin RJ45 connector Not used
J201 A
J201 B
J201 C
J201 D
8-Pin RJ45 connector

Tip & Ring for Svc Tel test

OE 1 In/Out, 64kb/s Co-dir1 In/Out for Svc Tel test
OE 2 In/Out, 64kb/s Co-dir2 In/Out for Svc Tel test
Call Input/Output, 4Wire Input/Output for Svc Tel test
J202 A
J202 B
J202 C
J202 D

No connection (Spare).
For connection of Level Detector Instrument
For connection of Signal Generator
For connection of Analogue Telephone
AUT Connectors Not used for SvcTel (EOW) Test:

J27112-Pin connector
For FAN test
J272BNC connector
For FAN frequency measurement.
J251 A
J251 B
J251 C
J251 D

J252BNC connector
P300 A
P300 B
P300 C
P300 B
64kb/s G703 Contra for Serial Board

64kb/s G703 CoDir for Serial Board
64kb/s G703 CoDir for Serial Board
64kb/s V11 Co/Contra Dir for Serial Board
For Clock Frequency measurement, Serial Board.

AUT Strap:
P401 Short between Pin 1 - 2
Short between Pin 3 - 4
For analogue outputs to ACU Board.

For alarm outputs 1-4 to ACU Board.
For alarm outputs 5-8 to ACU Board.
For relay readings from ACU Board.
Reset the SBC Controller, Default = No strap.

Activate ISP_EN_L for software download. Default = No strap.
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Internal
3.5
Test Station Equipment
The following equipment is needed to test and program the SvcTel (EOW) board.
3.5.1 Nera Equipment

PIUT Test Jig, K-7295 including:
- ET5157A PIUT Board (Nera UBN 6201 M3A)

- ET5162A Connection Board (UBT6226 with two 95-pin and two 55-pin connectors)
AUT Test Jig, K-7346 including:
- ET5189A AUT Board (Nera UBN 6439 M1A)
- VJTE-7348 Mechanical Enclosure for AUT.
Telephone Handset, VS-Code: 87A10-E2
3.5.2 Instruments
48V Power Supply, 1A, GPIB Controllable.
70V Power Supply 0.5A
Signal Generator & Level Detector
600 Ohm, Sine wave, 50 - 10 kHz, -50 to +10dBm
GPIB Interface
PCI RS-232 Board
Ex. Agilent E3645A

Ex. Agilent E3612A
Ex. AUTO-TIMS III
Ex. NI GPIB-USB-HS or Agilent 82357A/USB
Ex. Digi Acceleport 4r 920 PCI
3.5.3 JTAG Equipment

Boundary Scan Controller. JT3727 (/ PCI or TSI)
Boundary Scan POD.
JT2137/12 or JT2147 QuadPOD
3.5.4 General Equipment
Test PC with Windows XP Pro

Extra LAN board for PC
LAN Switch 100 M Bit/s
Handheld Scanner
Ex. INTELLINET 5-Port Switch.

Ex. Metrologic MS9520
3.5.5 Cables & Connectors

Cable
Type:
TP Cable
TP Cable
GPIB Cable
RS-232 Cable
48V / 70V Cable
TAP Cable
RJ45 Cable
RJ45 custom Cable
Connector
Type:
Banana Plug
Banana Plug
Description:
Standard
Standard
Standard
Null Modem (Female Female)
Nera UWMK 5051 or 5736-150 or 3101
3M 20-Pin
Standard crossed Ethernet twisted pair cable
RJ45 to 4 Banana plugs for connecting Instr. to AUT
Description:
Red
Black
Length:
1 meter
3 meter
1 meter
2 meter
2 meter
Max. 30 cm
1 meter
1 meter
Gender:
Male
Male
No.
Required:
4
1
1
2
2
2
4
1
No.
Required:
4
4
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Table 3-4 Cables and connectors
3.6
Test Station Software
The following programs are needed to test and program the Svc Tel board.
Test Type
Program type
Name
Used for
Boundary scan JTAG test SW from
TestStand PIP
Production package for TestStand
JTAG Technologies BV PIP TestStand
Production Integration Package for TS
PM3790
Boundary Scan Diagnostics
TDF2176
Test development package
Functional test Phillips Flash Utility
LPC2000 Flash Utility Loading Code to LPC2114
IP Address Server
Bootp Server
Ethernet Communication
TFTP Server
TFTPD32
Ethernet Communication
TCL platform
ActiveTCL
Sending configuration commands to UUT.
(Wish84.exe)
Test Sequencer
TestStand Runtime
Run TestStand Sequences
Table 3-2 Programs needed during testing
3.6.1 BSDL-Files used for Boundary Scan Testing

UUT:
LPC2114_87G33A.BSD
XC3S200_87G18.BSD
; Fake BSDL file for the Phillips Microcontroller. (IC120)

; BSDL file for the FPGA (IC601)
PIUT:
XC3S200_87G18.BSD
; BSDL file for the FPGAs (IC300 and IC400) on the PIUT
3.6.2 Common TCL Scripts used during Functional Tests.

Several files are used to configure the SvcTel, PIUT and AUT during functional testing.
There are too many to list them all, but some of the most important TCL scripts are listed below:
EOW_PIUT_SourceAll.TCL
- sbc_fpga_poll.tcl
- sbc_rw_udp.tcl
- sbc_field_access.tcl
- fpga_infoString.tcl
- eow_reg.tcl
- eow_api.tcl
- eow_gui.tcl
- ana_gui.tcl
AUT_SourceAll.TCL
- fpga54_reg.tcl
- aut_eow.tcl
- aut_gui.tcl
- aut_generic.tcl
=> Source functions needed for functional testing of EOW.

=> Poll FPGA or SBC to see if contact is made and the unit is ready.
=> SBC driver towards LPT port with use of lpttcl dll
=> Read and Write basic commands
=> Read out the revision and ID registers.
=> Set up EOW FPGA46 registers
=> EOW API Scripts
=> EOW API Scripts
=> Script for reading AD-values
=> Source functions needed for setup and configuration of AUT.
=> Set up AUT FPGA54 registers
=> Commands for test operations of EOW unit.
=> Commands to get and update parameters for all AUX boards.
=> Commands for test operations of EOW unit, (PRBS check, etc.)
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Internal
Also, TCL scripts for specific tests are listed under each test description.
3.6.3 First time Set-up of Test Station

The following describes first time set-up of the test station. (Only performed once).
See Figure 3-1 for more information.
First time HW Set-up:
1. Connect 48V power cable from PS to connector P4 on the PIUT test jig.
2. Connect GPIB-USB-B to the USB2 port on the PC.
3. Connect GPIB Cable from Power Supply to the GPIB-USB-B adapter.
4. Connect RS-232 cable from DigiBoard COM3 to connector P6 on the PIUT.
5. Connect LAN cable from PC to LAN Switch.
6. Connect LAN cable from Switch port 1 to connector P5B on the PIUT.
7. Connect LAN cable from Switch port 2 to connector P5A on the PIUT.
8. Connect Boundary Scan TAP1 cable to connector P2 on the PIUT.
9. Connect Boundary Scan TAP2 cable to connector P8 on the PIUT.
10.Connect LAN cable from Switch port 3 to AUT P1A.
11.Connect 70V power cable from 70V PS to P550 on AUT.
12.Connect RS-232 cable from DigiBoard COM4 to AUTO-TIMS III.
13.Connect Test Cable from AUTO-TIMS III to AUT J202-C
14.Connect Telephone handset to AUT J202-D.
15.Handset must be On Hook for all tests.
First time SW Set-up:
1. Install BootP server.
2. Place all TCL scripts in the following directory: C:\IFU\SvcTel\FCT\TestStand\LabView\TCL
3. Install ActiveTCL (version 8.4.7.0) in the following directory: C:\TCL.
4. Install TFTPD32 and set base directory to the directory where the FPGA code lies;
C:\IFU\SvcTel\FCT\tftp
5.
Download SBC code to the PIUT.
6.
Download SBC code to the AUT.
7.
Configure AT3 for 38400 bps, 8 data bits, No Parity, 1 Stop bit. (38400, 8, N, 1).
3.6.4 Set-up for each test

The following describes set-up before each new board is ready to be tested.
Before first board in a batch:
1. Set up the Power Supply, (Voltage = 48.00V, Current Limit = 200mA, Output = On)
2. Run BootP server (To issue an IP address for programming environment).
3. Run TFTPD32
4. Program the FPGA on the PIUT.
5. Program the FPGA on the AUT.
Note1: ActiveTCL (Wish84.exe) is automatically started from LabView and does not need to be started
Manually except for in some fault seeking situations.
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Before testing of each board:

1. Insert UUT into the PIUT Test Jig (K-7295)
2. Connect the RJ45 cables from UUT J200 (A-D) to J201 (A-D) on the AUT.
4.
TEST DESCRIPTIONS
4.1
Test Overview
Test
4.2 Test Coverage
4.3 Initial Process Tests
4.3.1 AOI tests
4.3.2 ICT or FPT tests
4.4 Power-On Tests
4.4.1 Current Limit test
4.5 Boundary Scan Test
4.5.1 General Information
4.5.2 Tests to developed
4.5.3 General Quality
Requirements
4.6 Functional Tests
4.6.1 Power Consumption
4.6.2 SBC Software Download
4.6.3 Ethernet Testing
4.6.4 SBC Address Detection
4.6.5 Front LED Test
4.6.6 Hot Swap Test (3.3V)
4.6.7 Voltage Measurements
4.6.8 FPGA Software Download

4.6.9 Power Consumption
4.6.10 Other Equipment 1 Input
8
9
10
4.6.11 Other Equipment 2 Input
11
4.6.12 4Wire Input
12
4.6.13 Telephone Input

(TIP/Ring)
4.6.14 DTMF Detector and
Ringing
4.6.15 Call In / Call Out
4.6.16 DTMF Generator
(Send Star from EOW FPGA)
4.6.17 500Hz Generator
4.6.18 64kb/s Channel 1
4.6.19 64kb/s Channel 2
4.6.20 Inventory
13
Short description
Test coverage calculations.
Tests performed before power is turned on
Automatic Optical Inspection of PCB. (Implementation not decided).
In-Circuit or Flying Probe test of assembled board. (Before power on).
Ensure there are no short circuits or damaged components. (Before BST).
Tests performed using JTAG test equipment:
1. Infrastructure test
2. Interconnect test
3. Cluster test for LEDs
4. Other cluster tests
#
1
2
3
4
5
6
7
14
15
16
17
18
19
20
Measure 48V DC Power Consumption. (Before Software Download)

Loading SBC SW to the Phillips LPC2114 Microcontroller.
Verify Ethernet communication with UUT.
Check the SBC and address bus connectors.
Verify that the front LED is working.
Verify Hot Swap functionality
Use TCL scripts to communicate with the SBC on the UUT and measure the
following voltages: +1.2V, +2.5V, +5V and -48V
Download the FPGA configuration file using ActiveTCL environment
Measure 48V DC Power Consumption after Software Download.
Connect Other Equipment 1 Input with analogue signal generator with
sinusoidal 1020Hz and -6dBm into 600ohm. Measure Outputs (with level
detector 600ohm).
Connect Other Equipment 2 Input with analogue signal generator with
sinusoidal 1020Hz and -6dBm into 600ohm. Measure Outputs (with level
detector 600ohm).
Connect 4 Wire Input with signal generator with sinusoidal 1020Hz and
various input levels into 600ohm. Measure Outputs (with level detector).
Connect Telephone Input with signal generator with sinusoidal 1020Hz and
0dBm into 600ohm. Measure Outputs (with level detector 600ohm).
Insert DTMF signal on AUT and verify DTMF detector (on-board) using
inputs. Verify (manually) ringing in the telephone for all (five) inputs.
Toggle Call Out from FPGA and verify Call In signal read out in FPGA.
Enable DTMF Generator and measure output levels at OE1, OE2, 4W, OE1
and OE2 with codec1/codec2 near end loop.
Enable 500Hz in FPGA and verify output on OE1.
Insert PRBS sequence in FPGA and verify 0 errors on received data in FPGA.
Insert PRBS sequence in FPGA and verify 0 errors on received data in FPGA.
Write inventory data to the SBC Flash: (Send file using TFTP protocol).
1. Set Article Code, HW Revision, Serial Number and Test Date in Main
Inventory. (Index 0)
2. Set Total Code, Total Revisions and Serial No in Sub Inventory.
(Index 1).
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Internal
4.6.21 Get EOW SvcTel SW Info
4.6.22 Verify all Inventory
21
22
3. Read out and check all inventory settings.

Use TCL scripting to collect SBC and FPGA SW info and transfer to WATS.
Switch Power Off and then On again. Read out all inventory settings.
Table 4-1 Test Overview
4.2
Test Coverage
Test coverage calculations are based on net-list for the FNF5660A R1A.
Nets tested by BST form the basis for the calculations.
Only BST Test Coverage is presently calculated. Nets not tested by BST, but tested with ICT or FCT may be
added, giving an indication of the total test coverage.
SUMMARY
Number
Number
Number
Number
of
of
of
of
nets
nets
nets
nets
with
with
with
that
MERGED NETS
ALL NETS
2
0
147
6
5
0
231
14
only bscan inputs

only bscan outputs
bscan inputs and outputs
are bscan TAP nets
Total number of direct access nets

Total number of nets with connector access only
Total number of nets without any access
250
148
192
Total number of nets in design
590
DIRECT BSCAN-ACCESSIBILITY
42%
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4.3
Initial Process tests
These tests are performed before the UUT is inserted in the Test Station.
4.3.1 Automatic Optical Inspection (AOI)

NOTE: Implementation of AOI is yet To Be Determined.
Tests that correct components are mounted and that they have correct orientation.
4.3.2 In-Circuit Testing (ICT)

NOTE: Use of ICT or FPT is yet To Be Determined (TBD).
Perform an ICT or FPT to at least test components not covered by boundary scan test.
In addition, the following functions shall be tested using the ICT (or FPT) test.
Measuring points
1
GND, TP 554
2
Check +1.2V for short circuit by measuring the impedance to GND
Measure at TP551 (1.2V)
3
Check +2.5V for short circuit by measuring the impedance to GND
4
Check +3.3V for short circuit by measuring the impedance to GND.
5
Check SBC_1.8V for short circuit by measuring the impedance to GND
6
7
8
Check +5V_Distribution for short circuit by measuring the impedance to GND.
Impedance
0 Ohm.
500 Ohm.
1000 Ohm
300 Ohm
1000 Ohm.
1000 Ohm.
300 Ohm.
500 Ohm.
Table 4-2: ICT Vital Test Points
4.4
Power-On tests
4.4.1 Current Limit test

The 48V Power Supply on the Boundary Scan Test Station must have current limiting. This is to protect the
board from excessive damage should there be a fault on the board. The Max Limit is found by adding the
average consumption of the Svc Tel, PIUT and AUT boards and then adding an appropriate margin.
Max. Limit
Typical drain
(48.00V DC):
(48.00V DC):
200 mA
100 mA
(Svc Tel + PIUT)
If excessive current consumption:

Turn off power immediately.
Measure the resistance between GND and +3.3V using a Multimeter:
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Internal
Expected value should be 300 Ohm. Inspect board carefully for short circuits and components mounted
incorrectly.
NOTE: Svc Tel current drain increases when the front connector is connected to the AUT.
4.5
Boundary Scan Test
In this section the term signal is used both for a single net and for two or more nets separated with series
resistors.
4.5.1 General Information

Netlist standard:
Netlist converter:
Total nets in design:
Direct access nets:
Test Coverage:
Mentor
mgc2jtn
590
250
250/590 => 42%
4.5.2 Tests to be developed

1. Infrastructure Test.
Verify that the JTAG chain is operational.
The following signals through the Svc Tel Connector (J500) are verified in this test:
TDI, TMS, TCK, TRST_L and TDO.
2. Interconnect Test, including;
- Integrated Pull Up/Down test.
(Must define Resistors as well as PWR and GND nets).
- Test of signals through J500 using AUT test board.
NC (Not Connected) nets must also be included.
(Must define PIUT, K-7295 as Test Adapter using ADP-file).
3. Cluster Test for SvcTel debug LEDs H600-H603.
4. Other Cluster tests as appropriate to achieve maximum test coverage.
Verify non-Boundary Scan circuits to improve test coverage.
Ex. Buffer circuits, Inverters, etc.
4.5.3 General Quality Requirements

The goal is to achieve a safe design without possible driver conflicts.
All warnings during Test Development must be handled, remaining warnings must be justified.
All Cluster Attentions (warning 2062 and 2063) must be handled.
Design name shall reflect the name and HW revision of the UUT.
Not Mounted (NM) components must be commented out in both the JTN and the DIF file.
Use part name (Nera VS name) in Part Lists, not Symbol Name.
Use descriptive comments throughout the design as well as headers in each file.
Boundary Scan Test should work on blank boards as well as on boards with all SW loaded.
The installation package should be verified on a blank pc without network connection to avoid any
missing files or links.
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4.6
Functional Tests
The following section describes functional testing of the IFU Svc Tel Board.
4.6.1 Power consumption

Test # 1:
Use a 48V GPIB controllable Power Supply and measure the 48V DC current used by the
SvcTel board.
Svc Tel Current = Total Current - PIUT current. (PIUT avg. current = approx. 36 mA)
Recommended Power Supply: Agilent E3645A or similar.
Test #
1.1
Current at
-48.00V DC
Measure Point Min. Limit Max. Limit

P4
20 mA
80 mA
Typical Value (No SBC or FPGA sw)

58 mA
Table 4-3: SvcTel Power consumption
Typical Power Consumption for the EOW SvcTel board is 1.65W => 34mA at 48V DC.
(No front connections).
Required Files:
PSU_E3645A_48V_PWR_ON.vi
age364xa.llb
NOTE1:
=> Set-up and Configure Power Supply.

=> LabView Instrument Driver for Agilent E3645A.
(Contains multiple files).
Svc Tel current drain changes when SBC and FPGA Code are loaded.
When re-testing, power to the Svc Tel should be removed in order to erase the FPGA code.
This will ensure consistent measurements.
NOTE2:
Test 4.6.9 will measure power consumption with SBC and FPGA Code loaded.
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4.6.2 SBC Software Download

Test # 2:
This section describes downloading of SBC code to the Phillips LPC2114 micro controller.
The SBC SW is stored in eMatrix. Make sure that the latest revision is used at all times.
At the time of writing this document the latest revision is: R2A01.
The following pins on the PIU Interface Port (J500) are verified in this test:
RTCK (RES2), RESET_L, DIAG_IN, DIAG_OUT and ISP_EN (RES1).
The LPC2114 is equipped with two memory sections: 128 kB Flash and 16 kB RAM. The flash memory is
used to store SBC code, EEPROM data storage and firmware.
Programming Flash memory on the Phillips LPC2114 shall be accomplished by using In-SystemProgramming (ISP) on UART0. This requires that the Phillips LPC2000 Flash Utility Program is installed.
Preparations for setup:
1.) Make sure the Phillips LPC2000 Flash Utility Program is installed.
2.) The SBC (LPC2114) on the PIUT must be programmed.
3.) The FPGA on the PIUT must be programmed. (Requires BootP Server and TFTP Server).
4.) Connect RS232 cable to P6 on the PIUT.
5.) LPC2114 must be put in Reset while ISP_EN is kept low.*
=> How to set ISP_EN low.
Controlled from PIUT. Command: sbc_set piut RES1_ISP_EN 0
=> Put LPC2114 in Reset.
Controlled from PIUT. Command: sbc_set piut RESET 0
*Note! When no valid code is detected in flash sectors, the LPC2114 will automatically enable ISP mode for
Flash programming.
Download of SBC code:
Send command to command line interface to download code to the LPC2114 device.
Example of download command:
LPC210x_ISP.exe "C:\Nera\NextGen\IFU\SBC_SW\SW-SBC-APP-R2A01.hex" 25000 LPC2114 COM1: 57600 1
Path and file name in quotation marks: "C:\Nera\NextGen\IFU\SBC_SW\SW-SBC-APP-R2A01.hex

Crystal frequency in kHz:
25000
Device name:
LPC2114
Communications port:
COM1:
Baud Rate:
57600
DTR/RTS selection:
1
(1 if the target hardware supports automatic reset and boot loader selection through the DTR/RTS signals, otherwise 0 )
Verification of correct SBC code:
Use TCL scripts to verify that the correct SBC code has been loaded.
Required Files:
UdpTclDriver.dll
=> Must be placed in the same directory as the TCL scripts.

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SW-ET5157A-FPGA29-R1A00_uc.nff
EOW_SourceAll.TCL
PIUT_SourceAll.TCL
PIU_PIUT_SBC_Download.tcl
SW-SBC-APP-R2A01.HEX
=> FPGA for PIUT. Must be in the AppSW folder.

=> Source all functions needed for EOW FCT.
=> Source all functions needed for PIU common FCT.
=> Download SBC code to the EOW SvcTel board using PIUT.
=> SBC SW to be downloaded.
4.6.3 Ethernet Testing

Verify Ethernet communication with UUT.
Test # 3:
Test #
3.1
Traffic through Pin 2B, 3B, 5B and 6B on J500. SU BUS

Measure
Response
Measure Point
SU BUS on J1
Comment
UUT IC120
Test Criteria
Pass / Fail
TCL Commands
Ping 10.0.1.15
or
SbcConnect 10.0.1.15
SbcGetSWversion
or
poll sbc timeout
Table 4-4: Ethernet Testing.
Required Files:
UdpTclDriver.dll
EOW_SourceAll.TCL
- sbc_fpga_poll.tcl
PIUT_SourceAll.TCL
PIU_Ethernet_Tests_A.TCL

=> Test Ethernet traffic on PIU.
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2006-08-17
Document ID
15205-891763 (NG-IFU\BASIC\00173)
Internal
4.6.4 SBC Address Detection

Test # 4:
Check the SBC and address bus connectors.
The purpose of this test is to check that the SBC and connections are correct. This is verified by checking
that the SBC detects the correct addresses. This test assumes that the SBC software and FPGA code are
already downloaded to the PIUT and SBC software is downloaded to the UUT.
The test can be performed automatically by running a TCL script.
The script should do the following:
1. Verify that the UUT reads the address set in the PIUT.
2. Alter the slot address in PIUT to 110.1110 (IFU 6, Slot14) and verify that the address is detected in
the UUT.
3. Alter the slot address in PIUT to 001.0001 (IFU 1, Slot 1) and verify that the address is detected in
the UUT.
4. Return 0 if the test succeeds, and an error code if the test fails.
Check the return value from the TCL script to determine pass/fail status of the test.
Test #
Test Type
4.1
TCL Script
Measure Point
J500 Pin 4B, 4D, 5C
and 6D
Test Criteria
Pass / Fail
Command
TBD
Table 4-5: SBC Address Detection Test.
Required Files:
UdpTclDriver.dll
PIUT_SourceAll.TCL
- sbc_fpga_poll.tcl
PIU_SBC_AddressTest.tcl

=> Source all functions needed for PIU Common functional testing.
=> Check SBC and connections are correct.
Internal
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Document ID
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D
15205-891763 (NG-IFU\BASIC\00173)
2006-08-17
Internal
4.6.5 Front LED Test

Test # 5:
The purpose of this test is to verify that the front LED is working correctly.
The LED is controlled from the SBC.
The LED can be set in different modes:

Green LED ON indicates no alarms on unit.
Red LED ON indicates critical alarms on unit.
Set the green LED to ON and verify by visual inspection that the green LED is green.
Set the red LED on and verify by visual inspection that the red LED is red.
Since this test requires interaction with the test engineer, the test should be put towards the beginning (after
SBC download) or end of the test sequence for the UUT.
Test #
5.1
Test Type
Visual
Inspection
Measure Point
Test Criteria
Front LED H1
Pass / Fail
Command
TBD
Table 4-6: Front LED Test.
Required Files:
UdpTclDriver.dll
sbc_fpga_poll.tcl
PIUT_SourceAll.TCL
PIU_SBC_LED.TCL
PIU_SBC_LED_Auto.TCL

=> Set SBC LED state
=> Restore LED state to Auto Mode.
Internal
Nera Networks AS
Page 26(58)

Rev Date
2006-08-17
Rev.
D
Document ID
15205-891763 (NG-IFU\BASIC\00173)
Internal
4.6.6 Hot Swap Test

Verify that the Hot Swap functionality is working correctly.
Test # 6:
This test is used for verifying that the Hot Swap controller is working correctly.
The connection between PIUT and UUT is also verified
.
The Hot swap signal (HSWAP) is controlled from the PIUTs FPGA1 (IC300, pin 99) and can be strapped
with a jumper (P306) to 3.3 volt to set the signal high. (This strap is used in boundary scan test.) The signal
goes trough PIUTs connector J1 on pin no. 10C to the UUT. On the UUT the signal goes to the Hot Swap
controller to enable/disable the 3.3 volt to pass trough.
This test assumes that the SBC software and FPGA code are already downloaded to the PIUT and SBC
software is downloaded to the UUT.
This test can be done automatically by running a TCL script. The scrip should do the following:
1. Set the Hot Swap signal low from the PIUT and verify that UUT powers down.
2. Set the Hot Swap signal high from the PIUT and verify that UUT powers up.
3. Return 0 if the test succeeds, and an error code if the test fails.
The script should read the SBC software version to check if the UUT is running.
Test #
Test Type
Measure Point
Test Criteria
6.1
TCL Script
J500 Pin 10C
Pass / Fail
Command
TBD
Table 4-7: Hot Swap Test.
Required Files:
UdpTclDriver.dll
PIUT_SourceAll.TCL
PIU_SBC_HotSwapTest.tcl

=> Perform Hot Swap Test
Internal
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Document ID
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D
15205-891763 (NG-IFU\BASIC\00173)
2006-08-17
Internal
4.6.7 Voltage Measurements

Test # 7:
Use TCL scripts to communicate with the SBC on the Svc Tel and measure the following:
Test #:
Test #:
Test #:
Test #:
+1.2V Supply
+2.5V Supply
+5.0V Supply
-48.0V Supply
7.1
7.2
7.3
7.4
Test #
7.1
7.2
7.3
7.4
Measure
+1.20V
+2.50V
+5.00V
-48.0V
Read AD Ana0 Input on Svc Tel by command to SBC

Measure Point
SvcTel SBC AD0
SvcTel SBC AD1
SvcTel SBC AD2
SvcTel SBC AD3
Min Limit
1.14 Volt
2.35 Volt
4.95 Volt
-49.5 Volt
Max Limit
1.26 Volt
2.70 Volt
5.25 Volt
-46.5 Volt
% Limit
+/- 5%
+/- 6%
+/- 3%
+/- 3%
Command
SbcGetADValues
SbcGetADValues
SbcGetADValues
SbcGetADValues
Table 4-8: Voltage measurements
Required Files:
UdpTclDriver.dll
EOW_SourceAll.TCL
- sbc_fpga_poll.tcl
PIUT_SourceAll.TCL
Read_EOW_AD.TCL
Test_7_1_Voltage_Measurements.vi

=> Read Ana0 Ana3 on the EOW board
=> LabView VI for this test.
Internal
Nera Networks AS
Page 28(58)

Rev Date
2006-08-17
Rev.
D
Document ID
15205-891763 (NG-IFU\BASIC\00173)
Internal
4.6.8 FPGA Software Download and Configuration

Test # 8:
This section describes how to download the FPGA configuration file* via local Ethernet bus
(SU_Bus) by using TCL-scripts. *(Also called configuration pattern).
Programming actions:
1.) Start the BootP server and verify that the UUT and is connected to the test net.
IP Address PIU
= 10.0.1.15
2.) Start the TFTP server.
Make sure the Base Directory is set to where the tcl scripts are located.
Example: C:\Nera\NextGen\IFU\SvcTel\FCT\tftp
Make sure the Server interface is set to:
10.0.0.1
3.) Start the wish84 program. (Or use the tclsh84 program)
a) Change directory to drive specified:
% cd C:/
b) Download FPGA code from Test PC to UUT
% source [filename]
Filename =
C:/Nera/NextGen/IFU/SVCTEL/FCT/TestStand/LabView/TCL/IFU_FPGA_Download.tcl
4.) Use TCL scripts to verify that the correct FPGA code has been loaded.
If the download is OK, then the LED H600 should be blinking.
Test
Test Type
#
8.1 Software Download
Software
Type
FPGA SW
Software Name
Indicator
Test Criteria
SW-FNF5660A-FPGA46-<rev>.nff
LED H600
Pass / Fail
Table 4-9-1: FPGA Download
Test
#
8.2
Type
Test Criteria
Commands
Setup FPGA configuration for FCT
Pass / Fail
autEOW::setupEOW
Table 4-9-2: FPGA Configuration for FCT
Required Files:
UdpTclDriver.dll
SW-ET5157A-FPGA29-R1A00_uc.nff
SW-FNF5660A-FPGA46-R1A00.nff
EOW_SourceAll.TCL
PIUT_SourceAll.TCL

=> FPGA for PIUT. Must be in the AppSW folder.
=> FPGA for the SvcTel. Must be in the AppSW folder.
=> Source all functions needed for PIU common FCT
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2006-08-17
Internal
IFU_FPGA_Download.TCL
Test_8_2.TCL
=> TCL script for FPGA download on PIU boards.

=> TCL script developed for Test 8.2
4.6.9 Power consumption after SW Download

Test # 9:
Use a 48V GPIB controllable Power Supply and measure the 48V DC current used by the
SvcTel after SBC Code and FPGA Code has been loaded.
Svc Tel Current = Total Current - PIUT current. (PIUT avg. current = approx. 36 mA)
Recommended Power Supply: Agilent E3645A or similar.
Test #
9.1
Current at
-48.00V DC
Measure Point Min. Limit Max. Limit

P4
20 mA
80 mA
Typical Value (SBC and FPGA sw)

53 mA
Table 4-10: SvcTel Power consumption
Required Files:
PSU_E3645A_48V_PWR_ON.vi
age364xa.llb
PIUT_SourceAll.TCL
=> Set-up and Configure Power Supply.

=> LabView Instrument Driver for Agilent E3645A.
(Contains multiple files).
Internal
Nera Networks AS
Page 30(58)

Rev Date
Rev.
D
2006-08-17
Document ID
15205-891763 (NG-IFU\BASIC\00173)
Internal
4.6.10 Other Equipment 1 Input Test

Test # 10:
Connect Other Equipment 1 Input with analogue signal generator with sinusoidal 1020Hz
and -6dBm into 600ohm. Switch K203 on AUT must be closed (High).
Connect Generator to AUT J202 1C, 2C.
(Cable: Orange, Green) Yellow Banana
Connect Level Detector to AUT J202 7C, 8C. (Cable: White, Gray) Green Banana
Measure the following Outputs (with level detector 600ohm):

Test #:
Test #:
Test #:
Test #:
Test #:
Test #:
Test #:
Test #:
Test #:
Test #:
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
10.9
10.10
Test #
Input Measure
Port
Measure Point
Min
Level
Output
Limit
OE1
(dBm)
-6 dBm -6 dBm TIP/Ring AUT J202 7C, 8C -7.0
-6 dBm -6 dBm
OE2
AUT J202 7C, 8C -6.41
-6 dBm +4 dBm
4W
AUT J202 7C, 8C +3.30
-6 dBm 0 dBm
4W
AUT J202 7C, 8C -0.51
-6 dBm -6 dBm
4W
AUT J202 7C, 8C -6.51
-6 dBm -10 dBm
4W
AUT J202 7C, 8C -10.61
-6 dBm -6 dBm
OE1
AUT J202 7C, 8C -6.51
-6 dBm -6 dBm
OE1
AUT J202 7C, 8C -6.51
-6 dBm 0 dBm TIP/Ring AUT J202 7C, 8C -1.00
-6 dBm 0 dBm TIP/Ring AUT J202 7C, 8C -1.00
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
10.9
10.10
Telephone (Tip & Ring)

Other Equipment 2
4Wire +4dBm Out
4Wire 0dBm Out
4Wire -6dBm Out
4Wire -10dBm Out
Other Equipment 1
(Loop Codec1 near end)
Other Equipment 1
Tip/Ring
Tip/Ring
Max
Limit
(dBm)
-5.0
-5.59
+4.50
+0.51
-5.49
-9.50
-5.49
-5.49
+1.00
+1.00
Tol.
Limit
(dBm)
+/- 1.00
+/- 0.41
Custom
+/- 0.51
+/- 0.51
Custom
+/- 0.51
+/- 0.51
+/- 1.00
+/- 1.00
Commands
autEOW::_10_01
autEOW::_10_02
autEOW::_10_03
autEOW::_10_04
autEOW::_10_05
autEOW::_10_06
autEOW::_10_07
autEOW::_10_08
autEOW::_10_09
autEOW::_10_10
Table 4-11: Other Equipment 1 Input Test.
Required Files:
UdpTclDriver.dll
EOW_SourceAll.TCL
PIUT_SourceAll.TCL
Test_10_1.TCL
Test_10_10.TCL

=> TCL script developed for Test 10.1.
Etc.
Internal
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Document ID
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D
15205-891763 (NG-IFU\BASIC\00173)
2006-08-17
Internal
4.6.11 Other Equipment 2 Input Test

Test # 11:
Connect Other Equipment 2 Input with signal generator with sinusoidal 1020Hz and -6dBm
into 600 Ohm.
Switch K204 on AUT must be closed (High).
Connect Generator to AUT J202 1C, 2C.
Connect Level Detector to AUT J202 7C, 8C.

Test #: 11.1
Telephone (Tip & Ring)
Test #: 11.2
Other Equipment 1
Test #: 11.3
4 Wire level -6dBm
Test #: 11.4
Other Equipment 2 -6dBm with CODEC 1 Near End Loop
Test #: 11.5
Other Equipment 2 -6dBm with CODEC 2 Near End Loop
Test
#
11.1
11.2
11.3
11.4
11.5
Input Measure
Port
Measure Point
Min
Max
Tol.
Level Output
Limit Limit Limit
OE2
(dBm) (dBm) (dBm)
-6 dBm -6 dBm TIP/Ring AUT J202 7C, 8C -7.00 -5.00 +/- 1.00
-6 dBm -6 dBm
OE1
AUT J202 7C, 8C -6.41 -5.59 +/- 0.41
-6 dBm -6 dBm
4W
AUT J202 7C, 8C -6.51 -5.49 +/- 0.51
-6 dBm -6 dBm
OE2
AUT J202 7C, 8C -6.51 -5.49 +/- 0.51
-6 dBm -6 dBm
OE2
AUT J202 7C, 8C -6.51 -5.49 +/- 0.51
Commands
autEOW::_11_01
autEOW::_11_02
autEOW::_11_03
autEOW::_11_04
autEOW::_11_05
Table 4-12: Other Equipment 2 Input Test.
Required Files:
UdpTclDriver.dll
EOW_SourceAll.TCL
PIUT_SourceAll.TCL
Test_11_1.TCL
Test_11_2.TCL
Test_11_3.TCL
Test_11_4.TCL
Test_11_5.TCL

Internal
Nera Networks AS
Page 32(58)

Rev Date
Rev.
D
2006-08-17
Document ID
15205-891763 (NG-IFU\BASIC\00173)
Internal
4.6.12 4Wire Input Test

Test # 12:
Connect 4 Wire Input with signal generator with sinusoidal 1020Hz and various input levels
into 600 Ohm.
Measure the following Outputs (with level detector 600 Ohm):

Test #: 12.1 Other Equipment 1
Test #: 12.3 Telephone (Tip & Ring)
Test #: 12.4 4 Wire level with CODEC 1 Near End Loop (-6dBm)
Test #: 12.5 4 Wire level with CODEC 2 Near End Loop (-6dBm)
Test
#
12.1
12.2
12.3
12.4
12.5
Input Measure
Port
Measure Point
Min
Max
Tol.
Level
Output
Limit Limit Limit
4W
(dBm) (dBm) (dBm)
+4 dBm -6 dBm
OE1
AUT J202 7C, 8C -6.51 -5.49 +/- 0.51
+0 dBm -6 dBm
OE2
AUT J202 7C, 8C -6.51 -5.49 +/- 0.51
-6 dBm -6 dBm TIP/Ring AUT J202 7C, 8C -7.00 -5.00 +/- 1.00
-10 dBm -6 dBm
4W
AUT J202 7C, 8C -6.51 -5.49 +/- 0.51
-10 dBm -6 dBm
4W
AUT J202 7C, 8C -6.51 -5.49 +/- 0.51
Commands
autEOW::_12_01
autEOW::_12_02
autEOW::_12_03
autEOW::_12_04
autEOW::_12_05
Table 4-13: 4Wire Input Test.
Required Files:
UdpTclDriver.dll
EOW_SourceAll.TCL
PIUT_SourceAll.TCL
Test_12_1.TCL
Test_12_5.TCL

Etc.
Internal
Nera Networks AS
Page 33(58)

Document ID
Rev.
Rev Date
D
15205-891763 (NG-IFU\BASIC\00173)
2006-08-17
Internal
4.6.13 Telephone Input Test (Tip/Ring)

Test # 13:
Connect Telephone Input with signal generator with sinusoidal 1020Hz and 0dBm into
600 Ohm.

Loop Codec1 Near End
Loop Codec2 Near End
Test #: 13.3 4 Wire
Test Input Measure Port Measure Point Min Limit
#
Level Output
(dBm)
13.1 0 dBm 0 dBm OE1 AUT J202 7C, 8C
-1.50
13.2 0 dBm 0 dBm OE2 AUT J202 7C, 8C
-1.50
13.3 0 dBm -6 dBm
4W AUT J202 7C, 8C
-7.20
Max Limit
(dBm)
+1.50
+1.50
-4.80
Commands
autEOW::_13_01
autEOW::_13_02
autEOW::_13_03
Table 4-14: Telephone Input Test.
Required Files:
UdpTclDriver.dll
EOW_SourceAll.TCL
PIUT_SourceAll.TCL
Test_13_1.TCL
Test_13_2.TCL
Test_13_3.TCL

Internal
Nera Networks AS
Page 34(58)

Rev Date
2006-08-17
Rev.
D
Document ID
15205-891763 (NG-IFU\BASIC\00173)
Internal
4.6.14 DTMF Detector and Ringing Test

Test # 14:
Insert DTMF signal generated on AUT and verify DTMF detector (on-board) using inputs:
Verify Telephone Ringing
Test #: 14.2 Other Equipment 1 with SW9 off and Loop CODEC1 near end Verify Telephone Ringing
Test #: 14.3 Other Equipment 1 with SW9 off and Loop CODEC 2 near end Verify Telephone Ringing
Test #: 14.4 4 Wire
Test #
14.1
14.2
14.3
14.4
14.5
Measure
Output
DTMF -Gen
DTMF -Gen
DTMF -Gen
DTMF -Gen
DTMF -Gen
Port
Measure Point
OE1
OE1
OE1
4W
OE2
J202
J202
J202
J202
J202
4D, 5D
4D, 5D
4D, 5D
4D, 5D
4D, 5D
Test Criteria
Commands
Telephone is Ringing
autEOW::_14_01
autEOW::_14_02
autEOW::_14_03
autEOW::_14_04
autEOW::_14_05
Table 4-15: DTMF Detector Input Test.
Required Files:
UdpTclDriver.dll
EOW_SourceAll.TCL
PIUT_SourceAll.TCL
Test_14_1.TCL
Test_14_2.TCL
Test_14_3.TCL
Test_14_4.TCL
Test_14_5.TCL

Internal
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Page 35(58)

Document ID
Rev.
Rev Date
D
15205-891763 (NG-IFU\BASIC\00173)
2006-08-17
Internal
4.6.15 Call In / Call Out Test

Test # 15:
This test shall verify that the Call In / Call Out function is working properly.
Measure ANA0 on AUT.
Test #: 15.1
Call Out ON Test

Set Call Out ON from EOW FPGA46.
Read out CALL_OUT voltage using AUT ANA0.
Expected value for Call Out On:
+2.9V
Test #: 15.2
Call Out OFF Test

Set Call Out OFF from EOW FPGA46.
Read out CALL_OUT voltage using AUT ANA0.
Expected value for Call Out OFF:
+1.0V
Test #: 15.3
Call In Test
Set Call Out ON from EOW FPGA46.
Use EOW FPGA46 to verify Call_In using telephone handset ringing.
Register MSM_CALL_INP_L is used.
Test
#
Type
Measure
Port
Measure Point
15.1
Call Out
ON
Tip/Ring
AUT ANA0
15.2
Call Out
OFF
Tip/Ring
AUT ANA0
+0.50
Test
#
15.3
Type
AUT
CALL_ANA
Voltage
AUT
CALL_ANA
Voltage
Measure
Min
Limit
(Volt)
+2.6
Max
Commands
Limit
(Volt)
+3.1 autEOW::_15_01
Port
Measure Point
Test Criteria
Commands
Call In
Telephone Ring
Call Out
J202 4D, 5D
Pass / Fail
autEOW::_15_03
+1.3
autEOW::_15_02
Table 4-16: Call In / Call Out Test.
Required Files:
UdpTclDriver.dll
EOW_SourceAll.TCL
PIUT_SourceAll.TCL
Test_15_1.TCL
Test_15_2.TCL
Test_15_3.TCL

Internal
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Page 36(58)

Rev Date
Rev.
D
2006-08-17
Document ID
15205-891763 (NG-IFU\BASIC\00173)
Internal
4.6.16 DTMF Generator Input Test (Send Star from EOW FPGA)
Test # 16:
Activate DTMF_STAR on UUT

(MSM_DTMF_STAR and MSM_DTMF_STAR_AUTO_EN)
Enable Internally Generated DTMF Generator and measure levels at:

Test #: 16.3 4 Wire
Test #: 16.4 Other Equipment 1 with CODEC 1 near end loop
Test #: 16.5 Other Equipment 1 with CODEC 2 near end loop
Test Measure Port Measure Point Min Limit
#
(dBm)
16.1 -15.5 dBm OE1 AUT J202 7C, 8C
-17.50
16.2 -15.5 dBm OE2 AUT J202 7C, 8C
-17.50
16.3 -15.5 dBm 4W AUT J202 7C, 8C
-17.50
16.4 -9.5 dBm OE1 AUT J202 7C, 8C
-11.50
16.5 -9.5 dBm OE1 AUT J202 7C, 8C
-11.50
Max Limit
(dBm)
-13.50
-13.50
-13.50
-7.50
-7.50
Commands
autEOW::_16_01
autEOW::_16_02
autEOW::_16_03
autEOW::_16_04
autEOW::_16_05
Table 4-17: DTMF Generator Input Test.
Required Files:
UdpTclDriver.dll
EOW_SourceAll.TCL
PIUT_SourceAll.TCL
Test_16_1.TCL
Test_16_2.TCL
Test_16_3.TCL
Test_16_4.TCL
Test_16_5.TCL

Internal
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Document ID
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Rev Date
D
15205-891763 (NG-IFU\BASIC\00173)
2006-08-17
Internal
4.6.17 500 Hz Generator Test

Test # 17:
This test shall verify the 500Hz Generator.

Measure 500Hz Call return signal level.
Expected value:
-18.0 dBm +/- 3.0 dBm
Enable the 500Hz Generator in the FPGA and verify output on:
Test Input Measure Port Measure Point Min Limit
#
Output
(dBm)
17.1 DTMF -17.0 dBm OE1 AUT J202 7C, 8C
-21.00
Gen.
Max Limit
(dBm)
-15.00
Commands
autEOW::_17_01
Table 4-18: 500 Hz Generator Test.
Required Files:
UdpTclDriver.dll
EOW_SourceAll.TCL
PIUT_SourceAll.TCL
Test_17_1.TCL

Internal
Nera Networks AS
Page 38(58)

Rev Date
Rev.
D
2006-08-17
Document ID
15205-891763 (NG-IFU\BASIC\00173)
Internal
4.6.18 64 kb/s Channel 1 Test

Test # 18:
This test shall verify that the 64 kb/s traffic on Channel 1 is running error free.
Insert PRBS sequence in FPGA and verify 0 errors on received data in the FPGA.
Traffic is looped in the AUT.
TCL Script parameters:
Input Parameter:
Output Parameter
Test #
18.1
Measure
G703
Measure Point
Ch 1
Test Time in Seconds

Test Pass / Fail
Test Criteria
Pass / Fail
Commands
autEOW::_18_01 $sekund
Table 4-19: 64 kb/s Channel 1 Test.
Required Files:
UdpTclDriver.dll
EOW_SourceAll.TCL
PIUT_SourceAll.TCL
Test_18_1.TCL

4.6.19 64 kb/s Channel 2 Test

Test # 19:
This test shall verify that the 64 kb/s traffic on Channel 2 is running error free.
Insert PRBS sequence in FPGA and verify 0 errors on received data in the FPGA.
Traffic is looped in the AUT.
TCL Script parameters:
Input Parameter:
Output Parameter
Test #
19.1
Measure
G703
Measure Point
Ch2
Test Time in Seconds

Test Pass / Fail
Test Criteria
Pass / Fail
Commands
autEOW::_19_01 $sekund
Table 4-20: 64 kb/s Channel 2 Test.
Required Files:
UdpTclDriver.dll
EOW_SourceAll.TCL

Internal
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Document ID
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D
15205-891763 (NG-IFU\BASIC\00173)
2006-08-17
Internal
PIUT_SourceAll.TCL
Test_19_1.TCL

4.6.20 Set Inventory

General:
Inventory data shall be written to the internal Flash in the SBC. (IC120, LPC2114)
TCL scripting over the TFTP protocol is used to communicate with the SBC.
Inventory data is passed from TestStand/LabView into a TCL script which communicates with the UUT.
All plug-in units shall have an inventory setting. The inventory is divided into a Main Inventory and a Sub
Inventory. (Up to 8 Sub-Inventories can be set for one unit.) The reason for this is to keep track of board
hardware revisions and software revisions loaded on each board.
Main Inventory:
The main inventory refers to the board Article Code and HW Revision. No software loaded on the board.
This is often referred to as the Hardware Code.
Example:
FNF5660A
R1A 91200001
2006-03-14
Sub Inventory:
This reflects the board with all software loaded. To distinguish it from the board Hardware Code, a -T is
added to the Article Code name. This is often referred to as the Total Code.
Example:
FNF5660A-T R1B 91200001
Board Marking:
The board Marker Identification Sticker will reflect the 1st Sub-Inventory. (Total Code).
Example:
FNF5660A-T R1B 91200001
Relation between Main- and Sub-Inventory (Hardware code and Total code):
The Serial Number is always the same for Main- and Sub-Inventory. This applies to all PIU boards.
The 1st sub-revision (Total Code) depends on the software and hardware revision. The relation between
the 1st sub-inventory, and the main inventory, is found in eMatrix.
Look-up Table:
A look-up table is used by the test sequence to find the correct main article code and main revision based on
the -T article code and revision combination.
The look-up table is in form of a text file named Evolution_ArtCodeConversion.txt.
This look-up table needs to be updated whenever new revisions are released. The file can be updated by Nera
or external production site.
Set the inventory data according to Table 4-21.
Test # Data to be set
Value
TCL Commands
20.1
Article code
FNF5660A
load UdpTclDriver
20.1
HW Revision
Example: R1A
SbcSetInventory FNF5660A RXX
20.1
Serial No.
Example: 91200001
20.1
Test date
[Current date in format yyyy-mm-dd] ######## yyyy-mm-dd
20.2
Total code
FNF5660A-T
load UdpTclDriver
20.2
Total Revision
Example: R1B
SbcSetExtraInventory 1 FNF5660A -T
20.2
Serial No.
Example: 91200001
RXX ########
Table 4-21: Inventory
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Rev Date
Rev.
D
2006-08-17
Document ID
15205-891763 (NG-IFU\BASIC\00173)
Internal
Required Files:
UdpTclDriver.dll
EOW_SBC_SetInventory.TCL

=> TCL script for setting EOW Inventory.
4.6.21 Get EOW SvcTel SW Info

Test # 21:
Use TCL scripting over the TFTP protocol to read SW Info from the UUT SBC. (IC120).
Transfer the data to Misc UUT Info in WATS database using file globals in TestStand.
See example below:
Read SW info according to Table 4-21.

Test #
21.1
21.1
21.1
21.1
21.1
21.1
21.1
21.1
21.1
21.1
21.1
21.1
21.1
21.1
21.1
Data to be read
SW_SBC_App_Name
SW_SBC_App_Revision
SW_SBC_App_ProgramID
SW_SBC_App_Date
SW_SBC_App_Time
SW_SBC_Boot_Name
SW_SBC_Boot_Revision
SW_SBC_Boot_ProgramID
SW_SBC_Boot_Date
SW_SBC_Boot_Time
SW_FPGA_Name
SW_ FPGA _Revision
SW_ FPGA _ProgramID
SW_ FPGA _Date
SW_ FPGA _Time
Value
SW-SBC-APP
Example: 2A01
Example: 1058
Example: 2006-06-15
Example: 12:36:06
SW-SBC-BOOT
Example: 2A01
Example: 1057
Example: 2006-06-09
Example: 16:22:45
SW-FNF5660A-FPGA46
Example: 1A00
Example: 21
Example: 2006-06-16
Example: 08:50:47
TCL Commands
load UdpTclDriver
SbcConnect 10.0.1.0
SbcGetSWVersion
Table 4-22: Get EOW SW Info
Required Files:
UdpTclDriver.dll

Internal
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Document ID
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2006-08-17
Internal
PIU_GetSWInfo.tcl
Test_21_1_Get_SvcTel_SW_Info.vi
=> TCL script for getting SW versions.

4.6.22 Verify All Inventory

Test # 22:
Use GPIB commands to control the Power Supply.

Switch Off all power to the UUT.
Wait for 3 seconds for the UUT to completely power down.
Switch On power to the UUT.
Wait for 3 seconds for the UUT to power up again.
Use TCL scripting to read out all inventory settings from the EOW SBC (IC120, LPC2114).
Read Inventory info according to Table 4-21.

Test #
22.1
22.1
22.1
22.1
22.1
22.1
22.1
Data to be read
EOW Article code
EOW HW Rev
EOW Serial No
EOW Manufacturing Date
EOW Total code
EOW Total Rev
EOW Total Serial No
Value
FNF5660A
Example: R1A
Example: 91200001
Example: 2006-07-17
FNF5660A -T
Example: R1B
Example: 91200001
TCL Commands
load UdpTclDriver
SbcConnect 10.0.1.0
SbcGetAllInventory
Table 4-23: Verify all Inventory
Required Files:
UdpTclDriver.dll
PIU_GetInventory.tcl
Test_22_1_Verify_All_Inventory.vi

=> TCL script for getting Inventory from PIU boards.
Internal
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Rev Date
2006-08-17
Rev.
D
Document ID
15205-891763 (NG-IFU\BASIC\00173)
Internal
5.
FAULT SEEKING
5.1
General
Always check the following:

Are all connections in place?
Make sure that the PIUT and AUT has SBC codes running.
Make sure that the FPGA Code on the PIUT and AUT is running.
Make sure LAN Switch is operational, (otherwise BootP server will not start).
Make sure BootP server and TFTP server are running.
Tests 4.6.9 and upwards require Svc Tel FPGA Code to be running.
Use a Golden Board to verify that the Test Station is OK.
5.1.1 Test 4.6.1 Power consumption

Current higher than Limit:
Look for shorts. Measure all secondary voltages.
Measure resistance as indicated in Chapter 4.3.2.
Current lower than Limit:
Look for missing components.
Measure all secondary voltages.
Measure resistance as indicated in Chapter 4.3.2.
5.1.2 Test 4.6.2 SBC Software Download

If problems occur on test 4.6.2 SBC Software Download, check the following:
- RS-232 Cable from PC to P6 on PIUT.
- Check if PIUT has FPGA Code loaded, H302 should be blinking slowly.
- Check IC122 25MHz Osc. R133 (0 Ohm) and C120 (56 pF)
- Check R146 (0 Ohm) ISP_EN_L, R147 (10 kOhm)
- Check IC121, R120 (100 kOhm), R138 (0 Ohm).
- Check IC124 PHY (Fast Ethernet MAC Controller).
5.1.3 Test 4.6.3 Ethernet Testing

If problems occur on test 4.6.3 Eth. Testing, check the following:
- Check Pin 2B, 3B, 5B and 6B on J500.
5.1.4 Test 4.6.4 SBC Address Detection

If problems occur on test 4.6.4 SBC Address Detection, check the following:
- Check IFU Address serial resistors; R139, R141 and R140.
- Check IFU Address Pull-Up resistors; R164, R165 and R166.
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2006-08-17
Internal
- Check Slot Address serial resistors; R142, R144, R143 and R145.
- Check Slot Address Pull-Up resistors; R167, R168, R169 and R170.
- Check IC120 Pin 12,8,4 (IFU Addr.) and Pin 2, 3 ,5 ,9 (Slot Addr.)
- If no other fault found, consider replacing IC120.
5.1.5 Test 4.6.5 Front LED Test

If problems occur on test 4.6.5 SBC Front LED Test, check the following:
- Front LED, H1.
5.1.6 Test 4.6.6 Hot Swap Test

If problems occur on test 4.6.6 Hot Swap Test, check the following:
This test is used for verifying that the Hot Swap controller is working and the connection between PIUT and
UUT. The Hot swap signal (HSWAP) is controlled from the PIUTs FPGA1 (IC300, pin 99) and can be
strapped with a jumper (P306) to 3.3 volt to set the signal high. (This strap is used in boundary scan test.)
The signal goes trough PIUTs connector J1 on pin no. 10C to the UUT. On the UUT the signal goes to the
Hot Swap controller to enable/disable the 3.3 volt to pass trough.
This test assumes that the SBC software and FPGA code are already downloaded to the PIUT and SBC
software is downloaded to the UUT.
This test is done automatically by running TCL script PIU_SBC_HotSwapTest.tcl. The scrip does the
following:
1. Verify that there is connection to UUT.
2. Set the Hot Swap signal low from the PIUT and verify that UUT powers down (not able to connect).
3. Set the Hot Swap signal high from the PIUT and verify that UUT powers up (able to connect).
If the test step fails, do the following steps:
Action Action
No
1.
Measure voltage on IC902 pin 13. Does
signal toggle when toggling HSWAP?
2.
Measure voltage on gate signal (IC902 pin 1)
when HSWAP is low. Is gate signal low?
Yes
No
Do next step
Check signal path from

PIUT to IC902.
Replace Hot Swap circuit
IC902
Replace transistor
Q902
Internal
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Rev Date
2006-08-17
Rev.
D
Document ID
15205-891763 (NG-IFU\BASIC\00173)
Internal
5.1.7 Test 4.6.7 Voltage Measurements

If problems occur on test 4.6.7 Voltage Measurements, check the following:
This test reads the secondary voltages. If the voltages are far outside the limits, other tests will most likely
also fail.
Action Action
No
1.
Measure voltage on IC120 with Multimeter.
Is measured value within limits?
+1.2V => ANA0 => Pin 11 or TP551
+2.5V => ANA1 => Pin 13 or TP552
+5.0V => ANA2 => Pin 14 or TP550
-48.0V => ANA3 => Pin 15
GND = TP554
Yes
No
SBC-ADC does not

work. Check
reference voltage on
IC120 pin 7. If
voltage is not 3.0V,
change voltage
reference G198,
otherwise change
IC120
Check voltage converters

and surrounding components
+1.2V => IC30
+2.5V => IC550
+5.0V => IC100
-48.0V => G3, G1
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Document ID
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15205-891763 (NG-IFU\BASIC\00173)
2006-08-17
Internal
5.1.8 Test 4.6.8 Download of FPGA SW using ActiveTCL environment

If problems occur on test 4.6.8 FPGA Download, check the following:
The FPGA needs to be downloaded every time you cold-boot the UUT. This is done using the TCL script
IFU_FPGA_Download.TCL that does the following:
1. Download the configuration file to the FPGA by using TFTP server.
2. Verify that the FPGA code is downloaded by writing and reading to the FPGA register.
3. Returning the FPGA version downloaded.
If the download is OK, the heartbeat-LED, H600, should be blinking approx. 1-2 Hz.
If the download fails, the LED will not blink.
Action Action
No
1.
Check if any of the H600 to H603
LEDs are on?
2.
Verify if the FPGA has been
programmed by checking DONE
signal. This signal shall be set high
when programming is OK.
Measure on R614-2
3.
Check if clock to FPGA is correct.
Clock is supplied from the PIUT.
EOW FPGA46 uses 10MHz clock.
Measure at R501-1
4.
Check secondary voltages supplied
to the FPGA.
Yes
No
Do step 4
Do step 2
Do step 3
Do step 4
Check clock
distribution
Do step 4
Do step 5
Replace suspected components in

secondary voltage distribution.
Repair short
circuit
There might be a faulty FPGA.
+1.2V => C627 Pin 1

+2.5V => R614 Pin 1
+3.3V => L600 Pin 2
5.
Voltages OK?
Check for short circuits on IC120
pin 27, 29 and 33.
5.1.9 Test 4.6.9 Power consumption after SW Download

Current higher than Limit:
Perform visual inspection and search for short circuits.
Current lower than Limit:
Make sure SBC Code and FPGA Code is running.
Perform visual inspection and search for missing components.
Internal
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Rev Date
2006-08-17
Rev.
D
Document ID
15205-891763 (NG-IFU\BASIC\00173)
Internal
5.1.10 Test 4.6.10 Other Equipment 1 Input

If problems occur on test 4.6.10 OE 1 Input, check the following:
General:
- Make sure FPGA Code has been loaded to the UUT. LED H600 should be blinking.
- Use Osc. Scope to measure OE1 Input signal in TP205 labeled OE1. Expected sinusoidal approx. 1V p-p.
- Check IC206 and surrounding components.
Test 10.1 OE1 to Tip & Ring Out:
- Check Fuse F500, expected -46.5 V.
- Check IC213 and IC260 and surrounding components.
Test 10.2 OE1 to Other Equipment 2:
- Also check switch6 (IC260) on B-side of UUT.
Test 10.3 OE1 to 4Wire +4dBm Out:
Test 10.4 OE1 to 4Wire +0dBm Out:
- If correct level, check switch3 (IC264) and R237 (27kOhm) and R238 (100 kOhm).
Test 10.5 OE1 to 4Wire -6dBm Out:
- If correct level, check switch4 (IC263) and R320 (8.2kOhm) and R319 (27 kOhm).
Test 10.6 OE1 to 4Wire -10dBm Out:
Test 10.7 OE1 to OE1 Codec 1 Near End Loop:
- Check level in TP204 labeled Codec1. Expected sinusoidal approx. 1V p-p
- If incorrect level Check IC248 (Codec1) and IC203 (Amplifier) and surrounding components.
- If ok level on TP204, then check IC205 and IC211 (OE1 output amplifiers).
Test 10.8 OE1 to OE1 Codec 2 Near End Loop:
-Check level in TP203 labeled Codec2. Expected sinusoidal approx. 1V p-p
Test 10.9 OE1 to Tip/Ring Codec 1 Near End Loop:
- If ok level on TP204, then check IC213 and IC260 (Tip/Ring output amplifiers).
Test 10.10 OE1 to Tip/Ring Codec 2 Near End Loop:
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Document ID
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15205-891763 (NG-IFU\BASIC\00173)
2006-08-17
Internal

- If ok level on TP203, then check IC213 and IC260 (Tip/Ring output amplifiers).
5.1.11 Test 4.6.11 Other Equipment 2 Input

If problems occur on test 4.6.11 OE 2 Input, check the following:
General:
- Use Osc. Scope to measure OE2 Input signal in TP202 labeled OE2. Expected sinusoidal approx. 1V p-p.
- Check IC207 and surrounding components.
Test 11.1 OE2 to Tip & Ring Out:
- Check Fuse F500, expected -46.5 V.
Test 11.2 OE2 to Other Equipment 1:
- Also check switch7 (IC226) on B-side of UUT.
Test 11.3 OE2 to 4Wire -6dBm:
Test 11.4 OE2 to Other Equipment 2 -6dBm with codec 1 Near End Loop:
Test 11.5 OE2 to Other Equipment 2 -6dBm with codec 2 Near End Loop:
5.1.12 Test 4.6.12 4Wire Input

If problems occur on test 4.6.12 4Wire Input, check the following:
General:
Test 12.1 4Wire to OE1 Out:
- Use Osc. Scope to measure 4Wire Input signal in TP201 labeled 4W. Expected sinusoidal 1V p-p.
- Check IC200 (Amplifier) and IC251 (amplifier) and surrounding components.
- Check Switch 2 (IC265) and resistors R326 (1.2k Ohm) and R325 (6.8 kOhm).
- If correct level in TP201, then check IC205 and IC211 and surrounding components.
Test 12.2 4Wire to OE2 Out:
Internal
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Rev Date
2006-08-17
Rev.
D
Document ID
15205-891763 (NG-IFU\BASIC\00173)
Internal
- Check Switch 1 (IC266) and resistors R324 (4.7k Ohm) and R323 (10 kOhm).
Test 12.3 4Wire to Telephone (Tip & Ring):
- Check Switch 0 (IC267) and resistors R385 (27k Ohm) and R329 (27 kOhm).
Test 12.4 4Wire to 4Wire with CODEC 1 Near End Loop:
- If ok level on TP204, then check IC208 and IC247 (4W output amplifiers).
Test 12.5 4Wire to 4Wire with CODEC 2 Near End Loop:
- If ok level on TP203, then check IC208 and IC247 (4W output amplifiers).
5.1.13 Test 4.6.13 Telephone Input (Tip/Ring)

If problems occur on test 4.6.13 Telephone Input, check the following:
General:
- Use Osc. Scope to measure input signal in TP206 labeled Tel. Expected sinusoidal 1V p-p.
- If incorrect level, check IC260 (Amplifier) and IC204 (Amplifier) and IC224 (Switch).
Test 13.1 Telephone Input to Other Equipment 1, CODEC 1 Near End Loop:
Test 13.2 Telephone Input to Other Equipment 2, CODEC 2 Near End Loop:
Test 13.3 Telephone Input to 4-Wire:
If correct level in TP206, then check:
- IC208 and IC247 and surrounding components.
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15205-891763 (NG-IFU\BASIC\00173)
2006-08-17
Internal
- Switch4 (IC263) and R320 (8.2kOhm) and R319 (27 kOhm).
5.1.14 Test 4.6.14 DTMF Detector and Ringing

If problems occur on test 4.6.14 DTMF Detector and Ringing, check the following:
General:
- Verify 25Hz on Pin 21 on IC260.
- Also check R397 (3.3k Ohm), Q202, R313 (100k Ohm).
Test 14.1 DTMF from AUT to Other Equipment1 and then to DTMF detector:
If no ring in telephone, check the following:
- Switch 9 (IC268) Pin4 should be High, at +3.3V
Also check R357 (10k Ohm), IC250 (Amplifier), IC232 (DTMF detector).
Test 14.2 DTMF from AUT to Other Equipment1 Codec1 Loop and then to DTMF detector:
- Switch 9 (IC268) Pin4 should be Low, at +0V
Test 14.3 DTMF from AUT to Other Equipment1 Codec2 Loop and then to DTMF detector:
- Switch 9 (IC268) Pin4 should be Low, at +0V
Test 14.4 DTMF from AUT to 4-Wire and then to DTMF detector:
- check R359 (10k Ohm), IC250 (Amplifier), IC232 (DTMF detector).
Test 14.5 DTMF from AUT to Other Equipment 2 and then to DTMF detector:
- check R258 (10k Ohm), IC250 (Amplifier), IC232 (DTMF detector).
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Rev Date
2006-08-17
Rev.
D
Document ID
15205-891763 (NG-IFU\BASIC\00173)
Internal
5.1.15 Test 4.6.15 Call In / Call Out Function

If problems occur on test 4.6.15 Call In / Call Out, check the following:
General:
Test 15.1 Call Out ON Test:
If incorrect voltage, check the following:
- R356, IC250 (Amplifier) and IC232 (DTMF detector).
- IC236 (Opto-coupler)
Test 15.2 Call Out OFF Test:
If incorrect voltage, check the following:
- R281 (1k Ohm), R354 (10k Ohm), Q200 should not be open.
- Expected approx -48V at R281.
Test 15.3 Call In Test:
- IC236 (Opto-coupler, Call Out)
- IC235 (Opto-coupler, Call In)
If OK test, then Pin 4 on IC235 should be approx 0.1V. If Not OK, the voltage will be +3.3V.
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Document ID
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D
15205-891763 (NG-IFU\BASIC\00173)
2006-08-17
Internal
5.1.16 Test 4.6.16 DTMF Generator

If problems occur on test 4.6.16 DTMF Generator, check the following:
General:
- Check IC233 (DTMF Generator) and IC212 (Amplifier) and surrounding components.
- Use TP207 to measure DTMF signal using Osc. Scope, expected 0.3V p-p.
Test 16.1 Generate DTMF from EOW and measure OE1 level:
Expected -15.5 dBm, if incorrect level, check the following:
- R352 (10k Ohm)
Test 16.2 Generate DTMF from EOW and measure OE2 level:
- R287 (10k Ohm)
Test 16.3 Generate DTMF from EOW and measure 4-Wire level:
- R300 (10k Ohm) and R294 (10k Ohm)
Test 16.4 Generate DTMF from EOW and measure level at OE1 with CODEC1 Loop:
- R239 (10k Ohm) and R352 (10k Ohm)
Test 16.4 Generate DTMF from EOW and measure level at OE1 with CODEC2 Loop:
- R340 (10k Ohm) and R352 (10k Ohm)
5.1.17 Test 4.6.17 500 Hz Generator

If problems occur on test 4.6.17 500 Hz Generator, check the following:
General:
- The 500Hz is generated inside the FPGA and routed similar to DTMF generator.
Test 17.1 Generate 500Hz from EOW and measure OE1 level:
- C227 (100n F), R211 (10k Ohm), C230 (1uF), R260 (10k Ohm).
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Rev Date
2006-08-17
Rev.
D
Document ID
15205-891763 (NG-IFU\BASIC\00173)
Internal
5.1.18 Test 4.6.18 64 kb/s Channel 1

If problems occur on test 4.6.18 64 kb/s Ch1, check the following:
General:
- IC202 (Inverter), T201 (Transformer), IC201 (Line Receiver).
5.1.19 Test 4.6.19 64 kb/s Channel 2

If problems occur on test 4.6.19 64 kb/s Ch2, check the following:
General:
- IC202 (Inverter), T200 (Transformer), IC201 (Line Receiver).
5.1.20 Test 4.6.20 Set Inventory

If problems occur on test 4.6.20 Set Inventory, check the following:
- Verify correct information in the Evolution_ArtCodeConvertion.txt file.
5.1.21 Test 4.6.21 Get EOW SvcTel SW Info

If problems occur on test 4.6.21 Get EOW SvcTel SW Info, check the following:
This test should not fail (after pass on all previous tests). Verify test set-up.
5.1.22 Test 4.6.22 Verify All Inventory

If problems occur on test 4.6.22 Verify All Inventory, check the following:
This test should not fail (after pass on all previous tests). Verify test set-up.
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D
15205-891763 (NG-IFU\BASIC\00173)
2006-08-17
Internal
6.
TEST STATION MAINTENANCE
6.1
General
Always have a known good UUT board (Golden Board) available.

This is useful in determining if faults are related to UUT or Test Station.
6.2
Maintenance schedule for the PIUT (K-7295) Test Jig
The PIUT Test Jig consists of the following parts:

- Mechanical Fixture
- PIUT Test Board ET5157A
- Connection board ET5162A
- Various cables.
The 55-pin and 95-pin connector on the ET5162A will be worn and eventually fail.
The manufacturer guarantees >500 matings for these connectors.
Experience shows that actual life-span is in excess of 5000 matings.
The following maintenance guidelines are given for the PIUT Test Jig:
1. A pre-configured and tested ET5157A board should always be available.
2. Upon failure or after 5000 tested UUTs the ET5162A connection board shall be replaced.
6.3
Maintenance schedule for the AUT (K-7346) Test Jig
The PIUT Test Jig consists of the following parts:

- Mechanical Fixture
- AUT Test Board ET5189A
- 4 RJ45 (Twisted pair TP) cables.
The RJ-45 Connectors and the RJ45 cables will eventually be worn.
The following maintenance guidelines are given for the AUT Test Jig:
1. A pre-configured and tested ET5189A board should always be available.
2. After 5000 manufactured boards, the RJ45 cables shall be replaced.
3. Upon failure the RJ45 connectors shall be replaced.
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2006-08-17
Rev.
D
Document ID
15205-891763 (NG-IFU\BASIC\00173)
Internal
7.
APPENDIX
Various design information.
7.1
Boot Screen
The picture below shows a successful cold boot seen from HyperTerminal.
Figure 7-4 Boot Screen of the IFU SVCTEL FNF5660A
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Document ID
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D
15205-891763 (NG-IFU\BASIC\00173)
2006-08-17
Internal
7.2
JTAG overview
BS Chain EOW / SvcTel

+3.3V
+3.3V
R171
R154 R153 R152 R149
3A
MC
SBC_FPGA$1I3SBC_TDI
60
R504
51
R505
51
SLTTMS
SLTTCK
SLTTRST_L
2
R506
100
10k
4A
R121
100
10k
5A
SBC_TDI
10k
6A
10k
10k
J500
SBC_TMS
Philips
LPC2114
52
SBC_TCK
56
SBC_TRST_L
87G33A
LPC2114
20
64
SBC_FPGA
$1I3SBC_TDO
IC120
1
100
R128
FPGA
R502
100
Xilinx
XC3S200_TQ144
FPGA_TMS
R503
2
2A
FPGA_TDO
1
100
111
XC3S200_87G18
FPGA_TCK
110
R629
22
SBC_FPGA$1I4TDO_FPGA
109
144
SBC_FPGASBC_TDO
IC601
Note:
IC120 is not compliant with IEEE 1149.1 with regard to Boundary Scan
Testing, it does not support the EXTEST function.
File: BS_Chain_SvcTel_PA2.vsd
Last Update: 15.03.2006
Figure 7-2 JTAG chain
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Rev Date
2006-08-17
Rev.
D
Document ID
15205-891763 (NG-IFU\BASIC\00173)
Internal
7.3
Configuration of Secondary Network Card in Test PC
The secondary LAN Board is used for communication with the EOW SvcTel and the PIUT Test Jig.
It is connected to a LAN Switch and then to the above equipment.
The board should be configured as shown below:
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Document ID
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D
15205-891763 (NG-IFU\BASIC\00173)
2006-08-17
Internal
Internal
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Page 58(58)

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Utrm SVC Tel Fnf5660a Rev D

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Unit Test Requirement, Manufacturing

EOW_Service Telephone Auxiliary Unit, FNF5660A

TEST STATION DESCRIPTION.....................................................................................12

Unit Test Requirement, Manufacturing

TEST STATION MAINTENANCE....................................................................................54

Nera Company Standards on Notes, FS0170-M30, Rev. A

Unit Test Requirement, Manufacturing

Nera Company Standards on Notes, FS0170-M30, Rev. A

Unit Test Requirement, Manufacturing

Purpose and scope

[6] In e-Matrix, object K-7346

AUT Test Jig (Based on ET5189A)

Table 1-1: References

Nera Company Standards on Notes, FS0170-M30, Rev. A

Unit Test Requirement, Manufacturing

Terminology and abbreviations

Table 1-2: Terminology and abbreviations

Nera Company Standards on Notes, FS0170-M30, Rev. A

Unit Test Requirement, Manufacturing

Nera Company Standards on Notes, FS0170-M30, Rev. A

Unit Test Requirement, Manufacturing

Figure 2-1: Block schematic

Nera Company Standards on Notes, FS0170-M30, Rev. A

Unit Test Requirement, Manufacturing

2.1.1 Service Telephone Auxiliary Unit

Figure 2-2: Service Telephone Board Component Layout

Connections on front edge of

Nera Company Standards on Notes, FS0170-M30, Rev. A

Unit Test Requirement, Manufacturing

Figure 2-3: Auxiliary Units front view

Table 2-3 Pinning of Svc Tel 4 x 8-Pin connector J200

Nera Company Standards on Notes, FS0170-M30, Rev. A

Unit Test Requirement, Manufacturing

2.1.3 Rear Connection, J500

Table 2-2 Pinning of SvcTel 95-Pin connector J500

Yellow shaded cells

BST Nets=50 (Incl. 39 NC)

Figure 2-4 J500 Physical Pin Layout

Nera Company Standards on Notes, FS0170-M30, Rev. A

Unit Test Requirement, Manufacturing

2.2.1 Download of Application SW to the Svc Tel

Visual control of Application software using LEDs:

2.2.2 Download of FPGA SW to the Svc Tel

Visual control of FPGA software using LED:

2.2.3 Download of Application SW to the AUT and PIUT Test Jigs

Visual control of Application software using LEDs:

2.2.4 Download of FPGA SW to the PIUT Test Jig, K-7295 (ET-5157A)

Visual control of PIUT FPGA software using LED:

2.2.5 Download of FPGA SW to the AUT Test Jig, K-7346 (ET-5189A)

Visual control of AUT FPGA software using LED:

Nera Company Standards on Notes, FS0170-M30, Rev. A

Unit Test Requirement, Manufacturing

TEST STATION DESCRIPTION

Test Station overview

48V Power Supply

PIUT Test Jig K-7295

Figure 3-3 Svc Tel Test Station overview

Test Jig overview

Two test jigs will be used to test the UUT:

Nera Company Standards on Notes, FS0170-M30, Rev. A

Unit Test Requirement, Manufacturing

PIUT Test Jig, K-7295