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Generate VHDL Code from Matlab Code

This post shows how easy it is to generate VHDL code from Matlab HDL coder. This example shows how easy it is to
convert a simple mux designed in matlab into VHDL using Matlab HDL coder. The matlab generated mux vhdl code is
then test to confirm the correctness of the code.
Consider the mux function created in Matlab as followsfunction [y] = mux(sel, x1, x2, x3, x4)
if sel == 00
y = x1;
elseif sel == 01
y = x2;
elseif sel ==10
y =x3;
else
y = x4;
end
end
The code is self explanatory, when sel is 00 then y is x1, when sel is 01 then y is x2, when sel is 10 then y is x3 and when sel is 11 then y is x4.
We need also to create a testbench code also in matlab for the above mux function. This matlab code function is shown below,
clear all;
x1 = 0001;
x2 = 0010;
x3 = 0100;
x4 = 1000;
sel(1) = 00;
sel(2) = 01;
sel(3) = 10;
sel(4) = 11;
for k = 1:4;
[y(k)] = mux(sel(k), x1, x2, x3, x4);
end
Now, this is all required for coding in matlab.
Next to generate the VHDL code(or verilog if you like), click on the HDL Coder which is in the application panel in the toolbar.
This brings up a HDL Generation Code window, like the following, which allows you to add the mux m-code and the testbench codes created earlier.

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Then just add the mux and testbench matlab files(.m files) using the Add MATLAB function and Add files button that you see in the above screenshot.
After adding the files, the screen looks like the following-

Then click on the Workflow Adviser button at the end of the window. This brings up the following window-

This is nothing but a process flow of converting the matlab code to hdl code. It is a series of steps.
The first thing is to just click on Run button.

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The next step is the Fixed-Point Conversion step. This is more important step. Here the matlab tries to get best suitable conversion type. Now here you have to decide whether
the converted numeric type is alright or not.
First Run the Simulation, then check the Proposed Type and if you are happy and satisfied then click on the Validate Type button.

The next step is to select the FPGA design software and the targeted device. Since this tutorial is not on synthesis but only on generation of HDL code, we will not use this
option. However if you wish to see this process follow the tutorial - Quick Guide Steps for using Matlab HDL coder with Xilinx ISE
Now moving to next step, we come to HDL Code Generation step. This is important and there are many options you can select and configure how to generate hdl code,
options like clock type, reset, function block generation are available to you according to your requirement. For example in the optimization tab, there is an option called
Generate Matlab Function Block under in the Simulink Integration section, select this if you want as was done here.
After reviewing options click on the Run button.

The outputs generated in this step is shown in the report window. Here mux_fixpt.vhd the VHDL code of the mux, resource utilization report was generated. Also another thing
that was generated is the Simulink Function Block that we had opted. This is shown below-

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It's nice to have this, since this can design can be tested in the simulink as well. Test bench around this block can be created to test the mux.
The HDL code that we were interested in is as followsLIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY mux_fixpt IS
PORT( clk
reset
clk_enable
sel
x1
x2
x3
x4
ce_out
y
);
END mux_fixpt;

: IN std_logic;
: IN std_logic;
: IN std_logic;
: IN std_logic_vector(1 DOWNTO 0); -- ufix2
: IN std_logic_vector(3 DOWNTO 0); -- ufix4
: IN std_logic_vector(3 DOWNTO 0); -- ufix4
: IN std_logic_vector(3 DOWNTO 0); -- ufix4
: IN std_logic_vector(3 DOWNTO 0); -- ufix4
: OUT std_logic;
: OUT std_logic_vector(3 DOWNTO 0) -- ufix4

ARCHITECTURE rtl OF mux_fixpt IS

-- Signals
SIGNAL enb
SIGNAL sel_unsigned
SIGNAL x1_unsigned
SIGNAL x2_unsigned
SIGNAL x3_unsigned
SIGNAL x4_unsigned
SIGNAL y_tmp

: std_logic;
: unsigned(1 DOWNTO 0); -- ufix2
: unsigned(3 DOWNTO 0); -- ufix4
: unsigned(3 DOWNTO 0); -- ufix4
: unsigned(3 DOWNTO 0); -- ufix4
: unsigned(3 DOWNTO 0); -- ufix4
: unsigned(3 DOWNTO 0); -- ufix4

BEGIN
sel_unsigned <= unsigned(sel);
x1_unsigned <= unsigned(x1);
x2_unsigned <= unsigned(x2);
x3_unsigned <= unsigned(x3);
x4_unsigned <= unsigned(x4);
enb <= clk_enable;
mux_fixpt_1_output : PROCESS (sel_unsigned, x1_unsigned, x2_unsigned, x4_unsigned)
BEGIN
--HDL code generation from MATLAB function: mux_fixpt
IF sel_unsigned = 1 THEN
y_tmp <= x2_unsigned;
ELSE
y_tmp <= x4_unsigned;
END IF;

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IF sel_unsigned = 0 THEN
y_tmp <= x1_unsigned;
END IF;
END PROCESS mux_fixpt_1_output;

y <= std_logic_vector(y_tmp);
ce_out <= clk_enable;
END rtl;
There were some comments generated by this process, which have been deleted in order to make this code readable.
Now we can move the mux VHDL code generated by matlab and test in other simulator like Xilinx or modelsim.
What follows next has nothing to do with Matlab HDL coder, the mux VHDL code was simply imported into FPGA simulator software and testbench was created to verify the
output of the matlab mux vhdl code.
The testbench used to test this mux is as followslibrary ieee;
use ieee.NUMERIC_STD.all;
use ieee.std_logic_1164.all;
entity mux_fixpt_tb is
end mux_fixpt_tb;
architecture TB_ARCHITECTURE of mux_fixpt_tb is
component mux_fixpt
port(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
clk_enable : in STD_LOGIC;
sel : in STD_LOGIC_VECTOR(1 downto 0);
x1 : in STD_LOGIC_VECTOR(3 downto 0);
x2 : in STD_LOGIC_VECTOR(3 downto 0);
x3 : in STD_LOGIC_VECTOR(3 downto 0);
x4 : in STD_LOGIC_VECTOR(3 downto 0);
ce_out : out STD_LOGIC;
y : out STD_LOGIC_VECTOR(3 downto 0) );
end component;
signal clk : STD_LOGIC;
signal reset : STD_LOGIC;
signal clk_enable : STD_LOGIC;
signal sel : STD_LOGIC_VECTOR(1 downto 0);
signal x1 : STD_LOGIC_VECTOR(3 downto 0) := "0001";
signal x2 : STD_LOGIC_VECTOR(3 downto 0):= "0010";
signal x3 : STD_LOGIC_VECTOR(3 downto 0):= "0100";
signal x4 : STD_LOGIC_VECTOR(3 downto 0):= "1000";
signal ce_out : STD_LOGIC;
signal y : STD_LOGIC_VECTOR(3 downto 0);
begin
UUT : mux_fixpt
port map (
clk => clk,
reset => reset,
clk_enable => clk_enable,
sel => sel,
x1 => x1,
x2 => x2,
x3 => x3,
x4 => x4,
ce_out => ce_out,
y => y
);

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CLK_GEN: process(CLK)
begin
CLK<= not CLK after 5 ns;
end process;
sti : process
begin
sel <= "00";
wait for 10 ns;
sel <= "10";
wait for 10 ns;
sel <= "01";
wait for 10 ns;
sel <= "11";
wait for 10 ns;
end process;

end TB_ARCHITECTURE;
configuration TESTBENCH_FOR_mux_fixpt of mux_fixpt_tb is
for TB_ARCHITECTURE
for UUT : mux_fixpt
use entity work.mux_fixpt(rtl);
end for;
end for;
end TESTBENCH_FOR_mux_fixpt;

The testbench is a simple testbench, wherein, stimuli signal sel is feed as 01, 01, 10 and 11. The Mux vhdl code generated by matlab has various clock, reset and so on
inputs other than the main data input x. Those ports were not used in above testbench.
Now if we stimulate the design we get the following waveform.

The waveform shows that the matlab generated VHDL code is correct. For consecutive sel inputs combination we get the desired result y as 0001, 1000,0010 and 1000 where
were defined as x1, x2, x3 and x4 in the testbench.

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Serial to parallel C program for

shift register
8051 for
VHDL code
toggling port bit
using Timer 0

Analysis and
Synthesis of
Combinational
Circuit using
VHDL software

How to use
Xilinx VHDL
Software with 2
to 4 decoder
VHDL code
example

Learning VHDL
using VHDL
Software |
Register
Transfer Level

4 to 1
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