ATmega328 Watchdog Timer Interrupt

http://playground.arduino.com/Code/Timer1
http://www.gammon.com.au/forum/?id=11497
http://donalmorrissey.blogspot.com/2010/04/putting-arduino-diecimila-to-sleeppart.html
When the ATmega328 enters sleep mode, the execution of the code pauses at a
certain point and will resume only after it is woken from sleep by one of its internal
hardware modules, e.g. timer expiring, external interrupt, WDT, etc.
ATmega328 16-bit Timer1
Clock source frequency:
Timer1 prescale values:
Prescale
1
8
64
256
1024

16 MHz
1, 8, 64, 256 or 1024
Timer per counter tick
(S)
0.0625
0.5
4
16
64

Max Period (ms)

8.192
65.536
524.288
2097.152
8388.608

ATmega328 Watchdog Timer

Clocked from separate on-chip oscillator (128 kHz)

3 operating modes: interrupt, system reset and interrupt & system reset.
Selectable time-out period from 16ms to 8s
Possible hardware fuse watchdog always on (WDTON) for fail-safe mode

The sequence for clearing WDE and chaning time-out configuration is as follows:
1. In the same operation, write a logic one to the Watchdog change enable bit
(WDCE) and WDE. A logic one must be written to WDE regardless of te
previous value of the WDE bit.
2. Within the next four clock cycles, write the WDE and Watchdog prescaler bits
(WDP) as desired, but with the WDCE bit cleared. This must be done in one
operation.
WDTCSR Watchdog Timer Control Register

Bit 7 WDIF: Watchdog Interrupt Flag

This bit is set when a time-out occurs in the Watchdog Timer and the
Watchdog Timer is configured for interrupt.

Bit 6 WDIE: Watchdog Interrupt Enable

When this bit is written to one and the I-bit in the Status Register is set, the
Watchdog Interrupt is enabled.

Bit 4 WDCE: Watchdog Change Enable

This bit is uded in timed sequences for changing WDE and prescaler bits. To
clear the WDE bit, and/or change the prescaler bits, WDCE must be set. Once
written to one, hardware will clear WDCE after four clock cycles.

Bit 3 WDE: Watchdog System Reset Enable

Bit 5, 2..0 WDP3..0: Watchdog Timer Prescaler 3, 2, 1 and 0.

ATmega328 Power Management and Sleep Modes

Power-down Mode. In this mode, the external Oscillator is stopped, while the
external interrupts, the 2-wire Serial Interface address watch, and the Watchdog
continue operating (if enabled). This sleep mode basically halts all generated clocks,
allowing operation of asynchronous modules only.
When waking up from Power-down mode, there is a delay from the wake-up
condition occurs until the wake-up becomes effective. This allows the clock to
restart and become stable after having been stopped.

Power Reduction Register

PRR provides a method to stop the clock to individual peripherals to reduce power
consumption. The current state of the peripheral is frozen and I/O registers cannot
be read nor written.

Minimizing Power Consumption

1.
2.
3.
4.

Analog to Digital Converter

Analog Comparator
Brown-out Detector
Port Pins