4/9/2014

VLSI DESIGN
UNIT-1
LECTURE-2

Basic MOS Transistor

nMOS enhancement mode Transistor

nMOS depletion mode Transistor

MOS transistors when Vds=0V Source

Vgs,Vsb=0V

4/9/2014

Action of enhancement mode transistor action(nMOS)

Source and drain regions are formed by doping desired n-impurity
concentration.
Source and drain are separated by two back to back connected diodes
hence electrons flows from source to drain. Depletion region surrounds
around source and drain junctions as they are reverse biased.
Gate oxide (Sio2) is grown above substrate between source and drain
while polysilicon/metal is deposited over it.
Channel is not formed when gate voltage is not applied(Vgs=0V)
There are two electric fields in the transistor ,vertical from gate to
substrate due to Vgs, horizontal from drain to source due to Vds.

nMOS depletion mode MOSFET

Transistor is normally ON.
The ntype impurities are buried in
the channel area.

When Vgs=0V, Vd>0 V current flows in the transistor.

When Vgs<0V, the current decreases towards OFF state as the electrons
repel away from the surface creating depletion region. The channel
disappers gradually.
For Vg>0V the depletion MOSFET acts as enhancement MOSFET.

4/9/2014

Vgs> 0V ,Vds= 0V

When positive gate voltage is

applied the positive voltage on
the

gate

plate

attracts

the

minority carriers (electrons) from

the substrate.
This also uncovers the positive ions
near

the

surface

forming

depletion region .
At a particular gate voltage the number of electrons near the surface
become equal to the doping concentration of the substrate. The surface
inverts to n-type. This voltage is known as Threshold Voltage (Vth).
A uniform channel is formed near the surface at threshold voltage(Vgs=Vth)

When Vgs>Vth and Vds<Vgs-Vth

No current flows in transistor until Vds>0V)
Current flows from drain to source as
electrons move through the channel
under the influence of the horizontal
electric field as well as vertical electric
field.
There is voltage drop in the channel due to VDS varying with distance,
(more near the drain end).
Effective gate voltage is Vg=Vgs-Vth.There will be no voltage available to
invert the channel at the drain end so long as Vgs-Vth>=Vds.

4/9/2014

The limiting condition comes when Vgs-Vth=Vds

For all voltages Vds<Vgs-Vth the transistor is in non-saturated region of
operation.

As

the

effective

voltage

is

insufficient to invert the surface

near the drain end the channel
starts to pinch off.
As the Vds is further increased
the

pinch

off

point

moves

towards the source.

Eventhough there is no channel
the constant electric field in the
Depletion region makes charge carriers to move with constant veltocity making
Current constant