EE201: Digital Circuits and Systems

EE201:

1 Combinatorial Logic

page 1 of 30

Digital Circuits and Systems

Section 1 - Combinatorial Logic

1.1 Encoders:
Definition
An encoder produces a digital code which
depends on which one of its input is activated

I0
I1
I2

Enc

IM

O0
O1

ON-1

Only one of M inputs is activated at a time

Encoder outputs a N-bit output code
Always: 2N M

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Example
4-Line to Binary Encoder:
o 4 inputs
o 2 outputs

A
B
C
D

Enc

Y
X

A
1
0
0
0

Inputs
B C
0 0
1 0
0 1
0 0

D
0
0
0
1

Outputs
Y
X
0
0
0
1
1
0
1
1

The logic diagram can be generated using

formal methods:

Y
AB/CD0001111000X1X1010XXX11XXXX100XXX

Y=D+C
Similarly:

X=D+B

EE201: Digital Circuits and Systems

1 Combinatorial Logic

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A
X

B
C

D
Application
Decimal to BCD Encoder:
S0

o 10 inputs
o 4 outputs

B0

Enc

S1

B3

S9

S0
1
0
0
0
0
0
0
0
0
0

S1
0
1
0
0
0
0
0
0
0
0

S2
0
0
1
0
0
0
0
0
0
0

S3
0
0
0
1
0
0
0
0
0
0

S4
0
0
0
0
1
0
0
0
0
0

S5
0
0
0
0
0
1
0
0
0
0

S6
0
0
0
0
0
0
1
0
0
0

S7
0
0
0
0
0
0
0
1
0
0

S8
0
0
0
0
0
0
0
0
1
0

S 9 B0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 1
1 1

B1
0
0
0
0
1
1
1
1
0
0

B2
0
0
1
1
0
0
1
1
0
0

B3
0
1
0
1
0
1
0
1
0
1

EE201: Digital Circuits and Systems

1 Combinatorial Logic

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1.2 Decoders:
Definition
An decoder activates only one of its outputs
depending on the binary code provided as input

I0

Dec

I1

IN-1

O0
O1
O2

OM-1

Decoder receives a N-bit input code

Only one of M outputs is activated at a time
Always: 2N M

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Example
Binary to 4-Line Decoder:
o 2 inputs
o 4 outputs

Dec

X
Y

A
B
C
D

Inputs
X Y
0 0
0 1
1 0
1 1

A
1
0
0
0

Outputs
B
C
0
0
1
0
0
1
0
0

D
0
0
0
1

The logic diagram can be generated using

formal methods:

A
X/Y01010100

_ _
_
A = X Y,B = X Y,C = X Y,

_
D=XY

EE201: Digital Circuits and Systems

1 Combinatorial Logic

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Implementation
X

Y
B

Application 1
BCD to Decimal Decoder:
o 4 inputs
o 10 outputs

B0
B1
B2
B3

Dec

S0
S9

EE201: Digital Circuits and Systems

B0
0
0
0
0
0
0
0
0
1
1

Inputs
B1 B2
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
0 0
0 0

B3
0
1
0
1
0
1
0
1
0
1

1 Combinatorial Logic

S0
1
0
0
0
0
0
0
0
0
0

S1
0
1
0
0
0
0
0
0
0
0

S2
0
0
1
0
0
0
0
0
0
0

Outputs
S3 S4 S5 S6
0 0 0 0
0 0 0 0
0 0 0 0
1 0 0 0
0 1 0 0
0 0 1 0
0 0 0 1
0 0 0 0
0 0 0 0
0 0 0 0

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S7
0
0
0
0
0
0
0
1
0
0

S8
0
0
0
0
0
0
0
0
1
0

S9
0
0
0
0
0
0
0
0
0
1

S0
B0B1/B2 B30001111000100001000011XXXX1000XX

S 0 B0 B1 B 2 B3

S 5 B1 B2 B3

S1 B0 B1 B2 B3

S 6 B1 B2 B3

S 2 B1 B 2 B3

S 7 B1 B2 B3

S 3 B1 B2 B3

S 8 B0 B3

S 4 B1 B 2 B3

S 9 B0 B3

Implementation

EE201: Digital Circuits and Systems

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So
B0
S1
B1

B2

S2
S3
S4

B3

S5
S6
S7
S8
S9

EE201: Digital Circuits and Systems

1 Combinatorial Logic

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Application 2
BCD to 7-segment Decoder:

a
b
c
d
e
f
g

Dec

B
C
D

f
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

No.
0
1
2
3
4
5
6
7
8
9
X
X
X
X
X
X

Segments
a, b, d, e, f, g
b, g
a, b, c, e, f
a, b, c, f, g
b, c, d, g
a, c, d, f, g
a, c, d, e, f, g
a, b, g
a, b, c, d, e, f, g
a, b, c, d, f, g
-

EE201: Digital Circuits and Systems

1 Combinatorial Logic

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Horizontal segments: a, c, f
a
c
f

=>
=>
=>

0, 2, 3, 5, 6, 7, 8, 9
2, 3, 4, 5, 6, 8, 9
0, 2, 3, 5, 6, 8, 9

Minimisation

a
AB/CD

00

00
01
11
10

1
0
X
1

01
0
1
X
1

11

10

1
1
X
X

1
1
X
X

11

10

1
0
X
X

1
1
X
X

Equation
a A C BD B D

Minimisation

c
AB/CD

00

00
01
11
10

0
1
X
1

01
0
1
X
1

EE201: Digital Circuits and Systems

1 Combinatorial Logic

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Equation
c A BC C D BC

Minimisation

f
AB/CD

00

00
01
11
10

1
0
X
1

01
0
1
X
1

11

10

1
0
X
X

1
1
X
X

Whats missing?
Equation
f A BC D C D BC B D

Implementation (a segment)

B
C
D
Implementation (with NAND gates)

EE201: Digital Circuits and Systems

1 Combinatorial Logic

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a A C BD B D

a a A C BD B D A C BD B D

A
B
C
D

EE201: Digital Circuits and Systems

1 Combinatorial Logic

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1.3 Multiplexers:
Definition
A multiplexer selects one of its inputs to direct to
the output depending on the binary code
provided at the select inputs

Mux

I0
I1

IN-1

S0 S1

SM

Multiplexer receives a M-bit selection code

Only one of N inputs is directed at the output
Always: 2M = N

EE201: Digital Circuits and Systems

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Example 1
Two-channel Multiplexer
o 2 inputs
o 1 select input
o 1 output

Mux
Z

Inputs
A B
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1

Select
S
0
1
0
1
0
1
0
1

Output
Z
0
0
0
1
1
0
1
1

The logic diagram

can be generated using formal methods and

minimising, it results:

_
Z =AS + B S
Implementation???

EE201: Digital Circuits and Systems

1 Combinatorial Logic

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Example 2
Two-channel two-bit Multiplexer
o 4 inputs
o 1 select input
o 2 outputs
A0
A1

Mux

Z0
Z1

B0
B1

Select
S
0
1

Output
Z1
A1
B1

S
After minimisation, results:

_
Z0 = A0 S + B0 S

_
Z1 = A1 S + B1 S

Implementation

A0
A1
B0
B1

2-channel
MUX

2-channel
MUX

Z0

Z1

Z0
A0
B0

EE201: Digital Circuits and Systems

1 Combinatorial Logic

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Homework: implementation using gates!

Example 3
Four-channel Multiplexer
o 4 inputs
o 2 select input
o 1 output
I0

Mux

I1

I2
I3
S0

S1
0
0
1
1

S0
0
1
0
1

Z1
I0
I1
I2
I3

S1

We have:

_ _
_
_
Z = I0 S1 S0 + I1 S1 S0 + I2 S1 S0 + I3 S1 S0

Implementation
I0
____

S1
____

S0
I1
____

S1
S0
I2
S1
____

S0
I3
S1
S0

Z0

EE201: Digital Circuits and Systems

1 Combinatorial Logic

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Homework: implementation with 2-channel MUX

Example 4
Eight-channel Multiplexer
o 8 inputs
o 3 select input
o 1 output
I0

Mux

I1

I6
I7

S0

S1

S2

S2
0
0
0
0
1
1
1
1

S1
0
0
1
1
0
0
1
1

S0
0
1
0
1
0
1
0
1

Z1
I0
I1
I2
I3
I4
I5
I6
I7

We have:

_ _ _
_ _
Z = I0 S2 S1 S0 + I1 S2 S1 S0 + + I7 S2 S1 S0
Homework: implementation with 2-channel MUX
Homework: implementation with logic gates

Applications

EE201: Digital Circuits and Systems

1 Combinatorial Logic

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Data selection, data routing, parallel to serial

conversion, waveform generation, logic function
generation, etc.

EE201: Digital Circuits and Systems

1 Combinatorial Logic

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Application 1
Parallel to serial conversion:
o
o
o
o
o
o

4 inputs
1 output
4-bit Register
2-bit Counter
4-channel Mux
1 serial line

X0
4:1 line
MUX

X1
X2

Serial
line

X3

S1

Clock

S2

2-bit
Counter

The Register contains parallel data

2-bit Counter generates S1 and S2

EE201: Digital Circuits and Systems

1 Combinatorial Logic

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At every Clock, a different input of the 4:1 line

Mux is outputted on the Serial line: X0, X1, X2, X3

EE201: Digital Circuits and Systems

1 Combinatorial Logic

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Application 2
Logic function generator:
E.g. 1
o Original function:
F ABC ABC AB

o Full form:
F A B C A B (0) A B C A B (1)

o 4-channel Multiplexer:
Z S1 S 2 I 0 S1 S 2 I1 S1 S 2 I 2 S1 S 2 I 3

o Matching data and select inputs:

C
0

4:1 line
MUX

_
C
1

S1

S2

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1 Combinatorial Logic

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Notes:
o There are other ways of implementing the

same function by matching different input

variables on the select inputs of the MUX
o In general the number of select lines needed

is equal to the number of input variables

minus 1 (there are also exceptions: see next)
Homework:
o Implement F in another way using 4-channel

MUX
o Implement F using 2-channel MUX
o Implement F using logic gates
o Implement F using NAND logic gates

EE201: Digital Circuits and Systems

1 Combinatorial Logic

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E. g. 2
o Original function:
F ABC AB D AB E

o Partial form:
F A B C A B D A B ( 0) A B E

o 4-channel Multiplexer:
Z S1 S 2 I 0 S1 S 2 I1 S1 S 2 I 2 S1 S 2 I 3

o Matching data and select inputs:

C
_
D

4:1 line
MUX

_
E

S1

S2

o Note: normal implementation would have

required a 16-channel MUX

E. g. 3

EE201: Digital Circuits and Systems

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o Original function:
F v w x y z v w x yz v w x y z v w x y z
vwx y zvwx y zvwx y zvwx y z
vwx y zvwx y zvwx y zvwx y z

o Implement F using 16-channel MUX

0
v
v
v
1

16 Channel
MUX

v
1
v
0
0

v
0
v
0
v
0

S1

S2

S3

S4

o Factorised function:
F (v w x v w x v w x ) y z
(v w x v w x ) y z
(v w x v w x v w x v w v w x ) y z
(v w x v w x ) y z

EE201: Digital Circuits and Systems

1 Combinatorial Logic

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F ( F1 ) y z ( F2 ) y z ( F3 ) y z ( F2 ) y z

o Implement F using 4-channel MUX

0
1
0

4
Channel
MUX

S1

S2

v
v
0
0

4
Channel
MUX
S1

S2

4
Channel
MUX

S1

S2

F1

F2

4
Channel
MUX
S1

S2

F3

Can you reduce it further if you had 2-ch MUX?

1.4 Demultiplexers:
O0

Definition
O1

DMUX its input to one of the

A demultiplexer transfers
outputs depending on the binary code provided at
the select inputs
ON-1

S0 S1

SM-1

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1 Combinatorial Logic

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Demultiplexer receives a M-bit selection code

The input is directed to one of the N outputs
Always: 2M = N

Example 1
Two-channel Demultiplexer
o 1 input
o 1 select input

EE201: Digital Circuits and Systems

1 Combinatorial Logic

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o 2 outputs

O0

O1

DMUX

O0
O1

S
o implementation using logic gates

O0

O1
S

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1 Combinatorial Logic

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Example 2
Eight-channel Demultiplexer
o 1 input
o 3 select inputs
o 8 output
I
S0
S1

O0

O1

S2
O2

O3

O4

O5

O6

O7

EE201: Digital Circuits and Systems

1 Combinatorial Logic

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Application

4-bit/4-word Serial Data Transmission System:

A
B

4:1
line
MUX

Serial line

D
S1

Mod-8
Counter

S2

Mod-4
Counter

Clock (16 pulses)

1:4
line
DMUX

S1

Mod-8
Counter

Is Mod-8 Counter correct?

S2

Mod-4
Counter

Serial line

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1 Combinatorial Logic

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The circuit serially transmits four 4-bit words stored

in registers A, B, C and D to registers W, X, Y and
Z
Initially all Counters are RESET to 0
16 clock pulses are applied on the Clock line
First clock determines such a select input
combination at MUX that the first bit from register
A is outputted to the serial line
The same clock determines such a select input
combination at DMUX that the incoming bit on the
serial line will be directed and stored in register W
Next clock triggers the transmission of bit 2 from
register A and its storage in bit 2 of register W, etc.
Each clock determines a SHIFT of bits in the
registers
Therefore clock five determines the transmission
of bit two from register B and its storage into bit
two of register X, etc.