This article has been accepted for publication in a future issue of this journal, but has not been

fully edited. Content may change prior to final publication. Citation information: DOI
10.1109/JESTPE.2015.2405094, IEEE Journal of Emerging and Selected Topics in Power Electronics

Single-Phase Grid Voltage Frequency Estimation

Using Teager Energy Operator Based Technique
Md. Shamim Reza, Student Member, IEEE, Mihai Ciobotaru, Senior Member, IEEE, and Vassilios G. Agelidis,
Senior Member, IEEE

AbstractThis paper reports the performance of a

technique for the estimation of single-phase grid voltage
fundamental frequency under distorted grid conditions. The
technique combines a Teager energy operator with a
frequency adaptive band-pass filter. The Teager energy
operator is based on three consecutive samples and is used to
estimate the fundamental frequency. The band-pass filter
relies on a recursive discrete Fourier transform (RDFT) and
an inverse RDFT, and is used to extract the normalised
amplitude of the grid voltage fundamental component. The
technique is computationally efficient and can also reject the
negative effects caused by DC offset and harmonics. It
requires less computational effort, can provide faster
estimation and is also less affected by harmonics as compared
to a technique relying on the RDFT based decomposition of
the single-phase system into orthogonal components. The
performance of the technique is verified by using both
simulation and experimental results.
Index TermsDiscrete Fourier transform, frequency
estimation, monitoring, single-phase voltage system, and
Teager energy operator.

I. INTRODUCTION
The grid voltage fundamental frequency in AC electricity
networks is a key parameter that constantly is required to be
monitored and controlled. This requirement is necessary in the
context of modern technological developments such as
microgrids in order to maintain the active power balance [15]. The frequency control of a microgrid is important during
the transitions between grid-connected and islanding modes,
where high deviations of frequency can occur [6, 7]. The
IEEE standard 1547 defines that the frequency of a microgrid
cannot differ from the grid frequency more than 0.1% during
the reconnection with the grid [6, 7].
Any digital signal processing (DSP) technique used for
grid voltage frequency estimation should be fast, accurate and
robust in the presence of grid disturbances such as voltage
transients, DC offset and harmonics. The technique should
also be simple and computationally efficient which will
contribute to an economical realization of the smart grid
vision [8] for phasor measurement units [9, 10], smart meters
[11, 12], load shedding and restoration functions [13, 14], and
power quality analysis [15].
Many DSP techniques for estimating the grid voltage
fundamental frequency have been reported in the technical
The authors are with the Australian Energy Research Institute, The
University of New South Wales, Sydney, NSW 2052, Australia, and also
with the School of Electrical Engineering and Telecommunications, The
University of New South Wales, Sydney, NSW 2052, Australia (e-mail:
m.reza@unsw.edu.au;
mihai.ciobotaru@unsw.edu.au;
vassilios.agelidis@unsw.edu.au).

literature. Among these techniques, the zero crossing

detection is a relatively simple one to implement [16]. The
presence of noise may introduce multiple zero crossings
which may lead to erroneous estimations and hence a prefiltering of voltage is required [16]. The frequency estimation
by using a single-phase phase-locked loop (PLL) requires a
virtual orthogonal voltage system, where there is less
information in single-phase systems than in three-phase ones
[17-20]. The PLL also requires an optimal tuning of the
parameters to obtain a trade-off between good dynamics and
estimation accuracy under grid disturbances [21]. On the other
hand, a frequency-locked loop (FLL) based single-phase grid
voltage frequency estimation technique also requires a virtual
orthogonal voltage system [22, 23]. There is also a
compromise required between good dynamics and estimation
accuracy obtained by the FLL under distorted grid conditions
[22, 23]. A technique based on Kalman filter (KF) can also be
used to obtain the grid voltage fundamental frequency [24,
25]. The accuracy and stability of the KF depends on the
model used for analysis and the tuning of the parameters. The
KF is also complex and computationally demanding for realtime implementations. The Newton-type algorithm (NTA) is a
nonlinear technique for frequency estimation and may also
suffer from instability due to a large voltage transient [11, 12].
The complexity of the NTA also increases when the number
of harmonics increases [26]. The computational burden of the
NTA under distorted grid conditions can be reduced by using
a pre-filter at the cost of a poor dynamic response [11, 12].
The demodulation based frequency estimation techniques
require implementation of a computationally demanding
finite-impulse-response (FIR) filter [9, 10, 27]. The Prony
method requires prior knowledge of the number of modal
components present in the grid voltage and is also
computationally demanding due to the handling of a large size
window and rooting of a high-order polynomial [28, 29]. On
the other hand, three consecutive samples (3CS) based
frequency estimation technique is ill-conditioned when the
middle voltage sample is equal or close to zero [7]. This illcondition can be avoided by holding the previously estimated
frequency, however, the methodology of determining the
threshold value of the middle sample is not reported in [7]. In
this case, a recursive algorithm is reported in [30], which does
not need to set the threshold value of the middle voltage
sample. However, the 3CS based techniques, as reported in [7,
30], require the implementation of the computationally
demanding FIR filter to reject the effects of harmonics and
noise. Another technique based on a Teager energy operator
(TEO), which also relies on the 3CS and does not suffer from
the ill-condition due to a zero or low value of a voltage
sample, can also be applied to estimate the grid voltage

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
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frequency [31-34]. However, the performance of the TEO is

affected under distorted grid conditions [31-34].
The discrete Fourier transform (DFT) is a basic technique
for spectral analysis but can lead to inaccurate results due to
spectral leakage and picket fence effect during time-varying
cases [35-37]. The spectral leakage information can also be
used to obtain the fundamental frequency [35, 36]. However,
large size moving windows for three DFT operations, which
increases the computational burden, are required to avoid the
interference caused by lower order harmonics [35, 36]. The
spectral leakage can also be reduced by using a desirable
sidelobe window based DFT [37]. Iterative approaches based
on the DFT can also be used for frequency estimation at the
expense of a high computational burden [38]. The
computational effort of the DFT can be reduced by using it
recursively [39]. The recursive DFT (RDFT) may suffer from
an accumulation error, however, can be removed by careful
coding [40, 41] or several other algorithms as reported in [39]
at the cost of additional complexity and computational burden.
An adaptive RDFT based PLL can be used to estimate the
fundamental frequency [42]. However, it requires an
additional numerically controlled oscillator and variable
sampling frequency [42]. The variable sampling frequency
approach may not be suitable when a low cost microcontroller is used, since the parameters of other digital
algorithms implemented on the same micro-controller has to
be adjusted for the new sampling frequency. On the other
hand, the frequency estimation by using a fixed window
RDFT based decomposition of a single-phase system into
orthogonal components (RDFT-OC) technique requires highorder FIR low-pass filter (LPF) to reject the negative effects
caused by harmonics [15].
The objective of this paper is to report the performance of a
computationally efficient DSP technique for instantaneous
estimation of the single-phase grid voltage fundamental
frequency under distorted grid conditions. The technique uses
a fixed sampling frequency and combines the TEO with a
frequency adaptive band-pass filter (BPF). The 3CS based
TEO is used to estimate the frequency. The RDFT and inverse
RDFT (IRDFT) principles are used to implement the BPF,
which is used to extract the normalised amplitude of the grid
voltage fundamental component. A linear interpolation
operation is combined with the RDFT in order to improve the
performance of the BPF when the number of voltage samples
in one fundamental cycle is not an integer value. The RDFT
and TEO based (RDFT-TEO) technique and its preliminary
simulation results under limited operating conditions of the
grid voltage were reported in [43]. On the other hand, a detail
theoretical analysis of the technique with a simplified TEO is
documented in this paper. Moreover, based on standard
requirements under a wide range of frequency variation [44,
45], both simulation and experimental performances of the
RDFT-TEO technique are reported in this paper.
The rest of the paper is organized as follows. The RDFTTEO technique is described in Section II. Section III contains
the simulation results of the technique. The experimental
performance comparison of the RDFT-TEO and RDFT-OC
[15] techniques are presented in Section IV. Finally, the
conclusions are summarized in Section V.

II. RDFT-TEO TECHNIQUE

A. Grid Voltage Fundamental Component Estimation
The DFT of the grid voltage waveform, v(n), at the n
sampling instant can be expressed by [46-48]
n

Vk n

v i e

2 ki
N

(1)

i n N 1

where k (k=0,1,2,,N-1) is the frequency index, N is the

number of voltage samples present in a window, and j is the
complex operator. In this paper, the window size of the DFT
is frequency adaptive and chosen as one fundamental cycle,
hence the frequency resolution (f) is f=f, where f is the grid
voltage fundamental frequency. Similar to (1), the DFT of the
grid voltage waveform at the (n-1) sampling instant can be
expressed by
n 1

Vk n 1

v i e

2 ki
N

(2)

i n N

The following recursive relation can be obtained by

subtracting (2) from (1).
Vk n Vk n 1 v n v n N e

2 kn
N

(3)

Equation (3) is called the RDFT and can be used to estimate

the spectral contents present in the grid voltage waveform
[39]. On the other hand, the time domain voltage waveform
for a single frequency kf can be obtained by taking the inverse
transform of (3). Therefore, based on the IRDFT, the
instantaneous time domain voltage waveform for the single
frequency kf can be obtained by [46]
j
1
Vk n e
N

vk n

2 kn
N

(4)

The RDFT and IRDFT, as given by (3) and (4), respectively,

can be cascaded in series to implement a digital BPF at the
center frequency kf. The discrete transfer function of the BPF
at the center frequency kf can also be achieved from (3) and
(4). The following expression is obtained from (4) after using
the value of Vk(n), as given in (3).
vk n

j
1
Vk n 1 e
N

2 kn
N

1
v n v n N
N

(5)

By replacing n with n-1, equation (4) can also be expressed as

vk n 1 e

2 k
N

j
1
Vk n 1 e
N

2 kn
N

(6)

By combining (5) and (6), the following relation is obtained.

vk n vk n 1 e

2 k
N

1
v n v n N
N

(7)

The following discrete transfer function is obtained after

performing the z-transform of (7).

H k ( z)

vk z
v z

1 zN

N 1 e j 2 k / N z 1

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
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(1 b ) z

bz

L 1

vk n

2
N

2 kn
2 kn
Re Vk n cos
Im Vk n sin N
N

Ak n sin k ( n ) nTs + k (10)

where Re and Im denote real and imaginary, respectively, Ak

and k are the amplitude and initial phase angle of the kf
frequency component, =2f is the fundamental angular
frequency, and Ts=1/fs is the sampling period. Therefore, the
single-phase grid voltage fundamental component can be
obtained by replacing k=1 in (10) and is given by
v1 n

2
N

Magnitude (abs)
Phase (deg)

0
-90
-180
0

2 n
2 n
Re V1 n cos
Im V1 n sin N
N

A1 n sin ( n ) nTs +1 (11)

where V1 is the DFT at the fundamental frequency and 1 is

the initial phase angle of the fundamental voltage component.
The response of the BPF (for v1) based on the RDFT and
IRDFT during a step input is shown in Fig. 2(a). As it can be
seen, the response time of the BPF during a step input is one
fundamental period. On other hand, the fundamental voltage
amplitude step response of the BPF under harmonics is shown
in Fig. 2(b). In this case, the input voltage waveform contains
+50% step change of fundamental voltage amplitude and
harmonics, as given in Table I. The harmonic contents

50

100

150

200
250
300
Frequency (Hz)

350

400

450

500

Fig. 1. Bode plot of the transfer function H1(z), as given by (8), where k=1.
Step Response
1
Input
Output

0.5

-0.5

0.005

0.01

0.015

0.02

0.025

0.03

0.035

0.04

Time (s)

(9)

The adaptive calculation of N requires storing of the input

voltage samples more than one nominal fundamental cycle
due to the interpolation operation and variable fundamental
frequency. As the value of N is inversely related with the
fundamental frequency for a constant sampling frequency, the
size of the memory mainly depends on the lower limit of the
fundamental frequency variation range.
For a real input voltage waveform, the time domain
expression of a sinusoidal voltage waveform at frequency kf
obtained by the RDFT and IRDFT can be expressed by [46]

0.5

90

1.5

(b)
Voltage Waveform
(p.u.)

0
180

(a)
Magnitude
(p.u.)

The Bode plot of H1(z) (for k=1) at the centre frequency equal
to the grid voltage nominal fundamental frequency (50 Hz) is
shown in Fig. 1. As it can be noticed, H1(z) can reject odd and
even harmonics including the DC offset. Moreover, H1(z)
provides unity amplitude and does not introduce any phase
lag/lead at the fundamental frequency. During the frequency
dynamics, the time-varying harmonics can also be removed
adaptively from the grid voltage fundamental component by
updating the value of N=fs/f, where fs is the sampling
frequency. However, the value of N can be an integer or noninteger under dynamic conditions. H1(z) can reject harmonics
effectively when the value of N is integer. For a non-integer
value of N i.e. L<N<L+1, a rounded function, such as ceil or
floor, can be used to obtain an integer value, where L is a
positive integer, floor(N)=L and ceil(N)=L+1. However, H1(z)
cannot reject harmonics effectively due to the rounding error
produced by the functions floor or ceil. Nevertheless, a linear
interpolation can be performed between the samples v(n-L)
and v(n-L-1) to obtain the value of v(n-N) in order to improve
the performance of H1(z). The linear interpolation operation
can be obtained by (9), where b=N-L [7].

Input
Output

1
0.5
0

-0.5
-1

-1.5
0.98

0.99

1.01

1.02

1.03

1.04

1.05

1.06

Time (s)

Fig. 2. Response of the BPF (for v1) based on the RDFT and IRDFT under (a)
step input. (b) +50% fundamental voltage amplitude step and harmonics, as
given in Table I.
TABLE I
HARMONICS AS A PERCENTAGE OF FUNDAMENTAL COMPONENT BASED ON
SECOND LEVEL TEST CLASS IN IEC STANDARD 61000-4-13
Harmonic

THD

2nd

3rd

4th

5th

7th

3.0 %

8.0 %

1.5%

9.0 %

7.5 %

14.58%

introduce 14.58% total harmonic distortion (THD) and are

chosen based on the definition for the second level test class
in IEC standard 61000-4-13 [11, 49]. It can be noticed from
Fig. 2(b) that the BPF takes one fundamental period as a
response time during the amplitude step and can also reject
the harmonics from the input voltage waveform.
B. Amplitude Normalisation of Estimated Grid Voltage
Fundamental Component
The real and imaginary parts of the RDFT, as given by (3),
for k=1 can be estimated separately and is given by
2 n
Re V1 n Re V1 n 1 v n v n N cos

N
2 n
Im V1 n Im V1 n 1 v n v n N sin

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
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The fundamental voltage amplitude can also be estimated

from the real and imaginary parts of the RDFT and is given by
[46]
2
A1 n
N

Re V1 n Im V1 n

(13)

The estimated fundamental voltage amplitude can be used to

normalize the estimated instantaneous fundamental voltage
component. Therefore, the normalised amplitude of the grid
voltage fundamental component can be obtained by
u
1

v (n)=

v1 n
A1 n

=sin ( n) nTs +1

(14)

where the superscript u of v1u ( n ) indicates that the estimated

fundamental voltage component has unity amplitude.
C. Fundamental Frequency Estimation
The TEO is a nonlinear operator and can be used to
estimate the energy of a sinusoidal signal [31-34]. The value
of the TEO is equal to the square of the product among
amplitude, angular frequency and sampling time [31-34]. It is
reported in [31] that the TEO can be obtained from the three
consecutive samples of a discrete sinusoidal signal. Therefore,
based on the constant fundamental parameters within the three
consecutive samples of v1, the following relation can be
obtained to get the value of TEO [31-34].

u
1

v1u n v1u n 2

(16)

In order to avoid the inverse trigonometric function operation,

sin{(n)Ts} in (16) can be approximated by
sin n Ts sin 0 Ts n Ts
sin 0 Ts cos n Ts cos 0 Ts sin n Ts

sin 0 Ts n Ts cos 0 Ts S0 2fTs C0 (17)

where =0+, 0 =2f0 is the nominal fundamental
angular frequency, f0 is the nominal fundamental frequency,
=2f is the fundamental angular frequency deviation, f
is the fundamental frequency deviation, cos{(n)Ts} 1,
sin{(n)Ts} (n)Ts, S0=sin(0Ts) and C0=cos(0Ts). As it
can be seen, both S0 and C0 are constants and can be estimated
offline. Therefore, the fundamental frequency deviation can
be estimated from (16) and (17) by using only three
consecutive samples of the normalised amplitude of the
fundamental voltage waveform and is expressed by
2

v n 1
u
1

f n

v1u n v1u n 2 S0
(18)

2 Ts C0

where indicates absolute value. The actual fundamental

frequency can be obtained by

f n f 0 f n

A12 n sin n Ts v12 n 1 v1 n v1 n 2

A12 n 2 n Ts2 v12 n 1 v1 n v1 n 2

v n 1

sin n Ts

(15)

where sin{(n)Ts} (n)Ts for a high sampling frequency

(fs>8f) [31]. It can be seen from the technical literature that the
TEO, as given by (15), can be used to estimate the
fundamental voltage amplitude of the grid voltage, where the
fundamental frequency is known or estimated separately [3134]. On the other hand, it can be noticed from (15) that the
fundamental frequency can also be estimated by using the
TEO, where the fundamental voltage amplitude is unity or
estimated separately. Therefore, the TEO is used in this paper
to estimate the grid voltage fundamental frequency. Based on
the normalised amplitude of the fundamental voltage
waveform, as obtained by (14), equation (15) can be
expressed as

(19)

D.
Block Diagram Implementation of the RDFT-TEO
Technique
The block diagram implementation of the RDFT-TEO
technique for the single-phase grid voltage fundamental
frequency estimation is shown in Fig. 3. The BPF is
implemented based on (11), (12), (13) and (14). On the other
hand, the TEO is implemented based on (18). It can be noticed
from Fig. 3 that v1u ( n ) is obtained by using the frequency
adaptive BPF. The value of v1u ( n ) is then used to estimate the
fundamental frequency deviation by using the TEO. Only
three consecutive voltage samples are required for the TEO
and hence can provide fast estimation of frequency deviation.
The estimated fundamental frequency is also fed back to
obtain the number of voltage samples present in one

cos(2 n / N )

z 1
v n

. .

u
1

v n

z 1

f n 1 order f n
IIR LPF
st

1/2 Ts C0

Teager Energy Operator

z 1
.

z 1

(1 b) z L bz L 1

f0

S0

sin(2 n / N )

Band-Pass Filter

f s / .

Fig. 3. Block diagram implementation of the RDFT-TEO technique for the single-phase grid voltage fundamental frequency estimation.

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f n

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Fundamental
Frequency (Hz)

(a)

47
46
45
44

42
1.99
58

2.01

2.02

2.03

2.04

2.05

Fundamental
Frequency (Hz)

57
56

RDFT-TEO
Actual

55
54
53
52
51
50
1.99

2.01

2.02

2.03

2.04

2.05

0.005

0.01

Error (Hz)

Relative Error (%)

(22)

0.004

0.008

0.003

0.006

0.002

0.004

0.001

0.002

0
42

44

46

48

50

52

54

56

Relative Frequency Error (%)

TLPF TRDFT

Time (s)
Fig. 4. Simulated frequency steps estimation. (a) -7.5 Hz (50 Hz to 42.5 Hz).
(a) +7.5 Hz (50 Hz to 57.5 Hz).

(21)

where TRDFT is the time delay provided by the BPF during

dynamics. Based on an assumption TRDFT 2Ts i.e. for a
high sampling frequency, expression (21) can be
approximated by
cut 5 / TRDFT

48

43

(20)

where cut is the angular cut-off frequency of the LPF. The

following condition has to be satisfied for the stability purpose
of the RDFT-TEO technique.
TLPF 2Ts TRDFT

49

Frequency Error (Hz)

TLPF 5 / cut

RDFT-TEO
Actual

50

(b)

fundamental cycle. As there is an interdependent loop present

in Fig. 2, the fast tracking of the fundamental frequency, when
compared with the estimation of the normalised amplitude of
the fundamental voltage component, will affect the stability of
the technique [50, 51]. Therefore, a first-order infiniteimpulse-response (IIR) LPF can be cascaded in series with the
TEO, as shown in Fig. 2, for ensuring a smaller bandwidth
with respect to the estimation of the amplitude normalized
fundamental voltage component [50, 51]. The use of LPF also
helps to reject high frequency disturbances present in the
estimated frequency under distorted grid conditions. The
settling time (TLPF ) obtained by the first-order IIR LPF can be
approximated by [23]

0
58

Fundamental Frequency (Hz)

The window size of the BPF is used as one fundamental time

period and it changes under variable frequency environment.
However, this variation is small and hence the value of TRDFT
can be approximated by 20 ms for the 50 Hz system.
Therefore, the approximated value of the angular cut-off
frequency of the LPF can be expressed by

cut 250 rad/s

(23)

It can be seen from Fig. 2 that the BPF and the TEO
require only few mathematical operations and two
trigonometric functions. A lookup table can be used for the
trigonometric functions for online implementation [52].
Therefore, the RDFT-TEO technique is relatively simple to
implement on a low cost digital signal processor for real-time
frequency estimation of the single-phase grid voltage
waveform.
III.

SIMULATION RESULTS

The simulation performance of the RDFT-TEO technique

is documented in this section. The simulations are carried out
in MATLAB/Simulink. A first-order discrete IIR Butterworth
LPF with the cut-off frequency 39.8 Hz (cut 250 rad/s) is
used in the technique. The sampling frequency is chosen as
fs=10 kHz. The fundamental frequency variation range
(507.5 Hz) is used based on the specification of the IEC
standard 61000-4-30 [44]. The estimation of the fundamental
frequency steps 7.5 Hz is shown in Fig. 4, where the grid
voltage contains only fundamental component with unity
amplitude. As it can be seen, the settling time of the RDFTTEO technique is around 1.5 fundamental cycles and is less

Fig. 5. Simulated estimated frequency error in steady-state operation with

harmonics, as given in Table I.

than the maximum time (0.2s for 50 Hz system) for phasor

estimation as specified by the IEC standard 61000-4-7 [45].
For evaluating the steady-state performance of the RDFTTEO technique, the fundamental component of the grid
voltage waveform is distorted by harmonics, as given in Table
I. The peak error of the estimated fundamental frequency by
using the RDFT-TEO technique is shown in Fig. 5, where the
grid voltage waveform contains 1.0 p.u. fundamental
amplitude, 14.58% THD, as given in Table I, and the
fundamental frequency is varied from 42.5 Hz to 57.5 Hz. As
it can be noticed, the RDFT-TEO technique can provide the
estimation of the fundamental frequency range of 50 Hz 7.5
Hz with an error less than 0.005 Hz under 14.58% THD.
Moreover, the maximum relative error of the estimated
fundamental frequency remains inside the acceptable range
(less than 0.03%) specified by the IEC standard 61000-4-7,
where the relative error is defined as
Relative Error (%) =

Actual Value - Estimated Value

Actual Value

100%

(24)
IV.

EXPERIMENTAL RESULTS

The experimental performance of the RDFT-TEO

technique is compared with the RDFT-OC one [15]. The
experimental setup, as shown in Fig. 6, consists of hardware
and software parts. The hardware part includes a
programmable AC power supply (REGATRON 4-Quadrant

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vLN

~
Electrical
Grid

Programmable
AC Power Supply

Voltage
Sensor

dSPACE
1103

Personal
Computer

Fig. 6. Laboratory setup for real-time experiment.

TABLE II
PARAMETERS OF THE RDFT-TEO AND RDFT-OC TECHNIQUES
RDFT-TEO

RDFT-OC

cut 250 rad/s

2 LPFs based on 250 points

Hamming window

50 Hz

Grid Simulator), a voltage sensor (LEM LV 25-400), a

dSPACE1103 (DS1103) control board, and a personal
computer (PC). The programmable power supply is used to
generate the real-time single-phase grid voltage waveform
(vLN, where the subscript LN indicates line-to-neutral). The
power supply is programmed from the PC to introduce various
grid conditions, such as DC offset, harmonics, frequency step,
frequency sweep, voltage sag, voltage flicker, phase jump,
notches and spikes, in the generated voltage waveform. On the
other hand, the voltage sensor measures the generated voltage
and steps down in a range of 10V to make it compatible with
the DS1103 control board. The output of the voltage sensor is
then sent to the 16 bit analog-to-digital converter (ADC) of
the DS1103 control board. The PC is used to monitor the realtime experimental results obtained from the DS1103 control
board. On the other hand, the software part of the
experimental setup contains MATLAB/Simulink, DS1103
Real-Time Interface (RTI) and Control Desk Interface. The
Simulink models of the RDFT-TEO and RDFT-OC
techniques with the parameters given in Table II are compiled
and uploaded to the DS1103 control board by using the
automatic code generation. The Control Desk Interface
running on the PC is used to set the parameters in real-time
and also to monitor the estimated values.
A. Experimental Case Studies
The following case studies are performed to compare the
performance of the RDFT-TEO and RDFT-OC techniques.
i. Steady-state with DC offset and harmonics (Case-1)
ii. Frequency step and harmonics (Case-2)
iii. Frequency sweep and harmonics (Case-3)
iv. Voltage sag and harmonics (Case-4)
v. Voltage flicker and harmonics (Case-5)
vi. Phase jump and harmonics (Case-6)
vii. Notches, spikes and harmonics (Case-7)
viii. Voltage sag, frequency step, phase jump and harmonics
(Case-8)
The grid voltage waveforms presented in all case studies
contain 14.58% THD, as given in Table I. The experimental
results are captured from a digital oscilloscope. Channel 1 of
the oscilloscope contains the voltage waveform. On the other
hand, Channels 2 and 3 show the fundamental frequency
estimated by the RDFT-TEO and RDFT-OC techniques,
respectively.
Case-1: Steady-State with DC Offset and Harmonics
The steady-state performances of the RDFT-TEO and
RDFT-OC techniques are compared under DC offset and

f 0.1 Hz/V

RDFT-TEO
RDFT-OC

Fig. 7. Experimental case-1: steady-state with DC offset (5%) and harmonics.

Channel 1 contains the voltage waveform, and Channels 2 and 3 show the
fundamental frequency estimated by the RDFT-TEO and RDFT-OC
techniques, respectively.

50 Hz

f 1.0 Hz/V

RDFT-TEO
RDFT-OC

Fig. 8. Experimental case-2: frequency step (-7.5 Hz: 50 to 42.5 Hz) and
harmonics. Channel 1 contains the voltage waveform, and Channels 2 and 3
show the fundamental frequency estimated by the RDFT-TEO and RDFT-OC
techniques, respectively.

harmonics. The grid voltage waveform is shown in Channel 1

of Fig. 7 and contains 5% DC offset and 14.58% THD, as
given in Table I. The estimations of the nominal fundamental
frequency by using the RDFT-TEO and RDFT-OC techniques
are shown in Channels 2 and 3, respectively, of Fig. 7. As it
can be noticed, both techniques provide similar estimation and
can also reject the negative effects caused by DC offset and
harmonics.
Case-2: Frequency Step and Harmonics
The performances of the RDFT-TEO and RDFT-OC
techniques are compared under frequency step and harmonics.
In this case study, the grid voltage waveform contains -7.5 Hz
(50 to 42.5 Hz) frequency step and 14.58% THD, as given in
Table I. The grid voltage waveform and the fundamental
frequency step estimations by using the RDFT-TEO and
RDFT-OC techniques are depicted in Fig. 8. As it can be seen,
both techniques can track the frequency step. The settling time
of the RDFT-TEO technique is less than 1.5 fundamental
cycles and is faster than the RDFT-OC one. It can also be seen
that the RDFT-TEO technique generates less ripple in the
steady-state estimation of off-nominal fundamental frequency
(42.5 Hz) when compared with the RDFT-OC one.

6 / 10
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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
10.1109/JESTPE.2015.2405094, IEEE Journal of Emerging and Selected Topics in Power Electronics

50 Hz

f 1.0 Hz/V

50 Hz

RDFT-TEO
RDFT-OC

f 0.5 Hz/V

Fig. 9. Experimental case-3: frequency sweep (+10Hz/s: 50 Hz to 57.5 Hz)

and harmonics. Channel 1 contains the voltage waveform, and Channels 2 and
3 show the fundamental frequency estimated by the RDFT-TEO and RDFTOC techniques, respectively.

RDFT-TEO
RDFT-OC

Fig. 11. Experimental case-5: voltage sag (30%) and harmonics. Channel 1
contains the voltage waveform, and Channels 2 and 3 show the fundamental
frequency estimated by the RDFT-TEO and RDFT-OC techniques,
respectively.

50 Hz

50 Hz

f 0.1 Hz/V

RDFT-TEO
RDFT-OC

f 1.0 Hz/V

RDFT-TEO
RDFT-OC

Fig. 10. Experimental case-4: voltage flicker (5%) and harmonics. Channel
1 contains the voltage waveform, and Channels 2 and 3 show the fundamental
frequency estimated by the RDFT-TEO and RDFT-OC techniques,
respectively.

Fig. 12. Experimental case-6: phase jump (-30) and harmonics. Channel 1
contains the voltage waveform, and Channels 2 and 3 show the fundamental
frequency estimated by the RDFT-TEO and RDFT-OC techniques,
respectively.

Case-3: Frequency Sweep and Harmonics

A fundamental frequency sweep of +10 Hz/s up to 57.5 Hz
is considered into the grid voltage waveform containing
harmonics, as given in Table I. The corresponding voltage
waveform and the estimations of the fundamental frequency
sweep are shown in Fig. 9. As it can be noticed, both the
RDFT-TEO and RDFT-OC techniques can track the
frequency sweep. In this case, the RDFT-TEO technique
offers a slightly faster response when compared with the
RDFT-OC.

Case-5: Voltage Sag and Harmonics

A grid voltage waveform containing 30% voltage sag and
14.58% THD, as given in Table I, is shown in Channel 1 of
Fig. 11. The fundamental frequency estimations by using the
RDFT-TEO and RDFT-OC techniques are also shown in
Channels 2 and 3, respectively, of Fig. 11. Similar to the
voltage flicker, the RDFT-TEO technique is more affected by
the voltage sag as compared to the RDFT-OC one. It can be
noticed from Fig. 11 that the RDFT-TEO and RDFT-OC
techniques present around 1.75 Hz and 0.13 Hz peak error,
respectively, during the voltage sag.

Case-4: Voltage Flicker and Harmonics

The grid voltage waveform, as shown in Channel 1 of Fig.
10, contains voltage flicker and harmonics, as given in Table
I. The frequency and amplitude of the triangular voltage
flicker are 2.5 Hz and 5% of fundamental amplitude,
respectively. The fundamental frequency estimations are also
shown in Fig. 10. As it can be observed, the performance of
the RDFT-TEO technique for frequency estimation is more
affected by the voltage flicker when compared with the
RDFT-OC technique. In this case, the peak error of the
estimated frequency by using the RDFT-TEO and RDFT-OC
techniques are around 0.15 Hz and 0.03 Hz, respectively.

Case-6: Phase Jump and Harmonics

The grid voltage waveform, as shown in Channel 1 of Fig.
12, contains a -30 phase jump and harmonics, as given in
Table I. The fundamental frequency estimations are also
shown in Channels 2 and 3 of Fig. 12. As it can be seen, the
performances of both the RDFT-TEO and RDFT-OC
techniques are affected by the phase jump. The maximum
error generated by the RDFT-TEO and RDFT-OC techniques
during a phase jump of -30 are around 3.88 Hz and 4.13 Hz,
respectively.

7 / 10
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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
10.1109/JESTPE.2015.2405094, IEEE Journal of Emerging and Selected Topics in Power Electronics

v
v

f 1.0 Hz/V

50 Hz

RDFT-TEO
RDFT-OC

50 Hz

f 0.1 Hz/V

RDFT-TEO
RDFT-OC

Fig. 13. Experimental case-7: notches, spikes and harmonics. Channel 1

contains the voltage waveform, and Channels 2 and 3 show the fundamental
frequency estimated by the RDFT-TEO and RDFT-OC techniques,
respectively.

Case-7: Notches, Spikes and Harmonics

In this case study, the performances of both the RDFTTEO and RDFT-OC techniques are compared under voltage
notches, spikes and harmonics. The grid voltage waveform
and the fundamental frequency estimations are shown in Fig.
13. As it can be observed, the performance of the RDFT-TEO
technique is slightly more affected by the voltage notches and
spikes when compared with the RDFT-OC one.

Fig. 14. Experimental case-8: voltage sag (-10%), frequency step (-1Hz),
phase jump (-10) and harmonics. Channel 1 contains the voltage waveform,
and Channels 2 and 3 show the fundamental frequency estimated by the
RDFT-TEO and RDFT-OC techniques, respectively.
TABLE III
PERFORMANCE AND COMPUTATIONAL EFFORT COMPARISONS OF THE RDFTTEO AND RDFT-OC TECHNIQUES
RDFT-TEO

Simplicity

RDFTOC

Interdependent loop

Case-8: Voltage Sag, Frequency Step, Phase Jump and

Harmonics
The performance of the RDFT-TEO and RDFT-OC
techniques under a voltage sag (-10%), frequency step (-1Hz),
phase jump (-10) and harmonics, as given in Table I, is
shown in Fig. 14. In this case study, the voltage sag,
frequency step and phase jump occur at the same time. It can
be noticed from the results presented in Fig. 14 that the
RDFT-TEO technique generates a slightly larger undershoot
but it provides faster response when compared with the
RDFT-OC one.
B. Performance and Computational Effort Comparisons of
the RDFT-TEO and RDFT-OC Techniques
Table III shows a summary of the performance and
computational effort comparisons of the RDFT-TEO and
RDFT-OC techniques. As it can be seen, both techniques
provide similar performance under DC offset. However, the
RDFT-OC technique does not contain interdependent loop
and the frequency estimation is less affected by the amplitude
excursions such as voltage flicker, voltage sag, notches and
spikes when compared with the RDFT-TEO one. On the other
hand, the RDFT-TEO technique is simpler and
computationally efficient as compared to the RDFT-OC one.
In the DS1103 control board platform, the RDFT-TEO and
RDFT-OC techniques take 2.96 s and 6.14 s turnaround
time, respectively, for providing the real-time frequency
estimation. When compared with the RDFT-OC technique,
the RDFT-TEO one takes 51.8% less turnaround time in the
DS1103 control board platform. In addition, the RDFT-TEO
technique can provide improved estimation under harmonics,
frequency step, frequency sweep and phase jump as compared
to the RDFT-OC one, as it can also be noticed from Table III.

Comparison Cases

Computational burden

Harmonics

DC offset

Frequency step

Frequency sweep

Voltage flicker

Voltage sag

Phase jump
Notches and spikes

symbol denotes which technique performs better with respect to the other
one and = symbol indicates both techniques show similar performance for a
case provided in the left column of Table III.

V. CONCLUSIONS
The performance evaluation of a power system
fundamental frequency estimation technique has been
reported in this paper. The technique relies on the Teager
energy operator and a band-pass filter. The three consecutive
samples based Teager energy operator is used to estimate the
fundamental frequency. The band-pass filter is implemented
based on the recursive DFT and inverse recursive DFT. The
technique is computationally efficient and can also estimate a
wide range of frequency variation accurately under the DC
offset and harmonics. The technique also requires less
computational effort, can provide faster estimation and is less

8 / 10
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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
10.1109/JESTPE.2015.2405094, IEEE Journal of Emerging and Selected Topics in Power Electronics

affected by harmonics as compared to a technique relying on

the recursive DFT based decomposition of the single-phase
system into orthogonal components. The presented simulation
and experimental results have confirmed the effective
applications of the technique for grid voltage fundamental
frequency estimation.

[20]

[21]

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Vassilios G. Agelidis (S
(S'89M'91
91SM
SM'00)
00) was born
in Serres, Greece. He received the B.Eng. degree in
electrical engineering from the Democritus
University of Thrace, Thrace, Greece, in 1988; the
M.S. degree in applied science from Concordia
University, Montreal, QC, Canada, in 1992; and the
Ph.D. degree in electrical engi
engineering
neering from Curtin
University, Perth, Australia, in 1997.
He has worked with Curtin University (1993
(1993
1999); the University of Glasgow, Glasgow, U.K.
(20002004);
(2000
2004); Murdoch University, Perth, Australia
(2005
(20052006);
2006); and the University of Sydney, Sydney, Aust
Australia
ralia (2007
(20072010).
2010).
He is currently the Director of the Australian Energy Research Institute,
School of Electrical Engineering and Telecommunications, University of New
South Wales, Sydney.
Dr. Agelidis was the recipient of the Advanced Research Fellowship
from the U.K.s Engineering and Physical Sciences Research Council in
2004. He was the Vice President for Operations with the IEEE Power
Electronics Society (PELS) from 2006 to 2007. He was an AdCom Member
of IEEE PELS from 2007 to 2009 and the Technical C
Chair
hair of the 39th IEEE
Power Electronics Specialists Conference in 2008 held in Rhodes, Greece.

Md. Shamim Reza (S'12) was born in Magura,

Bangladesh. He received his B.Sc. and M.Sc.
degrees in Electrical and Electronic Engineeri
Engineering
ng
(EEE)
from
Bangladesh
University
of
Engineering and Technology (BUET), Dhaka,
Bangladesh, in 2006 and 2008, respectively, and
the Ph.D. degree in Electrical Engineering from
the University of New South Wales (UNSW),
Sydney, NSW, Australia, in 2014. Curr
Currently,
ently, he is
working as a Research Associate at the UNSW.
His research interests include advanced digital
signal processing techniques for grid voltage monitoring, power quality
analysis, and smart metering.
Mihai Ciobotaru (S'04
S'04-M'08
M'08--SM'14)
SM'14) was bor
bornn in
Galati, Romania. He received his B.Sc. and M.Sc.
degrees in electrical engineering from the University
of Galati, Galati, Romania in 2002 and 2003
respectively, and the Ph.D. degree in electrical
engineering from the Institute of Energy
Technology, Aa
Aalborg
lborg University, Aalborg, Denmark,
in 2009.
From 2003 to 2004, he was an Associate
Lecturer at the University of Galati. From 2007 to
2010, he was an Associate Research Fellow at the
Institute of Energy Technology, Aalborg University. From 2010 to 2013, hhee
was a Research Fellow at the School of Electrical Engineering and
Telecommunications, University of New South Wales (UNSW), Australia. He
currently works as a Senior Research Associate at the UNSW, performing his
research activities under the Australian Energy Research Institute. His main
research activities are in grid integration of PV systems, control of grid
connected converters, and power management of hybrid energy storage
systems.

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