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DLogicPro
User Manual
OMICRON DLogicPro
OMICRON DLogicPro
Recommended:
Pentium 166MHz
64 MB RAM
Windows 95, Windows NT4.0 or higher
(32-bit Windows)
OMICRON DLogicPro
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OMICRON DLogicPro
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action against the other party in the event of any breach hereunder shall not
be deemed a waiver by that party as to subsequent enforcement of rights or
subsequent actions in the event of future breaches.
Substation 1
TOC
Substation 2
IOC
Distribution
Relay
Figure 0-1:
The distribution feeder protection relay with two phase and ground overcurrent
zones, is shown on ( Figure 0-1, page -9 )
Different fault conditions and the operations of the breakers after a fault occurs
have also to be considered in the design of the protective relays.
Abnormal distribution power system conditions include current inrush or
overloading of the distribution feeder during a power system disturbance or line
energization.
Failure of voltage or current transformers or the circuits connecting them to the
analog inputs of the relay leads to a difference between the primary currents and
voltages in the power system and the currents and voltages measured by the
relay.
To address all the requirements for speed and selectivity of operation during fault
conditions, as well as to avoid maloperation under abnormal, but non-fault
OMICRON DLogicPro
conditions, modern distribution feeder protection relays have multiple built-in logic
schemes.
DLogicPro is designed for the testing of logic schemes that still play a very
important part and define the overall performance of distribution feeder protection
relays.
The following modules are available for testing of logic schemes in modern
distribution feeder protrction relays:
10
Getting results
GETTING RESULTS
Test task
Modes of operation
The software can be used for different purposes and in different modes as described in detail
later in the document.
The first mode is for benchmarking or complete evaluation purposes. In this case
multiple logic schemes are selected in a point-and-click manner and the
software automatically executes a series of predefined tests, measures the relay
under test response, analyses the results and prepares the test report.
The second mode is for testing of a specific logic scheme, for example a
Sympathetic Trip Scheme. In this case the software automatically executes a
series of predefined tests required for the selected scheme, measures the relay
under test response, analyses the results and prepares the test report for the
operation of the scheme.
The third mode of operation of the software is for training purposes. It includes
multiple animated demonstrations of the sequence of events and the operation of
different relay elements at each step of a test sequence. This tool is designed to
help a protection or test engineer or technician with limited experience to
understand the dynamics of the logic schemes operation and the functioning of the
11
OMICRON DLogicPro
relay logic for different fault conditions and different substation or power system
equipment performance.
The logic for each of the above listed schemes is based on existing documents
and may be implemented with modifications in specific products.
The testing of logic schemes is intended to evaluate the performance of the Test Object
under different fault, system and substation conditions.
Different tests are designed to monitor the relay operation for the following fault
conditions:
12
Getting results
Some of the logic schemes apply to the relay under test abnormal system
conditions such as:
TEST METHODS
The testing of distribution feeder relays with built-in logic schemes can be
performed in several different ways
USING FIXED INPUT STATUS
In this mode the testing of relays is performed with their inputs energized
constantly and not synchronized with the test equipment. This approach can be
used for testing of very simple relay functions. It does not adequately represent the
dynamics of real life events and has very limited application for testing of modern
microprocessor based transmission line protection relays.
Using this method the test engineer or technician can test just a simple scheme,
For example:
if a Feeder Blocking scheme is tested,
the breaker status monitoring input of the test object will be continuously
energized. The Blocking input is energized as well. When the fault currents and
voltages are applied by the test device, this should result in non-operation of the
tested scheme, since the overcurrent element is blocked.
It is obvious that this method can not be used for testing of more advanced logic
schemes, such as Evolving Fault or Current Transformer Supervision.
13
OMICRON DLogicPro
For example:
using this method the test engineer or technician can test not only a simple Feeder Blocking
scheme, but also more advanced logic schemes, such as Fuse Saving scheme. In this case
the simulation will include multiple steps including successful or unsuccessful autoreclosing.
The fundamental requirement in the DLogicPro software is ease of use. The goal is to
achieve maximum results with a minimum effort. That is why, the test configuration and
execution efforts in most cases are limited to a point-and-click action.
For example, if the test is for a Feeder Blocking scheme and the test conditions
are downstream feeder fault, the sequence will include only three steps:
pre-fault with breaker in a closed position, nominal voltage and normal load
current conditions
pre-fault with breaker in a closed position, nominal voltage and normal load
current conditions
14
To simplify the testing, the current and voltage levels are limited within the output range of
the basic CMC module (no amplifiers are required). This way there is no need for the user to
define the requirements for the CMC.
Getting results
OVERVIEW
As mentioned earlier, the goal of the DLogicPro software is to allow the testing of logic
schemes and comparing the performance of different relays under identical test conditions.
During the testing of the previously listed schemes all basic and ground
overcurrent settings remain the same. The only changes made are in the logic
scheme selected for each individual subgroup of tests and the relay settings
specific to the scheme under test.
The fault currents and voltages are calculated based on a simple network model,
and user defined current pickup settings.
The following sections in this chapter describe the network model used for the
calculation of the fault currents and voltages and the settings of the test object
corresponding to this model.
Since the software has test and training modes of operation, the global test data is
entered by the user only if one of the two test mode options has been selected.
NETWORK MODEL
Since we are testing a distribution feeder relay, the network model used for
calculation of short circuit currents and voltages for a different fault is a steady
state single source fault analysis model ( Figure 0-1, page -15 ).
Substation A
7.5 miles
Type Delta
0.833 omhs/mile
12 kV
Figure 0-1:
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OMICRON DLogicPro
A 12 kV, 7.5 miles long line with delta configuration is used in the default model.
The system is homogenous (i.e. source and line impedances have the same
angle) and the Source to Line Impedance Ratio is SIR = 1.
The line impedance is 0.833 primary ohms per mile. The default line impedance
angle is 75 deg.
The zero sequence impedance is 3.33 primary ohms per mile. The line zero
sequence impedance angle is 75 deg.
The zero sequence to positive sequence impedance ratio is 4 and the zero
sequence compensation factor KL
If the rated current of the distribution feeder relay under test is 5 amperes, it is
assumed that the CT ratio setting is
16
Getting results
Because the source to line impedance ratio is 1, the source impedance in the
network model will have the same values, i.e.
ZS = 12.5 ohms
The source angle is 75 deg (default homogeneous system) and the K-factor
KS = 1.0
Three phase voltages and currents are required from the CMC to the relay under
test. Some distribution relays and schemes require currents only.
A different number of binary outputs of the CMC are programmed to simulate the
relay environment as a function of the scheme under testing.
A different number of binary inputs of the CMC are programmed to monitor the
relay operation as a function of the scheme under testing.
TEST OBJECT SETTINGS
The expected basic settings of the multifunctional relay under test associated with
the distribution feeder schemes are given below.
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OMICRON DLogicPro
Phase
Ground
Note: It is assumed that the inverse time characteristics have been tested as part of testing
of basic protection functions
Phase
Ground
18
Getting results
Instantaneous Overcurrent:
Phase
Ground
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OMICRON DLogicPro
STEPS IN TESTING
Modern multifunctional distribution feeder protection relays are very complex
devices that require during testing adequate simulation of their operating
environment, to ensure that they will perform correctly when installed in the field.
There is a sequence of steps related to the testing of electromechanical, solid
state or microprocessor based relays using different logic schemes for improved
fault clearing. They depend on the goals of the test and the level of knowledge of
the relay under test and it's operating principles
If the user is familiar with the principles of the distribution feeder relay under
test and the DLogicPro software, he/she can proceed with the actual testing
process.
For testing of the logic schemes of a new to the utility feeder relay, the user
should follow the step-by-step procedure described in Multiple Scheme Test
Mode.
To test a specific logic scheme, the steps required are described in Single
Logic Scheme Mode.
20
Steps in testing
The user has to select the appropriate settings for each logic scheme.
Analyze the Test Results
If the automatic analyses of the Test results indicates that some tests have failed,
the user should check the required wiring, relay operating times, relay settings,
relay logic diagrams, etc., to determine the reasons for the specific test failure.
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OMICRON DLogicPro
Figure 1-1:
22
The Main Selection window is the primary tool of the graphical user interface for
navigation through the software and for selection of the mode of operation.It
changes dynamically depending on the user's actions.
In this case it will be used to select the Sympathetic Trip scheme and review the
Principles of Operation, Hardware Requirements and Test Objectives.
Figure 1-2:
At this stage it is not required to have a CMC test device connected to the
computer for the software to run.
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OMICRON DLogicPro
II
Figure 2-1:
The individual scheme control window has multiple control buttons that can be
enabled or disabled depending on the actions of the user. Some of the control
buttons used for the graphical user interface can also be visible or invisible at
different times. This reduces the chances for an inappropriate action by the
DLogicPro software user.
24
This action dynamically changes the scheme control window: ( See also Figure
2-2, page - 25 )
Figure 2-2:
25
OMICRON DLogicPro
Figure 2-3:
Note: It is recommended
for users that do not have
experience in power system
or distribution line
protection, to start by
selecting the Slow speed
option.
26
Figure 3-1:
The frame with the animation speed options will be enabled and it's label will turn
red when the animation mode is selected.
It includes three option buttons. Select a slow, medium or fast speed depending
on your knowledge of the specific scheme displayed ( Figure 3-1, page -26 ).
IV
Start Animation
1. Click on one of the available animation control buttons bellow the label saying
Click bellow to start Animations .
For example, to watch the test sequence and relay operation for a Sympathetic
Trip Block followed by fault on own feeder, click on the [STL Block and Feeder
Fault].
During the animation each of the relay elements that are involved in the scheme
logic is displayed with a different color depending on it's status.
When an element picks-up, it's color will change from black to red, and when it
drops-out, the color will change back from red to black.
2. At the start of animation, a few additional changes occur:
A new [Pause] control button appears in the animation control frame (See
bottom of ( Figure 2-3, page -26 ). It allows the user at any moment to stop
the animation at the current state, so the current status of the simulation
and relay performance can be reviewed in detail. It changes to [Continue]
when clicked. If you want to proceed with the animation, click on
[Continue].
The status bar will display the name of the chosen fault scenario (See
bottom of ( Figure 4-1, page -27 ) and ( Figure 2-3, page -26 )
A progress bar ( Figure 2-3, page -26 ) will appear, showing the progress
of the animation
The Animated logic scheme Status Legend - 1.1 ( Figure 4-2, page -28 ),
will appear
The Animated logic scheme Status Legend - 1.2 ( Figure 4-3, page -28 ),
explains different stages of the process
Figure 4-1:
The Animated logic scheme Status Legend ( See also Figure 4-2, page - 28 )
and ( Figure 4-3, page -28 ), which changes according to the animation, shows
the details at any moment of the process.
The Name of the state ( Figure 4-2, page -28 ) - the Pre-Fault condition is shown
in red, while the State number (State 1) and the State Time is displayed in white
when it is a non-fault state or in red, when it is a fault state ( Figure 4-3, page -28 )
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OMICRON DLogicPro
Figure 4-2:
Figure 4-3:
3. A second timer to the right of the progress bar displays the current simulation
time since the fault inception ( See also Figure 4-4, page - 28 )
Figure 4-4:
1. To view the objective of the test included in the DLogicPro software, click on
[Test Objective].
28
2. The logic scheme control window will change as shown on ( Figure 5-1,
page -29 ).
Figure 5-1:
29
OMICRON DLogicPro
Figure 6-1:
Note: In the cases when the voltage signals are optional, the wiring between the test object
and the test device is shown in grey.
There are several options to print the information related to the distribution logic
scheme under consideration.
To Print:
1. Click on the Print option in the menu bar on top of the Scheme Control window
2. Select the information to be printed
3. The Print dialog box will appear, allowing the user to specify a printer, if
necessary.
The following options for printing ( See also Figure 7-1, page - 31 ) are available:
1. the Scheme Logic as displayed during the animation
2. the Test Objective
3. the Hardware Requirements for the selected scheme
4. the complete Scheme Documentation (all options offered above) for the
selected scheme
30
Figure 7-1:
31
OMICRON DLogicPro
GETTING RESULTS
IN
The goal of the test is usually a benchmark test of the logic schemes of a new to the utility
distribution feeder relay.
To perform such a test, the user should follow the step-by-step procedure
described below.
Note: It is recommended to set all available setting groups with different logic schemes,
especially the Fuse Saving scheme and the Autoreclosing Block scheme, and then during
the test to switch between the setting groups as required by the test selected.
Check the required time settings for each scheme in the protection users manual.
1. Wire the Test Object (distribution feeder relay), DC power supply (if necessary)
and the Test Device (CMC x56) according to the diagrams shown in Hardware
Requirements for each of the individual schemes.
2. Connect the parallel cable between the Test Device and the Test Computer
with D-LogicPro installed.
Note: Check if the relay uses 52a or 52b breaker status contacts. LogicPro simulates
52a breaker status.
32
The Main Selection window is the primary tool of the graphical user interface for
navigation through the software and for selection of the mode of operation.It
changes dynamically depending on the user's actions.
The analysis of the distribution feeder relay performance during the test is based
on the expected operating times of tested relay elements under different fault
conditions.
The software is loaded using some default settings. However, if the user needs to
change them based on the technical specifications of the distribution feeder relay
under test, the default setting can be changed using the following steps:
Note: The default times for Instantaneous overcurrent (IOC) (50 ms) and Time overcurrent
(TOC) (250 ms) faults, include a margin of 50 ms, i.e. IOC is set as instantaneous, while
TOC is set with definite time delay of 200 ms.
The time overcurrent element should be set with definite time delay characteristic. It is
assured that the inverse time characteristics have been already tested using different
testing tools.
Figure 4-1:
33
OMICRON DLogicPro
Figure 4-2:
The testing of Fuse saving scheme and the Block reclosing scheme, simulates a
single reclosing shot for some of the tests. The default dead time for the reclosing
shot is 300 ms.
The simulation of inrush condition after closing of the distribution feeder breaker is
based on the Cold Load Pickup time setting (CLP Time), with default value of 100
ms.
34
Figure 4-3:
to review or edit the Primary Settings - Select the PRIMARY option ( See
also Figure 4-4, page - 36 )
Note: The user has an option to select to enter the voltage values as Phase-to-Neutral
(default) or Phase-to-Phase.
Note: The default frequency setting is 60 Hz. When the user decides to change it for the
first time, the software will ask, whether to leave it as a new default.
35
OMICRON DLogicPro
Figure 4-4:
If PRIMARY Settings are displayed - the Secondary Settings will be disabled and
grayed out.
Changes in the Primary Currents and Voltages are automatically reflected in the
Secondary. When the [Apply] button is pressed - the program will apply the
settings and automatically will recalculate the SECONDARY Settings and display
the changes based on modification in the CT or PT ratio.
The Nominal Values Settings window ( See also Figure 4-3, page - 35 ) displays
the Secondary Settings for the currents and voltages as default.
36
Figure 4-5:
Overcurrent Settings
Note: The phase and ground overcurrent settings are used to calculate the fault currents for
the different fault conditions required by the specific test being executed.
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OMICRON DLogicPro
Figure 4-6:
Figure 4-7:
The calculated Fault Currents and Voltages for Feeder End Fault -(Single Phase
and 3 Phase Faults), appear at the bottom of the window ( See also Figure 4-8,
page - 39 ). The Vnom, Line Impedance and Source Impedance used for the
calculations, are also displayed.
38
The Settings are directly accessible from here, and when clicked, the Settings
options window will appear on the top of the current window.
The changes made in the settings will be automatically reflected in the calculations
of the Fault Currents and Voltages.
Figure 4-8:
Note: The voltages are calculate based on the single source model described earlier.
The fault currents are calculated as 1.1 x I set of the instantaneous, high or low set
overcurrent element.
Note: For single-phase-to-ground faults the current in the healthy phases is calculated as
0.1 x I nom.
V Scheme Selection
39
OMICRON DLogicPro
Figure 5-1:
As soon as the user clicks on any of the Check Boxes, the Main Selection window
changes as shown in ( Figure 5-2, page -41 ).
40
Figure 5-2:
Based on the selected logic schemes the software displays Test Boxes with
the test cases associated with each selected scheme on the left side of the
schemess Check Boxes. Each individual test case can be un-selected by
clicking its check box. ( See also Figure 5-2, page - 41 ).
When all tests have been completed, the Test Details window will display
the test summary.
If a mistake is made in the selection process:
1.
2. Another option is to click on [Clear] at the bottom of the window, that will result
in displaying the default value.
41
OMICRON DLogicPro
VII
1. As soon as the [Start Test] is clicked, a Message Box ( See also Figure 7-1,
page - 42 ) will appear before the beginning of the test asking the test engineer
or technician to check if the CMC is on.
If the CMC is on, just click [Yes]. Otherwise turn on the CMC and then click
[Yes], so that the tests may be performed.
The second option is to select [No], which will disable the [Start Test]
button and reset the selected test cases.
Figure 7-1:
CMC On - Off
2. After the CMC is turned On, it is initialized and starts the preprogrammed and
selected tests execution.
42
1. Before the execution of each group of tests associated with a specific logic
scheme, the user is reminded by the software ( Figure 8-1, page -43 ) to
enable the logic scheme setting of the distribution feeder protection relay to
match the expected by the test scheme.
Figure 8-1:
2. If the scheme has already been enabled or after the change, proceed by
clicking on the [OK] command button.
IX Tests Execution
1. The running test will display a flashing yellow background. At the same time to
the right of the selected test cases a small screen TEST Status will show a
brief description of each test.
Note: Before the execution of an individual test the background of the Test Box is white.
2. Immediately after each individual test is completed, the result is analyzed and
the background of the Test Box changes color.
If the relay operated as expected, the test is [OK] and the background turns
green.
If there is any out of range operation the test fails and the Test Box
background turns red.
After the completion of all tests the results are visible as the background color of
the Test Boxes.
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OMICRON DLogicPro
If the Multiple Schemes test is successful, the background of all Test Boxes should
be green.
Figure 9-1:
The Test Details window at the same time displays a message All tests are OK
( See Figure 9-1, page - 44 )
If even one test has failed, the Test Details window displays a different message. It
advises the user to check the relay logic, settings, etc., and the test objectives, and
results in the Test report.
3. If necessary, the test engineer can preview the Test report, print it and save it
as a file.
4. After all tests have been executed, the [Print Report] button in the Main
Selection window is enabled so that the test report can be previewed and/or
printed.
5. When the Print Report button is checked the Data Entry form is displayed as
well.
44
1. Before the test results are previewed or printed, the user is asked to fill in the
generic data for the test report.
Some of the entries are required and are supposed to be entered in the
white fields.
The rest of the fields are optional and have gray background, as shown on
( Figure 10-1, page -45 ).
The software will keep the entered information for a specific field, if the
Check Box in front of the field is checked.
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OMICRON DLogicPro
The software allows the user to save as a file for further use the most
frequently used information, (as shown in the detail ( Figure 10-2,
page -46 )
2. When [Close] is pushed a message will appear, warning that the data related
to the completed tests will be lost.
The measured operating times, the monitored protection functions for each
individual test are stored in the memory of the computer and are available in the
test report.
1. To preview these detailed test results, click the [Preview Report] command
button in the Data Entry form.
2. As a result, the Test Report window shown in ( Figure 11-1, page -47 ) and (
Figure 11-2, page -47 ) is displayed. You can scroll through the report as
necessary.
46
Figure 11-1:
47
OMICRON DLogicPro
1. Click on [Save As File] in the Data Entry window ( See also Figure 10-1,
page - 45 )
2. The Save As window will open allowing the user to choose a directory and file
format.
3. Unless changed, the File will be saved as Rich Text Format.
To print the results from the Multiple Test, click the [Print Report] in the Data
Entry form ( Figure 10-1, page -45 ). The Print dialog box is displayed, allowing
the user to specify a printer, if necessary.
XV Help
OMICRON DLogicPro software offers brief on-line explanations for the major tasks
to be performed. The Help Topics are accessible only through the Menu in the
Main Selection window. To see the different topics, click on DLogicPro Help
Topics... ( See also Figure 15-1, page - 49 )
48
Figure 15-1:
The help window opens with brief overview of the software, displayed in the front
page. ( See also Figure 15-2, page - 49 ).
Figure 15-2:
49
OMICRON DLogicPro
To view the available Help Topics, click on HelpTopics in the menu of the Help
window. ( See also Figure 15-3, page - 50 )
The full topic, or a selection of the content of the topic, can be printed from that
window as well. Some of the topics include additional sub topics with detailed
instructions as follows.
The Animation Mode offers:
Overview
Animation Scheme
Animation Controls
Animation Speed
The Test Mode offers:
Overview
Fault Currents/Voltages
Select Test Cases
Start Selected Tests
The Settings offer:
Overcurrent Settings
Time Test Settings
Nominal Values Settings
50
Overview
Data Entry
Print Preview
Print Test Results
When a specific topic is selected and displayed, its name is shown on the top of
the Help window and appears disabled in the HelpTopics menu. ( See also
Figure 15-4, page - 51 ).
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OMICRON DLogicPro
To perform such a test, the user should follow the step-by-step procedure
described below.
To achieve this task, the following steps should be performed:
.
1. Wire the Test Object (distribution feeder relay), DC power supply (if necessary)
and the Test Device (CMC x56) according to the diagrams shown in Hardware
Requirements for the communication aided scheme to be tested.
2. Connect the parallel cable between the Test Device and the Test Computer
with DLogicPro installed.
52
Note: Check if the relay uses 52a or 52b breaker status contacts. DLogicPro simulates
52a breaker status only.
Note: In the cases when the voltage signals are optional, the wiring between the test object
device is shown in grey.
Since a single scheme is tested, use the Hardware Requirements for the selected
scheme.
The analysis of the distribution feeder relay performance during the Single
Scheme test is based on the expected operating times under different fault
conditions.
The software is loaded using some default settings. However, if the user needs to
change them based on the technical specifications of the distribution feeder relay
under test, the default setting can be changed using the steps described in the
Multiple schemes test chapter ( See also Figure 4-1, page - 33 )
( See also Figure 4-2, page - 34 )
( See also Nominal Values (Voltage/Frequency) Secondary Settings window ,
page -35 )
( See also Nominal Values (Voltage/Frequency) Primary Settings window ,
page -36 )
( See also Overcurrent Settings , page -37 )
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OMICRON DLogicPro
V Scheme Selection
Figure 5-1:
2. The [Start Test] button remains disabled, when the check boxes are
unchecked.
3. As soon as you click on one of the Scheme Name Box, the Individual Scheme
Control Window will open as shown in ( Figure 5-2, page -55 ).
54
Figure 5-2:
4. If you want to return to the Main Selection window at any time, just click on
[Main]
.
DLogicPro allows the user to select from the available tests before starting the
tests execution.Click on [Select Test Case] in the Test Options frame to Start Test
Procedures.
Several changes occur in the Scheme Control Window as a result
of the Select Test Case action:
1. Based on the selected distribution feeder protection logic scheme the software
displays several Test Boxes with the test cases associated with the selected
scheme, on the left side of the graphical display window in a Test Options
frame. Each individual test case can be unselected by clicking its own check
55
OMICRON DLogicPro
Figure 6-1:
Faults Currents and Voltages for the first selected test case
Figure 6-2:
If necessary, unselect a test case to prevent its execution (all Test Cases are
selected as default).
56
VII
1. As soon as [Start Test] is clicked, a Message Box ( Figure 7-1, page -57 ) will
appear before the beginning of the test asking the test engineer or technician
to turn the CMC On.
If the CMC is on, just click [Yes]. Otherwise turn on the CMC and then click
[Yes], so that the tests may be performed.
The second option is to select [No], which will disable the [Start Test]
button and reset the selected test cases.
Figure 7-1:
CMC On - Off
57
OMICRON DLogicPro
1. Before the execution of the selected test cases associated with the selected
logic scheme, the user is reminded by the software ( Figure 8-1, page -58 ) to
enable the logic scheme of the distribution feeder protection relay to match
the expected by the test scheme.
Figure 8-1:
IX Tests Execution
Note: Before the execution of an individual test the background of the Test
Box is white.
2. Immediately after each individual test is completed, the result is analyzed and
the background of the Test Box changes color.
If the relay operated as expected, the test is OK and the background turns
green.
If there is any out of range operation the test fails and the Test Box
background turns red.
After the completion of all tests the results are visible as the background color of
the Test Boxes. If the scheme test is successful, the background of all Test Boxes
should be green.
58
Figure 9-1:
The Test Details window at the same time displays a message All tests are OK
( See Figure 9-1, page - 59 ).
If even one test has failed, the Test Details window displays a different message.
It advises the user to check the relay logic, settings, etc., the test objectives, and
results in the Test report.
3. If necessary, the test engineer can preview the Test report, print it and save it
as a file.
4. After all tests have been executed, the [Print Report] in the Main Selection
window is enabled so that the test report can be previewed and/or printed,
5. When the [Print Report] button is pushed the General Data Entry form is
displayed as well.
59
OMICRON DLogicPro
1. Before the test results are previewed or printed, the user is asked to fill in the
generic data for the test report.
Some of the entries are required and are supposed to be entered in the
white fields.
The rest of the fields are optional and have gray background as shown on (
Figure 10-1, page -60 ).
The software will keep the entered information for a specific field, if the
Check Box in front of the field is checked.
Figure 10-1:
2. If [Close] is pushed a message will appear, warning that the data related to the
completed tests will be lost.
The most frequently used data can be saved for future use, by clicking the [Save
General Report Data] in the Data Entry form. ( Figure 10-2, page -46 )
60
The measured operating times of each individual test are stored in the memory of
the computer and are available in the test report.
1. To preview these detailed test results, click on [Preview Report] in the Data
Entry form.
2. As a result, the Data Entry window shown in ( Figure 11-1, page -61 ) and (
Figure 11-2, page -62 ) is displayed. You can scroll through the report as
necessary.
Figure 11-1:
61
OMICRON DLogicPro
Figure 11-2:
1. Click on [Save As File] button in the Data Entry window ( See Figure 10-1,
page - 60 )
2. The Save As window will open allowing the user to chose directory and file
format.
3. Unless changed, the File will be saved as Rich Text Format.
62
To print the results from the test, click [Print Report] in the Data Entry form on (
Figure 10-1, page -60 ). The print dialog box is displayed, allowing the user to
specify a printer, if necessary.
XV Help
OMICRON DLogicPro software offers brief on-line explanations for the major
tasks to be performed. The Help Topics are accessible only through the Menu in
the Main Selection window.
Figure 15-1: Help Options under the Menu in the Main Selection window
To open the Help window with the available help topics, click on [DLogicPro Help
Topics.... ( See also Figure 15-1, page - 63 ).
To check the different Help Topics, click on HelpTopics in the menu of the help
window.( See also Figure 15-2, page - 64 ).
63
OMICRON DLogicPro
The full topic, or a selection of the content of the topic, can be printed from that
window as well.
64
The objective is to perform dynamic tests to evaluate the Cold Load Pickup logic
scheme of a distribution feeder relay, as a function of the conditions during line
energization, fault condition or combination of the two.
The Test Object is a multifunctional distribution feeder relay with CLP scheme.
The distribution system conditions and the breaker status signal are simulated by
the CMC.
65
OMICRON DLogicPro
inrush load current, but on the magnitude of the maximum load current after the
inrush condition is over.
Another alternative for avoiding the operation of the low set overcurrent elements
during line energization is instead of blocking the overcurrent element to increase
the setting for a certain time. This provides improved sensitivity, because the
higher setting of the low set elements is typically still lower than the setting of the
high set instantaneous element.
The logic requires breaker status information. The typical breaker status
monitoring function in relays is based on a normally open (52a) auxiliary contact of
the breaker. Some relays may monitor a normally closed (52b) or both auxiliary
contacts (this provides more reliable breaker status indication).
Simplified diagram of the Cold Load Pickup logic is shown in ( Figure 0-1,
page -66 ).
Substation A
Load
IA
IB
IC
52A
Breaker
Closed
Timer
CLP
Trip
TOC
IOC
Figure 0-1:
Fault Locations
Remote faults are simulated along the model distribution feeder with magnitudes
of the fault current that should result in the operation of the low set overcurrent
elements.
66
Substation A
Load
IA
IB
IC
Relay
Figure 0-2:
Test Cases
The Cold Load Pickup Logic scheme is tested for the following fault conditions:
1. For Line energization: - the relay should not trip.
2. For Line energization with fault: - the relay should not trip after closing of the
breaker, but after the fault is applied.
3. For Line fault: the relay should trip.
Hardware Requirements
The CMC test device is programmed to simulate the substation and power system
environment through the analog and binary outputs. At the same time the binary
inputs are used to monitor the operation of the test object.
A typical wiring diagram for the Cold Load Pickup logic test is shown on ( Figure
0-3, page -68 )
The CMC simulates the status of the normally open auxiliary contact for the
breaker (52-A), and the currents and voltages during the pre-fault, fault and
post-fault stages of the simulation.
Since many distribution feeder protection relays are current relays only, the
voltage inputs might not be available. That is why even that voltage outputs are
controlled by the testing software, the wiring of the voltage outputs of the CMC to
the distribution feeder relay is optional.
The potential free binary output of the CMC has one terminal connected to (+) DC
and the second terminal to the (+) DC terminal of the associated relay input. The
second terminal of the relay input is connected to (-) DC.
67
OMICRON DLogicPro
IA
CM C
Analog
O utputs
IA
IB
IB
IC
IC
IN
Digital
Inputs
Figure 0-3:
O ut 1
Analog
Inputs
IN
VA
VB
VC
VN
VA
VB
VC
VN
Digital
O utputs
RELAY
+ DC
- DC
In 1
52a
Digital
Inputs
Trip
Relay
O utputs
The Trip output of the relay is wired to a Trip sense input of the CMC and is used to
change from fault to post-fault state, as well as to measure the operating time in
order to evaluate the correct operation of the Cold Load Pickup logic during the
test.
The automatic test sequences for each test will have several different steps as
shown with animation in the DLogicPro software.
68
The only setting that has to be added for this group of test cases is the enabling of
the Cold Load Pickup logic and the associated with it relay settings based on the
recommendations in the relay service manual.
One relay input has to be programmed as normally open (52a) breaker status
monitoring input.
One relay output should be programmed to provide Trip
69
OMICRON DLogicPro
The objective is to perform dynamic tests to evaluate the Feeder Blocking Scheme
of a distribution feeder relay, as a function of the fault location and receiving or not
receiving of a blocking signal from the downstream feeder relay.
The Test Object is a multifunctional distribution feeder relay with Feeder Blocking
Scheme available and enabled.
BF Logic Description
(BF - Feeder Blocking Scheme Logic)
In distribution systems multiple sections of a loop are connected and fed from a
single source. Depending on where the loop is opened, the coordination required
between the different relays protecting the different sections of the loop may result
in significant increase of the fault clearing time for certain faults closer to the
source. These long times represent a power quality problem and may affect the
customers fed by the circuit.
In an effort to speed-up the fault clearing time, utilities are implementing a Blocked
Overcurrent protection scheme. It requires exchange of control signals between
the relays protecting the distribution circuit, i.e. some form of communications
between the devices on the loop.
Blocked overcurrent protection involves the use of start indication from
downstream relays provided as a blocking input of upstream relays. The idea is to
allow identical current and time settings to be employed on each of the relays
involved in the scheme. The relay nearest to the fault does not receive a blocking
signal and will trip the appropriate switching device in order to clear the fault. Any
other relay further away from the fault and closer to the source will receive a
blocking signal and will not trip for a certain time, thus allowing the downstream
device to clear the fault.
The advantage of this type of scheme therefore is that it reduces the amount of
required grading stages and consequently the fault clearance times.
Each overcurrent element of the devices that implement a Blocked Overcurrent
Scheme has to be set with a certain time delay that allows the receiving of a
blocking signal from a downstream device. At the same time each device should
be able to communicate the starting of an overcurrent element that is used to block
an upstream device.
The above requirements are taken into consideration in the design of the module
for testing of the Feeder Blocking Scheme logic in modern distribution feeder
protection relays.
70
Simplified diagram of the Feeder Blocking Scheme logic is shown in ( Figure 0-4,
page -71 ).
Substation A
Load
100
130
Trip
Trip
TOC
TOC
Start
AND
TOC
Trip
TOC Block
Figure 0-4:
Fault Locations
Faults are simulated at two locations along the model distribution line:
Substation A
Iflt
Iflt
Relay
Relay
Figure 0-5:
Load
Test Cases
The Feeder Blocking Scheme is tested for the following fault conditions:
1. For fault on own feeder: - the relay should trip.
2. For fault on next feeder: - the relay should not trip.
71
OMICRON DLogicPro
Hardware requirements
IA
CMC
Analog
Outputs
IA
IB
IB
IC
IC
IN
Out 1
Out 3
Digital
Inputs
Figure 0-6:
In 1
Analog
Inputs
IN
VA
VB
VC
VN
Digital
Outputs
RELAY
VA
VB
VC
VN
Digital
Inputs
+ DC
- DC
52a
+ DC
- DC
TOCBlock
Trip
Relay
Outputs
The CMC test device is programmed to simulate the substation and power system
environment through the analog and binary outputs. At the same time the binary
inputs are used to monitor the operation of the test object.
A typical wiring diagram for the Feeder Blocking Scheme logic test is shown on (
Figure 0-6, page -72 ).
The CMC simulates the status of the normally open auxiliary contact for the
breaker (52-A) and the Blocking signal received from the starting overcurrent
elements of the downstream protective relay.
The currents and voltages during the pre-fault, fault and post-fault stages of the
simulation are also provided by the CMC. However, the voltages are not required
for the testing of the scheme, since it is based on the operation of overcurrent
elements only. That is why they are shown in gray on the wiring diagram.
The potential free relay outputs of the CMC have one terminal connected to (+) DC
and the second terminal to the (+) DC terminal of the associated relay input. The
second terminal of the relay input is connected to (-) DC.
72
The Trip output of the relay is wired to a Trip sense input of the CMC and is used to
change from fault to post-fault state, as well as to measure the operating time and
evaluate the correct operation of the Feeder Blocking Scheme logic during the
test.
The automatic test sequences will have several different steps shown with
animation in the DLogicPro software.
The only setting that has to be changed for this group of test cases is the enabling
of the Feeder Blocking Scheme logic and the associated with it relay settings
based on the recommendations in the relay service manual. The time delay setting
should be sufficient to allow the starting element of the downstream relay to
operate and the opto input monitoring logic to detect it.
One relay input has to be programmed as a normally open (52a) breaker status
monitoring input. A second relay input should be programmed to monitor the
Blocking signal from the downstream protective device.
One relay output should be programmed to provide Trip signal monitored by the
CMC for the evaluation of the relay operation.
73
OMICRON DLogicPro
SYMPATHETIC TRIP
Objective
The objective is to perform dynamic test to evaluate the Sympathetic Trip scheme
of a distribution feeder relay, as a function of the fault location and receiving or not
receiving of a Sympathetic Trip blocking signal from the adjacent feeder relay.
The Test Object is a multifunctional distribution feeder relay with Sympathetic Trip
Scheme available and enabled.
SP Logic Description
(SP - Sympathetic Trip)
Distribution feeders are typically protected by phase and ground overcurrent
elements with instantaneous, definite time delayed or inverse time characteristics.
The low set time delayed elements are used to provide overload protection or
protection for line end faults, while the instantaneous elements should provide
high-speed fault clearing for close-in faults.
The pickup settings of the low set elements are defined by the loading of the
distribution feeder and the levels of the minimum fault currents for faults at the end
of the protected feeder.
The Cold-Load Pickup logic of the relays is designed to prevent the undesired
operation of the low set overcurrent elements during the inrush condition following
the closing of the feeder breaker. After the time expires, the overcurrent elements
are unblocked and can protect the line in the cases of overload or low current fault
conditions. The advantage of this scheme is that the low set overcurrent elements
are based not on the maximum inrush load current, but on the magnitude of the
maximum load current after the inrush condition is over.
However, there are certain cases when inrush current can flow through the relay
after the feeder has been in service for a while. For example, if a fault occurs on
any feeder connected to a distribution bus, it will take some time for the relay
protecting the feeder to detect the fault and the breaker to clear it. During that time
the distribution system is exposed to low voltage. When the breaker of the faulted
feeder trips, the voltage returns to its nominal level and many of the feeders may
experience an inrush, especially feeders with predominantly motor loads. This
condition may result in the operation of the overcurrent relays on healthy feeders.
To avoid such misoperation, advanced distribution feeder relays are equipped with
a Sympathetic Trip logic.
The principle of operation of this logic is based on the receiving of a blocking signal
from a distribution feeder relay that had detected and issued a trip signal for a fault
on the feeder it is protecting.
74
Sympathetic Trip
When the opto input of the relay on a healthy feeder is energized, it will block one
or more overcurrent protection elements for a user defined period of time. This
time should be longer than the expected inrush condition time. After the time
expires, the overcurrent elements are unblocked and can protect the line in the
cases of overload or low current fault conditions.
The logic requires a Sympathetic Trip blocking signal from a relay on an adjacent
faulted feeder.
The above requirements are taken into consideration in the design of the module
for testing of the Sympathetic Trip logic in modern transmission line protection
relays.
Simplified logic for the Sympathetic Trip scheme is shown in ( Figure 0-7,
page -75 ).
Substation A
IFdr1
Load
IFdr2
IFdr3
Trip
Fdr Prot.
STL Block
Timer
STL
TOC
IOC
Figure 0-7:
Fault Locations
Faults are simulated at two location on the substation bus:
1. Fault on an adjacent line
2. Fault on the protected line
75
OMICRON DLogicPro
Substation A
IFdr1
Load
IFdr2
IFdr3
Relay
Relay
Figure 0-8:
The three fault locations are shown on ( Figure 0-8, page -76 ).
Test Cases
The Sympathetic Trip Logic scheme is tested for the following fault conditions:
1. For Fault on Own Feeder: - the relay should trip.
2. For Fault on Adjacent Feeder: - the relay should not trip for the inrush current.
3. For Sympathetic Trip Logic Block with Feeder Fault: - the relay should trip after
the fault on own feeder.
Hardware Requirements
The CMC test device is programmed to simulate the substation and power system
environment through the analog and binary outputs. At the same time the binary
inputs are used to monitor the operation of the test object.
A typical wiring diagram for the Sympathetic Trip logic test is shown on ( Figure
0-9, page -77 ).
The CMC simulates the status of the normally open auxiliary contact for the
breaker (52-A), the Sympathetic Trip blocking signal from the adjacent relay and
the currents and voltages during the pre-fault, fault and post-fault stages of the
simulation.
Since the logic is based on overcurrent elements only, the voltage signals from the
CMC are optional.
The potential free relay outputs of the CMC have one terminal connected to (+) DC
and the second terminal to the (+) DC terminal of the associated relay inputs. The
second terminal of the relay inputs are connected to (-) DC.
76
Sympathetic Trip
The Trip output of the relay is wired to a Trip sense input of the CMC and is used to
change from fault to post-fault state, as well as to measure the operating time and
evaluate the operation of the Sympathetic Trip logic during the test.
IA
CM C
A nalog
O utp uts
IA
IB
IB
IC
IC
IN
D igital
Inp uts
Figure 0-9:
A nalog
Inp uts
IN
VA
VB
VC
VN
D igital
O utp uts
RELAY
VA
VB
VC
VN
O ut 1
+ DC
- DC
52a
O ut 2
+ DC
- DC
ST L
In 1
T rip
D igital
Inp uts
R elay
O utp uts
The automatic test sequence will have several steps shown with animation in the
D-LogicPro software.
The only setting that has to be changed for this group of test cases is the enabling
of the Sympathetic Trip logic and the associated with it relay settings based on the
recommendations in the relay service manual.
One relay input has to be programmed as normally open (52a) breaker status
monitoring input. A second input should be programmed to receive a Sympathetic
Trip blocking signal.
77
OMICRON DLogicPro
78
79
OMICRON DLogicPro
Substation A
IA
Load
r
IC
Ia, Ib, Ic
Trip
Ground OC
BCD
Negative Seq. OC
Fault Locations
Shunt and series faults are simulated along the model distribution feeder as shown
below:
1. Broken conductor fault
2. Short circuit fault
The fault locations are shown on ( Figure 0-10, page -80 ) and ( Figure 0-11,
page -80 )
Substation A
Load
IA
IB
IC
Relay
Figure 0-11: Fault location for the testing of the Broken Conductor detection logic
80
Test Cases
The Broken Conductor Detection scheme is tested for the following fault condition
1. For ground fault: - the relay should trip.
2. For broken conductor: - the relay should not trip and should indicate Broken
Conductor.
3. For broken conductor with ground fault: - the relay should indicate Broken
Conductor and then trip after the fault.
Hardware Requirements
The CMC test device is programmed to simulate the substation and power system
environment through the analog and binary outputs. At the same time the binary
inputs are used to monitor the operation of the test object.
A typical wiring diagram for the Broken Conductor Detection logic test is shown on
( Figure 0-12, page -82 ).
The CMC simulates the status of the normally open auxiliary contact for the
breaker (52-A), and the currents and voltages during the pre-fault, fault and
post-fault stages of the simulation.
Since the logic is based on overcurrent elements only, the voltage signals from the
CMC are optional.
The potential free relay output of the CMC has one terminal connected to (+) DC
and the second terminal to the (+) DC terminal of the associated relay input. The
second terminal of the relay input is connected to (-) DC.
The Trip and the Broken Conductor Detection outputs of the relay are wired to
sense inputs of the CMC and are used to change from fault to post-fault state, as
well as to measure the operating time and evaluate the operation of the Broken
Conductor Detection logic during the test.
81
OMICRON DLogicPro
IA
CMC
Analog
Outputs
IA
IB
IB
IC
IC
IN
Digital
Inputs
Out 1
Analog
Inputs
IN
VA
VB
VC
VN
Digital
Outputs
RELAY
VA
VB
VC
VN
+ DC
- DC
52a
In 1
Trip
In 3
BCD
Digital
Inputs
Relay
Outputs
Figure 0-12: Hardware wiring diagram for testing of Broken Conductor Detection logic
The automatic test sequences will have several steps shown with animation in the
D-LogicPro software.
82
Selective Overcurrent
SELECTIVE OVERCURRENT
Objective
SO Logic Description
(SO - Selective Overcurrent)
In distribution systems multiple sections of a loop are connected and fed from a
single source. Depending on where the loop is opened, the coordination required
between the different relays protecting the different sections of the loop may result
in significant increase of the fault clearing time for certain faults closer to the
source. These long times represent a power quality problem and may affect the
customers fed by the circuit.
In an effort to speed-up the fault clearing time, utilities are implementing a Blocked
Overcurrent protection scheme. It requires exchange of control signals between
the relays protecting the distribution circuit, i.e. some form of communications
between the devices on the loop.
An alternative to the Blocked Overcurrent scheme is the Selective Overcurrent
Logic. In this case the start contacts from a downstream relay are used to increase
the time delays of upstream relays, instead of blocking them.
The Selective Overcurrent Logic function temporarily increases the time delay
settings of one or more phase and ground overcurrent elements. This logic is
initiated by energizing the appropriate logic input of the upstream relay.
The relay nearest to the fault does not receive a Selective Overcurrent initiate
signal and will trip the appropriate switching device in order to clear the fault. Any
other relay further away from the fault and closer to the source will receive the
signal and because of the increased time delay will not trip for a certain time, thus
allowing the downstream device to clear the fault.
Each overcurrent element of the devices that implement a Selective Overcurrent
Scheme has to be set with a certain time delay that allows the receiving of a signal
from a downstream device. At the same time each device should be able to
communicate the starting of an overcurrent element that is used to block an
upstream device.
83
OMICRON DLogicPro
The above requirements are taken into consideration in the design of the module
for testing of the Selective Overcurrent logic in modern transmission line protection
relays.
Load
TOC
Start
Logic
Select
I
Trip
Trip
TOC
Start
Timer
Select
Timer
TOC
Trip
Trip
Logic Select
Fault Locations
Faults are simulated at two location along the model distribution feeder:
1. Feeder fault at the end of the own protected section
2. Feeder fault at the beginning of the next section
Substation
Iflt
Relay
Iflt
Relay
84
Load
Selective Overcurrent
Test Cases
The Selective Overcurrent scheme is tested for the following fault conditions
1. For fault on own feeder: - the relay should trip.
2. For fault on next feeder: - the relay should not trip (next feeder trip).
3. For fault on next feeder with next feeder breaker failure: - the relay should trip
with the Selective Overcurrent time delay.
Hardware Requirements
The CMC test device is programmed to simulate the substation and power system
environment through the analog and binary outputs. At the same time the binary
inputs are used to monitor the operation of the test object.
A typical wiring diagram for the Selective Overcurrent logic test is shown on (
Figure 0-15, page -86 ).
The CMC simulates the status of the normally open auxiliary contact for the
breaker (52-A) and the Selective Overcurrent initiate signal received from the
starting overcurrent elements of the downstream protective relay.
The currents and voltages during the pre-fault, fault and post-fault stages of the
simulation are also provided by the CMC. However, the voltages are not required
for the testing of the scheme, since it is based on the operation of overcurrent
elements only. That is why they are shown in gray on the wiring diagram.
The potential free relay outputs of the CMC have one terminal connected to (+) DC
and the second terminal to the (+) DC terminal of the associated relay input. The
second terminal of the relay input is connected to (-) DC.
The Trip output of the relay is wired to a Trip sense input of the CMC and is used to
change from fault to post-fault state, as well as to measure the operating time and
evaluate the operation of the Selective Overcurrent Scheme logic during the test.
85
OMICRON DLogicPro
IA
CM C
Analog
O utputs
IA
IB
IB
IC
IC
IN
O ut 1
O ut 3
Digital
Inputs
Analog
Inputs
IN
VA
VB
VC
VN
Digital
O utputs
RELAY
VA
VB
VC
VN
Digital
Inputs
+ DC
- DC
52a
+ DC
- DC
TO CBlock
In 1
Trip
Relay
O utputs
The automatic test sequences will have several different steps shown with
animation in the DLogicPro software.
The only setting that has to be changed for this group of test cases is the enabling
of the Selective Overcurrent Scheme logic and the associated with it relay settings
based on the recommendations in the relay service manual. The time delay setting
should be sufficient to allow the starting element of the downstream relay to
operate and the opto input monitoring logic to detect it.
One relay input has to be programmed as a normally open (52a) breaker status
monitoring input. A second relay input should be programmed to monitor the
Selective Overcurrent initiate signal from the downstream protective device.
One relay output should be programmed to provide Trip signal monitored by the
CMC for the evaluation of the relay operation.
86
87
OMICRON DLogicPro
Substation A
IFdr1
Ix-er
IFdr2
IFdr3
Trip
TOC
Start
TOC
Start
Timer
Blocking
Logic
Fault Locations
Faults are simulated at two locations in the distribution system:
1. On the distribution bus
2. On a distribution feeder
88
The three fault locations are shown on ( Figure 0-17, page -89 )
Load
Substation
ILoad
Load
ILoad
IFlt
IFlt
Relay
Relay
Figure 0-17: Fault location for the testing of the Distribution Bus Protection logic
Test Cases
The Distribution Bus Protection scheme is tested for the following fault conditions:
1. For fault on the bus: - the relay should trip.
2. For fault on feeder: - the relay should not trip (feeder trip).
Hardware Requirements
The CMC test device is programmed to simulate the substation and power system
environment through the analog and binary outputs. At the same time the binary
inputs are used to monitor the operation of the test object.
A typical wiring diagram for the Distribution Bus Protection logic test is shown on (
Figure 0-18, page -90 ).
The CMC simulates the status of the normally open auxiliary contact for the
breaker (52-A) and the Blocking signal received from the starting overcurrent
elements of the distribution feeder protection relays.
The currents and voltages during the pre-fault, fault and post-fault stages of the
simulation are also provided by the CMC. However, the voltages are not required
for the testing of the scheme, since it is based on the operation of overcurrent
elements only. That is why they are shown in gray on the wiring diagram.
The potential free relay outputs of the CMC have one terminal connected to (+) DC
and the second terminal to the (+) DC terminal of the associated relay input. The
second terminal of the relay input is connected to (-) DC.
The Trip output of the relay is wired to a Trip sense input of the CMC and is used to
change from fault to post-fault state, as well as to measure the operating time and
evaluate the operation of the Distribution Bus Protection Scheme during the test.
89
OMICRON DLogicPro
IA
CM C
A nalog
O utp uts
IA
IB
IB
IC
IC
IN
O ut 1
O ut 3
D igital
Inp uts
A nalog
Inp uts
IN
VA
VB
VC
VN
D igital
O utp uts
RELAY
VA
VB
VC
VN
+ DC
- DC
+ DC
- DC
In 1
52a
D igital
Inp uts
T O CB lock
T rip
R elay
O utp uts
Figure 0-18: Hardware wiring diagram for testing of the Distribution Bus Protection
The automatic test sequences will have several steps shown with animation in the
D-LogicPro software.
The only setting that has to be changed for this group of test cases is the enabling
of the Distribution Bus Protection logic and the associated with it relay settings
based on the recommendations in the relay service manual. The time delay setting
should be sufficient to allow the starting element of the distribution feeder relay to
operate and the opto input monitoring logic to detect it.
One relay input has to be programmed as a normally open (52a) breaker status
monitoring input. A second relay input should be programmed to monitor the
Blocking signal from the distribution feeder protection relay.
One relay output should be programmed to provide Trip signal monitored by the
CMC for the evaluation of the relay operation.
90
The objective is to perform dynamic test to evaluate the Backup Selective Tripping
scheme of a distribution feeder relay, as a function of the fault condition, relay
failure or combination of the two.
The Test Object is a multifunctional distribution feeder relay with Backup Selective
Tripping scheme available and enabled.
91
OMICRON DLogicPro
The above requirements are taken into consideration in the design of the module
for testing of the Backup Selective Tripping logic in modern transmission line
protection relays.
Simplified logic for the Block reclosing scheme is shown in ( Figure 0-19,
page -92 ).
Substation A
Load
IFdr1
IFdr2
IFdr3
Trip
TOC
Start
Timer2
Timer1
Trip
Feeder
Prot.
Relay
Failed
Fault Locations
Faults are simulated at:
1. Fault on a distribution feeder
Substation
ILoad
Load
ILoad
IFlt
IFlt
Relay
Relay
Figure 0-20: Fault locations for the testing of Backup Selective Tripping logic
92
Test Cases
The Backup Selective Tripping scheme is tested for the following fault conditions:
1. For feeder fault with relay OK: - the relay should not trip.
2. For feeder fault with relay failed: - the relay should trip with selected feeder trip
output.
3. For feeder fault with relay failed and breaker failure: - the relay should trip with
selected feeder trip output, and then with own trip output.
Hardware Requirements
The CMC test device is programmed to simulate the substation and power system
environment through the analog and binary outputs. At the same time the binary
inputs are used to monitor the operation of the test object.
A typical wiring diagram for the Backup Selective Tripping logic test is shown on (
Figure 0-21, page -94 ).
The CMC simulates the status of the normally open auxiliary contact for the
breaker (52-A) and the Relay Failure alarm signal received from the distribution
feeder relay.
The currents and voltages during the pre-fault, fault and post-fault stages of the
simulation are also provided by the CMC. However, the voltages are not required
for the testing of the scheme, since it is based on the operation of overcurrent
elements only. That is why they are shown in gray on the wiring diagram.
The potential free relay outputs of the CMC have one terminal connected to (+) DC
and the second terminal to the (+) DC terminal of the associated relay inputs. The
second terminal of the relay inputs are connected to (-) DC.
The Trip and Selective Feeder Trip outputs of the relay are wired to sense inputs of
the CMC and are used to change from fault to post-fault state, as well as to
measure the operating time and evaluate the operation of the Feeder Blocking
Scheme logic during the test.
93
OMICRON DLogicPro
IA
CM C
A nalog
O utp uts
IA
IB
IB
IC
IC
IN
D igital
Inp uts
A nalog
Inp uts
IN
VA
VB
VC
VN
D igital
O utp uts
R ELA Y
VA
VB
VC
VN
O ut 1
+ DC
- DC
52a
O ut 3
+ DC
- DC
R elayFail
In 1
In 2
T rip
Digital
Inp uts
Relay
O utp uts
Fdr T rip
Figure 0-21: Hardware wiring for testing of the Backup Selective Tripping logic
The automatic test sequences will have several steps shown with animation in the
D-LogicPro software.
The only setting that has to be changed for this group of test cases is the enabling
of the Backup Selective Tripping logic and the associated with it relay settings
based on the recommendations in the relay service manual.
One relay input has to be programmed as normally open (52a) breaker status
monitoring input. A second relay input is used to monitor the status of the feeder
relay - healthy or alarm.
94
One relay output should be programmed to provide Trip, while a second output
should issue a Trip signal for the selected breaker of a distribution feeder with a
failed relay.
95
OMICRON DLogicPro
96
Load
Ia
Ib
Ic
TBF
Prot Trip
Ext BF Start
BF Trip
52
IOC
BF Trip
Fault Locations
Faults are simulated at one location along the model distribution feeder:
1. Close-in single-phase-to-ground fault
97
OMICRON DLogicPro
Substation A
IA
Load
r
IB
IC
Relay
Figure 0-23: Fault location for the testing of the Breaker Failure Protection logic
Test Cases
The Breaker Failure Protection is tested for the following fault conditions:
1. For close-in fault: - the relay should trip and should not initiate adjacent breaker
trip.
2. For close-in fault with Breaker Failure: - the relay should trip and should also
initiate adjacent breaker trip.
3. For Overvoltage with Breaker Failure: - the relay should trip and should also
initiate adjacent breaker trip.
Hardware Requirements
The CMC test device is programmed to simulate the substation and power system
environment through its analog and binary outputs. At the same time the binary
inputs are used to monitor the operation of the test object.
A typical wiring diagram for the Breaker Failure Protection logic test is shown on (
Figure 0-24, page -99 ).
The potential free relay output of the CMC has one terminal connected to (+) DC
and the second terminal to the (+) DC terminal of the associated relay input. The
second terminal of the relay input monitoring the breaker status is connected to (-)
DC.
The Trip output of the relay and the Breaker Failure Trip output are wired to two of
the sense inputs of the CMC and are used to change from fault to post-fault state,
as well as to measure the operating time and evaluate the operation of the Breaker
Failure Protection logic during the test.
98
IA
CMC
Analog
Outputs
Digital
Outputs
Digital
Inputs
IA
IB
IB
IC
IC
IN
RELAY
Analog
Inputs
IN
VA
VB
VC
VN
VA
VB
VC
VN
Out 1
52a
+ DC
- DC
In 1
Trip
In 5
BFP
Digital
Inputs
Relay
Outputs
Figure 0-24: Hardware wiring diagram for testing of the Breaker Failure Protection logic
The automatic test sequences will have several different steps shown with
animation in the DLogicPro software.
The only settings that have to be changed for this group of test cases is the
enabling of the Breaker Failure Protection logic and the associated with it relay
settings based on the recommendations in the relay service manual.
One relay input has to be programmed as normally open (52a) breaker status
monitoring input.
One relay output should be programmed to provide Trip, while a second output
should give the indication for detected Breaker Failure Protection trip.
99
OMICRON DLogicPro
The expected Breaker Failure Protection time delay setting is 150 ms.
100
Switch-On-To-Fault
SWITCH-ON-TO-FAULT
Objective
101
OMICRON DLogicPro
Substation A
Load
0
0
0
Manual Close
tpu
tdo
Trip
Breaker Open
TOC Start
Fault Locations
Faults are simulated at 2 locations along the model distribution line:
1. Close-in fault
2. Remote fault
The fault locations are shown on Figure ( Figure 0-26, page -102 ).
Substation A
Load
IA
IB
IC
Relay
Figure 0-26: Fault locations for the testing of the Switch-On-To-Fault logic.
102
Switch-On-To-Fault
Test Cases
The Switch-Onto-Fault (SOTF) scheme is tested for the following fault conditions:
1. For Close-in ground fault: - the relay should trip without time delay
2. For Close-in phase fault: - the relay should trip without time delay
3. For Remote fault: - the relay should trip without time delay
Hardware Requirements
The CMC test device is programmed to simulate the substation and power system
environment through the analog and binary outputs. At the same time the binary
inputs are used to monitor the operation of the test object.
A typical wiring diagram for the SOTF logic test is shown on ( Figure 0-27,
page -104 ).
The CMC simulates the status of the normally open auxiliary contact for the
breaker (52-A).
The currents and voltages during the pre-fault, fault and post-fault stages of the
simulation are also provided by the CMC. However, the voltages are not required
for the testing of the scheme, since it is based on the operation of overcurrent
elements only. That is why they are shown in gray on the wiring diagram.
The potential free relay output of the CMC has one terminal connected to (+) DC
and the second terminal to the (+) DC terminal of the associated relay input. The
second terminal of the relay input is connected to (-) DC.
The Trip output of the relay is wired to a Trip sense input of the CMC and is used to
change from fault to post-fault state, as well as to measure the operating time and
evaluate the correct operation of the SOTF Scheme logic during the test.
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OMICRON DLogicPro
IA
CM C
Analog
O utp uts
IA
IB
IB
IC
IC
IN
Digital
Inputs
O ut 1
Analog
Inputs
IN
VA
VB
VC
VN
VA
VB
VC
VN
Digital
O utp uts
RELA Y
+ DC
- DC
In 1
52a
Digital
Inputs
Trip
Relay
O utputs
Figure 0-27: Hardware wiring diagram for testing of the Switch-Onto-Fault logic
The automatic test sequences will have several steps shown with animation in the
DLogicPro software.
The only setting that has to be changed for this group of test cases is the enabling
of the SOTF logic.
A relay input has to be programmed as a normally open (52a) breaker status
monitoring input.
One relay output should be programmed to provide Trip signal monitored by the
CMC for the evaluation of the relay operation.
104
105
OMICRON DLogicPro
The detection of unbalance voltage however should not affect the performance of
the relay under fault conditions. That is why the Voltage Transformer Supervision
logic includes another element that monitors the availability of unbalanced current
conditions. Under normal load conditions, the current unbalance will be a function
of the loading of each of the distribution feeder phases.
Detection of Voltage Transformer Supervision should immediately block all voltage
dependent elements, such as the directional functions. At the same time pure
overcurrent elements should be available to provide some form of backup
protection in the case that a fault occurs before the problem with the voltage
circuits or transformers is detected and fixed.
The above requirements are taken into consideration in the design of the module
for testing of the Voltage Transformer Supervision logic in modern distribution
feeder protection relays.
IA
Load
IB
IC
I0 or I2
V0 or V2
IOC
Direction
Trip
Figure 0-28: Simplified logic diagram for Voltage Transformer Supervision scheme
Fault Locations
Faults are simulated at one remote location along the distribution feeder:
A single phase VT failure is simulated at the substation.
A fault is simulated on the feeder.
106
IA
Load
IB
IC
Relay
Figure 0-29: Fault location for the testing of the Voltage Transformer supervision
Test Cases
The Voltage Transformer Supervision logic scheme is tested for the following fault
conditions:
1. For single phase voltage circuit failure: - the relay should not trip and should
give VT Fail alarm.
2. For single phase fault: - the relay should trip and should not give VT Fail alarm.
3. For single phase VT failure with fault: - the relay should give VT Fail alarm and
then should trip after the fault.
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OMICRON DLogicPro
Hardware Requirements
IA
CM C
Analog
Outputs
IA
IB
IB
IC
IC
IN
Digital
Inputs
Out 1
Analog
Inputs
IN
VA
VB
VC
VN
Digital
Outputs
RELAY
VA
VB
VC
VN
+ DC
- DC
52a
In 1
Trip
In 6
VTS
Digital
Inputs
Relay
Outputs
Figure 0-30: Hardware wiring for testing of the Voltage Transformer Supervision logic
The CMC test device is programmed to simulate the substation and power system
environment through the analog and binary outputs. At the same time the binary
inputs are used to monitor the operation of the test object.
A typical wiring diagram for the Voltage Transformer Supervision logic test is
shown on ( Figure 0-30, page -108 )
The potential free relay output of the CMC has one terminal connected to (+) DC
and the second terminal to the (+) DC terminal of the associated relay input. The
second terminal of each relay input is connected to (-) DC.
The Trip output of the relay and the VT Fail output are wired to inputs of the CMC
and are used to change from fault to post-fault state, as well as to measure the
operating time and evaluate the operation of the Voltage Transformer Supervision
logic during the test.
108
The only setting that has to be changed for this group of test cases is the enabling
of the Voltage Transformer Supervision logic and the associated with it relay
settings based on the recommendations in the relay service manual.
One relay input has to be programmed as normally open (52a) breaker status
monitoring input.
One relay output should be programmed to provide Trip while a second output
should give the indication for Voltage Transformer Supervision logic operation
109
OMICRON DLogicPro
Load
IA
IB
IC
I0 or I2
V0 or V2
Trip
Trip
Sequence OC
Phase OC
110
111
OMICRON DLogicPro
Substation A
Load
IA
IB
IC
I0 or I2
V0 or V2
Trip
Sequence OC
Trip
Phase OC
Fault Locations
Faults are simulated at one remote location along the distribution feeder:
1. A single phase CT failure is simulated at the substation.
2. A fault is simulated on the feeder.
Substation A
IA
L oad
r
IB
IC
Relay
Figure 0-32: Fault location for the testing of the Current-Transformer Supervision logic
112
Test Cases
The Current Transformer Supervision scheme is tested for the following fault
conditions
1. For single phase CT failure: - the relay should not trip and should give CT Fail
alarm.
2. For single phase fault: - the relay should trip and should not give CT Fail alarm.
3. For single phase failure with fault: - the relay should give CT Fail alarm and
then should trip after the fault.
Hardware Requirements
The CMC test device is programmed to simulate the substation and power system
environment through the analog and binary outputs. At the same time the binary
inputs are used to monitor the operation of the test object.
113
OMICRON DLogicPro
IA
CM C
Analog
Outputs
IA
IB
IB
IC
IC
IN
Digital
Inputs
Out 1
Analog
Inputs
IN
VA
VB
VC
VN
Digital
Outputs
RELAY
VA
VB
VC
VN
+ DC
- DC
52a
In 1
Trip
In 7
CTS
Digital
Inputs
Relay
Outputs
Figure 0-33: Hardware wiring diagram for testing of the Current-TransformerSupervision logic
The potential free relay output of the CMC has one terminal connected to (+) DC
and the second terminal to the (+) DC terminal of the associated relay input. The
second terminal of the relay input is connected to (-) DC.
The Trip output of the relay and the CT Fail output are wired to inputs of the CMC
and are used to change from fault to post-fault state, as well as to measure the
operating time and evaluate the operation of the Current-Transformer Supervision
logic during the test.
The automatic test sequences will have several different steps shown with
animation in the DLogicPro software.
114
The only setting that has to be changed for this group of test cases is the enabling
of the Current-Transformer Supervision logic and the associated with it relay
settings based on the recommendations in the relay service manual.
One relay input has to be programmed as normally open (52a) breaker status
monitoring input.
One relay output should be programmed to provide Trip, while a second output
should give the indication for detected Current-Transformer Supervision operation
115
OMICRON DLogicPro
FUSE SAVING
Objective
The objective is to perform dynamic test to evaluate the Fuse Saving scheme of a
distribution feeder relay, as a function of the fault condition, reclosing cycle or
combination of the two.
The Test Object is a multifunctional distribution feeder relay with Fuse Saving
scheme.
116
Fuse Saving
apply the Fuse Saving Scheme should be made based on the type of load
connected to the feeder.
The above requirements are taken into consideration in the design of the module
for testing of the Fuse Saving logic in modern distribution feeder protection relays.
A simplified diagram of Fuse Saving logic is shown in ( Figure 0-34, page -117 ).
Substation A
Load
IA
IB
IC
Gnd TOC
Ph TOC
Trip
Trip
Gnd IOC
Ph IOC
Trip
Load
AR in Progress
Figure 0-34: Simplified Fuse saving logic diagram
Fault Locations
Faults are simulated at one location along the model distribution circuit:
Fault behind the fuse
117
OMICRON DLogicPro
Substation
Loa
IA
IB
IC
Relay
Loa
Figure 0-35: Fault locations for the testing of the Fuse Saving logic
Test Cases
The Fuse Saving logic scheme is tested for the following fault conditions:
1. For SLG fault with Successful Reclosing: - the relay should trip without delay
after the initial fault.
2. For SLG fault with Unsuccessful Reclosing: - the relay should not-trip after the
reclosing (coordinates with fuse).
3. For 3LG fault with Successful Reclosing: - the relay should trip without delay
after the initial fault.
4. For 3LG fault with Unsuccessful Reclosing: - the relay should not-trip after the
reclosing (coordinates with fuse).
Hardware Requirements
The CMC test device is programmed to simulate the substation and power system
environment through the analog and binary outputs. At the same time the binary
inputs are used to monitor the operation of the test object.
118
A typical wiring diagram for the Fuse Saving logic test is shown on ( Figure 0-36,
page -119 ).
Fuse Saving
The CMC simulates the status of the normally open auxiliary contact for the
breaker (52-A), the status of the breaker and the reclosing.
The currents and voltages during the pre-fault, fault and post-fault stages of the
simulation are also provided by the CMC. However, the voltages are not required
for the testing of the scheme, since it is based on the operation of overcurrent
elements only. That is why they are shown in gray on the wiring diagram.
The potential free relay outputs of the CMC have one terminal connected to (+) DC
and the second terminal to the (+) DC terminal of the associated relay inputs. The
second terminal of the relay input is connected to (-) DC.
The Trip output of the relay is wired to a Trip sense input of the CMC and is used to
change from fault to post-fault state, as well as to measure the operating time and
evaluate the operation of the Fuse Saving Scheme logic during the test.
IA
CMC
Analog
Outputs
IA
IB
IB
IC
IC
IN
Out 1
Out 2
Out 3
Out 4
Digital
Inputs
In 1
Analog
Inputs
IN
VA
VB
VC
VN
Digital
Outputs
RELAY
VA
VB
VC
VN
+ DC
- DC
52a
+ DC
- DC
BlckAR
+ DC
- DC
ResetAR
+ DC
- DC
BrkOK
Trip
Digital
Inputs
Relay
Outputs
Figure 0-36: Hardware wiring diagram for testing of the Fuse Saving logic
119
OMICRON DLogicPro
The automatic test sequences will have several steps shown with animation in the
D-LogicPro software.
The only setting that has to be changed for this group of test cases is the enabling
of the Reclosing and the Fuse Saving logic and the associated with it relay settings
based on the recommendations in the relay service manual.
A relay input has to be programmed as normally open (52a) breaker status
monitoring input. A second input should be configured to monitor the health of the
breaker. A third input should monitor the availability of Block Reclosing signal and
a fourth input to Reset Reclosing after the end of each test.
One relay output should be programmed to provide Trip signal to the breaker.
120
Block Reclosing
BLOCK RECLOSING
Objective
The objective is to perform dynamic test to evaluate the Block Reclosing function
of a distribution feeder relay, as a function of the type of fault, and the breaker
status.
The Test Object is a multifunctional distribution feeder relay with built-in Block
Reclosing available and enabled.
BR Logic Description
(BR - Block Reclosing)
Most faults on overhead distribution feeders are caused by lightning, clashing
conductors and other transient phenomena. Considering the importance of the
reduction in the duration of outages, utilities are applying automatic reclosing of
the breakers of faulted distribution feeders. The success rate of auto reclosing is in
the range of 80-90%. After the initial trip, the relay recloses the circuit breaker after
a set time delay in order to allow the de-ionization of the air in the fault location.
The remaining percentage of faults is permanent in nature and requires immediate
tripping of the line breakers and blocking of the reclosing function. There are
different criteria or events that can be used to determine the need to block
reclosing:
If the fault detected by the relay is multiphase with high currents, there is higher
probability that it is a permanent fault. At the same time exposing the electric
power system to such conditions repeatedly during the reclosing sequence can be
dangerous for the stability of the system.
If the relay clears a fault with one of it's backup time delayed ground overcurrent
elements - there is a possibility that there is a downed conductor that requires
block of reclosing.
If the breaker controlled by the distribution feeder protection relay is not capable of
reclosing because of low pressure, or something else, obviously the reclosing
should be blocked. This condition is typically detected through a relay input
assigned to detect the Breaker Healthy status.
There might be other requirements to block reclosing. That is why all distribution
feeder relays with autoreclosing feature available will have an input dedicated to
Block Reclosing signals from external devices.
The above requirements are taken into consideration in the design of the module
for testing of the Block Reclosing scheme logic in modern distribution feeder
protection relays.
Simplified logic for the Block Reclosing scheme is shown in ( Figure 0-37,
page -122 ).
121
OMICRON DLogicPro
Substation A
Load
Ia
Ib
Ic
Trip
Breaker
Healthy
Reclosing
IOC
LockOut
SOTF
Block Reclosing
Figure 0-37: Simplified Block Reclosing logic diagram
Fault Locations
Faults are simulated at two location on the substation bus:
1. Close-in fault
2. Feeder fault
Substation A
Ia
Ib
Ic
Relay
Figure 0-38: Fault locations for the testing of Block Reclosing logic
122
Load
Block Reclosing
Test Cases
The Block Reclosing function is tested for the following fault conditions:
1. For close-in high current fault: - the relay should trip and should indicate
Reclose Lockout.
2. For breaker not healthy condition: - the relay should not trip and should
indicate Reclose Lockout
3. For Switch-Onto-Fault (3 Phase): - the relay should trip and should indicate
Reclose Lockout
4. For Block Reclosing input energized: - the relay should not trip and should
indicate Reclose Lockout
Hardware Requirements
The CMC test device is programmed to simulate the substation and power system
environment through the analog and binary outputs. At the same time the binary
inputs are used to monitor the operation of the test object.
A typical wiring diagram for the Block Reclosing logic test is shown on ( Figure
0-39, page -124 ).
The CMC simulates the status of the normally open auxiliary contact for the
breaker (52-A), the status of the breaker and the reclosing.
The currents and voltages during the pre-fault, fault and post-fault stages of the
simulation are also provided by the CMC. However, the voltages are not required
for the testing of the scheme, since it is based on the operation of overcurrent
elements only. That is why they are shown in gray on the wiring diagram.
The potential free relay outputs of the CMC have one terminal connected to (+) DC
and the second terminal to the (+) DC terminal of the associated relay inputs. The
second terminal of the relay input is connected to (-) DC.
The Trip and Reclose Lockout outputs of the relay are wired to sense inputs of the
CMC and are used to change from fault to post-fault state, as well as to measure
the operating time and evaluate the operation of the Block Reclosing Scheme logic
during the test.
123
OMICRON DLogicPro
IA
CM C
Analog
Outputs
IA
IB
IB
IC
IC
IN
Digital
Outputs
Out 2
Out 3
Out 4
Digital
Inputs
Analog
Inputs
IN
VA
VB
VC
VN
Out 1
RELAY
VA
VB
VC
VN
+ DC
- DC
52aA
+ DC
- DC
BlckAR
+ DC
- DC
+ DC
- DC
Digital
Inputs
ResetAR
BrkOK
Relay
Outputs
In 1
Trip
In 4
ReclLockout
Figure 0-39: Hardware wiring for testing of the Block Reclosing logic
The automatic test sequences will have several steps shown with animation in the
DLogicPro software.
The expected basic settings are given in the common section at the beginning of
this document. The only setting that has to be changed for this group of test cases
is the enabling of Reclosing and Block Reclosing logic and the associated relay
settings based on the recommendations in the relay service manual.
A relay input has to be programmed as normally open (52a) breaker status
monitoring input. A second input should be configured to monitor the health of the
breaker. A third input should monitor the availability of Block Reclosing signal and
a fourth input to Reset Reclosing after the end of each test.
One relay output is needed to provide the Trip signal to the breaker and a second
output should indicate Reclose Lockout. The default dead time is 0.3 sec.
124
Support
Support
When you are working with our products we want to provide you with the
greatest possible benefits. If you need any support, we are here to assist you!
OMICRON electronics GmbH, Oberes Ried 1, 6833 Klaus, Austria, +43 59495
125
Support
126