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User Guide
Version 1.02
Copyright 2015
Northwest Logic
Northwest Logic
Proprietary
Table Of Contents
1
OVERVIEW.............................................................................................................................................................2
SEND_SHORT_PACKET ......................................................................................................................................... 4
SEND_LONG_PACKET .......................................................................................................................................... 4
SEND_MULTIPLE_LONG_PACKETS ......................................................................................................................... 4
SEND_RX_VID_INTFC_FRAME ............................................................................................................................... 5
CLEAR_FRAMEDATA ............................................................................................................................................. 6
WRITE_FRAMEDATA ............................................................................................................................................. 6
PREPARE_FRAME ................................................................................................................................................. 6
ANNOUNCE_DATA_ID .......................................................................................................................................... 6
VERIFICATION TASKS..........................................................................................................................................7
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10
5.11
TEST_SHORT_PACKETS ........................................................................................................................................ 7
TEST_LONG_PACKET_LENGTHS ............................................................................................................................ 7
VIRTUAL CHANNEL TEST ......................................................................................................................................7
RANDOM PACKET TEST .......................................................................................................................................8
ULPS MODE TEST ..............................................................................................................................................8
MAXIMUM PACKET LENGTH TEST .........................................................................................................................8
ECC TEST .........................................................................................................................................................8
CRC TEST .........................................................................................................................................................9
UNSUPPORTED DATA TYPE TEST..........................................................................................................................9
RECEIVE VIDEO INTERFACE TEST ......................................................................................................................9
ULPS WITH HIGH SPEED PACKET TEST.............................................................................................................9
CSI2_PIXEL_FIFO .............................................................................................................................................. 10
LICENSING ........................................................................................................................................................... 11
This document contains Northwest Logic, Inc. proprietary information. Northwest Logic, Inc. reserves all
rights associated with this document and the information it contains.
No part of this document may be reproduced or transmitted in any form by any means for any purpose without
the express written permission of Northwest Logic, Inc.
Northwest Logic, Inc. reserves the right to makes changes to this document and associated specifications at
any time without notice. Northwest Logic, Inc. advises its customers to obtain the latest version of this
document before relying on any information it contains.
Northwest Logic, Inc. assumes no responsibility or liability arising from the use of any information, product or
services described in this document except as expressly agreed in writing with Northwest Logic, Inc.
CSI-2 Testbench
User Guide
1 Revision History
This section tracks revisions made to this document by version number
Revision
Date
Changes
1.00
07/09/10
1.01
10/24/13
1.02
10/08/2014
Initial Release.
Brought up to date with current test bench.
Added section on functional coverage.
Updated test description to include what functionality is verified and
reported as failed if not actual does not match expected.
CSI-2 Testbench
User Guide
2 Overview
The CSI-2 Testbench provides a CSI-2 bus functional model for basic simulation of CSI-2 logic designs utilizing the
Northwest Logic CSI-2 Controller Core.
The CSI-2 Testbench contains a CSI-2 Transmit Bus Functional Model (csi2_tx_top), a CSI-2 Receive Bus Functional
Model (csi2_rx_top), test scripts (csi2_tx_data_generator), a pixel FIFO (csi2_pixel_fifo), and logging functionality
as illustrated in Figure 2-1. The CSI-2 Testbench can be used to test User Logic on the Receive, Transmit, or both
the Receive and Transmit sides.
csi2_tb
csi2_tx_data_generator
Primary
Transfer Tasks
csi2_tx_top
TX
Controller
csi2_rx_top
DPHY
DPHY
RX
Controller
User Logic
Tasks
CSI2_Pixel_FIFO
Test Control
Commands
LOG
CSI-2 Testbench
User Guide
The CSI-2 Testbench is available in Verilog 2001. VHDL customers may also use the CSI-2 Testbench by cosimulating with a simulator which supports Verilog and VHDL.
Primary Testbench Components
csi_tb
o Example top level testbench
o The user customizes this file by adding their receive side logic and or replacing the
csi2_tx_data_generator module with their transmit logic.
csi2_tx_data_generator
o Provides high level tasks for interfacing to the CSI2 TX BFM (csi2_tx_top)
Tasks are simple to use and require very little MIPI CSI2 knowledge
Can generate any CSI2 Low Level Protocol Packet Format
Enables full control over packet data contents including auto generation of data
Support for all data types
csi2_tx_top
o Provides a CSI2 Transmit Bus Functional Model
o Uses the Northwest Logic CSI2 Transmit Controller
Delivered in one of two formats
Verilog source code when the Transmit Controller has been licensed
csi2_rx_top
o Provides a CSI2 Receive Bus Functional Model
o Uses the Northwest Logic CSI2 Receive Controller
Delivered in one of two formats
Verilog source code when the Receive Controller has been licensed
csi2_pixel_fifo
o Provides functionality to verify packets requested on the TX interface are received correctly at
the receive side.
Supports all CSI2 Low Level Protocol Packet Formats
Supports all CSI2 data types
Logs results and status to the log file
Log
o Transmit and Receive activity, status, and error information is logged to standard output
o User can easily add information to the log
CSI-2 Testbench
User Guide
3.1 send_short_packet
send_short_packet is xfer is one of two low level tasks that interface directly to the Transmit Bus Functional
Model, the other is the send_long_packet task. Send_short_packet can be used to send any short packet type that
conforms to the Low Level Protocol specified in the MIPI CSI2 specification.
Port
Direction
Size
vc
Input
[1:0]
data_type
Input
[5:0]
data_field
Input
[15:0]
Description
Virtual Channel number.
Data Type. Valid values for short packets are 0x00 0x0f. See the
MIPI CSI2 specification for further definition of the valid values.
Short Packet data field. For frame sync packets, this field contains a
frame number and for line sync packets this field is used as a line
number. See the MIPI CSI2 specification for further definition.
CSI-2 short packets do not contain any payload data so all the information contained in a short packet is passed in
with the call to the send_short_packet task. The send_short_packet task handles all interface handshaking with
the Transmit Bus Functional Model.
3.2 send_long_packet
send_long_packet is xfer is one of two low level tasks that interface directly to the Transmit Bus Functional Model,
the other is the send_short_packet task. send_long_packet can be used to send any long packet type that
conforms to the Low Level Protocol specified in the CSI-2 specification.
Port
Direction
Size
vc
Input
[1:0]
data_type
Input
[5:0]
wc
Input
[15:0]
Description
Virtual Channel number
Data Type. Valid values for short packets are 0x10 0x37. See the
MIPI CSI2 specification for further definition of the valid values
Length of payload in number of pixels
The pixel data for CSI-2 long packets comes from a frame buffer that is maintained by the verification
environment. The tasks for setting up the frame buffer are explained in following sections. The send_long_packet
task handles all interface handshaking with the Transmit Bus Functional Model.
3.3 send_multiple_long_packets
send_multiple_long_packets is used to a specific number of multiple long packets of a requested data type and
virtual channel number. The task sends a total of num_pkts of the type specified in the task. Note that only long
data types are supported.
Port
Direction
Size
Vc
Input
[1:0]
Description
Virtual Channel number
CSI-2 Testbench
User Guide
data_type
Input
[5:0]
wc
num_pkts
Input
Input
[15:0]
[15:0]
Data Type. Valid values for short packets are 0x10 0x37. See the
MIPI CSI2 specification for further definition of the valid values
Length of payload in number of pixels
Number of packets to send.
3.4 send_rx_vid_intfc_frame
The task send_rx_vid_intfc_frame is used to send a series of short and long packets like what is often seen from
MIPI CSI2 cameras.
Port
Direction
Size
data_id
pix_cnt
num_lines
enb_fs_fe_delay
enb_ls_le_pkts
Input
Input
Input
Input
Input
[5:0]
[11:0]
[4:0]
Description
Data Type. Must use valid pixel data types, like RAW8, RAW10, etc.
Number of pixels in a line of video
Number of video lines in a frame
Enable frame start and frame end packets
Enable line start and line end packets.
CSI-2 Testbench
User Guide
4 Support Tasks
The following tasks do not directly generate CSI-2 packets and are provided to facilitate use of the main packet
generating tasks.
4.1 clear_framedata
The verification environment maintains a simple circular buffer as a frame buffer that is used to supply pixel
data to the transmit BFM. A call to clear_framedata resets the pointers in the frame buffer resulting in an empty
buffer.
4.2 write_framedata
write_framedata writes a pair of 24 bit pixels into the frame buffer.
Port
Direction
Size
writedata
Input
[47:0]
Description
Pair of 24 bit pixels.
The frame buffer is sized to support the maximum pixel width of the CSI-2 TX controller pixel data inputs. If the
actual pixel width is less than 24 bits the CSI-2 TX controller will disregard any of the unused bits.
4.3 prepare_frame
prepare_frame write initializes the frame buffer with a short sequence of 8 pixels. A short sequence of pixel
values can be used for longer packets because the frame buffer operates in a circular buffer fashion, repeating the
same 8 pixel values over and over again.
4.4 announce_data_id
announce_data_id performs a Verilog $write() using the data id passed to it to print the data_id in ascii. This
task currently supports video data types only.
Port
Direction
Size
data_id
Input
[5:0]
Description
CSI-2 Data type. Only video types are supported.
CSI-2 Testbench
User Guide
5 Verification Tasks
Verification Tasks are used by Northwest Logic to verify the functionality of the CSI-2 Controller (TX) Core. These
tasks may be of interest to users of the Testbench either directly or as examples of how to create higher level
tasks using lower level tasks described in the previous sections.
5.1 test_short_packets
test_short_packets tests the transmission and reception of short packets using the Virtual Channel number passed
in to the task. It tests all supported short packet data types, 0x00 to 0x0f while using a walking ones pattern in
the short packet data field (the WC field).
Port
Direction
Size
vc
Input
[1:0]
Description
Virtual Channel number
The verification tests run test_short_packets for the four supported Virtual Channel numbers, 0,1,2 and 3. Short
packets received by the RX BFM are verified against the expected packet header field values (data type, virtual
channel, word count) and errors are reported to the log file. The test also monitors the ecc error flags from the
RX Controller, reporting any assertion of the ECC signals and stopping execution of the test at the point of failure.
The test also verifies that the number of packets received matches the number transmitted.
5.2 test_long_packet_lengths
test_long_packet_lengths tests the transmission and reception of long packets using the Virtual Channel number
passed in to the task along with a data type, start and end lengths. test_long_packet_lengths steps the packet
size by the appropriate number of pixels for a given data type.
Port
Direction
Size
vc
Input
[1:0]
data_type
Input
[5:0]
start_length
end_length
Input
Input
[15:0]
[15:0]
Description
Virtual Channel number
Data Type. Valid values for short packets are 0x10 0x37.
See the MIPI CSI2 specification for further definition of the
valid values
Start length for the requested test
End length for the requested test
The verification tests runs a packet length test for all supported data types and lengths started at the smallest
allowable packet size for a data type to the largest packet size for the data type.
Received packets received by the RX BFM are verified against the expected packet value, payload data is
compared to transmitted payload data, with errors reported to the log file. The test also monitors the ECC and
CRC error flags from the RX Controller, reporting any assertion of the ECC and CRC signals and stopping execution
of the test at the point of failure. The test also verifies that the number of packets received matches the number
transmitted.
CSI-2 Testbench
User Guide
The test also monitors the ECC and CRC error flags from the RX Controller, reporting any assertion of the ECC and
CRC signals and stopping execution of the test at the point of failure. The test also verifies that the number of
packets received matches the number transmitted.
CSI-2 Testbench
User Guide
5.8 CRC Test
The CRC test requires that a module be inserted into the PPI interface between the CSI-2 TX Controller and the TX
D-PHY that can insert errors anywhere within a packet. This module is typically not delivered as part of a standard
delivery.
The CRC test transmits a series of packets, introducing bit errors into the payload portion and crc fields of the
packet. On the receive side, the proper detection of the CRC error is verified, with any discrepancies reported to
the log file. The test verifies that the received packet header fields are correct. This test does not verify the
receive data since the receive data is guaranteed to be in error due.
CSI-2 Testbench
User Guide
6 Functional Coverage
The Northwest Logic Testbench environment verifies the following CSI-2 functionality over 1,2,3 and 4 data lanes
and various MIPI data lane rates (min, max and steps in between).
CSI-2 Function
TX
Yes
Yes
Yes
Yes
Yes
NA
NA
NA
Yes
Yes
Yes
NA
Yes
Yes
NA
Yes
Yes
Yes
NA
Yes
Yes
Yes
Yes
Yes
Yes
Yes
RX
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
NA
NA
Yes
Yes
Yes
Yes
Yes
NA
Yes
Yes
Yes
Yes
Yes
Yes
7 CSI2_Pixel_FIFO
The csi2_pixel_fifo monitors the TX requests at the TX BFM (csi2_tx_top) user interface and constructs the packets
it should expect to see at the RX BFM (csi2_rx_top) user interface. The constructed packets are stored in a FIFO
and then read out as the RX BFM receives packets. Errors are logged to the log file.
The CSI2_Pixel_FIFO is used in the verification simulations of the CSI-2 Controller Core (TX). It can be useful in
user simulations to verify that TX Controller, RX Controller, and DPHY modules are functioning properly.
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CSI-2 Testbench
User Guide
8 Licensing
The CSI-2 Testbench is delivered with Northwest Logics CSI-2 Controller Cores. It is not available on a stand-alone
basis.
Phone:
503-533-5800
Fax:
503-533-5900
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