LLOYD HEATH

Gilbert, AZ 85297 | H: (480)-642-7942 | C: (480)-577-7194 | lloydvheath@gmai.com

Senior Design Verification Engineer
Accomplished and resourceful integrated digital circuit design and verification engineer with over 10 years' experience
developing complex consumer and government electronic solutions. Extremely versatile and adaptable lifelong learner
with the ability to step into and lead a multitude of roles in a broad array of technologies. Proven track record of SoC
design execution from initial concept through planning, RTL design, synthesis, test bench development, verification, and
back-end work flows. Adept at uncovering the root cause of issues and developing effective solutions.
Skills
Design & Verificatio: Verilog, VHDL,
SystemVerilog, Vera, ABV, OVM, UVM, SPW,
FPGA, MATLAB, SIMULINK
Tools: Cadence, RTL Compiler, Visual Studio,
PrimeTime, VCS, NC-Verilog, TestKompress,
LBIST, LEC

Software: C, C++, C#, Perl, Python, Java, PHP,

Ruby, Rails, HTML5, CSS, Javascript, Jquery,
TK/TCL
Analysis: Static Timing Analysis, Object Oriented
Design/Analysis, Lifecycle, Logistic

Accomplishments
Developed and integrated Perl program into graphics core Cherrytrail scan validation flow; saved engineering
resources and significantly increased the pattern volume validation space - going from a team of three validating
162 patterns collectively to be accomplished by one engineer generating and validating 3,467 in a later project
stepping.
Avoided schedule impact and delays for the Cherytrail graphics core by quickly finding and root-causing
showstopper bug contained in the entire 54 partitions of the graphics core;
Managed, performed, signed off and delivered final logic built in seff test (LBIST) project collaterals and scan PV
timing closure for the Bay Trail graphics core, exceeding the corporate goal of over 40 million units sold
Guaranteed Bay Trail graphics core test coverage requirements of 91% for LBIST.
Met customer production goals of 800+ Clinac Medical units per month, resulting in over $2M in Corporate
revenue for production run. Overcame integration issues related to test equipment/fixture calibration and
procedure documentation, as well as production software readiness/release. Oriented and trained personnel to
properly run production tests.
Eliminated over $1M in mask cost charges by introducing first-pass release success methodology which cut
design cycle time by over 30% by taking an integral role in establishing project conventions for SoC IC design,
which resulted in defined standard design practices for a variety of key processes.
Professional Experience
Intel
Chandler, AZ
Hardware Graphics Engineer
06/2011 08/2015
Performed graphics core back-end, gate-level verification and pattern generation readiness for a multitude of SoC
devices. Delivered collateral's to manufacturing for testing of HVM production runs.
Generated ATPG Testkompress patterns for 3/8 channel EDT scan implementation
Ran VCS back-annotated gate-level simulations to validate and debug gate-level netlist and ATPG patterns.
Managed graphics core LBIST architecture; led top-level collateral generation and validation.
Implemented scan architecture ECO changes.
Executed Static Timing Analysis; PVT timing closure; provided STCL scripts to fix max corner timing violations
Developed perl programs to improve, enhance and automate back-end work flow.
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Jabil
Tempe, AZ
Test Development Engineer`
2010 - 2011
Managed, directed, and implemented development of functional test verification for electronic hardware/software devices in
a lean manufacturing environment. Achieved 100% functional test coverage for Clinac Medical Scanning devices with
enhanced capability - allowing production programming as part of the test procedure.
Architected functional verification test plan.
Designed, implemented, and analyzed test fixture hardware, software, and assemblies.
Performed integration of the test fixture, test software, and the Clinac Medical device.
Wrote and implemented the test software in Visual C++ utilizing the .net managed framework.
Developed and transitioned the engineering model test suite to production
Supervised and trained production technicians and operators to run all required tests
Freescale Semiconductor/Motorola (2002 2008)
Tempe, AZ
Senior Technical Staff Engineer/APD Technical Design Lead
2007 - 2008
Directed development and integration of real time digital Adaptive Pre-Distortion (APD) system to detect and correct
power amplifier (PA) non-linearities in EDGE, HSUPA, and 4G-LTE applications.
Established, maintained, and coordinated APD schedule and task allocation among firmware, digital baseband,
analog/RF, and system design roles.
Analyzed system performance optimization for various look up table (LUT) implementations.
Senior Staff Engineer/Audio Transceiver
2007
Implemented and delivered transmit path collateral's for class D audio transceiver to examine performance of traditional
synchronous clock based design versus non-clocked asynchronous design.
Developed verilog RTL code for 3D sound, equalizer, and cic filter transmit blocks.
Synthesized gate level netlist from RTL blocks using RTL compiler.
Created fixed point simulink transmit model and directed verillog testbench to verify RTL and gates for
synchronous design.
Generated bit exact test data from simulink model to drive testbench; verified correct operation by comparing
simulink and testbench outputs.
Utilized bit exact data to drive asynchronous gate netlist and testbench to verify performance against
synchronous; observed 30% estimate power reduction in asynchronous design.
Senior Staff Engineer/RF-IF Transceiver Design
2005 - 2007
Delivered 3G RFIC Transceiver GSM and CDMA mobile applications.
Achieved program goal of single all layer mask tape-out to foundry; followed by two subsequent metal releases for
production parts.
Wrote Verilog RTL for transmit path SRRC, Lagrange, and interpolation filtering.
Performed gate level simulations to verify HSIO DigRF 3G interface.
Wrote and implemented transactor level tests to verify higher level functionality of the DigRF interface.
Staff Engineer/Power Management Design Lead
Delivered power management integrated circuit (PMIC).

2002 - 2004

Digital chip lead for PMIC design and integration.

Performed system level case analysis and tradeoffs for PMIC operation.
Designed and implemented state machine, audio codec, spi, and led PWM back-light control logic.
Supported analog/mixed signal debug and executed VCS gate simulation to verify digital functionality.

Education
Master of Science: Electrical Engineering Communication Systems and Signal Processing
Arizona State University
Bachelor of Science: Electrical Engineering
University of Utah

Tempe, AZ
Salt Lake City, UT

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Training
VLSI Academy: Clock Tree Synthesis - currently enrolled
VLSI Essentials - currently enrolled
Coder Manual: Full Stack Programmer Development Course - currently enrolled, estimated completion October 2015
Udemy: OVM and UVM Testbenches from Scratch - currently enrolled
Advanced C++ - currently enrolled
Udemy: SoC Verification using SystemVerilog - Completed June 2015
University of Texas: edX Embedded Systems course - Certificate of Completion May 2015

Community Service
Home construction volunteer, Habitat for Humanity: Home construction volunteered to perform home construction
Feed My Starving Children: volunteered to oversee manage ship and provide quality control of food packages sent to
needy children worldwide
Sub for Santa Program: volunteered and helped with the distribution of toys to underprivileged children.