Motorola SeminarsandApplicationBooksLinearIntegratedCircuits 1979 DL

Master Index and Cross-Reference Guide
Reliability Enhancement Programs

Selector Guide
Memory/Microprocessor Support
Drivers/Receivers
Communication Interface (Telephony)
Voltage Comparators
Data Conversion
Voltage References
Linear 1C Selector Guides
Package Information
Application Notes and Engineering Bulletins
MOTOROLA
LINEAR INTERFACE
INTEGRATED CIRCUITS
Prepared by
Technical Information Center
This Linear interface Data Book contains technical information on a portion

of Motorola Linears product offering. Detailed information on other Linear
products is contained in a separate Linear Data Book. For your convenience,
this book contains the following:
Cross-Reference
Selector Guides (by Product Category)
Datasheets
Package Information
Abstracts Covering Application Notes and Engineering Bulletins
Motorola reserves the right to make changes to any products herein to

improve reliability, function or design. Motorola does not assume any liability
arising out of the application or use of any product or circuit described herein;
neither does it convey any license under its present patent rights nor the
rights of others.
Printed in U.S.A.
Series C
MOTOROLA INC., 1979
Previous Edition 1976
All Rights Reserved
MDTU, MECL, MECL 10,000, MHTL, MRTL, mW MRTL,

Jind.M TTL are. trademarks of Mptorolainc.
CONTENTS
Page
CHAPTER 1 - M ASTER IN D E X A N D CROSS REFERENCE G UIDE ...............................................
Master Index ............................................................................................................................................
Cross-Reference G u id e...........................................................................................................................
CHAPTER 2 - RELIABILITY ENH ANC EM ENT PROGRAMS .............................................................
The "Better" P rogram .............................................................................................................................
Standard HI-REL Programs ...................................................................................................................
M IL-M -38510 JAN-Qualified Product.................................................................................................
JEDEC Processed Product .....................................................................................................................
Screening Procedures.............................................................................................................................
CHAPTER 3 SELECTOR G UIDE .............................................................................................................
Bus In te rfac e............................................................................................................................................
Memory Interface.....................................................................................................................................
Computer and Terminal Interface .......................................................................................................
Peripheral Interface.................................................................................................................................
Numeric Display Interface .....................................................................................................................
Precision Circuits Data Conversion ...............................................................................................
Voltage References .................................................................................................................................
Voltage Comparators...............................................................................................................................
Communication Interface (Telephony) ...............................................................................................
CHAPTER 4 M E M O R Y /M IC R O P R O C E S S O R SUPPORT ...............................................................
Device Listing ..........................................................................................................................................
Data Sheets (See Page 4-2 for page numbers.)
CHAPTER 5 D R IV E R S /R E C E IV E R S .....................................................................................................
Device Listing ..........................................................................................................................................
CHAPTER 6 C O M M U N IC A T IO N INTERFACE (Telephony) .............................................................
Device Listing ...........................................................................................................................................
CHAPTER 7 VOLTAGE COMPARATORS ............................................................................................
Device Listing ..........................................................................................................................................
CHAPTER 8 - DATA C O N V E R S IO N .........................................................................................................
Device Listing ..........................................................................................................................................
CHAPTER 9 VOLTAGE REFERENCES .................................................................................................
Device Listing ..................................... ...................................................................................................
CHAPTER 10 LINEAR IC SELECTOR GUIDES ..................................................................................
Operational Amplifiers ...........................................................................................................................
Voltage Regulators...................................................................................................................................
Circuits for Consumer Applications.....................................................................................................
Special-Purpose Circuits .......................................................................................................................
High-Frequency Amplifiers ...................................................................................................................
CHAPTER 11 PACKAGE IN FO R M A TIO N ............................................................................................
CHAPTER 12 -A P P L IC A T IO N NOTES A N D ENGINEERING BULLETINS ...................................
1-1
1-2
1-10
2-1
2-2
2-3
2-4
2-5
2-6
3-1
3-2
3-9
3-15
3-17
3-18
3-19
3-20
3-21
3-23
4-1
4-2
5-1
5-2
6-1
6-2
7-1
7-2
8-1
8-2
9-1
9-2
10-1
10-2
10-6
10-10
10-14
10-16
11-1
12-1
and Cross-Reference Guide
MASTER INDEX
T h is in d e x in c lu d e s a l l d e v ic e s in M o to r o la L in e a r 's p ro d u c t
lin e . D e v ic e s w it h L in e a r in th e p a g e n u m b e r c o lu m n a r e f u lly
c h a r a c t e r i z e d in t h e s e p a r a t e L i n e a r D a t a B o o k ; h o w e v e r ,
s e le c tio n c h a r a c te r is tic s a r e g iv e n in C h a p te r 1 0 o f t h is v o lu m e
fo r y o u r c o n v e n ie n c e .
Device
Number
AM26LS31
CA3054
CA3059
CA3079
CA3139
DS8641
HA1199
LF155
LF155A
LF156
LF156A
LF157
LF157A
LF255
LF256
LF257
LF355
LF355A
LF355B
LF356
LF356A
LF356B
LF357
LF357A
LF357B
LM101A
LM 104
LM 105
LM107
LM 108
LM108A
LM 109
LM111
LM117
LM117L
LM124
LM139
LM139A
LM 140
LM158
LM201A
LM204
LM205
LM207
LM209
LM 211
LM217
LM217L
LM224
LM239
LM239A
LM258
LM301A
LM304
LM305
Function
Page
Quad RS-422 Line with Three-State O utp u t............................................ .............................. 5-3

Dual Differential A m plifier.................................................................................................... Linear
Zero Voltage Switch .............................................................................................................. Linear
Zero Voltage Switch .............................................................................................................. Linear
TV Tuning Circuit .................................................................................................................... Linear
Quad Unified Bus Transceiver ..................................................................................................... 5-6
AM Radio Subsystem ............................................................................................................ Linear
Monolithic JFET Operational Am plifier............................................................................... Linear
Monolithic JFET Operational A m plifier............................................................................... Linear
Monolithic JFET Operational A m plifier........................................................................... .. Linear
General Purpose Adjustable Operational A m plifier.......................................................... Linear
Adjustable Negative Voltage Regulator ............................................................................. Linear
Adjustable Positive Voltage Regulator ............................................................................... Linear
General-Purpose Operational A m plifier............................................................................. Linear
Precision Operational Amplifier ........................................................................................... Linear
Precision Operational Amplifier .......................................................................................... Linear
Positive Voltage R egulator.................................................................................................... Linear
Voltage Comparator........................................................................................................................ 7-3
Quad Operational A m plifier.................................................................................................. Linear
Quad Comparator (Single Supply) ............................................................................................... 7-7
Quad Comparator (Single Supply) ...............................................................................................7-7
Series of Positive Voltage Regulators ................................................................................. Linear
Dual Operational Amplifier .................................................................................................. Linear
General-Purpose Operational A m p lifie r............................................................................. Linear
Adjustable Negative Voltage Regulator .............................................................................. Linear
General-Purpose Operational A m plifier............................................................................. Linear
Positive Voltage Regulator .................................................................................................... Linear
Voltage Comparator........................................................................................................................ 7-3
Adjustable Voltage Regulator .............................................................................................. Linear
Adjustable Voltage Regulator .............................................................................................. Linear
Quad Operational Amplifier ................................................................................................ Linear
Quad Comparator (Single S u pp ly)............................................................................................... 7-7
Quad Comparator (SingeSupply) ............................................................................................... 7-7
Dual Operational Amplifier ................................................................................................... Linear
Adjustable Negative Voltage Regulator ............................................................... .......... Linear
1-2
MASTER INDEX
Device
Number
LM307
LM308
LM308A
LM309
LM311
LM317
LM317L
LM324
LM339
LM339A
LM340
LM358
LM2901
LM2902
LM2904
MC8T13
MC8T14
MC8T23
MC8T24
MC8T26A
MC8T28
MC8T95
MC8T96
MC8T97
MC8T98
MC26S10
MC26S11
MC75S110
M CI 302
MC1306
MC1309
MC1310
MC1323
M C I324
MC1327
MC1330A
M CI 349
MC1350
MC1351
MC1352
M C I 355
MC1357
MC1358
MC1364
MC1372
MC1373
MC1391
MC1393A
MC1394
MC1398
M C1399
M C1400
MC1400A
MC1403
MC1403A
MC1404
MC1404A
MC1405
MC1406
MC1408
MC1411
M C1412
Function
Page

Precision Operational A m p lifie r...................................... ................................................... Linear
Precision Operational A m p lifie r........................................................................................... Linear
Positive Voltage R egulator................................................................................................... Linear
Voltage Com parator............................................... ......................................................................... 7-3
Adjustable Positive Voltage Regulator ................................ ....... ..................................... Linear
Quad Operational Amplifier ........................................................... ..................................... Linear
Quad Comparator (Single S u p p ly).............................................................................................. 7-7
Quad Comparator (Single S u p p ly).......................... ................................................................ 7-7
Series of Positive Voltage Regulators ............................................................. . .............. Linear
Quad Comparator ......................................................................................................................... 7-11
Quad Operational Amplifier ................................................................................................ Linear
Dual Operational Amplifier ........................ ......... ......... ..................................................... Linear
Dual Line Driver ............................................................................................................................. 5-9
Triple Line Receiver with Hysteresis.......................................................................................... 5-12
Dual Line D riv e r............................................................................................................................. 5-9
Triple Line Receiver with Hysteresis.......................................................................................... 5-12
Quad Three-State Bus Transceiver........................................................................................... 4-99
Non-Inverting Bus Transceiver ............................. ........................................................... 4-118
Hex Three-State Buffer/Inverter ........................................................................................ 4-113
Hex Three-State Buffer/Inverter ......................................................................................... 4-113
Hex Three-State Buffer/Inverter ...................................... .................................................. 4-113
Hex Three-State Buffer/Inverter ..................... ................................................................... 4-113
Quad Open-Collector Bus Transceiver...................................................................................... 5-16
Quad Open-Collector Bus Transceiver..................................................................................... 5-16
Dual Line Driver ......................................................... .................................................................. 5-19
7-Stage D iv id e r................................................... .................................................................... Linear
1/2-W att Audio Amplifier ................................................................................................... Linear
FM Stereo D em odulator....................................................... ....................... ......................... Linear
FM Stereo D em odulator.......................................................................................... ............. Linear
Triple Doubly Balanced Chroma Demodulator .............................................................. Linear
Dual Doubly Balanced Chroma Demodulator ................................................................. Linear
Dual Doubly Balanced Chroma Demodulator ................................................ .............. Linear
Lew-Level Video D etector...................................................................................................... Linear
IF Amplifier .............................................................................................................. .............. Linear
IF Amplifier .............................................................................................................................. Linear
TV Sound Circuit...................................................................................................................... Linear
TV Video IF A m p lifie r...................................... ......... .......................................................... Linear
Limiting FM IF Amplifier ...................................................................................................... Linear
IF Amplifier and Quadrature Detector .............................. ................................................ Linear
TV Sound IF A m p lifie r............................................................ ................. ............................. Linear
Automatic Frequency C ontrol.............................................................................................. Linear
Color TV Video Modulator .................................................................................................... Linear
TV Video M o d u lato r................................................................................................................ Linear
TV Horizontal Processor........................................................................................................ Linear
TV Vertical Processor ............................................................................................................ Linear
TV Horizontal Processor........................................................................................................ Linear
TV Color Processing C irc u it.................................................................................................. Linear
TV Color Processing C irc u it.................................................................................................. Linear
Precision Voltage R e fere n ce.......................................................................................................... 9-3
Precision Voltage R eferen ce..........................................................................................................9-3
Precision Low-Voltage Reference................................................................................................ 9-4
Precision Low-Voltage Reference..................................................................................................9-4
Precision Low-Drift Voltage Reference ...................................................................................... 9-8
Precision Low-Drift Voltage R eferen ce........................................................... .............................9-8
Analog-to-Digital Converter Subsystem ...................................................................................... 8-3
6-Bit Multiplying Digital-to-Analog Converter.......................................................................... 8-17
Peripheral Driver A r ra y ................................................................................................................. 5-25
Peripheral Driver A r ra y ................................................................................................................. 5-25
1-3
MASTER INDEX
Device
Number
MC1413
M 1414
MC1416
MC1420
MC1422
MC1430
MC1431
M C1433
MC1435
MC1436
MC1436C
MC1437
MC1438
MC1439
MC1444
MC1445
MC1454
MC1455
MC1456
MC1456C
MC1458
MC1458C
MC1458N
MC1458S
MC1463
MC1466
M C1468
MC1469
MC1472
MC1488
MC1489
MC1489A
M C1494
MC1.495
MC1496
MC1500
MC1500A
MC1503
MC1503A
MC1504
MC1504A
MC1505
MC1506
MC1508
M C1514
M C1520
M C I 530
MC1531
MC1533
MC1535
M C1536
MC1537
MC1538
MC1539
M C1544
M C1545
M C1550
M C1552
M C1553
MC1554
M C I555
M C I 556
Function
Page
Peripheral Driver A rra y .................................................................................................................5-25

Dual Differential Comparator ............................ ........................................................................ 7-15
Peripheral Driver A r ra y .......................... ......................................................................................5-25
Differential Output Operational Amplifier ......................................................................... Linear
Timing Circuit with Adjustable Threshold........ ............................................................
Linear
Operational Amplifier ....................................................................... ................................... Linear
Operational Amplifier ........................................................................................................... Linear
Operational Amplifier ............................................................................................................ Linear
High-Voltage Operational Amplifier .................................................................................. Linear
High-Voltage Operational Amplifier ............. ............. ....................................... ............... Linear
Power Booster..................................................................................... .............. ; ................. Linear
High-Slew-Rate Operational Amplifier ............................................ .................................. Linear
AC-Coupled 4-Channel Sense Amplifier .......................... ......................................................... 4-3
Wideband Amplifier ............................................................................................................. Linear
1-Watt Power A m p lifie r............................................................................. ............................ Linear
Timing C irc u it......................................................................................................................... Linear
High-Performance Operational Amplifier ........................................................................ Linear
High-Performancc Operational Amplifier ........................................ ................................ Linear
Dual Operational Amplifier ..................................................................... ............................ Linear
Dual Operational Amplifier ................................................................................................. Linear
Lcw-Noise Dual Operational A m p lifie r............................................................................... Linear
High-Slew-Rate Dual Operational Amplifier .................................................. ................. Linear
Voltage and Current R egulator............ ............................................................................. . Linear
Dual 15-Volt Tracking Regulator .................. .................................................................. Linear
Adjustable Positive Voltage Regulator .............................................................................. Linear
Dual Peripheral Positive NAND Driver ...................................................................................... 5-29
Quad MDTL Line Driver .............................................................................................................. 5-32
Quad MDTL Line R eceiver...........................................................................................................5-38
Quad MDTL Line R eceiver................................................... ........... ........................................... 5-38
Four-Quadrant M u ltip lie r................................................. .................................................... Linear
Four-Quadrant M u ltip lie r..................................................................................................... Linear
Balanced Modulator-Demodulator ..................................................................................... Linear
Precision Voltage R eferen ce.............................................. .................................................. :. .9-3'
Precision Voltage R eferen ce..........................................................................................................9-3
Precision Low-Voltage Reference..................................................................................................9-4
Precision Low-Voltage Reference............................................................. .................................. 9-4
Precision Low-Drift Voltage R eference................................ ....................................................... 9-8
Precision Low-Drift Voltage R eferen ce........................................................................................ 9-8
Analog-to-Digital Converter Subsystem ......................... ............................................................ 8-3
8-Bit Multiplying Digital-to-Analog Converter.............................. ....................................... 8-29*
Dual Differential Comparator ..................................................................................................... 7-15
Differential Output Operational Amplifier ......................................................................... Linear
Operational Amplifier .............................................................................. ............................ Linear
High-Voltage Operational Amplifier .................................. ................................................ Linear
Dual Operational Amplifier ................................................. ........... .............. ..................... Linear
Power Booster......................................................................................................................... Linear
High-Slew-Rate Operational Amplifier ............................................................................... Linear
AC-Coupled 4-Channel Sense Amplifier ......................................................................................... ................. 4Wideband Amplifier ..................................... ...................................................................... Linear
RF-IF Amplifier .................................................................................... .................................. Linear
Video A m p lifie r................................................................................... .................................. Linear
Video A m p lifie r........................................... ............. ......... . ................................................. Linear
1-Watt Power A m p lifie r.............................. .......................... ......... ...................................... Linear
Timing C irc u it......................................................................................................................... Linear
High-Performance Operational Amplifier ......................................................................... Linear
1-4
MASTER INDEX
Device
Number
MC1558
MC1558N
MC1558S
MC1563
MC1566
MC1568
MC1569
M C1590
MC1594
MC1595
MC1596
M C1709
MC1709A
MC1709C
MC1710
MC171OC
MC1711
M CI 711C
MC1712
MC1712C
MC1723
MC1723C
MC1733
MC1733C
MC1741
MC1741C
MC1741N
MC1741NC
MC1741S
MC1741SC
MC1747
MC1747C
MC1748
MC1748C
MC1776
MC1776C
MC26S10
M C26S11
MC3232A
MC3242A
M C3245
MC3301
MC3302
MC3303
M C3310
MC3325
MC3333
MC3340
MC3344
MC3346
MC3357
MC3358
MC3360
M C3370
MC3380
MC3386
MC3393
MC3401
MC3403
MC3405
MC3408
MC3410
Function
Page

Low-Noise Dual Operational A m p lifie r............................................................................... Linear
High-Slew-Rate Dual Operational Amplifier ...................................................................... Linear
Voltage and Current Regulator............ ............................................................................ Linear
Dual 15-Volt Tracking Regulator .................................................................................... Linear
Adjustable Positive Voltage Regulator ....................................................... ...................... Linear
Wideband Amplifier with AGC ............................................................................................ Linear
Four-Quadrant Multiplier ...................................................................................................... Linear
Four-Quadrant M u ltip lie r.......................................... ......................................................... Linear
Balanced Modulator-Demodulator ....................... ................ ........................................... Linear
Differential Comparator ...................................... ................................................... ................... 7-19
Differential Comparator ...................................... ........................................................................7-19
Dual Differential Comparator ......................................................................................................7-23
Dual Differential Comparator ......................................................................................................7-23
Wideband DC Amplifier .......... ......................................................................... ................... Linear
Wideband DC Amplifier ........................................................................................................ Linear
Adjustable Positive or Negative Voltage Regulator .......................................................... Linear
Adjustable Positive or Negative Voltage Regulator .......................................................... Linear
Differential Video A m p lifie r................................................................................................... Linear
Differential Video A m p lifie r................................................................................................... Linear
General-Purpose Operational A m p lifie r............................................................... ............ Linear
Low-Noise Operational A m p lifie r......................................................................................... Linear
Low-Noise Operational A m p lifie r......................................................................................... Linear
High-Slew-Rate Operational Amplifier ............................................................................... Linear
High-Slew-Rate Operational Amplifier ................................................................................ Linear
Dual MC1741 Operational A m plifier............................................ ...................................... Linear
Dual MC17 4 1 C Operational Amplifier ............................................................................... Linear
Programmable Operational A m plifier............. ................................................................. Linear
Programmable Operational A m p lifie r................................................................................. Linear
Quad Open-Collector Bus T ransceiver......................................................................................5-16
Quad Open-Collector Bus Transceiver
............................................................................ 5-16
Memory Address Multiplexer and Refresh Address Counter ................................................4-11
Memory Address Multiplexer and Refresh Address C o u n te r........... ....................................4-16
Quad TTL-to-MOS Driver ..............................................................................................................4-21
Quad Operational Amplifier .............................. ................................................................. Linear
Quad Comparator .........................................................................................................................7-27
Quad Differential-Input Operational A m p lifie r................................................................. Linear
W ide-B andA m plifier............................................................................................................. Linear
Automotive Voltage Regulator ................................................. .......................................... Linear
Vari-Dwell Ignition .................................................................................................................. Linear
Electronic Attenuator ............................................................................................................ Linear
Programmable Frequency Switch ....................................................................................... Linear
General-Purpose Transistor A r r a y ....................................................................................... Linear
Lcwv-Pcwer FM IF .................................................................................................................... Linear
Dual Low-Power Operational A m p lifie r............................................................................... Linear
1/4-W att Audio Amplifier ..................................................................................................... Linear
Zero Voltage S w itc h ............................................................................................................... Linear
Emitter-CoupledAstable M ultivibrator............................................................................... Linear
General-Purpose Transistor A r r a y ....................................................................................... Linear
Two-Modulus Prescaler ........................................................................................................ Linear
Quad Operational Amplifier .................. ............................................................................. Linear
Quad Differential-Input Operational A m p lifie r................................................................. Linear
Dual Operational Amplifier plus Dual Voltage Comparator............................................ Linear
8-Bit Multiplying Digital-to-Analog Converter...........................................................................8-43
10-Bit D-to-A Converter ................. ............ ..............................................................................8-49
1-5
MASTER INDEX
Device
Number
MC3410C
M C3412
MC3416
MC3417
MC3418
MC3419
M C3420
MC3423
M C3430
MC3431
MC3432
MC3433
MC3437
MC3438
MC3440A
MC3441A
MC3443
MC3446A
MC3447
MC3448A
MC3449
MC3450
MC3452
MC3453
MC3456
MC3458
MC3459
MC3461
MC3467
MC3468
MC3470
MC3476
M C3480
MC3481
MC3482A
MC3482B
MC3485
M C3486
MC3487
MC3488A
MC3488B
M C3490
MC3491
MC3492
M C3494
MC3503
MC3505
MC3510
MC3517
MC3518
MC3519
M C3520
MC3523
MC3556
MC3558
MC4558
MC4558AC
MC4558C
M C4558N
MC4558NC
MC4741
MC4741C
Function
Pago
10 -Bit D-to-A Converter ................ ............................................................................................ 8-49

High-Speed 12-Bit D /A Converter ............................................................................................. 8-60
Cross point Switch ..................................................................................... ............................................................. 6-3
Continuousiy-Variable-Slope Delta M odulator/Dem odulator................................................6-12
Continuously-Variable-Slope Delta M odulator/Dem odulator................................................6-12
Subscriber Loop Interface Circuit .............................................................................................6-30
Switch mode Regulator Control C irc u it................................................................................ Linear
Overvoltage Sensing Circuit ........................................ ......................................................... Linear
High-Speed Quad Com parator............ ......................................................................................7-31
High-Speed Quad C om parator.......... ....................................................................................... 7-31
High-Speed Quad Com parator.....................................................................................................7-31
High-Speed Quad C om parator..................................................................................................... 7-31
Hex Unified Bus Receiver ................................. .......................................................................... 5-44
Quad Unified Bus Transceiver ............... .................................................................................... 5-47
Quad Interface Bus Transceiver .................................................................................................5-50
Quad Interface BusTransceiver .................................................................................................5-50
Quad Interface Bus Transceiver ..............................................................................................5-50
Quad Interface Bus Transceiver ..............................................................................................5-54
Bidirectional Instrumentation Bus Transceiver........................................................................5-57
Quad Three-State Bus Transceiver....................................................................................... ..5 - 6 3
Triple Bidirectional Bus Switch ............................................................................................ 4-104
Quad Line R e c e iv e r....................................................................................................................... 5-68
Quad Line R e c e iv e r............................. ..................................................................................... 5-68
Quad Line Driver
....................................................................................................................... 5-75
Dual Timing C irc u it........................................................................................... ...................... Linear
Dual Low-Power Operational A m p lifie r................................................................................. Linear
Quad NMOS Memory Driver ....................................................................................................... 4-24
Dual NMOS Memory Sense Amplifier .......................................................................................4-28
Triple Pream plifier............................... ..........................................................................................4-34
Magnetic Read A m p lifie r............................................................................................................. 4-39
Floppy Disk Read Amplifier System .......................................................................................... 4-59
Programmable Operational A m plifier................................................................................... Linear
Memory Controller C irc u it........................................................................................................... 4-73
Quad Single-Ended Line Driver .................................................................................................. 5-79
Octal Three-State B u ffer/In verter........................................................................................ 4-109
Octal Three-State B u ffer/In verter......................................................................................... 4-109
Quad Single-Ended Line Driver ..................................................................................................5-79
Quad R S-422/423 Line Receiver................................................................................................5-80
Quad RS-422 Line Driver with Three-State Outputs ............................................................... 5-83
Dual RS-423/232C D riv e r.........................................................................................................5-87
Dual R S-423/232C Driver ........................................................................................................ 5-87
7-Digit Gas Discharge Display Driver ........................................................................................ 5-90
8-Segment Visual Display Driver .............................................................................................5-96
8-Segment Visual Display Driver .............................................................................................5-96
7-Digit Gas Discharge Display Driver ........................................................................................ 5-90
Quad Differential-Input Operational A m p lifie r................................................................... Linear
Dual Operational Amplifier plus Dual Voltage Comparator............................................. Linear
10-Bit D-to-A Converter ............................................................................................................... 8-49
Continuously-Variable-Slope Delta M odulator/Dem odulator................................................ 6-12
Continuously-Variable-Slope Delta Modulator/Dem odulator............................................... 6-12
Subscriber Loop Interface Circuit .............................................................................................. 6-30
Switch mode Regulator Control C irc u it................................................................................ Linear
Overvoltage Sensing Circuit .................................................................................................. Linear
Dual Timing C irc u it............................................................................................................... Ljnear
Dual Low-Power Operational A m plifier............................................................................... Linear
Dual High-Frequency Operational A m plifier...................................................................... Linear
Dual High-Frequency Operational A m plifier..................... ................................................ Linear
Quad MC1741 Operational A m p lifie r................................................................................. Linear
Quad MC1741 Operational A m p lifie r....... ......................................................................... Linear
1-6
MASTER INDEX
Device
Number
MC6875
MC6880A
MC6881
MC6882A
MC6882B
MC6885
MC6886
MC6887
MC6888
MC6889
MC6890
MC75S110
MC7805
MC7805A
MC7805AC
MC7805C
MC7806
M C7806A
MC7806AC
MC7806C
MC7808
MC7808A
MC7808AC
MC7808C
MC7812
MC7812A
MC7812AC
MC7812C
MC7815
MC7815A
MC7815AC
MC7815C
MC7818
MC7818A
MC7818AC
MC7818C
MC7824
MC7824A
MC7824AC
MC7824C
MC78L02AC
MC78L05AC
MC78L05C
MC78L08AC
MC78L08C
MC78L12AC
MC78L12C
MC78L15AC
MC78L15C
MC78L18AC
MC78L18C
MC78L24AC
MC78L24C
MC78M05C
M C78M06C
M C78M08C
MC78M12C
M C78M15C
MC78M18C
MC78M20C
MC78M24C
MC7902C
Function
Page
M6800 Clock G enerator Driver

..............................................................................................4-88
Quad Three-State Bus Transceiver .......................................................................................... 4-99
Triple Bidirectional Bus S w itc h ............................................................................................ 4-104
Octal Three-State B u ffei/L atch ............................................................................................ 4-109
Octal Three-State Buffee'Latch................................................ ....... ................................ . 4-109
Hex Three-State Buffei/lnverter ...........................................................................................4-113
Hex Three-State Buffei/lnverter ...........................................................................................4-113
Hex Three-State Buffei/lnverter .......................................................................................... 4-113
Hex Three-State Buffed Inverter ...........................................................................................4-113
Noninverting Bus Transceiver................................. .................................................................4-118
8-Bit Bus-Compatible MPU D'A Converter ............................................................................... 8-61
Dual Line D riv e r.............................................................................................................................. 5-19
Positive Voltage Regulator (1.5 A) .......... ....................................... ................................ Linear
Positive Voltage Regulator (1.5 A) .................................................................................... Linear
Positive Voltage Regulator (1.5 A) ..................................................................................... Linear
Positive Voltage Regulator (1.5 A) ........................................................... ......................... Linear
Positive Voltage Regulator (1.5 A) ........... ...................................................................... Linear
Positive Voltage Regulator (1.5 A) .............................. ............ ..................................... Linear
Positive Voltage Regulator (1.5 A) .............. ...................................................................... Linear
Positive Voltage Regulator (1.5 A) ................................................................... ................ Linear
Positive Voltage Regulator (1.5 A) .......................................... ......................................... Linear
Positive Voltage Regulator (1.5A ) .......... : .................................................. .................... Linear
Positive Voltage Regulator (1.5 A) .................... ............................................................... Linear
Positive Voltage Regulator (1.5 A ) ..................................................................................... Linear
Positive Voltage Regulator (1.5 A ) ........ .......................................... ................................... Linear
Positive Voltage Regulator (1.5 A) ................................................................... .............. Linear
Positive Voltage Regulator (1.5 A ) ..................................................................................... Linear
Linear
Positive Voltage Regulator (1.5 A) ................................................................................
Positive Voltage Regulator (1.5 A) ............................................... ..................................... Linear
Positive Voltage Regulator (1.5 A) ................................................................................... Linear
Positive Voltage Regulator (100 m A ) .................................................... ........................... Linear
Positive Voltage Regulator (100 m A ) ................................................................................. Linear
Positive Voltage Regulator (100 m A ) .......................................................... ..................... Linear
Positive Voltage Regulator (100 m A ) ................................................................................ Linear
Positive Voltage Regulator (100 m A ) ........................................................... ..................... Linear
Positive Voltage Regulator (100 m A ) ......................................................... ...................... Linear
Positive Voltage Regulator (500 m A ) .................. ........................................................... Linear
Positive Voltage Regulator (500 m A ) ........................ ........................................................ Linear
Negative Voltage Regulator (1.5 A) ................................................................................... Linear
1-7
MASTER INDEX
Device
Number
MC7905C
MC7905.2C
MC7906C
MC7908C
MC7912C
MC7915C
MC7918C
MC7924C
MC79L03AC
MC79U03C
MC79L05AC
MC79L05C
MC79L12AC
MC79L12C
MC79L15AC
MC79L15C
MC79L18AC
MC79L18C
MC79L24AC
MC79L24C
MC8T13
MC8T14
MC8T23
MC8T24
MC8T26A .
MC8T28
MC8T95
MC8T96
MC8T97
MC8T98
MC10317L
MC10318L
MC10318L9
MC34001
MC34002
MC34004
MC34022
MC35001
MC35002
MC35004
MC35022
MC55325
MC75107
MC75108
MC75S110
' MC75125
MC75127
MC75128
MC75129
MC75140P1
MC75325
MC75365
MC75368
M C75450
MC75451
MC75452
MC75453
MC75454
MC75461
MC75462
MC75463
MC75464
Function
Page

Negative Voltage Regulator (1.5 A) ....................... ............................................................ Linear
Negative Voltage Regulator (1.5 A) ....................... ............................................................ Linear
Negative Voltage Regulator (1.5 A) ................................................................................... Unear
Negative Voltage Regulator (100 m A ) ............................................................................... Linear
Negative Voltage Regulator (100 m A ) ............................................................... ............... Linear
Negative Voltage Regulator (100 m A ) .............................................................................. Linear
Negative Voltage Regulator (100 m A ) .............................................................................. Linear
Negative Voltage Regulator (100 m A ) ............................................................. ................. Linear
Negative Voltage Regulator (100 m A ) .................... .......................................................... Linear
Negative Voltage Regulator (100 m A ) .................... ......................................................... Linear
Negative Voltage Regulator (100 m A ) ........................................... ................................... Linear
Dual Line D riv e r................................................................................................................................5-9
Triple Line Receiver ......................................................................................................................5-12
Dual Line D riv e r..................................................................... ..........................................................5-9
Triple Line Receiver ......................................................................................................................5-12
Quad Bus Transceivei/MPU Bus Extender .............................................. ............................. 4-99
Noninverting Bus Transceiver.................................................................................................. 4-118
Hex Three-State Buffei/Inverter ........................................................................................... 4-113
Hex Three-State Buffer/Inverter ............... ........................................................................... 4-113
Hex Three-State Buffei/Inverter ...........................................................................................4-113
Hex Three-State Buffed Inverter ...........................................................................................4-113
7-Bit High-Speed A^D Converter ...................... ....................................................................... 8-65
High-Speed8 - Bit C/A Converter ................................................ ............................................. 8-66
High-Speed8 - Bit iy A Converter .......................................... ....................................................8-66
Single TRIMFET Operational Amplifier .......................................................................... Linear
Dual TRIM FET Operational Amplifier ............................................................................... Linear
Quad TRIM FET Operational Amplifier ............................................................................. Linear
Dual Precision TRIMFET Operational A m plifier.............................................................. Linear
Single TRIMFET Operational Amplifier ........................... . ............................................ Linear
Dual TRIMFET Operational Amplifier ............................................................................... Linear
Quad TRIMFET Operational Amplifier ............................................................................. Linear
Dual Precision TRIMFET Operational A m plifier.......................................... ................... Linear
Dual Memory Driver .................................................. ............................................................... 5-120
Dual Line Receiver ............................................ ....................................................................... 5-103
Dual Line Receiver .....................................................................................................................5-103
Dual Line D riv e r.............................................................................................................................5-19
7 - Channel Line R eceiver................................................... ...................................................5-108
7 - Channel Line Receiver........................................................................................................5-108
8 - Channel Line R eceiver.................................. ..................................................................... 5-112
8-Channel Line R eceiver.............................. .........................................................................5-112
Dual Line Receiver ............................... . i .............................................................................5-116
Dual Memory Driver ................... ................................................................................................ 5-120
Q uadM O S Clock Driver ........................................................................................ ...................4-124
Dual MECL-to-MOS D riv e r............................................ ...........................................................4-132
Dual Peripheral Driver, Positive AND ...................................................................................5-126
Dual Peripheral Driver, Positive AND ....................................................................................5-131
Dual Peripheral Driver, Positive N A N D .............................................................................. 5-131
Dual Peripheral Driver, Positive O R ........................................................................................5-131
Dual Peripheral Driver, Positive NOR ....................................................... ............................ 5-131
High-Voltage Peripheral D riv e r............................................................................................... 5-135
High-Voltage Peripheral D riv e r......................................................... ......................................5-135
High-Voltage Peripheral D riv e r.............................................................................................. 5-135
High-Voltage Peripheral D riv e r................................................................................................5-135
1-8
MASTER INDEX
Device
Number
Function
Page
MC75491
, Quad Light-Emitting Diode (LED) Driver .......................................................................... 5-140
MC75492
Hex Light-Emitting Diode (LED) Driver ................................................................................ 5-140
MCCF3326
Flip-Chip Automotive Voltage Regulator .......................................................................... Linear
MCCF3333
Vari-Dwell Ignition Circuit .................................................................................................. Linear
MMH0026
DualM O S Clock Driver .............. ............. ....................................... ...................................... 4-137
MMH0026C
Dual MOS Clock D r iv e r................................................ ................................................ ......... 4-137
NE565
Phase-Locked Loop ................................................................... ................. ......................... Linear
NE592
Video Amplifier .................... .............................................................................................. Linear
SE592
Video Amplifier ..................................................................... ............................................... Linear
SN75431
Dual Peripheral Driver ............................................................................................................... 5-146
SN75432
SN75451 BP
SN75452BP
Dual Peripheral Driver ............................................................................................ .......... 5-147
SN75453BP
Dual Peripheral Driver ............................... ............................................. ..............................5-147
SN75454BP
Dual Peripheral Driver ..................... .......................................................................................... 5-147
TCA4500A
FM Stereo Demodulator ................................................ ...................................................... Linear
TDA1190P
TV Sound System .................................................................................................................. Linear
TDA1190Z
TV Sound System .................................................................................................................. Linear
TDA2002
Audio Power A m p lifie r.......................................................................................................... Linear
TDA2002A
Audio Power A m p lifie r.......................................................................................................... Linear
1-9
LINEAR
( M ) MOTOROLA
MOTOROLA -
INTEGRATED CIRCUITS
LINEAR INTEGRATED CIRCUITS CROSS REFERENCE
. . . provides a complete interchangeability list linking over 3000

devices offered by most major Linear Integrated Circuits manufacturers
to the nearest equivalent Motorola device. The Motorola Direct
Replacement column lists devices with identical pin connections and
package and the same or better electrical characteristics and tempera-
ture range. The "Motorola Functional Equivalent" column provides a

device which performs the same function but with possible differences
in package configurations, pin connections, temperature range or
electrical specifications,
709BE AD559S
PART NO.
70SBE
70SBH
709CE
7G9CH
709CJ
710BE
710CE
711BE
711BN
711CE
711CJ
723BE
723CE
723CJ
741BE
741BH
741BN
741CE
747BE
747BN
747CE
748BE
748CE
809BE
809CE
823AE
1458CE
3232
3245
6605J
6605L
8216
8226
9614DC
9614DM
9615DC
96150M
9615FM
9616CDC
9616EDC
96t6DM
96170C
9620DC
9620DM
9621DC
9621DM
9S220C
9622DM
9624DC
96240M
9625DC
96250M
9627CDC
MOTOROLA
MOTOROLA
DIRECT
SIMILAR
REPLACEMENT REPLACEMENT
MC1709G
MC1709F
MC1709CG
MC1709CF
MC1709CP2
MC1710G
MC1710CG
MC1711G
MC1711L
MC1711CG
MC1711CP
MC1723G
MC1723CG
MC1723CL
MC1741G
MC1741F
MC1741L
MC1741CG
MC1747G
MC1747L
MC1747CG
MC1748G
MC1748CG
MC1776G
MC1776CG
MC1723G
MC14S8CG
MC3232AL
MC3245L
MC3443P
MC3443P
MC8T26AL
MC8T28L
MC75S110L
MC75S110L
MC75108L
MC55108L
MC55108L
MC1488L
MC1488L
MC1488L
MC1489AL
MC75S110L
MC75S110L
MC75108L
MC55108L
MC75140P1
MC75140P1
MMK0026CL
MMK0026CL
MMK0026CL
MMH0026CL
MC1489AL
PART NO.
96270M
9636AT
9637T
9638T
9640J
9640D
9640DC
9640NC
9665DC
9665PC
S666DC
9666PC
S667DC
9667PC
9668DC
9668PC
55107ADM
55107BDM
55108ADM
5S108BDM
55110DM
55121DM
55122DM
55207DM
55208DM
55325DM
55325FM
75107ADC
75107APC
75107BDC
75107BPC
75108ADC
75108APC
75108BDC
75108BPC
75110DC
75110PC
75121DC
75121PC
7S122DC
75122PC
75123DC
75123PC
75124DC
75124PC
75207DC
75207PC
75208DC
75208PC
753250C
75325PC
75450ADC
75450APC
MOTOROLA
MOTOROLA
DIRECT
SIMILAR
MC1489AL
MC3488AP
MC3486P
MC3487P
MC3443P
MC3443P
MC3440AP
MC3440AP
MC1411I
MC1411P
MC1412L
MC1412P
MC1413L
MC1413P
MC1416L
MC1416P
MC55107L
MC55107L
MC55108L
MC55108L
MC75S110L
MC8T13L
MC8T14L
MC55107L
MC55108L
MC55325L
MC55325L
MC75107L
MC75107P
MC75107L
MC75t07P
MC75108L
MC75108P
MC75108L
MC75108P
MC75S110L
MC75S110P
MC8T13L
MC8T13P
MC8T14L
MC8T14P
MC8T23L
MC8T23P
MC8T24L
MC8T24P
MC75107L
MC75107P
MC75108L
MC75108P
MC75325L
MC75325P
MC75450L
MC75450P
1-10
PART NO.
75450BDC
75450BPC
75451APC
75451ATC
75451BRC
'75451BTC
75452ARC
75452ATC
75452BRC
75452BTC
75453ARC
75453ATC
75453BRC
75453BTC
75454ARC
75454ATC
75454BRC
75454BTC
75460DC
75460PC
75461RC
75461TC
75462RC
75462TC
75463RC
75463TC
75464RC
75464TC
75491DC
75491PC
75491ADC
75491APC
75492DC
75492PC
75492ADC
75492APC
AD301AL
AD505J
AD505K
AD505S
AD509J
AD509K
AD509S
AD518J
AD518K
AD518S
AD530
AD531
AD532J
AD559JD
AD559K
AD559KD
AD559S
MOTOROLA
MOTOROLA
DIRECT
SIMILAR
MC75450L
MC75450P
MC75451U
MC75451P
MC75451U
SN75451BP
MC75452U
MC75452P
MC75452U
SN75452BP
MC75453U
MC75453P
MC75453U
SN75453BP
MC75454U
MC75454P
MC75454U
SN75454BP
MC75450L
MC75450P
MC75461U
MC75461P
MC75462U
MC75462P
MC75463U
MC75463P
MC75464U
MC75464P
MC75491P
MC75491P
MC75491P
MC75491P
MC75492P
MC75492P
MC75492P
MC75492P
LM301AH
MC1776CG
MC1776CG
MC1776G
LM301AH
LM301AH
LM101AH
LM301AH
LM301AH
LM101AH
MC1595L
MC1595L
MC1595G
MC1408L8
MC1408L8
MC1408L8
MC1508L8

A05S9S0 CA3054
PART NO.
MOTOROLA
MOTOROLA
DIRECT
SIMILAR
ADS59SD
AD560J
AD580K
AD580M
A0580S
AD580T
AD741CJ
AD741J
AD741K
AD741L
AD741S
AD7520D
AD7520F
AD7520N
AM26S10DC
AM26S10PC
AM26S11DC
AM26S11PC
AM725A31T
AM166039F
AM166039T
AMLM101
AMLM101A
AMLM101AD
AMLM101AF
AMLM101D
AMLM101F
AMLM105
AMLM105F
AMLM10SH
AMLM107
AMLM107D
AMLM107F
AMLM111D
AMLM111H
AMLM201
AMLM201A
AMLM201AD
AMLM201AF
AMLM201D
AMLM201F
AMLM205
AMLM205F
AMLM205H
AMLM207
AMLM2070
AMLM207F
AMLM2110
AMLM211H
AMLM301
AMLM301A
AMLM301AD
AMLM301D
AMLM30S
AMLM30SA
AMLM30SF
AMLM305H
AMLM311D
AMLM311H
AMU3F7733312
AMU3F7733393
AMU3F7748312
AMU3I7741312
AMU3I7741393
AMU5B7733312
AMU5B7733393
AMU5B7741312
MC1508L8
MC1403U
MC1403P1
MC1403AP1
MC1503U
MC1S03AU
MC1741CG
MC1741G
MC1741G
MC1741G
MC1741SG
MC3410L
MC3410L
MC3410L
MC26S10L
MC26S10P
MC26S11L
MC26S11P
MC1556G
LM301AH
LM301AH
IM 101AH
LM101AH
LM101AH
LM101AH
LM101AH
LM101AH
LM105H
LM105H
LM105H
LM107H
LM107H
LM107H
LM111J
LM111H
LM201AH
LM201AH
LM201AN
LM201AH
LM201AN
LM201AH
LM205H
LM20SH
LM205H
IM207H
LM207H
LM207H
LM211J
LM211H
LM301AH
LM301AH
LM301AJ
LM301AJ
LM305H
LM305H
LM305H
LM305H
LM311J-8
LM311H
MC1733L
MC1733CL
MC1748G
MC1741F
MC1741CL
MC1733G
MC1733CG
MC17416
PART NO.
MOTOROLA
MOTOROLA
DIRECT
SIMILAR
AMU5B7741393 MC1741CG
AMU5B7747312 MC1747G
AMU5B7747393 MC1747CG
AMU5B7748312 MC1748G
AMU5B7748393 MC1748CG
AMU5R7723312 MC1723G
AMU5R7723393 MC1723CG
AMU6A7723312 MC1723L
AMU6A7723393 MC1723CL
AMU6A7733312 MC1733L
AMU6A7733393 MC1733CL
AMU6A7741312 MC1741L
AMU6A7741393 MC1741CL
AMU6A7748312
AMU6A7748393
AMU6W7747312 MC1747L
AMU6W7747393 MC1747CL
CA101AT
LM101AH
CA101T
LM101AH
LM107H
CA107T
LM108AJ-8
CA108AS
CA108AT
LM108AH
LM108J-8
CA108S
LM108H
CA108T
LM139AJ
CA139AG
CA139G
LM139J
LM201AH
CA201AT
CA201T
LM207H
CA207T
CA208AT
LM208AH
LM208J-8
CA208S
LM208H
CA208T
LM239AN
CA239AE
LM239AJ
CA239AG
LM239N
CA239E
LM239J
CA239G
LM301AH
CA301AT
CA307T
LM307H
LM308N
CA308AS
CA308AT
LM308AH
LM308H
CA308S
CA339AE
LM339AN
LM339AJ
CA339AG
LM339N
CA339E
LM339J
CA339G
MC1723CP
CA723CE
CA741CS
MC1741CP1
CA741CT
MC1741CG
CA741S
MC1741U
CA741T
MC1741G
CA747CE
MC1747CL
CA747CF
MC1747CL
CA747CT
MC1747CG
CA747E
MC1747L
CA747F
MC1747L
CA747T
MC1747G
CA748CS
MC1748CP1
CA748CT
MC1748CG
CA748S
MC1748U
CA748T
MC1748G
CA758E
CA1310E
MC1310P
MC1352P
CA1352E
MC1391P
CA1391E
MC1394P
CA1394E
MC1398P
CA1398E
CA14S8S
MC1458CP1
1-11
MC1748G
MC.1748CP1
LM201AH
MC1310P
PART NO.
CA1458T
CA1558S
CA1558T
CA2111AE
CA2111AQ
CA3000
CA3001
CA3002
CA3004
CA3005
CA300&
CA3007
CA3008
CA3008A
CA3010
CA3010A
CA3011
CA3012
CA3013
CA3014
CA3015
CA3015A
CA3016
CA3016A
CA3020
CA3020A
CA3021
CA3022
CA3023
CA3026
CA3028A
CA3028AF
CA3028AS
CA3028B
CA3028BF
CA3028BS
CA3029
CA3029A
CA3030
UA3030A
CA3031
CA3032
CA3033
CA3033A
CA3035
CA3035V1
CA3037
CA3037A
CA3038
CA3038A
CA3040
CA3041
CA3042
CA3043
CA3044
CA3044V1
CA3045
CA3045F
CA3046
CA3047
CA3047A
CA3048
CA3052
CA3053
CA3053F
CA3053S
CA3054
MOTOROLA
MOTOROLA
SIMILAR
DIRECT
MC1458G
MC1SS8U
MC1558G
MC1357P
MC1357PO
MC1550G
MC1550G
MC1550G
MC1550G
MC1550G
MC1550G
MC1550G
MC1709F
MC1709F
MC1709G
MC1709G
MC1590G
MC1590G
MC1357P
MC1357P
MC1709G
MC1709G
MC1709F
MC1709F
MC1554G
MC1454G
MC1590G
MC1590G
MC1590G
CA3054
MC1550G
MC1550G
MC1550G
MC1550G
MC1550G
MC1S50G
MC170SP2
MC1709P2
MC1709P2
MC1709P2
MC1712G
MC1712CG
MC1533L
MC1533L
MC1352P
MC1352P
MC1709L
MC1709L
MC1709L
MC1709L
MC1510G
MC1351P
MC1357P
MC1357P
MC1364P
MC1364P
MC3346P
MC3346P
MC3346P
MC1433L
MC1433L
MC3301P
MC3301P
MC1550G
MC1550G
MC1S50G
CA3054

CA3056 DS8897N
PART NO.
CA3056
CA3056A
CA3058
CA3059
CA3064
CA3064E
CA3065
CA3066
CA3067
CA3068
CA3070
CA3071
CA3072
CA3076
CA3078AS
CA3078AT
CA3078S
CA3078T
CA3079
CA3085
CA3085A
CA3085AF
CA3085AS
CA3085B
CA3085BF
CA3085BS
CA3085F
CA3085S
CA3086
CA3086F
CA3090AQ
CA3091D
CA3120E
CA3125E
CA3134E
CA3134EM
CA3134QM
CA3136A
CA3137E
CA3139
CA3146
CA3401E
CA6078AS
CA6078AT
CA6741S
CA6741T
CA3302E
CMP-01CJ
CMP-01CP
D555CJ
03232
03242
03245
08216
08226
DAC-01
DAC-08
DAC-IC10BC
OM7820AD
DM7820J
DM7822J
DM7837J
OM7838J
OM7887J
OM7887N
0M7889J
OM7889N
MOTOROLA
MOTOROLA
DIRECT.
SIMILAR
MC1741C6
MC1741G
CA3059
CA3059
MC1364P
MC1364P
MC1358P
MC1399P
MC1323P
MC1352P
MC1399P
MC1399P
MC1323P
MC1590G
MC1776G
MC1776G
MC1776CG
MC1776CG
CA3059
MC1723G
MC1723G
MC1723L
MC1723G
MC1723G
MC1723L
MC1723G
MC1723L
MC1723G
MC3386P
MC3346P
MC1310P
MC1594L
MC1344P
MC1323P
TDA1190Z
TDA1190Z
TDA1190Z
MC3346P
MC1323P
CA3139
MC3346P
MC3401P
MC1776G
MC1776G
MC17766
MC1776G
MC3302P
MC15S6G
MC1556P
MC1555G
MC3232AP
MC3242AP
MC3245P
MC8T26AL
MC8T26L
MC1S06L
MC1408L8
MC3410L
MC75140P1
MC75140P1
MC1489AL
MC3437L
MC3438L
MC3490P
MC3490P
MC3491P
MC3491P
PART NO.
OM7897J
OM7897N
OM8820AN
DM8820J
DM8820N
DM8822J
OM8822N
OM8837N
OM8838N
OM8861N
OM8863N
DM8887J
DM8889J
0M8897J
OM75491N
DM75492N
DS0026CG
DS0026CH
DS0026CJ
DS0026CN
OS0026G
DS0026H
DS0026J
DS0056CG
DS0056CH
DS0056CJ
DS0056CN
DS0056G
DS0056H
DS0056J
DS1488J
DS1488N
DS1489AJ
0S1489AN
DS1489J
OS1489N
DS3486J
DS3486N
OS3487J
DS3487N
OS3612H
DS3612N
OS3632H
OS3632J
OS3632N
DS3644J
DS3644N
DS3650J
OS36SON
OS3651J
OS3651N
OS3652J
DS3652N
0S3653J
DS3653N
OS3674J
DS3674N
DS55107J
DS55107W
DS55108J
DS55108W
DS55110J
OS55121J
OS55121W
OS55122J
DS55122W
OS55325J
MOTOROLA
MOTOROLA
DIRECT
SIMILAR
MC3494P
MC3494P
MC75140P1
MC75140P1
MC75140P1
MC1489AL
MC1489AP
MC3437P
MC3438P
MC75491P
MC75492P
MC3490P
MC3491P
M03494P
MC75491P
MC75492P
MMK0026CG
MMK0026CG
MMH0026CL
DS0026CP1
MMH0026G
DS0026G
DS0026L
MMH0026CG
MMH0026CG
MMH0026CL
MMH0026CP1
MMH0026G
MMHQ026G
MMK0026L
MC1488L
MC1488P
MC1489AL
MC1489AP
MC1489L
MC1489P
MC3486L
MC3486P
MC3487L
MC3487P
MC1472U
MC1472P1
MC1472U
MC1472U
MC1472P1
MC3245L
MC3245P
MC3450L
MC3450P
MC3430L
MC3430P
MC3452L
MC3452P
MC3432L
MC3432P
MC3460L
MC3460P
MC55107L
MC75107L
MC55108L
MC55108L
MC75S110L
MC8T13L
MC8T13L
MC8T14L
MC8T14L
MC55325L
1-12
PART NO.
DS75107J
DS75107N
DS75108J
DS75108N
DS75110J
DS75110N
DS75121J
OS75121N
DS75122J
DS75122N
DS75123J
DS75123N
OS75124J
DS75124N
DS75207J
DS75207N
DS75208J
DS75208N
OS75325J
DS75325N
DS75450J
DS75450N
OS75451H
DS75451N
DS75452H
DS75452N
OS75453H
DS75453N
OS75454H
OS75454N
DS75461H
DS75461N
OS75462H
DS75462N
DS75463H
OS75463N
DS75464H
DS75464N
OS75491J
DS75491N
DS75492J
OS75492N
DS7837J
DS7837W
OS7838J
OS7838W
OS7887J
DS7889J
DS7897J
DS8833J
0S8833N
OS8834J
OS8834N
OS8835J
DS8835N
0S8837J
DS8837N
DS8838J
DS8838N
DS8839J
DS8839N
DS8887J
OS8887N
DS8869J
OS8889N
DS8897J
0S8897N
MOTOROLA
MOTOROLA
DIRECT
SIMILAR
MC75107L
MC75107P
MC75108L
MC75108P
MC75S110L
MC75S110P
MC8T13L
MC8T13P
MC8T14L
MC8T14P
MC8T23L
MC8T23P
MC8T24L
MC8T24P
MC75107L
MC75107P
MC75108L
MC75108P
MC75325L
MC75325P
MC75450L
MC75450P
MC75451U
SN75451BP
MC75452U
SN75452BP
MC75453U
SN75453BP
MC75454U
SN75454BP
MC75461U
MC75461P
MC75462U
MC75462P
MC75463U
MC75463P
MC75464U
MC75464P
MC75491P
MC75491P
MC75492P
MC75492P
MC3437L
MC3437L
MC3438L
MC3438L.
MC3490P
MC3491P
MC3494P
MC8T28L
MC8T28P
MC8T26AL
MC8T26AP
MC8T26AL
MC8T26AP
MC3437L
MC3437P
MC3438L
MC3438P
MC8T28L
MC8T28P
MC3490P
MC3490P
MC3491P
MC3491P
MC3494P
MC3494P

HA1199 LM117H
PART NO.
MOTOROLA
MOTOROLA
SIMILAR
DIRECT
HA1199
ICB8000C
ICB8001C
ICB8741C
ICK8500ATV
ICH8SOOTV
ICHOIALNOP
ICL101ALNFB
1CL101ALNTY
(CI301ALNPA
ICL301ALNTY
ICL741CLNPA
ICL741CLNTY
ICL741LNDP
ICL741LNFB
ICL741LNTY
ICL8001CTZ
ICL8001MTZ
ICL8007CTA
(CL8007MTA
ICL8008CPA
ICL8008CTY
ICL8013A
ICL8013B
ICL8013C
ICL8017CTW
ICL8017MTW
ICL8021C
ICL8021M
ICL8022C
ICL8022M
ICL8043CDE
ICL8043CPE
ICL8043M0E
ICL8048CDE
ICL8046DPE
IH5101UE
IH5101MIE
in641
in652
ITT654
ITT656
ITT1330
ITT1352
1773064
ITT3065
ITT3066
ITT3701
in3707
ITT3710
in3714
L144AP
1201
L202
L203
LD111CJ
LF152D
LF155AH
LF155AJG
LF155AL
LF155H
LF155JG
LF155L
LF156AH
LF156AJG
LF156AL
LF156H
HA1199
LM111J
LM111J
MC1741CG
MC1776CG
MC1776CG
LM101AH
LM101AH
LM101AH
LM301AH
LM301AH
MC1741CP1
MC1741CP1
MC1741L
MC1741L
MC1741L
LM111J
LM111J
MC1709CG
MC1709CG
LM301AN
LM301AN
MC1594G
MC1594G
MC1594G
LM301AN
LM301AN
MC1776G
MC1776G
MC1776G
MC1776G
MC1776G
MC1776G
MC1776G
MC1776G
MC1776G
MC1545G
MC1545G
MC1385P
MC1411P
MC1412P
MC1413P
MC1330P
MC1352P
MC1364P
MC1358P
MC1399P
TDA1I90Z
MC1399P
MC1391P
MC1394P
LM324N
MC1411P
MC1412P
MC1413P
MC1405L
LF155J
LF155AH
LF155AJ
LF155AH
LF155H
LF155J
LF1S5H
LF156AH
LF156AJ
LF156AH
LF156H
PART NO.
LF156JG
LF156L
LF157AH
LF157AJG
LF157AL
LF157H
LF157JG
LF157L
LF252D
LF255H
LF255JG
LF255L
LF255P
LF256H
LF256JG
LF256L
LF256P
LF257H
LF257JG
LF257L
LF257P
LF347N
LF347AN
LF347BN
LF351H
LF351AH
LF351BH
LF351N
LF351AN
LF351BN
LF352D
LF353H
LF353AH
LF3538H
LF353N
LF3S3AN
LF353BN
LF355AH
LF355AJG
LF355AL
LF355AP
LF355BH
LF355BJ
LF355BN
LF355H
LF355JG
LF355L
LF355N
LF355P
LF356AH
LF356AL
LF356AJG
LF356AP
LF356BH
LF3568J
LF356BN
LF356H
LF356JG
LF356L
LF356N
LF356P
LF357AH
LF3S7BH
LF357BJ
LF357BN
LF357H
LF357JG
MOTOROLA
MOTOROLA
DIRECT
SIMILAR
LF156J
LF156H
LF157AH
LF157AJ
LF157AH
LF157H
LF157J
LF157H
LF255J
LF2S5H
LF255J
LF255H
LF255J
LF256H
LF256J
LF256H
LF256J
LF257H
LF257J
LF257H
LF2S7J
MC34Q04P
MC34004AP
MC34004BP
MC34001G
MC34001AG
MC34001BG
MC34001P
MC34001AP
MC34001BP
LF355J
MC34002G
MC34002AG
MC34002BG
MC34002P
MC34002AP
MC34002BP
LF355AH
LF355AJ
LF355AH
LF355AN
LF355BH
LF355BJ
LF355BN
LF355H
LF355J
LF355H
LF355N
LF355N
LF3S6AH
LF356AH
LF356AJ
LF3S6AN
LF3S6BH
LF356BJ
LF356BN
LF356H
LF356J
LF356H
LF356N
LF356N
LF357AH
LF3S7BH
LF357BJ
LF357BN
LF357H
LF357J
1-13
PART NO.
LF357L
LF357N
LF357P
IH0001ACH
LK0001AH
LKOOOIACO
LH0001AD
LH0001ACF
LH0001AF
LH0002CH
LK0002H
LH0004CH
LK0004H
LK0042CH
LH101F
LH101H
LH201F
LH201H
LH740ACH
LH740AH
LH2101AD
LH2101AF
LH2201AD
LH2201AF
LH2301AD
LH2301AF
LM100F
LM100H
LM101AD
LM101AF
LM101AH
LM101AJ
LM101AJ-14
LM101AJG
LM101AL
LM101D
LM101F
LM101H
LM101J-14
LM104F
LM104H
LM104J
LM104L
LM105F
LM105H
LM105JG
LM105L
LM106H
LM107F
LM107H
LM107L
LM108AD
LM108AF
LM1C8AH
LM108AJ
LM108D
LM108F
LM108H
LM109H
LM10SK
LM109LA
LM111D
LM111H
LM1120
LM112F
LM112H
LM117H
MOTOROLA
MOTOROLA
SIMILAR
DIRECT
REPLACEMENT
REPLACEMENT
IF357H
LF357N
LF3S7N
MC1776CG
MC1776G
MC1776CG
MC1776G
MC1776CG
MC1776G
MC1538R
MC1538R
MC1436G
MC1536G
MC1776G
MC1741F
MC1741G
MC1741F
MC1741G
LF355H
LH55H
MC1537L
MC1537L
MC1537L
MC1537L
MC1437L
MC1437L
LM105H
LM105H
LM101AH
LM101AH
LM101AH
LM101AJ
LM101AJ
LM101AJ
LM101AH
LM101AJ
LM101AH
LM101AH
LM101AJ
LM104H
LM104H
LM104H
LM104H
LM105H
LM105M
LM105H
LM105H
MC1710G
LM107H
LM107H
LM107H
LM108AJ
LM108AF
LM108AH
LM108J-8
LM108J
LM108F
LM108H
LM109H
LM109K
LM109K
LM111J
LM111H
MC1556L
MC1556L
MC1556G
LM117H

LM117K LM309H
PART NO.
MOTOROLA
MOTOROLA
DIRECT
SIMILAR
LM117K
LM118D
LM118F
LM118H
LM120H-5.0
LM120H-5.2
LM120H-6.0
LM120H-8.0
LM120H-12
LM120H-15
LM120H-18
LM120H-24
LM120K-S.0
LM120K-5.2
LM120K-6.0
LM120K-8.0
LM120K-12
LM120K-15
LM120K-18
LM120K-24
LM122F
LM122H
IM124AD
LM124AF
LM124AJ
LM124D
LM124F
LM124J
LM125H
LM126H
LM128H
LM139AO
LM139AJ
LM1390
LM139J
LM140K-5.0
LM140K-6.0
LM140K-8.0
LM140K-12
LM140K-15
LM140K-18
LM140K-24
LM140LAH-S.0
LM140LAH-6.0
LM140LAH-8.0
LM140LAH-12
LM140LAH-15
LM140LAH-18
LM140LAH-24
LM143D
LM143F
LM143H
LM14SK
LM148D
LM148J
LM148F
LM149D
LM149F
LM158AH
LM158H
LM158JG
LM158L
LM163J
LM171H
LM200F
LM200H
LM201AD
LM117K
MC1741SL
MC1741SL
MC1741SG
LM120H-5.0
MC7905.2CK
LM120H-6.0
LM120H-8.0
LM120H-12
LM120H-15
LM120H-18
LM120H-24
LM120K-5.0
MC7905.2CK
LM120K-6.0
LM120K-8.0
LM120K-12
LM120K-15
LM120K-18
LM120K-24
MC1555G
MC1555G
LM124J
LM124J
LM124J
LM124J
LM124J
LM124J
MC1568G
MC1568G
MC1568G
LM139AJ
LM139AJ
LM139J
LM139J
LM140K-5.0
LM140K-6.0
LM140K-8.0
LM140K-12
LM140K-15
LM140K-18
LM140K-24
MC76L05ACG
MC78L06ACG
MC78L08ACG
MC78L12ACG
MC78L15ACG
MC78L18ACG
MC78L24ACG
MC1536G
MC1536G
MC1S36G
MC790SCK
LM148J
LM148J
MC4741L
MC4741L
MC4741L
LM158H
LM158H
LM158J
LM158H
MC3450L
MC1590G
LM205H
LM205H
LM201AJ
PART WO.
LM201AF
LM201AH
LM201AJ
LM201AJG
LM201AL
LM201AN
LM201AP
LM201AJ-14
LM201D
LM201F
LM201H
LM201J
LM201J-14
LM204H
LM204F
LM20SF
LM20SH
LM206H
LM207F
LM207H
LM208AD
LM208AF
LM208AH
LM208AJ
LM208D
LM208F
LM2C3H
LM20SK
LM209H
LM211D
LM211H
LM212D
LM212F
LM212H
LM217H
LM217K
LM2180
LM218F
LM218H
LM22CH-5.0
LM220H-5.2
LM220H-6.0
IM220H-8.0
LM220H-12
LM220H-15
LM220H-18
LM220H-24
LM220K-5.0
IM220K-5.2
LM220K-6.0
LM220K-8.0
LM220K-12
LM220K-15
LM22CK-18
LM220K-24
LM222H
LM224AD
LM224AF
LM224AJ
LM224D
LM224F
LM224J
LM225H
LM226H
LM228H
LM239AO
LM239AJ
MOTOROLA
MOTOROLA
DIRECT
SIMILAR
LM201AH
LM201AH
LM201AJ
LM201AJ
LM201AH
LM201AN
LM201AN
LM201AJ
LM201AJ
LM201AH
LM201AH
LM201AJ
LM201AJ
LM204H
LM204H
LM205H
LM20SH
MC1710CG
LM207H
LM207H
LM208AJ
LM208AF
LM208AH
LM208AJ-8
LM208J-8
LM208F
LM2C8H
LM209K
LM209H
LM211J
LM211H
MC1556L
MC1556L
MC1456G
LM217H
LM217K
MC1741SL
MC1741SI
MC1741SG
MC7905CK
MC7905.2CK
MC7906CK
MC7908CK
MC7912CK
MC7915CK
MC7918CK
MC7924CK
MC7905CK
MC79052CK
MC7906CK
MC7908CK
MC7912CK
MC79I5CK
MC7918CK
MC7924CK
MC1555G
LM224J
LM224J
LM224J
LM224J
LM224L
LM224J
MC1568G
MC1S68G
MC1568G
LM239AJ
LM239AJ
PART WO.
MOTOROLA
MOTOROLA
DIRECT
SIMILAR
I LM239D
I LM239J
LM240LAH-5.0
LM240LAH-6.0
LM240LAH-8.0
LM240LAH-12
LM240LAH-15
LM240LAH-18
LM240LAH-24
LM24CLAZ-5.0
LM240LAZ-6.0
LM240LAZ-8.0
LM240LA2-12
LM240LAZ-I5
LM240LA2-18
LM240LAZ-24
LM243H
IM245K
LM2480
LM248J
LM249D
LM249J
LM258AH
LM258H
LM2901N
LM300F
LM271H
LM300H
LM301AD
LM301AF
LM301AH
LM301AJ
LM301AJG
LM301AL
LM301AN
LM301AP
LM302H
LM304F
LM304H
LM304J
LM304L
LM304N
LM305AH
LM305AJG
LM305AL
LM305AP
LM305F
LM305H
LM305JG
LM305L
LM305P
LM306H
LM307F
LM307H
LM307L
LM307N
LM307P
LM308AD
LM308AF
LM308AH
LM308AH-1
LM308AH-2
LM308AJ
LM308D
LM308H
LM308N
LM309H
LM239J
LM239J
MC78L05ACG
MC78LC6CG
MC78L08ACG
MC78L12ACG
MC78L15ACG
MC78L18ACG
MC78L24ACG
MC78L05ACP
MC78LG6ACP
MC78L08ACP
MC78L12ACP
MC78L15ACP
MC78LI8ACP
MC78L24ACP
MC1536G
MC7905CK
LM248J
LM248J
MC4741L
MC4741L
LM258H
LM258H
LM2901N
LM305H
MC1590G
LM305H
LM301AJ
LM301AH
LM301AH
LM301AJ
LM301AJ
LM301AH
LM301AN
LM301AN
LM310H
LM304H
LM304H
LM304H
LM304H
LM304H
LM305H
LM305H
LM305H
LM305H
LM305H
LM305H
LM305H
LM305H
LM305H
MC1710CG
LM307H
LM307H
LM307H
LM307N
LM307N
LM308AJ
LM308AJ
LM308AH
LM308AH
LM308AH
LM308AJ-8
LM308J
LM308H
LM308N
LM30SH

LM309K LM741J-14
PART NO.
MOTOROLA
MOTOROLA
SIMILAR
DIRECT
LM309K
LM309KC
LM309LA
LM311D
LM311H
LM311N
LM31 IN-14
LM3120
LM312F
LM312H
LM317H
LM317K
LM317P
LM317T
LM318D
LM318F
LM318H
LM318N
LM320H-5.0
LM320H-5.2
LM320H-6.0
LM320H-8.0
LM320H-12
LM320H-15
LM320H-18
LM320H-24
LM320K-5.0
LM320K-6.0
LM320K-8.0
LM320K-12
LM320K-15
LM320K-18
LM320K-24
LM320MP-5.0
LM320MP-5.2
LM320MP-6.0
LM320MP-8.0
LM320MP-12
LM320MP-15
LM320MP-18
LM320MP-24
LM320T-S.0
LM320T-5.2
LM320T-6.0
LM320T-8.0
LM320T-12
LM320T-15
LM320T-18
LM320T-24
LM322H
LM322N
LM324AJ
LM324AN
LM324J
LM324N
LM325AN
LM325H
LM325N
LM326H
LM326N
LM328AN
LM328H
LM328N
LM339AD
LM339AN
LM339N
LM34GK-5.0
LM309K
LM309K
LM309K
LM311J
LM311H
LM311N
IM311J
MC1456L
MC1456L
MC1456G
LM317H
LM317K
LM317T
LM317T
MC1741SCL
MC1741SCL
MC1741SCG
MC1741SCP1
LM320H-5.0
MC7905.2CK
LM320H-6.0
LM520H-8.0
LM320H-12
IM320H-15
LM320H-18
LM320H-24
LM320K-5.0
LM320K-6.0
LM320K-8.0
LM320K-12
LM320K-15
LM320K-18
LM320K-24
MC7905CT
MC7905.2CT
MC7906CT
MC7908CT
MC7912CT
MC7915CT
MC7918CT
MC7924CT
LM320T-5.0
MC7905.2CT
LM320T-6.0
LM320T-8.0
LM320T-12
LM320T-15
LM320T-18
LM320T-24
MC1455G
MC1455P1
LM324J
LM324N
LM324J
LM324N
LM339AJ
LM339AN
LM339N
LM340K-5.0
MC3403P
MC1468L
MC1468G
MC1468L
MC1468G
MC1468L
MC1468L
MC1468G
MC1468L
PART NO.
MOTOROLA
MOTOROLA
SIMILAR
OtRECT
LM340K-6.0
LM340K-8.0
LM340K-12
LM340K-15
LM340K-18
LM340K-24
LM340KC-5.0
LM340KC-6.0
LM340KC-8.0
LM340KC-12
LM340KC-15
LM340KC-18
LM340KC-24
LM340LAH-5.0
LM340LAH-6.0
LM340LAH-8.0
LM340LAH-12
LM34QLAH-15
LM340LAH-18
LM340LAH-24
LM340LAZ-5.0
LM340LAZ-6.0
LM340LAZ-8.0
LM340IAZ-12
LM340LAZ-15
LM340LAZ-18
LM340LAZ-24
LM340T-5.0
LM340T-6.0
LM340T-8.0
LM340T-12
LM340T-15
LM340T-18
LM340T-24
LM341P-5.0
LM341P-6.0
LM341P-8.0
LM341P-12
LM341P-15
LM341P-18
LM341P-24
LM342P-5.0
LM342P-6.0
LM342P-8.0
LM342P-12
LM342P-15
LM342P-18
LM342P-24
LM343D
LM343H
LM345K
LM348D
LM348J
LM346N
LM349D
LM349J
LM349N
LM358AH
LM358AN
LM:58H
LM058JG
LM358L
LM358N
LM358P
LM363AJ
LM363AN
LM363J
LM340K-6.0
LM340K-8.0
LM340K-12
LM340K-15
LM340K-18
LM340K-24
MC7805CK
MC7806CK
MC7808CK
MC7812CK
MC7815CK
MC7818CK
MC7824CK
'
MC78L05ACG
MC78L06ACG
MC78L08ACG
MC78L12ACG
MC78L15ACG
MC78L18ACG
MC78L24ACG
MC78L05ACP
MC78L06ACP
MC78L08ACP
MC78L12ACP
MC78L15ACP
MC78L18ACP
MC78L24ACP
MC7805CT
MC7806CT
MC7808CT
MC7812CT
MC7815CT
MC7818CT
MC7824CT
MC78M05CT
MC78M06CT
MC78M08CT
MC78M12CT
MC78M15CT
MC78M18CT
MC78M24CT
MC78M05CT
MC78M06CT
MC78M08CT
MC78M12CT
MC78M15CT
MC78M18CT
MC78M24CT
MC1436G
MC1436G
MC7905CK
LM348J
LM348J
LM348N
MC4741CL
MC4741CL
MC4741CL
LM358H
LM356N
LM358H
LM358J
LM358H
LM3S8N
LM358N
MC3450L
MC3450P
MC3450L
1-15
PART NO.
MOTOROLA
MOTOROLA
SIMILAR
OtRECT
LM363N
LM371H
LM376JG
LM376L
LM376N
LM376P
LM386N
LM555CH
LM555CN
LM555H
LM556CD
LM556CJ
LM556CN
LM556D
LM556J
LM565CH
LM565CN
LM565H
LM703LN
LM709AH
LM709AJ
LM709CH
LM709CJ
LM709CN
LM709CN-8
LM709H
LM709J
LM710CH
LM710CN
LM710H
LM711CH
LM711CN
LM711H
LM723CD
LM723CH
LM723CJ
LM723CN
LM723D
LM723H
LM723J
LM733CD
LM733CH
LM733CJ
LM733CN
LM733D
LM733H
LM733J
LM741AD
LM741AF
LM741AH
LM741AJ-14
LM741CD
LM741CF
LM741CH
LM741CJ
LM741CJ-14
IM741CN
LM741CN-14
LM741D
LM741ED
LM741EH
LM741EJ
LM741EJ-14
LM741EN
LM741F
LM741H
LM741J-14
MC3450P
MC1590G
LM305H
LM305H
LM305H
LM305H
MC1306P
MC1455G
MC1455P1
MC1555G
MC3456L
MC3456L
MC3456P
MC3556L
MC3556L
NE565N
NE565N
NE565N
MC1350P
MCI 709AG
MC1709AL
MC1709CG
MC1709CL
MC1709CP2
MC1709CP1
MC1709G
MC1709L
MC1710CG
MC1710CP
MC1710G
MC1711CG
MC1711CP
MC1711G
LM723CJ
LM723CH
LM723CJ
LM723CN
LM723J
LM723H
LM723J
MC1733CL
MC1733CG
MC1733CL
MC1733CP
MC1733L
MC1733G
MC1733L
MC1741L
MC1741F
MC1741G
MC1741L
LM1741CJ
LM741CF
LM741CH
LM741CJ
LM741CJ-14
LM741CN
LM741CN-14
LM741J-14
MC1741CL
MC174ICG
MC1741CU
MC1741CL
MC1741CP1
LM741F
LM741H
LM741J-14

LM746N ML107T
PART NO.
LM746N
LM747CD
LM747CF
LM747CH
LM747CJ
LM747CN
LM747D
LM747F
LM747H
LM747J
LM748CH
LM748CJ
LM748CN
LM748H
LM748J
LM1310N
LM135 IN
LM1391N
LM1394N
LM1414J
LM1414N
LM1458H
LM1458J
LM1458N
LM1458N-14
LM1488J
LM1488N
LM14S9AJ
LM1489AN
LM1489J
LM1489N
LM1496H
LM1496J
LM1496N
LM1514J
LM1558H
LM1558J
LM1596H
LM1596J
LM1800AN
LM1800N
LM 1805
LM1808N
LM1828N
LM1841N
LM1845N
LM1848N
LM1850N
LM1900D
LM2111N
LM2113N
LM2900J
LM2900N
LM2902J
LM2902N
LM2904N
LM2905N
LM3011H
LM3026
LM3045
LM3046N
LM3054
LM3064N
LM306SN
LM3066N
LM3067N
LM3070N
MOTOROLA
MOTOROLA
DIRECT
SIMILAR
MC1323P
LM747CJ
LM747CF
LM747CH
LM747CJ
LM747CN
LM747J
LM747F
LM747H
LM747J
MC1748CG
MC1748CU
MC1740CP1
MC1748G
MC1748U
MC1310P
MC1351P
MC1391P
MC1394P
MC1414L
MC1414P
MC14586
MC1458U
MC1458P1
MC1458P2
MC1488L
MC1488P
MC1489AL
MC1489AP
MC1489L
MC1489P
MC1496G
MC1496L
MC1496P
MC1514L
MC1558G
MC1558U
MC1596G
MC1596L
MC1310P
MC1310P
MC1385P
TDA1190Z
MC1323P
MC1356P
MC1344P
MC1323P
MC3426L
MC3301L
MC1357P
MC1357P
MC3301L
MC3301P
LM2902J
LM2902N
LM2904N
MC1455P1
MC1550G
CA3054
MC3346P
MC3346P
CA3054
MC1364P
MC1358P
MC1399P
MC1323P
MC139SP
PART NO.
MOTOROLA
MOTOROLA
DIRECT
SIMILAR
LM3071N
LM3075N
LM3086N
LM3126
LM3146
LM3146A
LM3301N
LM3302J
LM3302N
LM3401N
LM3900N
LM3905N
LM4250CH
LM4250CN
LM4250H
LM5S25J
LM5528J
LM5529J
LM5534J
LM5535J
LM5538J
LM5529J
LM7524J
LM7524N
LM7525J
LM7805KC
LM7806KC
LM7808KC
LM7812KC
LM7815KC
LM7818KC
LM7824KC
LM78L05ACH
LM78L05ACZ
LM78L05CH
LM78L05CZ
LM78L08ACH
LM78L08ACZ
LM78L08CH
LM78L08CZ
LM78L12ACH
LM78L12ACZ
LM78L12CH
LM78L12CZ
LM76L15ACH
LM78L15ACZ
LM78L15CH
LM78L15CZ
LM78L18ACH
LM78L18ACZ
LM78L18CH
LM78L18CZ
LM78L24ACH
LM78L24ACZ
LM78L24CH
LM78L24CZ
LM55107AJ
LM55108AJ
LM55109J
LM55110J
LM55121J
LM55122J
LM55123J
LM55124J
LMS5325N
LM75107AJ
LM75107AN
MC1399P
MC1375P
MC3386P
MC1399P
MC3346P
MC3346P
MC3301P
MC3302L
MC3302P
MC3401P
MC3401P
MC1455P1
MC1776CG
MC1776CP1
MC1776G
MC5525L
MC5528L
MC5529L
MC5534L
MC5535L
MC5538L
MC5539L
MC7524L
MC7524P
MC7525L
MC7805CK
MC7806CK
MC7808CK
MC7812CK
MC7815CK
MC7818CK
MC7824CK
MC78L05ACG
MC78L05ACP
MC78L05CG
MC78L05CP
MC78L08ACG
MC78L08ACP
MC78L08CG
MC78L08CP
MC78L12ACG
MC78L12ACP
MC78L12CG
MC78L12CP
MC78L1SACG
MC78L15ACP
MC78L15CG
MC78L15CP
MC78L18ACG
MC78L18ACP
MC78L18CG
MC78L18CP
MC78L24ACG
MC78L24ACP
MC78L24CG
MC78L24CP
MC55107L
MC55108L
MC75S110L
MC75S110L
MC8T13L
MC8T14L
MC8T23L
MC8T24L
MC55325L
MC75107L
MC75107P
1-16
PART NO.
LM75108AJ
LM75108AN
LM75110J
LM75110N
LM75121J
LM75121N
LM75122J
LM7S122N
LM75123J
LM7S123N
LM75124J
LM75124N
LM75207L
LM75207N
LM75208J
LM75208N
LM75324J
LM75324N
LM75325J
LM75325N
LM75450N
LM75451N
LM75452N
LM75453N
LM75454N
MC1310A
MC1408B
MC1408F
MC1458JG
MC1458L
MC1458P
MC1558JG
MC1558L
MH0026H
MH0026CH
MH0026CN
MH0026G
MK0026CG
MH0026F
MH0026CF
MIC709-1
MIC709-5
MIC710-1C
MIC710-5C
MIC711-1C
MIC711-5C
MIC712-1B
M1C712-1C
MIC712-10
MIC712-5B
MIC712-5C
MIC712-5D
MIC723-1
MIC723-5
MIC741-1C
MIC741-1D
MIC741-5C
M1C741-5D
ML101AF
ML101AM
ML 101AT
ML101F
ML101M
ML101T
ML107F
ML107M
ML107T
MOTOROLA
MOTOROLA
DIRECT
SIMILAR
MC75108L
MC75108P
MC75S110L
MC75S110P
MC8T13L
MC8T13P
MC8T14L
MC8T14P
MC8T23L
MC8T23P
MC8T24L
MC8T24P
MC75107L
MC75107P
MC75108L
MC75108P
MC75325L
MC75325P
MC75325P
MC75325L
MC75450P
MC75451P
MC75452P
MC75453P
MC75454P
MC1310P
MC1408P8
MC1408L8
MCI458U
MC1458G
MC14S8P1
MC1558U
MC15S8G
MMH0026CG
MMK0026CG
MMH0026CP1
MMH0026CG
MMK0026CG
MMH0026CL
MMK0026C1
MC1709G
MC1709CG
MC1710G
MC1710CG
MC171tG
MC171 ICG
MC1712F
MC1712G
MC1712L
MC1712CF
MC1712CG
MC1712CL
MC1723G
MC1723CG
MC1741G
MC1741L
MC1741CG
MC1741CL
LM101AH
LM101AH
LM101AH
LM101AH
LM101AH
LM101AH
LM107H
LM107H
LM107H

ML108AF QP-08B
PART NO.
ML108AF
ML 108AM
ML108AT
MI108M
ML108T
ML111M
ML111S
ML111T
ML118F
ML118M
ML118T
ML201AF
ML201AM
ML201AT
ML201F
ML201M
ML201T
ML207F
ML207M
ML207T
ML208AF
ML208AM
ML208AT
ML208M
ML208T
ML211M
ML211S
ML211T
ML218F
ML218M
ML218T
ML301AP
ML301AS
ML301AT
ML301P
ML301S
ML301T
ML307P
ML307S
ML307T
ML308AM
ML308AT
ML308M
ML308T
ML311M
ML311P
ML31IS
ML311T
ML318M
ML318T
ML709AF
ML709AM
ML709AT
ML709CP
ML709CT
ML709F
ML709M
ML709T
ML723CF
ML723CM
ML723CP
ML723CT
ML723F
ML723M
ML723T
ML741AF
ML741AM
MOTOROLA
MOTOROLA
DIRECT
SIMILAR
MC1556G
LM108AJ
LM108AH
LM108J
LM108H
LM111J
LM111J
LM111H
MC1741SG
MC1741SG
MC1741SG
LM201AH
LM201AH
LM201AH
LM201AH
LM201AH
LM201AH
LM207H
LM207H
LM207H
MC1556G
LM208AJ
LM208AH
LM208J
LM208H
LM211J
LM211N
LM211H
MC1741SG
MC1741SG
MC1741SG
LM301AN
LM301AN
LM301AH
LM301AN
LM301AN
LM301AN
LM307H
LM307N
LM307H
LM308AJ
LM308AH
LM308J
LM308H
LM311J
LM311J
LM311N
LM311H
MC1741SCP1
MC1741SCG
MC1709AF
MC1709AL
MC1709AG
MC1709CP2
MC1709CG
MC1709F
MC1709L
MC1709G
MC1723CL
MC1723CL
MC1723CL
MC1723CG
MC1723L
MC1723L
MC1723G
MC1556G
MC1556G
PART NO.
ML741AT
ML741CP
ML741CS
ML741CT
ML741F
ML741M
ML741T
ML747CP
ML747CT
ML747F
ML747M
ML747T
ML748CP
ML748CS
ML748CT
ML748F
ML748M
ML748T
ML1436T
ML1437P
ML1458P
ML1458S
ML1458T
ML1488M
ML1489AM
ML1489M
ML1536T
ML1537M
ML1558M
ML1S58T
ML3046P
ML4250T
ML42S0CS
ML4250CT
ML4251T
ML4251CS
ML4251CT
ML6503M
ML7503M
N5065A
N5070B
N5071A
N5072A
N5556T
N5556V
N5558F
N5558T
N5558V
N5595A
N5595F
N5596A
N5596K
N5709A
N5709G
N5709T
N5709V
N5710A
N5710T
N5711A
N5711K
N5723A
N5723T
N5733K
N5741A
N5741T
N5741V
N5747A
MOTOROLA
MOTOROLA
DIRECT
SIMILAR
MC1556G
MC1741CP2
MC1741CP1
MC1741CG
MC1741F
MC1741L
MC1741G
MC1747CL
MC1747CG
MC1747F
MC1747L
MC1747G
LM301AN
LM301AN
MC1748CG
MC1748G
MC1748G
MC1748G
MC1436G
MC1437P
MC1458P2
MC1458P1
MC1458G
MC1488L
MC1489AL
MC1489L
MC1536G
MC1537L
MC1558I.
MC1558G
MC3346P
MC1776G
MC1776CG
MC1776CG
MC1776G
MC1776CG
MC1776CG
MC1537L
MC1437L
MC1358P
MC1399P
MC1399P
MC1323P
MC1456G
MC1456P1
MC1458L
MC1458G
MC1458P1
MC1495L
MC1495L
MC1496L
MC1496G
MC1709CP2
MC1709CF
MC1709CG
MC1709CP1
MC1710CP
MC1710CG
MC1711CP
MC1711CG
MC1723CP
MC1723CG
MC1733CG
MC1741CP2
MC1741CG
MC1741CP1
MC1747CL
1-17
PART NO.
N5747F
N5748A
N5748T
N8T13B
N8T13P
N8T14B
N8T14E
N8T15A
N8T15F
N8T16A
N8T23B
N8T23E
N8T24B
N8T24E
N8T26AB
N8T26AE
N8T26B
N8T28B
N8T37A
N8T38A
N8T95B
N8T95F
N8T96B
N8T96F
N8T97B
N8T97F
N8T98B
N8T98F
NE501A
NE501K
NE515A
NES15G
NE515K
NE516A
NE516G
NE516K
NE531G
NE531T
NE531V
NE533G
NE533T
NE533V
NE537G
NE537T
NE5401
NE550A
NE550L
NE5S5JG
NE55SL
NE555P
NE555T
NE555V
NE556A
NE556I
NE565A
NES65K
NE592A
NE592K
OP-OIC
OP-OIG
OP-OIH
OP-OU
OP-OIL
OP-OIP
OP-O8
OP-O8A
OP-Q8B
MOTOROLA
MOTOROLA
SIMILAR
DIRECT
MC1747CL
MC1747CG
MC1748CG
MC8T13P
MC8T13L
MC8T14P
MC8T14L
MC1488L
MC1488L
MC1489L
MC8T23P
MC8T23L
MC8T24P
MC8T24L
MC8T26AP
MC8T26AL
MC8T26AP
MC8T28P
MC3437P
MC3438P
MC8T95P
MC8T95L
MC8T96P
MC8T96L
MC8T97P
MC8T97L
MC8T98P
MC8T98L
MC1733CL
MC1733CG
MC1420G
MC1520F
MC1420G
MC1420G
MC1520F
MC1420G
MC1439G
MC1439G
MC1439P
MC1776CG
MC1776CG
MC1776CG
MC1456G
MC1456G
MC1SS4G
MC1723CP
MC1723CG
MC1455U
MC1455G
MC14S5P1
MC14S5G
MC1455P1
MC3456P
MC3456L
NE565N
NE565N
NE592A
NE592K
MC1536
MC1536
MC1536
MC1536G
MC1536G
MC1536P
MC1776
MC1776
MC1776

OP-O8C SG208AM
PART NO.
OP-O8C
OP-O8E
PA239A
RC702T
RC709D
RC7090N
RC708DP
RC709T
RC710DC
RC7tODP
RC710T
RC711DC
RC711DP
RC711T
RC723D
RC723T
RC733D
RC733T
RC741D
RC7410N
RC741DP
RC741Q
RC741T
RC747D
RC747T
RC748T
RC1414DC
RC1414DP
RC1488DC
RC1489ADC
RC1489DC
RC8T13DO
RC1437D
RC1437DP
RC14S80N
RC1458T
RC1556T
RC1558T
RC3302DB
RC4131DP
RC4131T
RC4136D
RC4136DP
RC4136J
RC4136N
RC4195T
RC4195TK
RC4444R
RC45580N
RC4S58JG
RC4558L
RC4558P
RC4558T
RC8T13MP
RC8T14DD
RC8T14MP
RC8T23DD
RC8T23MP
RC8T24DD
RC8T24MP
RC7S107AD
RC75107ADP
RC75108AD
RC75108ADP
RC75109D
RC75109DP
RC75110D
MOTOROLA
MOTOROLA
DIRECT
SIMILAR
MC1776
MC1776
MC1303P
MC1712CG
MC17Q9CL
MC1709CP1
MC1709CP2
MC1709CG
MC1710CL
MC1710CP
MC1710CG
MC1711CL
MC1711CP
MC1711CG
MC1723CL
MC1723CG
MC1733CL
MC1733CG
MC1741CL
MC1741CP1
MC1741CP2
MC1741CF
MC1741CG
MC1747CL
MC1747CG
MC1748CG
MC1414L
MC1414P
MC1488L
MC1489AL
MC1489L
MC8T13L
MC1437L
MC1437P
MC1458P1
MC1458G
MC1456CG
MC1558G
MC3302P
MC1471SCP1
MC1741SG
MC3403L
MC3403P
MC3403L
MC3403P
MC1468G
MC1468R
MC3416L
MC4558CP1
MC4558CU
MC4558CG
MC4558CP1
MC4558CG
MC8T13P
MC8T14L
MC8T14P
MC8T23L
MC8T23P
MC8T24L
MC8T24P
MC75107L
MC75107P
MC7S108L
MC75108P
MC75S110L
MC75S110P
MC75S110L
PART NO.
RC7S110DP
RC75325DD
REF-01CJ
REF-01DJ
REF-01J
REF-01HJ
REF-02CJ
REF-020J
REF-02HJ
REF-02J
RM702Q
RM702T
RM709D
RM709Q
RM709T
RM710D
RM710T
RM711DC
RM711T
RM723D
RM723T
RM733D
RM733T
RM741D
RM741DP
RM741Q
RM741T
RM747D
RM747T
RM748T
RM1514DC
RM15370
RM41360
RM4136J
RM4195T
RM4195TK
RM4558D
RM4558JG
RM4S58L
RM45S8T
RM5S107AD
RM55325DD
RV3301DB
S8T13E
S8T14E
S5556T
S5558E
S5558T
S5596F
S5596K
S5709G
S5709T
S5710T
S5711K
S5723T
SS733K
S5741T
SE501K
SE515G
SE515K
SE516A
SE51GG
SE516K
SE528E
SE528R
SE531G
SE531T
MOTOROLA
MOTOROLA
DIRECT
SIMILAR
MC75S110P
MC75325L
C1404U10
C1404U10
C1504AU10
C1404AU10
C1404U5
C1404U5
C1404AU5
C1504AU5
MC1712F
MC1721G
MCI709L
MC1709F
MC1709G
MC1710L
MC1710G
MC1711L
MC1711G
MC1723L
MC1723G
MC1733L
MC1733G
MC1741L
MC1741P
MC1741F
MC1741G
MC1747L
MC1747G
MC1748G
MC1514L
MC1537L
MC3503L
MC3503L
MC1S66G
MC1568R
MC4558U
MC4558U
MC4SS8G
MC4558G
MC55107L
MC55325L
MC3301P
MC8T13L
MC8T14L
MC1556G
MC1SS8L
MC1558G
MC1596L
MC1596G
MC1709F
MC1709G
MC1710G
MC1711G
MC1723G
MC1733G
MC1741G
MC1733G
MC1520F
MC1520G
MC1520G
MC152CF
MC1520G
MCI544L
MC1544L
MC1539G
MC1539G
1-18
PART NO.
SE533G
SE533T
SE537G
SE537T
SE550L
SE555JG
SE555L
SE555T
SE556A
SE565A
SE565K
SE592A
SE592K
SG100T
SG101AD
SG101AT
SG101J
SG101T
SG104T
SG105N
SG105T
SG107J
SG107T
SG108AJ
SG108AT
SG103J
SG108T
SG109K
SG109T
SG111D
SG111T
SG118J
SG118T
SG120K-05
SG120K-5.2
SG120K-12
SG120K-15
SG120T-05
SG120T-5.2
SG120T-12
SG120T-15
SG124J
SG140K-05
SG140K-06
SG140K-8
SG140K-12
SG140K-15
SG140K-18
SG140K-24
SG200T
SG201A0
SG201AM
SG201AN
SG201AT
SG201J
SG201M
SG201N
SG201T
SG204T
SG205N
SG205T
SG207J
SG207M
SG207N
SG207T
SG20SAJ
SG208AM
MOTOROLA
MOTOROLA
DIRECT
SIMILAR
MC1776G
MC1776G
MC1556G
MC1556G
MC1723G
MC1555U
MC1555G
MC1555G
MC3556L
MLM565CP
MLM565CP
SE592L
SE592G
MC1723G
LM101AH
LM101AH
LM101AH
LM101AH
LM104H
LM105H
LM105H
LM107H
LM107H
LM108AJ
LM108AH
LM108J
LM108H
LM109K
LM109H
LM111J
LM11IH
MC1741SL
MC1741SG
LM120K-05
MC7905.2CK
LM120K-12
LM120K-J5
LM120T-05
MC7905.2CK
LM120T-12
LM120T-15
LM124J
LM14CK-5.0
LM140K-6.0
LM140K-8.0
LM140K-12
LM140K-15
LM140K-18
LM140K-24
MC1723G
LM201AH
LM201AN
LM201AN
LM201AH
LM201AH
LM201AN
LM201AN
LM201AH
LM204H
LM205H
LM205H
LM207H
LM207H
LM207H
LM207H
LM208AJ
LM208AJ-8

SG208AT SG3501AT
PART NO.
SG208AT
SG208J
SG208M
SG2C8T
SG209K
SG209T
SG2110
SG211M
SG211T
SG218J
SG218M
SG218T
SG224J
SG224N
SG300N
SG300T
SG301AD
SG301AM
SG301AN
SG301AT
SG304T
SG305AT
SG305N
SG305T
SG307J
SG307M
SG307N
SG307T
SG308AJ
SG308AM
SG308AT
SG308J
SG308M
SG308T
SG309K
SG309T
SG311D
SG3JIM
SG311T
SG318J
SG318M
SG318T
SG320K-05
SG320K-5.2
SG320K-12
SG320K-15
SG320T-05
SG320T-5.2
SG320T-12
SG320T-15
SG324J
SG324N
SG340K-05
SG340K-06
SG340K-08
SG34CK-12
SG340K-15
SG340K-18
SG34CK-24
SG555CM
SG555CT
SG555T
SG556CJ
SG556CN
SG556J
SG556N
SG710CD
MOTOROLA
MOTOROLA
DIRECT
SIMILAR
LM208AH
LM208J
LM208J-8
LM208H
LM209K
LM209H
LM211J
LM211N
LM211H
MC1741SL
MC1741SL
MC1741SG
LM224J
LM224N
MC172XP
MC1723CG
LM301AH
LM301AN
LM301AN
LM301AH
LM304H
LM305H
LM305H
LM305H
LM307N
LM307N
LM307N
LM307H
LM308AJ
LM308AN
LM308AH
LM308J
LM308N
LM308H
LM309K
LM309H
LM311J
LM31IN
LM311H
MC1741SCL
MC1741CP1
MC1741CG
LM320K-5.0
MC7905.2CK
LM320K-12
LM320K-15
LM320T-5.0
MC7905.2CT
LM320T-12
LM320T-15
LM324J
LM324N
MC7805CK
MC7806CK
MC7808CK
MC7812CK
MC7815CK
MC7818CK
MC7824CK
MC1455P1
MC1f5SG
MC1555G
MC3456L
MC3456P
MC3556L
MC3556L
MC1710CL
PART NO.
SG710CN
SG710CT
SG710D
SG710N
SG710T
SG711CD
SG711CN
SG711CT
SG711D
SG711N
SG711T
SG723CD
SG723CN
SG723CT
SG723D
SG723T
SG733CD
SG733CN
SG733CT
SG733D
SG733N
SG733T
SG741CD
SG741CF
SG741CM
SG741CN
SG741CT
SG741D
SG741F
SG741T
SG741SCM
SG741SCT
SG741ST
SG747CJ
SG747CN
SG747CT
SG747J
SG747T
SG748CD
SG748CM
SG748CN
SG748CT
SG748D
SG748T
SG777CJ
SG777CM
SG777CN
SG777CT
SG777J
SG777T
SG1118AJ
SG1118AT
SG1118J
SG1118T
SG1217
SG1217J
SG1217T
SG1250T
SG1401N
SG1401T
SG1402N
SG1402T
SG1436CT
SG1436M
SG1436T
SG1456CT
MOTOROLA
MOTOROLA
DIRECT
SIMILAR
MC1710CP
MC1710CG
MC1710L
MC1710CP
MC1710G
MC1711CL
MC1711CP
MC1711CG
MC1711L
MC1711CP
MC1711G
MC1723CL
MC1723CP
MC1723CG
MC1723L
MC1723G
MC1733CL
MC1733CP
MC1733CG
MC1733L
MC1733L
MC1733G
MC1741CL
MC1741CF
MC1741CP1
MC1741CP2
MC1741CG
MC1741L
MC1741F
MC1741G
MC1741SCP1
MC1741SCG
MC1741SG
MC1747CL
MC1747CP2
MC1747CG
MC1747L
MC1747G
MC1748CP1
MC1748CP1
MC1748CP1
MC1748CG
MC1746G
MC1748G
LM308AJ
LM308AN
LM308AN
l V308AH
LM108AJ
LM108AH
IW108AJ
LM108AH
LM108J
LM108H
MC1741G
MC1741SL
MC1741SG
MC1776G
MC1533G
MC1533G
MC1594L
MC1594L
MC1436CG
MC1436U 1
MC1436G
MC1456CG
1-19
PART NO.
SG1456T
SG1456M
SG1458T
SG1468J
SG1468N
SG1468T
SG1495D
SG1495N
SG1496D
SG1496N
SG1496T
SG1501AD
SG1501AT
SG1501D
SG1501T
SG15020
SG1S02N
SG1503
SG1524J
SG1536T
SG1556T
SG1558T
SG1595D
SG 15960
SG1596T
SG1660D
SG1660J
SG1660M
SG1660T
SG1760D
SG1760F
SG1760J ,
SG1760M
SG1760T
SG2118AJ
SG2118AM
SG2118AT
SG2118J
SG2118M
SG2118T
SG2250T
SG2401N
SG2402N
SG2402T
SG2501AD
SG2501AT
SG2501D
SG2501N
SG2501T
SG2502D
SG2502N
SG2502T
SG2503
SG2524J
SG3118AJ
SG3118AM
SG3118AT
SG3118J
SG3118M
SG3118T
SG3250T
SG3401N
SG3401T
SG3402N
SG3402T
SG3501AD
SG3501AT
MOTOROLA
MOTOROLA
SIMILAR
DIRECT
MC14S6G
MC1458P1
MC1458G
MC1468L
MC1468L
MC1468G
MC149SL
MC1495L
MC1496L
MC1496L
MC1496G
MC1568L
MC1538G
MC1568L
MC1568G
MC1568L
MC1568L
MC1503U
MC3520L
MC1536G
MC1556G
MC1558G
MC1595L
MC1596L
MC1596G
LM301AH
LM308J
LM308N
LM308H
LM307H
LM307H
LM308J
LM&08N
LM308H
LM208AJ
LM208AJ-8
LM208AH
LM208J
LM208J-8
LM208H
MC1776G
MC1433G
MC1494L
MC1494L
MC1468L
MC1468G
MC1468L
MC1468L
MC1468G
MC1468L
MC1468L
MC1468G
MC1403AU
MC3520L
MLM308AL
MLM308AP1
MLM308AG
MLM308L
MLM308P1
MLM308G
MC1776G
MC1433G
MC1433G
MC1494L
MC1494L
MC1468L
MC1468G

SG3501D SN75127
PART NO.
MOTOROLA
MOTOROLA
DIRECT
SIMILAR
SG3501D
SG3501N
SG3501T
SG3S02D
SG3502G
SG3502N
SG3503
SG3524J
SG4250CM
SG4250CT
SG4250T
SG4501D
SG4501N
SG4501T
SG7805CK
SG7805K
SG7806CK
SG7806K
SG7808CK
SG7808K
SG7812CK
SG7812K
SG7815CK
SG7815K
SG7818CK
SG7818K
SG7824CK
SG7824K
SH0013HC
SH0013HM
SH2001FC
SH2001FM
SH2001HC
SH2001HM
SH2002FC
SH2G02FM
SH2002HC
SH2002HM
SH2002HC
SH2200FC
SH2200FM
SH2200HC
SH2200HM
SH2200PC
SH8090FM
SN5510FA
SN5510L
SN52101AL
SN52104L
SN52105L
SN52106J
SN52106L
SN52107L
SN52108AL
SN52108L
SN52109L
SN52510J
SN52510L
SN52514J
SN52555L
SNS2558L
SNS2702AFA
SN52702AJ
SN52702AL
SN52702FA
SN52702J
SN52702L
MC1468L
MC1468L
MC1468G
MC1468L
MC1468G
MC1468L
MC1403U
MC3420L
MC1776CP1
MC1776CG
MC1776G
MC1468L
MC1468L
MC1468G
MC7805CK
MC7805CK
MC7806CK
MC7806CK
MC7808CK
MC7808CK
MC7812CK
MC7812CK
MC7815CK
MC7815CK
MC7818CK
MC7818CK
MC7824CK
MC7824CK
MMH0026CG
MMH0026G
MC75462P
MC75462P
MC75462P
MC75462P
MC75462P
MC75462P
MC75462P
MC75462P
MC75462P
MC75462P
MC75462P
MC75462P
MC75462P
MC75462P
MC1508L8
MC1510F
MC1510G
LM101AH
LM101H
LM105H
MC1710L
MC17^0G
LM107H
LM108AH
LM108H
LM109H
MC171CL
MC1710G
MC1514L
MC1555G
MC1558G
MC1712F
MC1712L
MC1712G
MC1712F
MC1712L
MC1712G
PART NO.
MOTOROLA
MOTOROLA
DIRECT
SIMILAR
SN52709AFA
SN52709AJ
SN52709AL
SN52709FA
SN52709J
SN52709L
SN52710FA
SN52710J
SN52710L
SN52711FA
SN52711J
SN52711L
SN52723FA
SN52723J
SN52723L
SN52733J
SN52733L
SN52741FA
SN52741J
SN52741L
SN52747FA
SN52747J
SN52747L
SN52748L
SN52770L
SN52771L
SN52810FA
SN52810J
SN52810L
SN52811FA
SN52811J
SN52811L
SN55107AJ
SN55107BJ
SN55108AJ
SN5S108BJ
SN55109J
SN55110J
SN55244J
SN55325J
SN72301AL
SN72301AP
SN72304L
SN72305AL
SN72305L
SN72306J
SN72306L
SN72306N
SN72307L
SN72308AL
SN72308L
SN723G9L
SN72311L
SN72311P
SN72376L
SN72440J
SN72440N
SN72510J
SN72510L
SN72510N
SN72514J
SN72514N
SN72555L
SN72555P
SN72558L
SN72558P
SN72702J
MC17C9AF
MC1709AL
MC1709AG
MC1709F
MC1709L
MC1709G
MC1710F
MC1710L
MC1710G
MC1711F
MC1711L
MC1711G
MC1723F
MC1723L
MC1723G
MC1733L
MC1733G
MC1741F
MC1741L
MC1741G
MC1747F
MC1747L
MC1747G
MCI748G
MC1556G
MC1556G
MC1710F
MC1710L
MC1710G
MC1711F
MC1711L
MC1711G
MC55107L
MC55107L
MC55108L
MC75108L
MC75S110L
MC75S110L
MC1544L
MC55325L
LM301AH
LM301AN
LM304H
LM305H
LM305H
MC1710CL
MC1710CG
MC1710CP
LM307H
LM308AH
LM308H
LM309H
LM311H
LM311N
LM305H
MC3370P
MC3370P
MC1710CL
MC1710CG
MC1710CP
MC1414L
MC1414P
MC1455G
MC1455P1
MC14S8G
MC1458P1
MC1712CL
1-20
PART NO.
SN72702L
SN72709J
SN72709L
SN72709N
SN72709P
SN72710J
SN72710L
SN72710N
SN72711J
SN72711L
SN72711N
SN72720J
SN72720L
SN72720N
SN72723J
SN72723L
SN72733J
SN72733L
SN72741FA
SN72741J
SN74741L
SN72741N
SN72741P
SN72747FA
SN72747J
SN72747L
SN72747N
SN72748L
SN72748P
SN72770L
SN72771L
SN72810J
SN72810L
SN72810N
SN72811J
SN72811L
SN7281 IN
SN72905
SN72906
SN72908
SN72912
SN72915
SN72L022P
SN72L044JA
SN72L044N
SN75107AJ
SN75107AN
SN75107BJ
SN75107BN
SN75108AJ
SN75108AN
SN75108BJ
SN75108BN
SN75121J
SN75121N
SN75122J
SN75122N
SN75123J
SN75123N
SN75124J
SN75124N
SN75125J
SN75125N
SN75126J
SN75126N
SN75127J
SN75127N
MOTOROLA
MOTOROLA
DIRECT
SIMILAR
MC1712CG
MC1709CL
MC1709CG
MC1709CP2
MC1709CP1
MC1710CL
MC1710CG
MC1710CP
MC1711CL
MC1711CG
MC1711CP
MC1710CL
MC1710CG
MC1710CP
MC1723CL
MC1723CG
MC1733CL
MC1733CG
MC1741CF
MC1741CL
MC 174 ICG
MC1741CP2
MC1741CP1
MC1747CF
MC1747CL
MC1747CG
MC1747CP2
MC1748CG
MC1748CP1
MC14S6G
MC1456G
MC1710CL
MC1710CG
MC1710CP
MC1711CL
MC 171 ICG
MCA711CP
MC7905CT
MC7906CT
MC7908CT
MC7912CT
MC7915CT
LM358N
LM324N
LM324N
MC75107L
MC75107P
MC75107L
MC75107P
MC75108L
MC75108P
MC75108L
MC75108P
MC8T13L
MC8T13P
MC8T14L
MC8T14P
MC8T23L
MC8T23P
MC8T24L
MC8T24P
MC75125L
MC75125P
MC3481/5L
MC3481/5P
MC75127L
MC75127P

SN75128J TL494CN
PART NO.
SN75128J
SN75128N
SN75129J
SN75129N
SN75138N
SN75138J
SN75140P
SN75150J
SN75150N
SN75154J
SN75154N
SN75188J
SN75188N
SN7S189AJ
SN75189J
SN75189AN
SN75189N
SN75207J
SN75207N
SN75208J
SN75208N
SN75261N
SN75322N
SN75362P
SN75365J
SN75365N
SN75368J
SN75368N
SN75369P
SN75450AJ
SN75450AN
SN75450BN
SN75450N
SN75451AP
SN75451P
SN75452P
SN75453P
SN75454P
SN75460AJ
SN75460AN
SN75461
SN75461AP
SN75462
SN75462AP
SN75463
SN75463AP
SN75464
SN75464AP
SN75461N
SN75466J
SN75466N
SN75467J
SN75467N
SN75468J
SN75468N
SN75475P
SN75475JG
SN75491N
SN75492N
SN76000P
SN76104N
SN76105N
SN76111N
SN76113N
SN76115N
SN76116N
SN76117N
MOTOROLA
MOTOROLA
SIMILAR
DIRECT
MC75128L
MC75128P
MC75129L
MC75129P
MC3443P
MC3443P
MC75140P1
MC1488L
MC1488P
MC1489L
MC1489P
MC1488L
MC1488P
MC1489AL
MC1489L
MC1489AP
MC1489P
MC75107L
MC75107P
MC75108L
MC75108P
MC3245L
MC3245P
MMH0026CP
MC75365L
MC75365P
MC75368L
MC75368P
MMH0026CP1
MC75450L
MC75450P
MC75450P
MC75450P
MC75451P
MC75451P
MC75452P
MC75453P
MC75454P
MC75460L
MC75460P
MC75461
MC75461P
MC75462
MC75462P
MC75463
MC75463P
MC75464
MC75464P
MC75491P
MC1411L
MC1411P
MC1412L
MC1412P
MC1413L
MC1413P
MC1472P1
MC1472U
MC75491P
MC75492P
MC1306P
MC1310P
MC131GP
MC1310P
MC1310P
MC1310P
MC1310P
MC1310P
PART NO.
MOTOROLA
MOTOROLA
SIMILAR
DIRECT
SN76130N
SN76131N
SN76149N
SN76242N
SN76243N
SN76246N
SN76298N
SN76514L
SN76514N
SN76S64N
SN76565N
SN76591P
SN76594P
SN76600P
SN76642N
SN76644N
SN76650N
SN76651N
SN76653N
SN76660N
SN76665N
SN76666N
SN76669N
SN76675N
SN76678P
SSS101AL
SSS101AJ
SSS107J
SSS107P
SSS201AJ
SSS201AL
SSS201AP
SSS207J
SSS207P
SSS301AJ
SSS301AL
SSS301AP
SSS741BJ
SSS741BL
SSS741BP
SSS741CJ
SSS741CL
SSS741CP
SSS741GJ
SSS741GP
SSS741J
SSS741L
SSS741P
SSS747B2
SSS747BP
SSS747CK
SSS747CM
SSS747CP
SSS747GK
SSS747GM .
SSS747GP
SSS747L
SSS747P
SSS1408A-6Z
SSS1408A-7Z
SSS1408A-8Z
SSS1458J
SSS1508A-8Z
SSS1558J
TAA630
TBA120S
TBA440
MC1303P
MC1303P
MC1303P
MC1399P
MC1399P
MC1323P
MC1398P
MC1496G
MC1496P
MC1364P
MC1364P
MC1391P
MC1394P
MC1350P
MC1357P
MC1352P
MC1352P
MC1351P
MC1352P
MC1357P
MC1364P
MC1358P
MC1356P
MC1375P
MC1355P
LM101AH
LM101AH
LM107H
LM107H
LM201AH
LM201AH
LM201AN
LM207H
LM207H
LM301AH
LM301AH
LM301AN
MC1741G
MC1741F
MC1741P2
MC1741CG
MC1741CF
MC1741CP2
MC1741SG
MC1741SG
MC1741G
MC1741F
MC1741P2
MC1747F
MC1747L
MC1747CG
MC1747CF
MC1747CL
MC1747G
MC1747F
MC1747L
MC1747F
MC1747L
MC1408L6
MC1408L7
MC1408L8
MC1458G
MC1508L8
MC1556G
MC1327P
MC1358P
MC1352P
1-21
PART NO.
TBA520
TBA920
TBA920S
TBA940
TBA950
TBA990
TBA1190Z
TDA1190Z
TDA2002
TL022CJG
TL022CL
TL022CP
TL022MJG
TL022ML
TL044CJ
TL044CN
TL044MJ
TL071ACJG
TL071ACL
TL071ACP
TL071BCJG
TL071BCL
TL071BCP
TL071CJG
TL071CL
TL071CP
TL072ACJG
TL072ACL
TL072ACP
TL072BCJG
TL072BCL
TL072BCP
TL072CJG
TL072CL
TL072CP
TL074ACJ
TL074ACN
TL074BCJ
TL074BCN
TL074CJ
TL074CN
TL081ACJG
TL081ACL
TL081ACP
TL081BCJG
TL081BCL
TL081BCP
TL081CJG
TL081CL
TL081CP
TL082ACJG
TL082ACL
TL082ACP
TLC82BCJG
TL082BCL
TL082BCP
T1082CJG
TL082CL
TL082CP
TL084ACJ
TL084ACN
TLC84BCJ
TL084BCN
TL084CJ
TL084CN
TL494CJ
TL494CN
MOTOROLA
MOTOROLA
SIMILAR
DIRECT
MC1327P
MC1391P
MC1391P
MC1344P
MC1344P
MC1327P
TBA1190Z
TDA1190Z
TDA2002
LM358J
LM358H
LM358N
LM158J
LM158H
LM324J
LM324N
LM124J
MC34001BU
MC34001BG
MC34001BP
MC34001AU
MC34001AG
MC34001AP
MC34001U
MC34001G
MC34001P
MC34002BU
MC34002BG
MC34002BP
MC34002AU
MC34002AG
MC34002AP
MC34002U
MC34002G
MC34002P
MC34004BL
MC34004BP
MC34004A
MC34004AP
MC34004L
MC34004P
MC34001BU
MC34001BG
MC34001BP
MC34001AU
MC34001AG
MC34001AP
MC34001U
MC34001G
MC34001P
MC34002BU
MC34002BG
MC34002BP
MC34002AU
MC34002AG
MC34002AP
MC34002U
MC34002G
MC34002P
MC34004BL
MC34004BP
MC34004AL
MC34004AP
MC34004L
MC34004P
TL494CJ
TL494CN

TL49SCJ *iA732DC
MOTOROLA
MOTOROLA
DIRECT
SIMILAR
PART NO.
TL495CJ
TL495CJ
TL495CN
TL495CN
TL497CJ
MC3420L
TL497CN
MC3420P
TL497MJ
MC3S20L
UDN5711M
MC1471P1
UDN5712M
MC1472P1
UDN5713M
MC1473P1
UDN5714M
MC1474P1
UON-6144A
MC3490P
UDN-6164A
MC3490P
UDN-6184A
MC3490P
UDN-7183A
MC3491P
UDN-7184A
MC3491P
UDN-7186A
MC3491P
MC3494P
UHD-490
MC3494P
UHD-491
MC3494P
UHP-490
UHP-491
MC3494P
UHP-495
MC3490P
ULN2001A
ULN2001A
ULN2002A
ULN2002A
ULN2003A
ULN2003A
ULN2004A
ULN2004A
ULN2111A
MC1357P
ULN2111N
MC1357PQ
ULN2113A
MC1357P
ULN2M3N
MC1357P
ULN2114A
MC1323P
ULN2114K
MC1323P
ULN2114N
MC1323P
ULN2120A
MC1310P
ULN2121A
MC1310P
ULN2122A
MC131QP
ULN2124A
MC1399P
ULN2125A
MC1344P
ULN2127A
MC1399P
ULN2128A
MC1310P
ULN2136A
MC1356P
ULN2139D
MC1439G
ULN2139G
MC1439G
ULN2139H
MC1439P2
ULN2139M
MC1439P1
ULN2151D
MC1741CG
ULN2151G
MC1741CF
ULN2151H
MC1741CP2
ULN2151M
MC1741CP1
ULN2156D
MC1456G
ULN2156G
MC1456G
ULN2156H
MC1456G
ULN2156M
MC1456G
ULN2157A
MC1458P2
ULN2157H
MC1458P2
MC1458G
ULN2157K
ULN2165A
MC1358P
ULN2165N
MC1358PQ
ULN2209A
MC1356P
ULN2210A
MC1313P
MC1324P
ULN2224A
ULN2228A
MC1323P
ULN2244A
MC1310P
ULN2262A
MC1399P
MC1364P
ULN2264A
ULN2267A
MC1323P
ULN2298A
MC1398P
ULN2741D
MC1741CG
ULN2747A
MC1747CL
MOTOROLA
MOTOROLA
DIRECT
SIMILAR
PART NO. REPLACEMENT REPLACEMENT
ULS21390
MC1539G
ULS2139G
MC1539G
ULS2139H
MC1539L
ULS2139M
MC1439P1
ULS2151D
MC1741G
ULS2151G
MC1741F
ULS2151H
MC1741L
ULS2151M
MC1741CP1
ULS21560
MC1556G
ULS2156G
MC1556G
ULS2156H
MC1556G
ULS2156M
MC1556G
ULS2157A
MC1558L
ULS2157H
MC1558L
ULS2157K
MC1558G
jjA0802DC-1
MC1408L8
MC1408L7
uA0802DC-2
uA0802DC-3
MC1408L6
dA0802DM-1
MC1508L8
A0802PC-1
MC1408P8
A0802PC-2
MC1408P7
MC1408P6
vA0802PC-3
LM101AJ
vAIOIAD
wA101AF
LM101AJ
UA101AH
LM101AH
UA101D
LM101AJ
pAIOIF
LM101AJ
uAIOIH
LM101AH
nA104HM
LM104H
LM105H
wA105HU
nA107H
LM107H
A 108AD
LM108AJ
(/A108AF
LM108AF
pAIOSAH
LM108AH
wA108D
LM108J
A108F
LM108F
uAIOBH
LM108H
A109KM
LM109K
dA201AD
LM201AJ
(/A201AF
LM201AJ
A201AH
LM201AH
(iA201D
LM201AJ
mA201F
LM201AJ
vA201H
LM201AH
(/A207H
LM207H
pA208AD
LM208AJ
LM208AF
//A208AF
tfA208AH
LM208AH
(iA206D
IM208J
LM208F
pA208F
wA208H
LM208H
VA209KM
LM209K
mA301AD
LM301AJ
<jA301AH
LM301AH
A301AT
LM301AN
LM304H
nA304HC
LM305H
uA305HC
cA305HC
LM30SH
pA307H
LM307H
ij A307T
LM307N
A308AD
LM308AJ
MA308AH
LM308AH
MA308D
LM308J
pA308H
LM308H
wA309KC
LM309K
LM311N
uA311T
LM305H
uA376TC
1-22
MOTOROLA
MOTOROLA
SIMILAR
DIRECT
PART NO.
REPLACEMENT REPLACEMEN1
fiA555KC
MC1455G
<iA555HM
MC1555G
MC1455P1
(iA555TC
(iA556DC
MC3456L
A5S60M
MC3556L
MA556PC
MC3456P
A702DC
MC1712CL
(/A702DM
MC1712L
MC1712F
(<A702FM
(.A702HC
MC1712CG
jA702HM
MC1712G
wA702MJ
MC1712L
//A702ML
MC1712G
iiA709ADM
MC1709AL
MC1709AF
A709AFM
WA709AHM
MC1709AG
VA709AMJ
MC1709AL
mA709AMJG
MC1709AU
mA709AML
MC1709AG
mA709CJ
MC1709CL
MC1709CU
xA709CJG
iA709CL
MC1709CG
xA709CN
MC1709CP2
<iA709CP
MC1709CP1
jA709DC
MC1709CL
i A7090M
MC1709L
(/A709FM
MC1709F
iiA709HC
MC1709CG
A709HM
MC1709G
iiA709MJ
MC1709L
wA709MJG
MC1709U
(iA709ML
MC1709G
*iA709TC
MC1709CP1
MC1709CP2
(/A709PC
iA710DC
MC1710CL
ii A710DM
MC1710L
A710KC
MC1710CG
A710HM
MC1710G
*,A710PC
MC1710CP
I/A711DC
MC1711CL
vA711DM
MC1711L
mA711HC
MC1711CG
pA711HM
MC1711G
A711PC
MC1711CP
(jA715DC
MC1741SCL
mA715DM
MC1741SL
(/A715HC
MC1741SCG
I/A715HM
MC1741SG
mA723CJ
MC1723CL
A723CL
MC1723CG
i<A723CN
MC1723CP
uA723DC
(iA723DC
jjA723DM
MC1723L
WA723HC
I/A723HC
(iA723HM
MC1723G
jA723MJ
MC1723L
(iA723ML
MC1723G
<iA723PC
(iA723PC
pA725AHM
LM108AH
LM308AH
pA725EHC
ijA725KC
LM308AH
WA725HM
LM108AH
MC1420G
iA727HC
(/A727HM
MC1520G
(jA730HC
MC1420G
>i A730HM
MC1520G
<iA732DC
MC1310P

nA732PC mA78L05ACLP
MOTOROLA
MOTOROLA
DIRECT
SIMILAR
PART NO.
MA732PC
MC1310P
MC1733CL
jiA733CJ
MC1733CG
A733CL
mA733CN
MC1733CP
MC1733CI
pA733DC
pA733DM
MC1733L
MC1733F
Â733FM
MC1733CG
ii A733HC
(iA733HM
MC1733G
A733MJ
MC1733L
mA733ML
MC1733G
LM311J
mA734DC
A734DM
LM311J
LM311H
iiA734HC
LM311H
mA734HM
LF355H
nA740HC
LF155H
>iA740HM
jA741ADM
MC1741L
MC1741F
(/A741AFM
mA741AHM
MC1741G
MC1741CL
*.A741CJ
MC1741CU
*A741CJG
MC1741CG
*A741CL
.A741CN
MC1741CP2
MC1741CP1
mA741CP
fiA741DC
*i A741DC
MC1741L
pA741DM
MC1741L
pA741EDC
MC1741G
)iA741EHC
MC1741CF
iA741FC
MC1741F
iA741FM
UA741HC
jiA741HC
mA741HM
MC1741G
mA741MJ
MC1741L
MC1741U
f<A741MJG
MC1741G
k A741ML
MC1741CU
jiA741RC
MC174 111
A741RM
MC1741CP2
)iA741PC
>iA741TC
MA741TC
CA3059
A7420C
MC1323P
uA746DC
MC1323P
PA746HC
MC1747L
UA747AOM
MC1747G
A747AHM
MC1741CL
jiA747CJ
MC1747CG
jiA747CL
MA747CN
MC1747CP2
MC1747CL
pA747DC
MC1747L
(iA747DM
MC1747CCBM
jiA747EDC
MC1747CICM
(iA747EHC
MC1747CG
(<A747HC
MC1747G
(/A747HM
MC1747L
XA747MJ
MC1747G
,iA747ML
tiA747PC
MC1747CP2
MC1748F
(iA748AFM
MC1748G
pA748AHM
MC1748CL
(iA748CJ
MC1748CU
tiA748CJG
MC1748CG
XA748CL
MC1748CP2
<<A748CN
MC1748CP1
)iA748CP
MC1748CL
fiA748DC
uA748DM
MC1748L
MC1748F
MA748FM
MOTOROLA
MOTOROLA
SIMILAR
DIRECT
PART NO.
jiA748HC
MC1748CG
OA748HM
MC1748G
Â748MJ
MC1748L
pA748MJG
MC1748U
A748ML
MC1748G
jiA748TC
MC1748CP1
jiA749DC
MC1435L
MC1435G
pA749DHC
,iA749DM
MC1535L
MC1435G
,/A749KC
MC1356P
/iA753TC
tiA754HC
MC1355P
MC1355P
iA754TC
MC1350P
mA757DC
MC1350P
A757DM
pA758DC
MC1310P
MC1310P
cA758PC
MC1310P
f>A767DC
pA767PC
MC1310P
MC1741S
mA772
LM339J
(iA775DC
jiA775DM
LM339J
LM339N
jiA775PC
jjA776DC
MC1776CG
tiA776DM
MC1776G
f<A776HC
MC1776CG
pA776HM
MC1776G
jiA776TC
MC1776CP1
LM308AJ-8
>iA777CJ
LM308AJ-8
MA777CJG
LM308AH
pA777CL
LM308AN
Â777CN
LM308AN
(iA777CP
LM3Q8AJ-8
iiA777DC
LM308AH
)iA777HC
LM108AJ-8
/iA777MJ
LM108AJ-8
//A777MJG
LM108AH
jiA777ML
LM308AN
(iA777TC
MC1399P
iiA780DC
MC1399P
/iA780PC
>iA781DC
MC1399P
MC1399P
fiA781PC
MC1327P
mA7860C
>i A787PC
MC1399P
MC1438R
fiA791KC
MC1538R
fiA791KM
MC1438R
#iA791P5
MC1496G
/iA796HC
MC1596G
)iA796HM
fiA796DC
MC1496L
PA796DM
MC1596L
MC3458G
mA798HC
MC3558G
A798HM
pA798RC
MC3458U
M798RM
MC3558U
mA798TC
MC3458P1
MC1741G
jiA799HC
MC1741G
(iA799HM
MC1312P
fiA1312PC
MC1314P
fiA1314PC
fiA1315PC
MC1315P
fiA1391PC
MC1391P
MC1394P
A1394PC
MC14S8CG
fiA1458CKC
MC1458CP1
mA1458CP
MC1458CU
>iA1458CRC
1-23
MOTOROLA
MOTOROLA
SIMILAR
DIRECT
PART NO.
MC1458CP1
A1458CTC
mA1458E
MC1458G
fiA1458HC
MC1558G
mA1458P
MC1458P1
(/A1458RC
MC1458U
MC1458P1
MA14S8TC
MC1558G
f<A1SS8E
MC1558G
<iA15S8HM
PA2136PC
MC1356P
MC14SSU
pA2240DC
MC155SG
pA2240DM
MC1455P1
,/A2240PC
CA3054
PA3026HM
pA3045
MC3346P
MC3346P
A3046DC
CA3054P
A3054DC
MC1364P
mA3064PC
MC1358P
>i A3C65PC
M3086DM
MC3386P
i A3301P
MC3301P
wA3302P
MC3302P
A3303P
MC3303P
jiA3401P
MC3401P
/iA3403D
MC3403L
A3403P
MC3403P
MC4741CL
*jA4136DC
MC4741L
fiA4136DM
MC4741CP
pA4136PC
PA4558HC
MC4558CG
MC4558G
mA4558HM
iA4558TC
MC4558CP1
MC7805CT
iiA7805CKC
MC7805CK
A7805KC
Â7805KM
MC7805K
MC7805CT
MA780SUC
MC7806CT
(iA7806CKC
MC7806CK
PA7806KC
MC7806K
fiA7806KM
MC7806CT
(jA7806UC
MC7808CT
iiA7808CKC
MC7808CK
MA7808KC
MC7808K
mA7808KM
MC7808CT
pA7808UC
MC7812CT
/A7812CKC
MC7812CK
fiA7812KC
MC7812K
mA7812KM
MC7812CT
mA7812UC
MC7815CT
Â7815CKC
MC7815CK
fiA7815KC
MC7815K
fiA7815KM
nA7815UC
MC7815CT
MC7818CT
pA7818CKC
MC7818CK
)<A7818KC
>jA7818KM
MC7818K
MC7815CT
MA7818UC
MC7824CT
A7824CKC
MC7824CK
fiA7824KC
MC7824K
fiA7824KM
MC7824CT
Â7824UC
LM117K
VA78GKM
LM117K
Â78GKC
LM117K
MA78GKM
LM317T
A78GU1C
MC7805CK
pA78K05KC
fiA78L02ACJG
MC78L02ACG
MC78L05ACG
Â78L05ACJG
J/A76L05ACLP MC78L05ACP

fiA78L05AHC pA8T13PC
MOTOROLA
MOTOROLA
SIMILAR
DIRECT
J.A78L05AHC
MC78L05ACG
fiA78L05AWC MC78L05ACP
MC78L05CG
pA78L05CJG
fiA78L05CLP
MC78L05CP
M78L05HC
MC76L05CG
(>A78L05WC
MC78L05CP
M78L06ACJG
MC78L06ACG
,iA78L06ACLP MC78L06ACP
KA78L06CJG
MC78L06CG
A78L06CLP
MC78L06CP
MC78LC8ACG
A78L08ACJG
(iA78L08ACLP MC78L08ACP
MC78LC8CG
*iA78L08CJG
dA78L08CLP
MC78L08CP
MC78L12ACG
>iA78L12ACJG
(iA78L12ACLP MC78L12ACP
<*A78L12AHC
MC78L12ACG
A78L12AWC
MC78L12ACP
MC78L12CG
A78L12CJG
.A78L12CLP
MC78L12CP
pA78L12HC
MC78L12CG
MA78L12WC
MC78L12CP
*iA78L15ACJG
MC78L15ACG
pA78L15ACLP MC78L1SACP
iA78L15AHC
MC78L15ACG
A78L15AWC
MC78L15ACP
MA78L15CJG
MC78L15CG
mA78L15CLP
MC78L15CP
(jA78L15HC
MC78L15CG
iA78L15WC
MC78L15CP
jiA78L26AWC
MC7802ACP
LM317H
iA78MGHC
LM317T
A78MGT2C
>i A78MGU1C
LM317T
A78M05CKC MC78M05CT
<<A78M05HC
MC78M05CG
MC78M05CG
</A78M05HM
MC78M05CT
dA78M05UC
dA78M06CKC MC78M06CT
A78M06HC
MC78M06CG
(/A78M06HM
MC78MG6CG
MC78M06CT
A78M06UC
<<A78M08CKC MC78M08CT
f>A78M08HC
MC7SM08CG
MC78M08CG
A78M08HM
mA78M08LIC
MC78M08CT
ii A78M12CKC
MC78M12CT
mA78M12HC
MC78M12CG
MC78M12CG
>jA78M12HM
mA78M12UC
MC78M12CT
(iA78M15CKC MC78M15CT
MC78M15CG
k A78M15KC
MC78M15CG
A78M15HM
MC78M15CT
kA78M15UG
MC78M18CG
(iA78M18HC
A78M18HM
MC78M18CG
MC78M18CT
*iA78M18UG
mA78M20CKC
MC78M20CT
MC78M20CG
(iA78M20HC
(iA78M20HM
MC78M20CG
(jA78M20UG
MC78M20CT
MC78M24CT
mA78M24CKC
MC78M24CG
<i A78M24HC
MC76M24CG
;iA78M24HM
MC78M24CT
fiA78M24UC
MC7902K
tiA7902KC
pA7902KM
MC7902K
MOTOROLA
MOTOROLA
DIRECT
SIMILAR
(iA7902UC
MC7902CT
jiA7905KC
MC7905CK
jiA7905KM
MC7905CK
iiA7905UC
MC7905CT
A7906KC
MC7906CK
(iA7906KM
MC7906CK
A7906UC
MC7908CT
fiA7908KC
MC7908CK
A7908KM
MC7908CK
fiA7908UC
MC7908CT
/A7912KC
MC7912CK
{A7912KM
MC7912CK
M7912UC
MC7912CT
MC7915CK
<iA7915KC
MC7915CK
fiA7915KM
fiA7915UC
MC7915CT
pA7918CKC
MC7918CT
M7918KC
MC7918CK
fiA7918KM
MC7918CK
dA7918UC
MC7918CT
A7924CKC
MC7924CT
(A7924KC
MC7924CK
A7924KM
MC7924CK
A7924UC
MC7924CT
<jA79L05AHC
MC79L05ACG
pA79L05AWC
MC79L05ACP
A79L05KC
MC79L05CG
(iA79L05WC
MC79L05CP
pA79L12AKC
MC79L12ACG
iiA79L12AWC
MC79L12ACP
A79L12HC
MC79L12CG
iiA79L12WC
MC79L12CP
jiA79L15AHC
MC79L15ACG
nA79L15AWC
MC79L15ACP
pA79L15HC
MC79L15CG
A79L15WC
MC79L15CP
tiA79M05AHM
MC7905CK
kA79M05AUC
MC7905CT
pA79M05CKC MC7905CT
(iA79M0SHM
MC7905CK
(/A79M05UC
MC7905CT
MC7906CK
(.A79M06AHM
(jA79M06AllC
MC7906CT
pA79M06CKC MC7906CT
MC7906CK
(A7SM06HM
M79M06UC
MC7906CT
(A79M08AHM
MC79C8CK
(iA79MC8AUC
MC7908CT
A79M08CKC MC7908CT
(iA79M08HM
MC7908CK
MC7908CT
(<A79M08UC
MC7912CK
l>A79M12AHM
iA79M12AUC
MC7912CT
<iA79M12CKC MC7912CT
MC7912CK
<iA79M12HM
OA79M12UC
MC7912CT
MC7915CK
A79M15AHM
*iA79M15AUC
MC7915CT
pA79M15CKC MC7915CT
fiA79M15HM
MC7915CK
A79M15UC
MC7915CT
MC7918CK
|tA79M18AHM
A79M18AUC
MC7918CT
pA79M18HM
MC7918CK
MC7918CT
(iA79M18UC
MC7924CK
(A79M24AHM
jiA79M24AUC
MC7924CT
1-24
MOTOROLA
MOTOROLA
DIRECT
SIMILAR
PART WO. REPLACEMENT REPLACEMENT
pA79M24HM
MC7924CK
iiA79M24UC
MC7924CT
pA8T13DC
MC8T13L
pA8T13PC
The "Better"
Program
Motorolas reliability and

quality-enhancement program
was developed to provide
improved levels of quality
and reliability for standard
commercial products.
THE BETTER program is offered on CMOS, Linear, TTL, TTL/LS, DTL, HTL,
and NMOS in dual-in-line ceramic and plastic packages.
Motorola standard commercial integrated circuits are
manufactured under stringent in-process controls and
quality inspections combined with the industrys finest
outgoing quality inspections. The "BETTER program
offers three levels of extra processing, each tailored to
meet different user needs at nominal costs.
The program is designed to:
Eliminate incoming electrical inspection
Eliminate need for independent test labs
and associated extra time and costs
Reduce field failures
Reduce service calls
Reduce equipment downtime
Reduce board and system rework
Reduce infant mortality
Save time and money
increase end-customer satisfaction
SETTER PROCESSING STANDARD PRODUCT PLUS:
100% SCREEN
LEVEL
I
S"
TEMP CYCLE. 10 CYCLES

-25C to +150#C
BURN-IN MIL-STD-883
POST BURN-IN ELECTRICAL
100C FUNCTIONAL
DC PARAMETRIC AT 25#C*
TIGHTENED QA SAMPLE
LEVEL
II
-D"
LEVEL
III
DS"
X
X
X
X
X
X
X
X
X
X
X
X
X
'N M O S <Xxt Functional and tic 100% at 100*C.
BETTER AQL GUARANTEES

TEST
CONDITION
HIGH TEMPERATURE FUNCTIONAL

DC PARAMETRIC
DC PARAMETRIC
DC PARAMETRIC (LINEAR AND NMOS)
AC PARAMETRIC
DYNAMIC TEST (LINEAR AND NMOS)
EXTERNAL VISUAL AND MECHANICAL
HERMETICITY
(NOT APPLICABLE JO PLASTIC PACKAGES)
Ta = 100c
T a = 25 C
Ta MIN, TA MAX
TA MIN, TA MAX
TA = 25C
Ta = 25#C
MAJOR
MINOR
GROSS
FINE
HOW TO ORDER
LEVEL 1
AOL
LEVEL II
LEVEL III
0.15
0.28
0.40
0.65
0.65
0.65
0.11
2.50
0.40
1.00
0.28
0.40
0.65
0.65
0.65
0.11
2.50
0.40
1.00
0.15
0.28
0.40
0.65
0.65
0.65
0.11
2.50
0.40
1.00
PART MARKING
MC14001B
CP
I
Part
T
Standard
T
BETTER
Identification
Package
Suffix
PROCESSING
LEVEL 1 = SUFFIX S
LEVEL (1 = SUFFIX D
LEVEL ill = SUFFIX DS
2-2
The Standard Motorola part number with the corre

sponding BETTER" suffix can be ordered from your
local authorized Motorola distributor or Motorola sales
offices. "BETTER" pricing will be quoted as an adder to
standard commercial product price.
The Motorola
Standard high rel
Programs
M otorola, a pioneer in the m anufacture of high-reliability integrated cir
cuits*. now offers you a tw o-w ay program for Hi Rel products.
1. A growing line of J A N -Q U A L IF IE D integrated circuits.
2. An extensive program to supply JE D E C PRO C E S SE D devices that
approaches the Q ualified Reliability goals without the delay and high cost
of the actual qualification program.
M otorola stocks many circuits which meet J A N -Q U A L IF IE D specifica
tions, and is actively pursuing an expansion of this qualification listing
with product in all IC categories encompassing Bipolar Digital, Linear
and M O S technologies.
M otorola JE D E C P R O C E S SE D products com plem ent J A N -Q U A L IFIE D products by making available hi-rel versions of nearly all Motorola
full-tem perature range circuits, while adding the advantage of hi-rel
standardization.
The Motorola JEDEC Program

offers you these benefits:
1.
2.
3.
4.
5.
Standardization of environmental and electrical test procedures.

Less specification writing required.
Less time required in negotiating specifications.
Fast delivery.
Lower costs.
'Motorola, in early 1971, was the first company to be qualified as a MIL-M-38510 approved facility by the De
fense Electronics Supply Center of DOD.
m in i
MIL-M-38510 JAN-Qualifled Product

Screening Levels Available:
Class B & Class C
How to order
MIL-M-38510
JAN-Qualified Product
M38510 /XXX
INDICATES A
QUALIFIED
DEVICE
MILITARY
DESIGNATOR
XX
i
CASE
DETAIL
DEVICE TYPE
CLASS B. OR C
OUTLINE
SPECIFICATION WITHIN DETAIL
(SEE DEVICE
(SEE CASE
NUMBER
SPECIFICATION CLASS TABLE)
OUTLINE TABLE)
Case Outline Table

Source: MIL-M-38510D Amendment I
Appendix C
Designation
Description
A
B
C
D
F-1
F-3
D-1
F-2
14-lead
14-lead
14-lead
14-lead
FP (1/4 x 1/4")
FP (3/16 x 1/4)
DIP (1/4 x 3/4)
FP (1/4 x 3/8)
E
F
G
H
D-2
F-5
A-1
F-4
16-lead
16-lead
8-lead
10-lead
DIP (1/4 x 7/8)

FP (1/4" x 3/8)
can
FP (1/4 x 1/4)
1
J
K
L
A-2
D-3
F-6
NONE
10-lead can
24-lead DIP (1/4 x 1-1/4)
24-lead FP (3/8 x 5/8)
NONE
M
N
P
Q
A-3
NONE
D-4
D-5
12-lead can
NONE
8-lead DIP (1/4 x 3/8)
40-lead DIP (9/16 x 2-1/16")
R
S
T
U
D-8
NONE
NONE
NONE
20-lead DIP (1/4 x 1-1/16)

NONE
NONE
NONE
D-6
D-7
18-lead DIP (.300" x 1")

22-lead DIP (.400 x 1.1)
Letter
w
X
Y
Y
i
LEAD
FINISH
(SEE LEAD
FINISH TABLE)
Features:
1. Manufactured in a governmentapproved facility.
2. G.S.I. (Government Source
Inspection)
Example of MIL-M-38510 JANQualified markings
ORDER: JM38510/00104BCB
MARKING: JM38510/00104BCB
Reserved for use with special non-standard case

outlines which are specified in the individual
detail specifications.
2-4
Lead Finish Table_____

AType A or B Per MIL-M-38510
with hot solder dip_________
BType A or B Per MIL-M-38510
with acid tin plate__________
CType A or B Per MIL-M-38510
with gold plate_____________
XAny of the above, for
ordering purposes only.
lU lilU IM M B
lllllll
JEDEC Processed Product

Screening Levels Available:
Class B & Class C
How to order
JEDEC
Processed Product
xxxx/
I
MOTOROLA
DEVICE TYPE
(WITHOUT
LETTER
PREFIX)
JC
CLASS B. OR C
(SEE DEVICE
CLASS TABLE)
CASE OUTLINE
(SEE CASE
OUTLINE TABLE)
LEAD FINISH
(SEE LEAD
FINISH TABLE)
Case Outline Table

Source: MIL-M-38510D Amendment I
Appendix C
Designation
Description
A
B
C
D
F-1
F-3
D-1
F-2
14-lead
14-lead
14-lead
14-lead
FP (1/4" x 1/4")
FP (3/16 x 1/4)
DIP (1/4" x 3/4")
FP (1/4" x 3/8")
E
F
G
H
D-2
F-5
A-1
F-4
16-lead
16-lead
8-lead
10-lead
DIP (1/4" x 7/8")

FP (1/4" x 3/8)
can
FP (1/4" x 1/4)
1
J
K
L
A-2
D-3
F-6
NONE
10-lead can
24-lead DIP (1/4" x 1-1/4")
24-lead FP (3/8" x 5/8")
NONE
M
N
P
O
R
S
T
A-3
NONE
D*4
D-5
12-lead can
NONE
8-lead DIP (1/4" x 3/8)
40-lead DIP (9/16" x 2-1/16")
D-8
NONE
NONE
NONE
20-lead DIP (1/4" x 1-1/16")

NONE
NONE
NONE
Letter
V
w
D-6
X
Y
Dual-in-line packages not listed above

Flat packages not listed above
All other configurations not listed above.
D-7
JEDEC DESIGNATOR
PER JEDEC
PUBLICATION NO. 101
Features:
1. Lower cost than JA N -Q ualified.
2. Devices manufactured using
design and processing guidelines
contained in M IL -M -3 8 5 1 0 and
M IL -S T D -8 8 3
3. Product supplied with Motorola
standard data sheet electricals
Exam ple of JE D E C
Processed Markings
DEVICE: 5400/BCBJC
ORDER: 5400/BCBJC
MARKING: 5400/BCBJC
18-lead DIP (.300" x 1")

22-lead DIP (.400" x 1.1")
2-5
Lead Finish Table_____

AType A or B Per MIL-M-38510
with hot solder dip_________
BType A or B Per MIL-M-38510
with acid tin plate__________
CType A or B Per MIL-M-38510
with gold plate_____________
XAny of the above, for
ordering purposes only.
Him, Screening Procedures

2
For MIL-M-38510 Jan-Qualified and JEDEC Processed Product

(To MIL-STD-883 Requirements)
In recognition of the fact that the level of
screening has a direct impact on the cost
of the product, as well as its quality and
reliability, two standard levels of screening are
provided to coincide with two device classes,
or levels of quality assurance.
Flexibility is provided in the choice of test
conditions and stress levels to provide
screens tailored to a particular product or
application. Selection of a level better than

that required for the specific product and
application will result in unnecessary
expense. A level less than that required may
result in a risk that reliability requirements
will not be met. For general hi-rel applications,
the Class B screening levels should
be considered.
Device Class Table

CLASS B
METHOD
SCREEN
Internal Visual (Precap)
Stabilization Bake
Temperature Cycling
Constant Acceleration
Seal (a) Fine
(b) Gross
Interim Electrical
Parameters
Burn-In Test
Interim Electrical
Parameters
2010 Condition
B and 38510
1008,24 hrs test
Condition C
or Equivalent
1010 Condition C
2001 Condition E
Yi plane
1014
Per applicable
device
1
specification
1015
160 hrs @ 125 C
or Equivalent
Per applicable
device
1
specification
Per applicable
device
2
specification
Final Electrical Tests

(a) Static tests
(1) 25C (subgroup 1.
table 1.5005)
(2) Max. & min. rated
operating temp,
(subgroups 2 & 3.
table 1.5005)
(b) Dynamic tests &/or
switching tests @ 25C
(subgroup 4 and 9.
table 1.5005)
(c) Functional test@ 25C
(subgroup 7. table 1
5005)
Qualification or Quality
Conformance Inspection
5005
Class B
External Visual
2009
CLASS C
ROMT
100%
100%
100%
100%
100%
METHOD
2010 Condition
Band 38510
1008,24 hrs test
Condition C
or Equivalent
1010 Condition C
2001 Condition E
Yi plane
1014
RQMT
100%
Per applicable
device
specification
100%
100%
100%
100%
100%
100%
100%
100%
100%
S am ple
at
Group A
100%
Sample
at
Group A
100%
100%
Sample
per
38510
100%
5005
Class C
2009
Sample
per
38510
100%
1 When specified in the applicable device specification 100% of the devices shall be tested.
2 MIL-M-38510 QUALIFIED product is tested per applicable 38510 detail specification. JEDEC PROCESSED
product is tested per the Motorola standard data sheet electrical specification.
3 For JEDEC PROCESSED product. Groups A and B per 5005 and JEDEC Publication No. 101.
Groups C and D are available upon request.
2-6
BUS INTERFACE
Microprocessor Bus
General features include:
Single +5.0 V Power Supply Requirement
Three-State Logic Output
Low Input Loading - 200 jiA Max.
This family of devices is designed to extend the

limited drive capabilities of today's standard 6800 and
8080 type NMOS microprocessors. All devices are fabri
cated with Schottky T T L technology for high speed.
DATA BUS EXTENDERS
Quad, Bidirectional, with 3-State Outputs

MC6880A/MC8T26A# Inverting
HtWMf__
enable[7
MC6889/MC8T28# Non-inverting
V ./-------------
] vcc
Input *
R w tM r
Output
i Dfivtr
# These devices may be

ordered by either of
the paired numbors.
<5| EmM
input
B u ll ( T
Output
Driver
ta p s
I3 | Bui 4
I Drivir
1j Input
tE -^ 5 7 '
Both typos:
T a - 0 to 75C
But a [ T
Or(v*r
Input
[g 3
2
and ^
Drh*r
Input Current
Device
Number
MC8880A/MC8T2SA
MC6889/MC8T2B
Packages:
L S u ffix Cato 620
P S u ffix - Caw 648
Ip ] But 3
'IH
mA Max
28
26
IL
MAMax
>OHL
Output Disabled
Leakage Currant High Logic Stats
HA Max
-200
-200
100
100
Dfivir
Input
*PLH*PHL
Propagation Delay Time High to Low or
Low to High
ntMax
14
17
BIDIRECTIONAL BUS SWITCH
M6800 CLOCK GENERATOR
MC6881/MC3449# For exchanging TTL level digital

information between selected pairs of ports in a
3-port network.
MC6875 Provides the non-overlapping two-phase

clock signals for M6800 MPU systems.
XI
1 VCC
1 MPU 01
X2
Ext In
i Reset
4 x f0
l MPU 0 2
2 x f0
Memory
Ready
But $2
#This device may be

the numbers.
System Reset
D M A /R ef Grant
DM A/R ef Req
Gnd
Both types:
TA - 0 to 70C
Memory Clock
V q l c " 0.3 V Max
Packages:
L Suffix Case 620
P Suffix - Case 648
VOHC " V CC - 0.3 V M in

f OD - 2.0 M H i Typ
MC6881/MC3449 TRUTH TABLE
v OL
>OD
# I q l " 8-0 mA V 0 - 2 .7 V
MAMax
Volts Max
25
0.8
>IL
V |L - 0 4 V
MAMax
-200
Enable
Select
Control
Data Flow
0
0
1
0
2 3
3 - 2
0
1
1
>IH
O V |H -2 .7 V
fiAMax
40
X D on't Cara
3-2
1
X
1-3
3 -* 1
High Impedance
Microprocessor Bui (continued)

ADDRESS AND CONTROL BUS EXTENDERS
Octal, Buffer/Latch Unidirectional with 3-State Outputs
#Theie devices may bs
the paired number*.
MC8B82A/MC3482A# Inverting
j "
output r r
dntblt L _ -
MC6882B/MC3482B# - Non-Inverting
j
Output r
Entbta L .
ao] vcc
Out 1 ^
Tgjouta
Out 1
To] Out B
Jsl
Jsl
is ] InB
In 1 ^
TT]
In 7
In 2 [ T
Ta]
Out 7
Out 3 [*6*
Tb]
Out a
In 3 ( T
T4 ]
In 6
In 4 ^
is ] 10 5
Out 4 ^
Gnd
[To
Output
Enable
0
0
0
1
Latch
1
1
0
X
Input
0
1
X
X
T7|
Out
TT]
Latch
m ] VCC
All types:
T a - 0 to 75C
Packages:
LSuffix -Case 732
P Suffix - Case 738
ia) m a
3
Tt] In 7
Out 2 ^
Ta] Out 7
Out 3 [*6~
7 b ] Out 6
In 3 |~7*
TT] In 6
ln 4 [ T
T I ] In 5
Out 4 p T
T7| Out B
TT]
Gnd [To
k
Output
Enable
0
0
0
1
Output
1
0
?
z
Davies
Number
MC6882A/MC3482A
MC6882B/MC3482B
Latch
1
1
0
X
Output
0
1
Input
0
I
X
X
Oo
z
VOL
lOL " 48 mA
Volts Max
VOH
lOH 5-2 mA
Volts Min
os
mA Typ
*PHL
nsTyp
0.5
2.4
2.4
-8 0
-8 0
a.o
0.S
Ltlch
10
Hex, Unidirectional, with 3-State Outputs

M C 68 87/M C 8T 9 7#- Non-inverting
MC6888/MC8T98# - Inverting
Two Enable inputs, one controlling four buffers
and the other controlling- the remaining two
buffers.
?#] Vcc
Erv*b>4 [7
MC6885/MC8T95# - Non-inverting
MC6886/MC8T96# Inverting
Two-input Enable controls all six buffers.
En*OE 1 [7
tnput A
[7
TJ) tnput E
Tt] Output E
[7
75] tnput O
5
0.6
r Q
A ll fo u r types:
T a 0 to 76C
7a| EutMi
u j Input F
Output F
Input 8 [ 7
Output 8 [ 7
Package*:
input
L Suffix Cate 620

P Suffix - Case 648
7 ] Output O
C |7
- 3
Outout c [7
Ip ] Input O
Dr
ona [T
T | Output O
A dd in v e rttr fo r MC6888/MC8T98.
A d d Inverter fo r MC6S86/MC8T96.
' V0 L
9 I o l 48 mA
Votta Max
Output A | 7
Tjjj Output F
Input C [ T
Gnd [ T
tnput A (2
u ] Input F
Output D [T*
Output C
- O
tfl] 6nOf 2
Output A J T
Input B |*4*
v cc
VOH
O I q h -S J mA
Volta Min
2.4
3-3
os
mATyp
-8 0
*PLH
n* Typ
t P(Enable|
ns Typ
6.0
11
BUS INTERFACE (continued)
Minicomputer Bus Transceivers and receivers for bus organized minicomputers employing
120-ohm terminated lines.
+5.0 v
+5.0 v
To Computer or Parlpharali
A ll thrao dovices:
T A - 0 to 70C
Package*:
H E X RECEIVERS
MC3437 Hysteresis-equipped for improved noise
immunity. DS8837 equivalent.
Input
4f7
m vcc
Output 4 flT
Ts| Input 1
Input 5 ^
^ O u tp u t
Output sfT
13] Input 2
&
Input s fs "
W
Output < i\
MC3437
MC3438
DS8641
L S u ffix Cato 620 J S u ffix
P S u ffix - Cato 648 - N S u ffix
xc
QUAD TRANSCEIVERS
12] Output 2
n ] Input 3
OiHbt* b [ T
jo] Output 3
Gnd I?
T J o lw b l. A
DS8641-MC3438
Open collector driver outputs allow
wire-0R connection. MC3438 has
hysteresis-equipped receiver for improved
noise immunity (not available with DS8641).
MC3438 is equivalent to the DS8838.
B u t3 [T
i f ] VCC
L i s ] But 1
Input 3 [IT
'l(R )
V ,(R, - 4 . 0 V
pAMax
SO
H y s ttm h
V o ttt Min
0.5
*PLH(R)
C L -1 5 p F
nsMax
30
Output 3
[7
j t
13] Output '
But 4 QT
"
Input 4 [ 7
Output 4 ^
_ 1 4 ]Input 1
f t l
r r T L- 12] Bus 2
I ' J 1 7T]
2
*3 Input
,
Dlsabl. B ( T
to] Output 2
G n d fT
T | Oitabl. A
Racchwr
Hystra*is
Volts
Min
0.2S*
*MC3438 only.
tPLH(D) <PLH(R)
'BUS
Ib US V|H<BUSI e c L - C L V l (BUS)
50 mA
Volts Max
0.7
4.0 V
jiAM ax
100
16 pF
ns Max
25
15 pF
ns Max
30
Computer Bus
NEW IBM 360/370 I/O INTERFACE
Line Receivers and Drivers designed to operate compatibly. The MC75125/MC75127 Seven-Channel
Receivers, MC75128/MC75129 Eight-Channel Receivers, and the MC3481/MC3485 Drivers meet the new
IBM System 360/370 I/O standard requirements.
SEVEN-CHANNEL LINE RECEIVERS
3
MC75127 Standard V c c
and Ground Pinouts.
MC75125
All typos:
TA - 0 t o 7 0 C
Packages:
L Suffix - Cass 620
P Suffix - Case 648
Logic: Y - A
Logic: Y a
EIGHT-CHANNEL LINE RECEIVERS

MC75128 - Active-High Strobe
MC75129 - Active-Low Strobe
ill
20
3C
18
4A
16
5A
6A
6A
7E
14
7A
7A
8E
13
7Y
8A
8A
9E
12
8Y
is
1S
1A
1A
2A
3A
4A
SA
2A
Packages:
L Suffix Case 732
P Suffix - Case 738
positive logic: Y AS
Gnd 10
V CC
1Y
3A
2Y
3Y
4Y
BY
Gnd 1 0 E
2S
Input
Resistance
k
Min/Max
V | H 3.11 V
mA Max
tPLH
CL 50 pF
ns Max
MC7612S/76127
7.4/20
0.42
25
MC75128/76129
7.4/20
0.42
25
Device
Number
'IH(R)
3-5
6Y

New IBM 360/370 I/O Interface (continued)
QUAD LINE DRIVERS

(To be introduced)
MC3485 - Open emitter driver
with combined open collector
fault flag and inverted outputs.
MC3481 Open emitter driver

with individual fault flags.
Both types:
T A = 0to70OC
Driver
O u tp u t A
E
Fault Flag A
0
Input A
E
Enable AB
E
Input B E
Feult Flag B E
Driver B
E
Gnd
5
Driver O utpu t A [ T
v cc
is] O u tp u t D
14
Te] V c c
D river O u tp u t D
Drivsr O utpu t A ( T
] Fault Flsg O
13]
14]
In p u t O
ia l In p u t D
Packages:
L Suffix - Case 620
P Suffix-C ase648
to] Fault Flag C

3
Number
Fault Flag
(Open C ollector)
jjj
1 3 Enable CO
i i | In p u t C
Drlvar O u tp u t D
_____
Driver r j
O u tp u tfl
I
Drlvar
t i l In p u t C
to] Driver O u tp u t C
Driver C
Driver O u tp u t C
Volts Max.
os*
V0 -0
mA Max
tPLH
9Ct-100pF
nsTyp
3.11
0.0
26
VOH
9 lOH " -69.3 mA
MC3481/348S
F a u lt Protection
GENERAL-PURPOSE I/O INTERFACE

Line drivers and receivers designed to operate com
patibly. The MC8T13/MC8T14 combination is specified
for general TT L system applications. The MC8T23/

MC8T24 combination is oriented toward older IBM
360/370 system requirements.
DUAL LINE DRIVERS
TRIPLE LINE RECEIVERS
MC8T13 Open emitter driver; specified for general

T T L systems.
MC8T23 Open emitter driver; specified to meet
older IBM system requirements.
MC8T14 Hysteresis-equipped receiver; specified for

general T T L systems.
MC8T24 - Hysteresis-equipped receiver; specified to
meet older IBM system requirements.
All (our devices:

T a - 0 to 7SC
Packages:
L Suffix Case 620
P Suffix - Case 648
Device
Number
MC8T13
MC8T33
VOH
OIqh -76 mA
OIQH--B93 mA*
VoltsMax
2.4
3.11*
|H(RI
os
OVq -O
mAMax
*PLH
O C t - 1 5 pF
-30
-30
rtsMax
Device
Number
VoltsMin
20
20
MC8T14
MC8T24
0.3
0.2
3-6
VHIB)
VimB)-3V
tPLH(R)
3.11V* OCL-16pF
mAMix
nsMsx
0.17
0.17*
30
30
Instrumentation Bus
QUAD INTERFACE TRANSCEIVERS
These devices are designed to meet the GPIB bus specification of IEEE Standard 488-1978, for the inter
connection of Measurement Apparatus.
MC3440AP Three drivers with
common Enable input; one
driver without Enable.
O utput and
Termination
Gnd ^
Bu* A (T
Receiver i
O utput A 11
MC3441AP - Four drivers with

common Enable input.
5J vcc
3
g
3
iE
iE
3
ill
E
T - b BuC
3
Receiver
O utput C
Driver
Driver
Input A
ill Input C
Drlvar
Input B
iE
Receiver r j
O utput B
Bus B [ 7
Logie Ond [ T
MC3443P Four drivers with

common Enable input; no
termination resistors.
Enable E
Driver
13 In p u t D
Receiver
O utpu t 0
But D
MC3446AP For low-power instruments, including

MOS.
E
E
U
E
E
E
E
E
MC3448A For common Send-Receive bus;

bidirectional.
Receiver
' Input
Hysteresis
mV Min
Drive
Output Voltage
0 I q L 48 mA;
Volts Max
<PHL
(Driver or
Receiver)
its Max
MC3440AP
400
400
0.S
O.S
30
MC3441AP
MC3443P
400
0.4
25(D) 22 (R)
MC3446AP
400
0.6
60 (D) 40 (R)
M C3448A
400
0.6
17 (D) 23 (R)
Device
Number
3-7
30

Instrumentation Bus (continued)
OCTAL LOW-POWER INTERFACE TRANSCEIVER

These devices are designed to meet the GPIB bus specifi
cations of IEEE Standard 488:1978, for the intercon
nection of Measurement Apparatus.
MC3447 Open collector, 3-State
outputs with terminations.
/
13vcc
A ll types:
T a 0 to 70C
----------T - 23] Bus 0
Packages:
L Suffix - C a t e 623
P3 Suffix Cato 724
(Narrow)
--------- T 22] Bus 1

--------- T 21*1 Bus 2
L^-
--------- T 2o] Bus 3
vcc
T i l Bus 4
---------
Bus Indicates
O Bu*
T ttm in s tio n t
--------- l| ] B u s 5
H ti
- O - T 3 3 s/S ( , -4>
--------- T
Data 7ffo
s/ r
(sipTT
Devico
Number
Receiver
Input
Hysteresis
mV Min
Drive
Output Voltage
I q l 48 mA;
Volt* Max
MC3447
400
0.S
--------- T -
U-
Receiver)
nt Max
3 0 (D ) 22 (R )*
I Bus
Gnd
HIGH-CURRENT PARTY-LINE BUS TRANSCEIVERS

Devices for industrial control and data communication.
MC26S10 Inverting
MC26S11 Non-inverting
Quad transceivers with open-collector drivers and
PNP-buffered inputs for MOS compatibility.
Packages:
L Suffix - Cate 620
P Suffix -C a ta 648
T e jt
C ondition
L im its
* O utpu t C
v OL (O)
lO L - 100 m A
0.8 V o lt* Max
I 3] Driver
Input C
'O (D )
VOH 4-B V
1 0 0 /lA Max
'O I(D )
V Cc " 0 v *
V 0 H 4.6 V
100 p A Max
'IH (D)
Receiver
Enable
V IH -2 .7 V
30 MA Max
Input O
jo| Receiver
- J Output O
'I L ( D )
V ic - 0.4 V
-0.B 4 m A Max
*P ( 0 )
MC2SS10
MC26S11
15 n t Max
19 n t Max
j ] But D
*P(R)
Both Typa t
1S n t Max
Driver
Inverter on MC26S11 only.
3-8
MEMORY INTERFACE AND CONTROL

NMOS Memories to TTL Systems
MULTIPLEXED 16-PIN RAM CONTROL
(For 4K , 16K, and 64K Dynamic Memories)
MC3480 Memory Controller. Used with all three levels

of RAM.
junction with an oscillator, will also generate the neces
sary signals required to insure that the dynamic me
mories are refreshed for the retention of data.
With Schottky TT L technology for high performance,
and high input impedance for minimum loading of the
MPU bus. the MC3480 reduces package count, and
reduces system access/cycle times by 30%. The chip
enable allows expansion to larger-word capacity.
The memory controller chip is designed to greatly

simplify the interface logic required to control popular
16-pin 4K, 16K, or 64K dynamic NMOS RAMs in a
microprocessor system such as the M6800. The con
troller will generate, on command from the micro
processor, the proper RA and timing signals required to
successfully transfer data between the microprocessor
and the NMOS memories. The controller, in con
------ w
E )v Cc
M c [I
tlE
]mc
t2 [T
]c E
Row Eosbls
<] Raf Clk
Rafrath Enable
t4 (T
jo] Raf RaquMt
te [T
is] Ref Grant

Taj A12/14
R / W In [7
CAS
r/w
Ref En O ut ^
n ] A 1 3/15
Row En O ut [T
is] RAS 1
R/W O ut (jo
Js] HAS 2
>] RAS "3
CAS E l
<3 RAS 4
T a - o to 70 C
MC t l t2 t3 t4 tS
Packages:
Designed to interface directly with MC3232A or

MC3242A address/multiplexers/refresh counters.
3-9
L Suffix - Case 623

P Suffix - Cate 649
MEMORY INTERFACE and CONTROL (continued)

NMOS Memories to T T L System* (continued)
Multiplexed 16-Pin RAM Control (continued)
(For 4K , 16K, and 64K Dynamic Memories)
MC3232A 6-Bit (4K RAM) Address Multiplexer/Refresh Counter

MC3242A - 7-Bit (16K RAM) Address Multiplexer/Refresh Counter
MC3482A/B 8-Bit Address Multiplexer (See Microprocessor Bus Section)
MC3232A Designed for multiplexing 12 address
lines into 6 for the 16-pin multiplexed 4K RAMs, while
also containing a 6-bit refresh counter.
MC3242A Designed for multiplexing 14 address lines

. into 7 for the 16-pin multiplexed 16K RAMs, while
also containing a 7-bit refresh counter.
Count
Ref En
T
A1 T
A1 T
A2 T
A8 T
AO T
A6 7
55 T
0 2 To
o i ii
Qnd ]Z
m vcc
E a Row En
Count 1
Ref En T
E l AS
A11
ED A4
Both types:
T a - 0 to 75C
Packages:
ED
A10
DU A3
ED AB
m
Row En T
N.C. T
A1 T
623
649
65
733
710
53
OS
s a CE
m
Q
V CC
ED A 6
A 13
E3 AS
A 12
A8 T
A2 T
AS T
[3
AO T
E3 A 1 0
A4
A ll
A3
A7 To
m 3
55 77
10
02 H
O i 73
IB 53
Ond 71
CE
m
m
03
OB
MC3232A
A11
O u tp u t B
12.
Total
Address
Lines
A6
AO
Output 0
N - 6-B lt fo r M C3232A
7-8 It fo r M C3242A
3-10
MEMORY INTERFACE AND CONTROL (continued)

NMOS Memorial to T T L Systems (continued)
BUS EXTENSION
(See Microprocessor Bus)
Data Bus (Bidirectional) Extenders
MC6880A/MC8T26A - Inverting
MC8889/MC8T28A - Non-inverting
MC6887/MC8T97 Hex Non-inverting

MC6888/MC8T98 - Hex Inverting
MC6882A/MC3482A - Octal Inverting
MC6882B/MC3482B - Octal Non-inverting
Address Bus (Unidirectional) Extenders

MC6885/MC8T95 - Hex Non-inverting
MC6886/MC8T86 - Hex Inverting
Bus Switches
MC3449 - Triple Bidirectional
DATA AND ADDRESS LINE DRIVERS

(Low Level)
MC3459 - Quad Address Line Driver
Input
1A
E
Input
2A E
Output
E
A
ID E
28 E
Output
E
0
Ond
E
Input
---- -------
73] vcc
T a 0 to 70C
nj
Packages:
L Suffix - Coto 632
P Suffix Cate 646
12l lnp
20
ie :
Input
n ] 0u2>u*
Device
v OH <n'OH
Number Volts Min mA
iU T
H
Jd -
T '
2.4
MC34B9
V0 L >OL
Volts Max mA
2.0
0.7
Propagation
Delay
ns Max
^
P
Features
26
360
High fan-out capability
80
*0"! Output
CLOCK AND CHIP ENABLE LINE DRIVERS

(High Level)
MC3245 Quad Clock Drivers
with Refresh Select Logic
MC75365 - Quad Clock Driver or

High-Current NAND Gate
iU v c c
v CC2 (T
is) O utput
j 4| Channel
H Jvcci
O utput A|2~
Input 1a [3~
14] Input O
13) Input 3CD ,n p u tB
12] Enable 2
Input 3A b |~5
12] Input 2CO
Channel
Input 1B[6
U ] Input 1C
Select C
Device
Number
MC324S
M M H0026
MMH0028C
G n d (?
T A - 0 to 70C
T a * 0 to 70C
Packages:
L Suffix Case 620
P Suffix - Case 648
Packages:
L Suffix - Case 620
P Suffix - Case 648
OH
mA
V0 L
Volts Max
(Pin Connections fo r U or PI Package)

T ^:
MMH0026 55 to 126C
MMH0026C - 0 to 70C
O utput B|7
9 ]N C
VOH
Volts Min
V g e [ 3"
Input 2AB [T
Tc| O utput
Gnd
In p u t A
i H Enable 3
^1
Dual Clock Driver
NCE
IS jO u to u tD
Select O
O utpu t b E
MMH0026
MMH0026C
>OL
mA
'DHL
ns Max
Cl
pF
Packages
G Suffix Case 601
L Suffix Case 632
U Suffix - Case 693
PI Suffix - Case 626 (For
MMH0026C only)
Feature
V D D - 0 .B
-1 .0
Ooos not require second high voltage

supply. Low input loading._________
V CC2 "
-1
Derivot
power fro m T T L 5-V
supply, and V q c 2 and V (;c 3 from Vgg
and V g g supplies from NMOS memories.
V C - 1.0
For very high capacitance loads.
Vg -f 1.0
* V | - V EE
3-11
NMOS Memories to MECL Systems

DRIVER/TRANSLATORS
MECL-to-MOS driver/translators convert standardmemory systems. The MC75368 may also be used as
MECL 10,000 input signals to suitable levels for NMOS
positive logic NOR or non-inverting gates.
MC7S368 - Dual Clock Line Drivers suitable for driving

address, control, and timing inputs.
Maximum Supply Voltage:

MC7S368- 18 V
T A = 0 to 7 0 C
Package*:
L Suffix Cato 632
P Suffix - Case 646
Device
v OH
'OH
VOL
9 'OL *OHL e CL
Number Volts Min
mA Volt* Max
mA ns Max
pF
MC7536B VCC2 - 0 3
0.3
10
26
300
-1
SENSE AMPLIFIER
MC3461L Dual Sense Amplifier with MECL 10,000compatible control inputs and complementary,
open-emitter outputs. Designed for 7001 and 2105
type NMOS IK R A M s.
t h
mA Max
tpQ (Amplifier)
nsMax
tp o (Enable)
nsMax
1200
10
6.0
O utput
Gnd
E
O utput
E
1A
O utput
E
2A
O u tp u tl A
Enable
It
Input
2A E
Input
1A E
Letch
Input E
V EE
(-5.2 V) E
T a 0 to 7BC
Package:
Cate 620
3-12
I Reference
I Gnd
Hs) O utput
I
2B
g s r
jg j O utput* B
Enable
ill Input
IB
Input
2B
^ A m pl. Input
IC| Term ination
^
<RT >
7 ] V CC
J f(+7.5
V)
Magnetic Memories to TTL Systems

SENSE AMPLIFIERS
. . . for Magnetic Tape Memories
A two-component preamplifier/amplifier combination

that provides the interface between magnetic tape heads
and digital logic. Suitable for both open reel and car
tridge tape systems. Triple preamp has individually ad
justable gain controls. LSI Read Amplifier performs
peak detection and threshold detection functions, as
required for NRZI/phase encoded recording formats.
TAPE AMPLIFIER SYSTEM
Electronic Gain
Control
N R Z I/0
Code Select
MC3468 Read Amplifier
MC3467 Triple Preamplifier

Channel Select
(A o r B)
Threshold Detector
O u tp u t TO
Threshold
Level Input
Threshold A m plifier
Input A
Threshold A m plifier
Inverting Input
Threshold A m pliflor
Input B
EGC
Both types:
T a - 0 to 70C
Packages:
L Suffix - Case 726
P Suffix Case 701
O ifferentiation
Components
Inputs A
Inputs B
. . . for Plated Wire and Thin-Pilm Memories

and other low-level sensing applications.
M C I544 - T a = -5 5 to 125C
MC1444 T a = 0 to 70C
Features 4-channel input with decoded channel
selection and strobed output capability.
Packages:
MC1S44/MC1444
L Suffix - Case 620
Device
Number
MC1S44
MC1444
VO H
v OL
lo H - 4 0 0 /iA lo L 10 mA
tP D
VTH
n i Max
mV
V o lts Max
V o lts M in
25
0.5
2.4
0.6 to 1.S
25
0.5
0.3 to 2.3
2.4
3-13
Channel
Select |__
Inputs I [8^
__ Capacitor
111 Restore
Input
jjo] Ground
O utput

Magnetic Memories to T T L Systems (continued)
FLOPPY DISK READ AMPLIFIER SYSTEM
MC3470 Designed as a monolithic READ Amplifier

System for obtaining digital information from floppy
disk storage. It is designed to accept the differential ac
signal produced by the magnetic head and produce a
digital output pulse that corresponds to each peak of the
input signal. The gain stage amplifies the input wave*
form and applies it to an external filter network, enabling
the active differentiator and time domain filter to
produce the desired output. It combines all the active
circuitry to perform the floppy disk READ amplifier
function in one circuit, and is guaranteed to have a
maximum peak shift of 5.0%, adjustable to zero.
T a Oto 70C
Package:
P Suffix-C ate
6.0 V
12 V
Qnd
CORE DRIVER
MC55325 - T a -5 5 to 125C
MC75325 - T a 0 to 70C
Contains two source switches and two sink switches.
Source and sink selection is determined by one of
two logic inputs, and turn-on is determined by the
appropriate strobe.
Puckago*:
L S u ffix - Case 620
P Suffix - Case 648 (MC75326 only)
Device
Number
v *at
ls in k r W e e " 6 0 0 mA
Volt* Max
O VCC2 " 24 V
mA Max
off
tPLH
(Source)
niMax
tPLH
(Sink)
nsMax
MC56326
MC7B328
0.70
0.75
160
200
60
60
46
46
3-14
COMPUTER AND TERMINAL INTERFACE

LINE DRIVERS AND RECEIVERS
for ModemAerminal Applications
Voltage Mode
RS-232C SPECIFICATION
RECEIVERS
D R IVER
MC1489 - Quad; 0.25 V input hysteresis.

MC1489A - Quad; 1.1 V input hysteresis.
MC1488 -> Quad; output current limiting.
---------- V.J Input A T
* 3 VCC
R npenM I T
All devices:
TA - 0 to 70C
Control A L .
13]
Output A [ T
TT\ AMponM
U Control D
Input 0
Package:
L Suffix Cate 632
6
=
i___ /
6.0
Device
Number
MC14S9
MC1489A
lo | Input C
Output B [
7 1 RMponw
JLI Control C
*8] Output C
k
v OL
*PHL
C L 15pF
V cc/V gg 9.0 V
os
Volts Max
nsMax
mA
- 6.0
16.0 to 12
175
l7 | Output
RoiponM
Control 0
Ond Q
V 0H
V c c /V E E " * M V
Volts Min
Input 0
Input V ih l
V olts
1.0 to 1.6
1.76 to 2.26
Input V|LH
Volts
0.76 to 1.26
0.76 to 1.25
tpHL
0 RL - 380 n
nsMax
60
60
RS-422/423 SPECIFICATION
RECEIVER
D R IVER
MC3486 Quad; three-state outputs and input hysteresis.
MC3487 - Quad; three-state outputs.

-------- ^
--------
v-
II
UK
3 j
Both devices:
T a 0 to 70C
Packages:
L Suffix Case 620
P Suffix - Case 648
Channol C
Outputs
-O
Output A/C
Control
Id
Ond |~b
VoD(Differentlal)
v OL
v OH
R L -1 0 0 n
O I q h 60 mA 9 l0 L " 48 mA
PLH/*PHL
Volts Min
nsTyp
Volts Max
Volts Min
16
2.0
2.0
0.6
13] Output B
171 Output B/D

J Control
77] Output O
is l
3
id
e v iD - t i o v
V TH(DI
V
c
c
0
to 5.25 V tPHL^PLH *P(Control)
V|CM " *7.0 V
nsTyp
nsTvp
mA Max
Volts Max
26
20/26
*3.26
t 0.2
3-15
COMPUTER AND TERMINAL INTERFACE (continued)

Line Driven and Receivers for Modem/Terminal Applications (continued)
Differential Current Mode

DRIVERS
RECEIVERS
MC75107/MC55107 Dual; active pullup output.
MC75108/MC55108 - Dual; open collector output.
MC75S110 Dual; industry standard.
3
Outputs
VCC |Y 12
VCE
. xi
D
Output*
2Z 2Y
T a 0 to 70C
(MC75xxx)
-5S to 125C
(MC55xxx)
VEE
2A
20
NC
14
13
12
11
10
L Suffix Cate 632

P Suffix - C a w 646
(MC76xxx only)
A
1
ll 3 T f l 3 G n 3 0 t I r
t A 10
Logic
Inputt
1C 2C
Inhibit
Inputt
2A 28
Logie
Inputt
Ond
Input!
1A
IB
MC3453 Quad; common inhibit input; current sink

approximately 12 mA.
Output StrotM
VCC
NC Output StrotM Strob* Ond

IV
10
S
MC3450 Quad; active pullup outputs; common threestate enable.

MC3452 Quad; open collector outputs.
Input A
[ 3 v cc
(2
is l Input B
Output A
2
(3
Output B
js)
Output C
ij]
inhibit [T
Output O
All three devices:

T A 0 to 7 0C
Packaoes:
LSuffix -C as e 620
P Suffix - Csse 648
io| Input D
Input C [7
Ond [B
VEE
ALL RECEIVERS
BOTH DRIVERS
>0 (off)
O (on)
mAMin
pA Max
6.6
100
*PHL
nsMax
15
3-16
Input V j h
mV Max
e V |D o s v
Ij A Max
iH
*IL
V ,D - - 2 jOV
uA Max
*PLH
nsMax
26
76
-10
26
PERIPHERAL INTERFACE
Dual Drivers
. . . f o r relays, lamps, and other peripherals requiring more power than generally available from logic gates.
Representative Diagrams
MC754xx Series
i t n
i r i i H
MC75450 - Similar to MC75451, but with uncommitted

output transistors.
MC147x Series
av
28
2C
Sub
26 ttflU
1A
IV
IB
1C
IE
i r
IV
Gnd
(MC75451/MC75461)
(MC1472)
Logic Output
(Including
Trantittor Inversion)
BV : e r
70 V
30V
MC75451
MC7S452
MC75453
MC754S4
30 V
SN75451B*
SN754B2B*
SN7S453B*
SN754S48*
3S V
MC75461
MC75462
MC754S3
MC7S464
Gnd
All Device*
T a o to 70C
Logic gates vary to provldo output shown:
AND
NANO
OR
NOR
VCC 2A
Hi-Z Input
MC1472
"Same ai equivalent MC type*, but with guaranteod twitching limit*.
Packaging:
MC78460
L Suffix - Cate 632
P Suffix - Cate 646
MC75451 64/MC75461 -6 4
P Suffix - Cs*e 626
U Suffix Cate 693
MC1472
P1 Suffix - Case 626
U Suffix - Cate 693
Driver Arrays
. . . Seven Darlington transistors with output clamp
diodes.
Oovice
Number
MC1411
MC1412
Application
General Purposo
14-25 V PMOS
MC1413
MC1416
6 V CMOS or TTL
8 IB V MOS
-O t;:
All Typet:
V M ax 5 0 V
Max 600 mA
Input Element
Basic
Ztner and Series 10,6 k ll
resistor
Series 2.7 kSi resistor
Series 10.5 k t l rosistor
TA o to 85C
Packages:
L Suffix Cate 620
P Suffix Cate 648
~ i
vcc
Dual Receiver
^*ino
Input Input 2
M C 75140P1.- Dual single-ended receiver with common

strobe and reference inputs for maximizing noise
immunity. Useful for bus-organized (party line)
TTL systems.
T A 0 to 7 0 C
Vt h
VRef
*PLH(U
100 V
1.6 to 3.6 V
35 nt
Package Cate 626
iH
iH
L H
iP
Output Strobo Lin* Gnd

1
Input Input 1
3-17
NUMERIC DISPLAY INTERFACE

. . . for mating multiplexed LED or gas discharge numeric displays to MOS or T T L logic systems.
LED Drivers for Common-Cathode Displays

MC75491 - Quad segment driver
MC75492 Hex digit driver
3
Input 1 | 1
? J ] In p u t 4
12] C ollector 4
C ollector 1 [ T
Gnd [*4~
C ollector 2 n r
Both Devices:
TA - 0 to 7 0 C
Gnd ^
Input 3 ^
O utpu t 3 ^
~8~| Input 3
Device
Number
MC7S491
MC75492
12] In p u t 6
In p u t 2 ^
9 I Em itter 3
Input 2 [ T
13| O u tp u t 6
O utput 2 m
Packages:
LSuffix -C a s e 632
P S uffix-C ase646
Vs s
Ttfl Collector 3
Em itter 2
~14| Input 1
O utput 1 ( T
13l Em itter 4
Em itter 1 ^
H ]v ss
-O i
f< 3 ~
O utpu t 4
l
V | = 10V
mAMax
VOL
Volts Max
1.2
1.2
3.3
3.3
>OL
mA
280
SO
To) Input 5
~9~| O u tp u t 6
T | In p u t 4
Vss
Volts Max
10
10
Gas Discharge Drivers

MC3491
MC3492
MC3490 - High Level

MC3494 Low Level
Seven digit anode drivers
Eight segment cathode drivers with

programmable current.
Programming ^
* * ] O utput 1
' I O utput 2
*1 O utput 3
_iJ
O utpu t 4
O utpu t 8
All Devices:
TA 0 to 70C
la ] O utpu t 6
12]
O utput 7
i> ] O utpu t 8
To] Substrate (Gnd)
* Inverter on MC3494 only.
Package: P Suffix Case 701
Package: P Suffix Case 648

Current
Output Voltage
Deviation
Breakdown
Compliance
Output
Device ON Current
(AH 8 Outputs)
Range
Voltage
mAMax
Volts Min
Number
%Max
Volts
1 .8B
80
8.0 to 80
MC3491
10
80
8.0 to 80
MC3492
0.28
10
3-18
Device
Number
MC3490
MC3494
Breakdown
Voltage
Volts Min
48
48
Input Voltage
(OPF-Stata)
Volts
-8.0 Min
-2.0 Max
Input Voltage Input

(ON-Stata)
Current
M AM ax
Volts
480
-2.0 Max
-380
-8.0 Min
PRECISION CIRCUITS DATA CONVERSION

Low-cost building blocks for construction of D-A/
A-D systems. Involves use of advanced technologies
such as ion implantation, laser trimming and CMOS
processing where necessary to achieve the required

functional capability, operating accuracy and production
repeatability.
D-A Converters General Purpose

Multiplying D-A converters designed to supply an
output current that is a linear product of an analog input
reference voltage and a digital input word. Devices for
6-, 8- and 10-bit digital word inputs are available.
- 8-Blt- 6-BltA1 A 2 A 3 A 4 A S A 6 A 7 A 6 A 9 A 1 0
Pd
Device
Number
6-Bit
MC1506*
MC1406
8-B it
MC1S08L8*
MC1408L8
MC1408L7
MC1408L6
MC3408
10-Bit
MC3S10*
MC3410
MC3410C
Ê E
-5 V
Error
t Sottiing
% M ax mW Max n tT y p
0.78
120
0.39
0.78
0.5
170
0.05
220
ISO
300
250
o
VRef"
2 V
mA
S u ffix
1.9 to 2.1
1.9 to 2.1
Cate
632
620
L, P
620, 648
620
690
L. P
6S0, 648
3.8 to 4.2
0.1
T a 55 to 126 C,
Dovicet w ith o u t a tte ritk : T A 0 to 70C.
- - - Dottod terminal* available

on 6- and 8-bit unit* only.
D-A Converters High Speed

j i ) Gnd
LSB 88 ( T
MC10318 - A high speed 8-bit D /A converter capable of data conversion

rates in excess of 25 MHz. it is intended for applications in high speed
instrumentation and communication equipment, display processing, storage
oscilloscopes, radar processing, and TV broadcast systems. The inputs are
compatible with MECL 10,000 series logic, while the complementary current
outputs have 51 mA full scale capability. 8-bit accurate ( 1/2 LSB) and
monotonic over the full temperature range, the outputs typically settle in less
than 15 ns.
TA = 0 to 70C
B7 | T
jU W
B6 [3
i^1 *out
B 5 (4
?5| NC
B4 [5
i i v raf+
B3 [6
TT| Comp
B2 [ T
To] v f0 f-
MSB B1 [8
Package*:
L S u ffix - Case 620/680
Error
Device
Number
% Max
M C10318L
0.19
M C 10318L9
0.10
^Settling
n*Typ
,o a l o
VRef 10.S6 V
mATyp
67B
16
61
676
16
61
pD
@ VEE d - 5 J V
mW Max
v EE
PRECISION CIRCUITS - DATA CONVERSION (continued)
A-D Subsystems
2-Chip A-D Converter System Functional Diagram
These devices are relatively complex
subsystems. The bipolar, dual-ramp A-D
converter has up to 4-1 /2-digit conversion
capability. The CMOS logic subsystem
specifically adapts the A-D converter to a
3-1 /2-digit DVM function.
MCI 505/1405 A-D Converter
MC14435 - Digital Logic

(Soo CMOS Data Book fo r data.)
MC1443SEFL/EVL* - T A = -5 5 to 1 2 5 C - Case 620

MC14435FL/VL*
- T A =-4 0 to85C -C a s e 620
MC14435FP/VP*
- T a -4 0 to 85C -Case 648
MC150SL T a -6 5 to 125C -C a s e 620

MC1405L - T a 0 to 70C
-Case 620
Linearity
Error
% Max
Voltage
Reference
Volts
1.16 to 1.36
0.05
Temperature
Coefficient
of Reference
& V c 'c - 5 X ) V
% /C
mA Max
0.006
12
OL
>OL
OL
pC{qui ascent) 9 V q d " 5J0 V @ VD D 5 .0 V @ V q d " 5.0 V
V D D - S .0 V (Digit Selects) (BCD Outputs) (All Outputs)
m W M ax
mAMin
mA Min
mA Min
1.76
1.6
1.6
-0 .2
M C14435EFL/FL/FP : V DD - 3.0 to 18 Vdc

M C1443SE VL/VL/VP: V DD - 3.0 to 6.0 Vdc
VOLTAGE REFERENCES
Precision Low-Voltage
References
A family of precision low-voltage bandgap voltage

reference, these devices are designed for applications
requiring low temperature drift.
MC1403/MC1503
v ln [ [
NC [T
3 nc
Vout [*
MC1404/MC1504
Paclcaoes:
U Suffix-C ase693
NP
Vm
Gnd [ j
7 ] nc
V jE M P [J
NC [ *
3 .N C
Gnd [
NC
3 nc
___I L
V OUt
t h im
Low Temperature Drift, Low Voltage Reference

AVoutM T
TVP
*0
mA
Max
2.5 t 25 mv
10
40
25
55
25
40
25
55
25
40
25
55
25
40
25
55
25
^ OUt
Volts
6.25 I 60 mV
10
o
3
<
10
5.0 t 50 mV
10
ppm/C
Max
Device
4.BC V |< 1 6 V /
Number
15 V < V |< 4 0 V
MCI 403
MC1403A
MCI 503
MC1603A
MC1404U5
MC1404AU8
MC1504U5
MC1504AU5
MC1404U6
MC1404AU5
MClil04U6
MC1504AU6
M C1404U 10
mV Max
3.0/4.5
RSllna
V |n V00t+
ResiM d
0.0 mA
2.6 V to 40 V
mV M ix
N/A
Io< 10 mA
mVMax
10
ta
oC
0 to +70
-5 5 t o + 125
N/A
6.0
10
N/A
6.0
10
N/A
5.0
10
0 to *70
-5 5 to +125
0 to *70
-6 5 t o +125
_ MC1404AU10
MC1504U10
- MC1504AU10
0 to +70
-5 5 to +125
3-20
VOLTAGE COMPARATORS
General Purpose Comparators

. . . for detecting the polarity relationship between two
analog levels and giving a corresponding T T L output.
3
MC1710 T a -5 5 to 125C
MC1710C - T a = 0 to 70C
Single comparators
MC1711 T a -5 5 to 125C
MC1711C T a = 0 to 70C
Dual comparators with strobes and wire-ORed
outputs
Package*:
G Suffix - Cate 601 (MCI 710)
___ ,G Suffix - Cate 603 (MCI 711)
1 2 j N .C
l Suffix - Cate 632
P Suffix Cate 646 (for
MCI 710C, MC1711C only)
Inputs 2
(Pin Connections
for L or P Package)
'Connected to p in 4 via the substrate on
somo plastic units.
'Connected to pin 6 via tho substrate on

some plastic units.
MC1514 - T a -5 5 to 125C
MC1414 - TA = 0 to 70C
Dual comparators with strobes.
Packages:
L Suffix Cate 632
P Suffix - Case 646 (MC1414 only)
3-21
Device
Number
V |0
mV Max
pAM ax
AVOL
V /V M in
MC1710C
MC1710
5.0
2.0
25
20
1000
1250
MC1711C
MC1711
5.0
3.5
100
75
700
700
MC1514
MC1414
2.0
5.0
20
25
1250
1000
l|B
VOLTAGE COMPARATORS (continued)
Precision Comparators
Da vcc
m pun - a i : >
. . . featuring low input loading, high voltage gain, and a

choice of either dual or single positive power supply
operation.
i ! 7 utpu*
j 6 Balance/Strobe
3 S Balance
(Pin Connections for J-8 or N Package)

Packages:
H Suffix - Casa 601
J-8 Suffix Case 693
J Suffix - Case 632
N Suffix - Case 626 (LM311 only)
LM111 TA = -5 5 to 1 2 5 C
LM211 TA = -2 5 to 85C
LM311 T a = 0 to 70C
Single comparators; high gain, high input imped
ance; strobe and balance inputs provided.
Device
Number
V lO
m VM ax
IB
nAM ax
VOL
9 I q |_ 60 m A
V o lts M ax
LM111
LM211
LM311
3.0
3.0
7.5
100
100
250
1.5
1.5
1.5
Quad Comparators . . . for applications requiring multiple comparators.

MC3430
MC3431
High-speed quad comparators with threestate Enable common to all four devices;
5 volt supply; T a = 0 to 70C.
}-
MC3432 1
MC3433 I ~ ua(* comParator$ w>th open collector
'
outputs, common strobe input; 5 volt
supply; T a = 0 to 70C.
| T a = 0 to 70C
Single supply voltage comparators.
Packages:
L Suffix - Cate 620
P Suffix - Case 648
Output 3 ^
u j Output 3
Output 1 ^
13 ]
12] On<*
vcc |7
["
Packages:
J Suffix-Casa632
N Suffix Case 646 (For
all devices except
LM139, LM139A)
Device
Number
Device
Number
MC3430
MC3431
MC3432
MC3433
Vis
m VM ax
6.0
10
6.0
10
IB
jiA M a x
20
20
20
20
tPHL
nsM ax
45
45
60
60
MC3302
LM2901
LM139
LM 139A
LM239
LM239A
LM339
LM 339A
3-22
Output 4
Input 1 4
7 7| Input 4
Input 1 [ 7
1 p|
Input 2
T ] Input 3
input 2
S j Input 3
V lO
@ 2SC
m V Max
l(B
9 25<>C
nAM ax
20
7.0
5.0
2.0
5.0
2.0
5.0
2.0
1000
250
100
100
250
250
250
250
tnput 4
v OL
e iO L " 2 -0 m A *
I o l " 3 -0 m A
(sink
O V O L - 500 m V 9 I q l " 4.0 m A
m V Max
m A M in
6.0
6.0
6.0
6.0
6.0
6.0
6.0
400*
4 0 0 **
500
500
600
600
500
500
COMMUNICATION INTERFACE (Telephony)

Crosspoint Switch
AnodO
A1
U _
Catftoda P 7 "
MC3416 Low-cost solid-state crosspoint switch

offers Important advantages in modern telephone
exchanges employing space-division switching.
Features 4 x 4 two-wire monolithic structure for
PABX applications. Select inputs are both CMOS
and TT L compatible.
Rqm S in i
*
Cm x o m
za
Column
SflOCt A
Co*umn
SoitctB
Column
SalactC
C o lu m n
Satact
C a f* o d a
Package*:
P Suffix - Cate 649
L Suffix - Cate 623
ovAK-io v
MftMin
100
'm
i.
.
i_
ID A
nS
zi A;r
V
.
1 ArvoO*
C atftod a
o * S 't c l[ - ^ "
L_
|
C *th O <W 1
ron
BVa k
Va k
Ia k " 20 mA BVk a
9 Ia k 20 mA
Volt* Min
Volt* Max
Ohm* Max
25
1.1
10
AnoO t
02
3 nr
z rr
jD 0
1
1S1 W
1
oa
13-|
1cm
1
__
D|
\*
1
21 l_
T a - o to 70C
'off
|
L
I
L
i
I
I
I
r
1
1 7 1 c ,h0*,
1
X2
| now si*c<
i l l
X
Ci*ioa
JLi
*VJ
" j
XI
Voice Encoding/ Decoding

Simplified voice encoding/decoding using continuous
Variable Slope Delta Modulator (CVSD) technique.
Analog i ^
Input 1
MC3417/MC3517 - 3-bit algorithm; for military secure
Analog f" T "

Faaooack 1 .....
communication and general-purpose lowsampling rate applications.
Svtiabie 1 T"
o ,,n r r
Control 1 1
MC3418/MC3518 - 4-bit algorithm; telephone quality.

Packages:
L Suffix Cate 620
P Suffix - Cate 648
TA 0 to 70C - MC3417/MC3418
-5 5 to +125C - MC3517/MC3518
R if 1
input 1*1 1 *
f.iW |
input 1 - l L L .
Device
Number
Total Loop
Offset Voltage
mV Max
tp o . Clock Trigger
to Output
M Max
MC3417/MC3B17
MC3418/MC3S18
16 k
38 k
i5 .0
2.0
2.6
2.6
vee |
3-23
1Thrtthold
1Co<nc>6anc
J J J Output
"io lvcc
JOutput
b
CVSD Decoder
CVSD Encoder
14 Ic ia O
...................
1Iwnt*
Analog
Output I
Sample Rate
Sample*/*
Typ
t |v c c
-lin c o a * '
15 lp .e o a .
"T n D .g .tai
__Z1Output
COMMUNICATION INTERFACE (Telephony) (continued)
Digital Voice Channel

SUBSCRIBER LOOP INTERFACE CIRCUIT
MC3419/MC3519 - Designed to replace the hybrid

transformer in Class 5, PBAX and Subscriber Carrier
Equipment, this circuit provides signal separation for
two-wire differential to four-wire single-ended conver
sions and suppression of longitudinal signals at the twowire input. The transhybrid gain is externally selected
and provides dc line current for powering the telset. It

operates from up to a 60 V supply. On-hook power is
below 5 mW and current sensing outputs are provided
for off-hook status from both tip and ring leads. It
offers size and weight reduction over present approaches
and is compatible with IEEE and REA specifications.
TA O to 70C - MC3419
-4 0 to +8SC - MC3S19
Packages:
L Suffix Case 726
P Suffix - Case 701
V CC
EP
TS
RS
BP
PD
R3
T ------V W -
m
CP
MC3419
R4
W V r
RX
CN
R2
TX1
TX2
BN
EN
V AG
V EE1
V EE2
3-24
MEMORY/MICROPROCESSOR SUPPORT
Temperature Range
Commercial
Military
MC1444
M C3232A
M C3242A
M C3245
M C3459
MC3461
MC3467
M C3468
MC3470
M C3480
MC6875
M C 6 88 0A /
8T26A
M C 6881/
3449
MC6882A. B /
MC3482A, B
M C 6 88 5-88 /
MC8T95-98
M C 6 88 9/
8T28
MC6890
MC75365
MC75368
MMH0026C
M C1544
Page
AC-Coupled 4-Channel Sense A m p lifie rs....................................... 4-3
Memory Address Multiplexer/Refresh Address C o u n te r............ 4-11
Memory Address Multiplexer/Refresh Address C o u n te r............ 4-16
Quad TTL-to-MOS D river.................................................................... 4-21
Quad NMOS Memory Address D riv e r.............................................. 4-2 4
High-Speed NMOS/MECL Sense Amplifier .................................. 4-28
Triple Magnetic Tape Memory Preamplifier ................................. 4-3 4
Magnetic Tape Memory Read A m p lifie r ......................................... 4-3 9
Floppy Disk Read Amplifier System ................................................. 4-59
Dynamic Memory Controller ............................................................. 4-7 3
M 6800 2-Phase Clock Generator/Driver ....................................... 4-8 8
Quad 3-State Bus Transceiver..........................................................
4-99
Bidirectional Bus Extender/Switch
................................................
4-1 04
Octal 3-State B u ffe r/L a tc h ...............................................................
4-109
Hex 3-State Buffer/Inverters............................................................. 4-113
MC6890A
M M H0026
Non-Inverting Bus Transceiver.........................................................

8-Bit Bus-Compatible MPU D /A Converter....................................
Quad MOS Clock Driver ....................................................................
Dual MECL-to-MOS Driver ...............................................................
Dual MOS Clock D r iv e r......................................................................
4-118
4-123
4-1 24
4-132
4-1 37
MOTOROLA
AC-COUPLED
FOUR-CHANNEL
SENSE AMPLIFIER
HIGH SPEED, LOW THRESHOLD SENSE AMPLIFIERS
S ILIC O N M O N O L IT H IC
IN T E G R A T E D C IR C U IT
The MC1444 and MC1544 are high-speed quad sense amplifiers

for use w ith plated wire, th in film or other m emory systems requiring
very low threshold sensitivity and narrow pulse w idths. B oth devices
feature internal capacitive coupling to reduce the effects o f voltage
offsets.
Threshold Level - 1.5 m V (T yp ), 100 ns Rectangular Pulse
Decoded In p u t Channel Selection
O u tp u t Strobe C apability
DC Level Restore Gate on Internal Capacitors Eliminates Repe

titio n Rate L im ita tio n s
L S U F F IX
CASE 620
__ C apacitor
1JJ Restoro
In p u t
Channel I
Select \ .__
Inp u ts * [_8_
TRU TH TABLES
Channel Select
Channel
Pin
Pin
7 (X ) 8 (Y ) Selected
A
H
H
B
H
L
C
H
L
D
L
L
O u tp u t
In p u ts
S trobe
H = high level (steady state. V j ^ V iH (m in ) o r ^ I D ^ v th

L lo w level (steady state). V j ^ v | L (m a x) or v l D ^ v th
X * irre le va n t (any in p u t, in c lu d in g tra nsition s)
_J = tra n s itio n fro m lo w level to high lovel
X T - low -level o u tp u t pulse
10l G round
L
X
X
X
H
H
JT
D iffe re n tia l
C a pa cito r
In p u t
C h an n el A
Restore
X
X
X
H
X
X
X
X
H
L
H
L
H
L
O u tp u t
Channel
Selects
X
X
X
X
L
X
X
L
H _ r
_ r
h
H
H
H
H
H
H
U "
~LT
U
C hannel A used as an exam ple, o th e r channels

fu n c tio n s im ila rly . Soo channel select table.
4-3
MC1444, MC1544
MAXIMUM RATINGS (T A +25C unless otherwise noted).

Symbol
Value
U nit
Power Supply Voltages*1*
Rating
V cc
V EE
7.0
-8.0
Vdc
Input Common-Mode Voltage Range
V ICR
+5.0.
-6.0
Vdc
Input Differential-M ode Voltage R a nge'll
V|DR
+5.0.
-6.0
Vdc
Input Capacitor Restore, Channel Select, and

Strobe Voltage
V|(CR)
V HCS)
V HS
+5.5
Vdc
PD
1.0
6.7
Watt
m W /C
Ta
0 to +75
-5 5 to +125
Storage Temperature Range
Tstg
-65 to +150
Operating Junction Temperature
Tj
+ 175
Power Dissipation (Package Lim itation)

D e ra te above T A 2 5 C
Operating Am bient Temperature Range
MC1444
MC1544
(1) A ll voltage values, except differential voltages, are w ith respect to the network ground terminal.
(2) Differential in put voltages are at A1 w ith respect to A2, and similarly B1 to B2, C l to C2, and D1 to D2.
FIGURE 2 - EQ UIVALEN T CIRCUIT SCHEMATIC
RECOMMENDED OPERATING CONDITIONS

Characteristic
Power Supply Voltages
Symbol
Min
T yp
Max
U nit
VCC
v Ee
4.75
-5 .7
5.0
-6.0
5.2S
-6.30
MC1444, MC1544
ELECTRICAL CHARACTERISTICS (Unless otherwise noted, tpecificatiom apply fo r 4.75 V < Vcc * 5.25 V , -5.7 V > V g e > -6.3 V ,
__________ __________________________ T A - 25C.I___________ __________________
M CI 444
M C I 544
Characteristic
Symbol
Min
Typ
Max
Min
Typ
Max
U nit
Input Threshold Voltage (Figure 4)

(VCC - 5.0 V, V EE - -6.0 V, T A - Thigh o T,ow > (1)
V,h
0.3
1.0
2.3
0.5
1.0
1.5
mV
MA
Input Bias Current (Selected Channel)
'IB
20
50
20
50
Input Offset Current (Selected Channel)
*10
1.0
10
1.0
10
Channel Select Input Current-High Logic State,
'lH(CS)
2.6
2.6
mA
<V |H (C S )"3-5 v >

Channel Select Input Current Low Logic State.
'lL(CS)
1.0
1.0
mA
<V|L(CS) 0 V)
Capacitor Restore Input Current High Logic State,
10
'IH(CR)
10
<V|H(CR) 3.5 V)
Capacitor Restore Input Current-Low Logic State,
IV |L (C R | 0 V )
'IL(C R)
-3.5
-3.5
mA
Strobe Input Current-High Logic State,
'lH(S)
200
200
HA
(V|H(S) * 3.5 V)
Strobe Input Current-Low Logic State
'ILIS I
200
200
>iA
*V|L(S) 0 V)
Channel Select Input Voltage-Low Logic State
V|L(CS>
0.7
0.7
Channel Select Input Voltage-High Logic State
V|H(CS)
2.1
-
2.1
0.8
0.8
2.0
0.8
0.8
2.0
Capacitor Restore Input Vottage-Low Logic State
V|L(CR)
Capacitor Restore Input Voltage-High Logic State
V|H(CR)
Strobe Input Voltage-Low Logic State
VlL(S)
2.0
-
Strobe Input Voltage-High Logic State
V|H(S)
2.0
V lC R *
V|C R -
4.7
-6.0
4.7
-6.0
Input Differential Voltage Range
VlOR
3.7
3.7
Output Voltage-Low Logic State
VOL
0.4
0.5
0.4
0.5
(lO L 10 m A )
O utput Voltage-High Logic State
(lOH -400 (iA)
v OH
2.4
2.4
Positive Power Supply Current
ic e
30
mA
>EE
30
30
Negative Power Supply Current
30
mA
V
V
SWITCHING CHARACTERISTICS (unless otherwise noted, T a 25C. V c c 5.0 V. Vgg * -6.0 V)

MC1544
MC1444
Symbol
Min
Typ
Max
Min
Typ
Max
U nit
Propagation Delay Time

Differential Inputs to High Logic State O utput
PLH(D)
40
40
ns

Differential Input to Low Logic State Output
*PHL(D)
18
25
18
25
ns

Strobe Input to High Logic State Output
*PLH(S)
30
30
ns

Strobe In p u t to Low Logic State O utput
tPHL(S)
18
25
18
25
ns
*L(CSI
45
45
ns
L(CRO)
15
15
ns
*L(S)
10
10
ns
<L(CR)
10
10
Common-Mode Recovery Time

(ein i * +2.0 V)
(ein i - - 2 . 0 V )
*CMR+
*CMR-
50
50
Differential-Mode Recovery Time

(ein 1 + 1 .0 V )
(eln 1 - - 1 . 0 V )
DMR+
*DM R-
65
65
Characteristic
Lead Time from Channel Select Input to

Application o f Differential Input Voltage
Lead Time from Application o f a 50 mV Offset
Signal to Application o f the Capacitor Restore Signal
Lead Time from Application o f Strobe Input to
Application o f D ifferential Input Signal
Lead Time from Application o f Capacitor Restore
Signal to Application o f Differential Input Signal
ns
ns
50
50
ns
<1* Thigh - ?5C fo r M C1444,125C fo r M C I544.

T |o w 0C fo r MC1444v -55C fo r M C I544.
4-5
65
65
MC1444, MC1544
FIGURE 3 - THRESHOLD VOLTAGE TEST CIRCUIT

VEE
Vcc
Vcc
FIGURE S - THRESHOLD VOLTAGE TEST

fa.
Vjh-----* INPUT
SIGNAL
*** iCHANNEL
SELECT X
CHANNEL
SELECT Y
-too a
3 V ---- -
C ZI
3V V
V"
_ A ______ A_
,|0* CAPACITOR * V
FIGURE 6 - t L(cs). *L(CR). *LIS). *PLH(D)

* INPUT SmV
S.GNAL
7 \
U_CS) -H K I
CHANNEL
SELECT V
so*
3 V ------- ,
STROBE
IT T .
KTTLltl V0HGATE
OUTPUT Vqi.
NOTE: t j j j Kd tjgj to b( nonnd at hmrttd (dstnd fiat)

a ntctmfY O Hint desiredcfurmd. For
" I ->>5 <TLH I
THL <10 in
:t
L(CS)-<
4 CAPACITOR
RESTORE
0
St
'T
J iT l
SELECT X
17
3 V ----- /
1CHANNEL
*J CHANNEL
SELECT Y
FIGURE 7 - tpLH(S) *PHL(S)

t i . ____ SnV
INPUT
SIGNAL
LICRIH K I
IL
3 V ----
sm
o
VOH-
LIS) H
11
vql*-
HI-------1 iPLKtO)
NOTE: iia i- 'in j tTLH I

tTH Lf< I0
4-6
0-
F
R t- I
VOH-
oM,
IJ V --p
V0 L ------------tPHL(S)
NOTE: *.-&
*TLH I
THL I
...
MC1444, MC1544
FIGU RE 9 - t(_ (C R O )
FIGURE 8 - tpLHlCSMPHUCSl
_
5mV-
*"i COMPOSITE
I T
CHANNEL
SELECT X
' CAPACITOR
,in5 STROBE
0-
T
fl-----I
MmV -
" 2 CHANNEL
SELECT X
E F Is
'"^CHANNEL
SELECTY
RESTORE
INPUT
V _
'"J CHANNEL
SELECT V
raoaninn
\ J ~
* 0H'
'ouln
PHL1CS>
-I
I "t tPLK(CS)
NOTE: Tg tot o\!ttf duofld hct input,

..
il
OEFINITIONS
VOH
VOL
VIH(SI
VIL(S)
Vth
V|CM+
VlCMVIH(CR)
VlUCRI
VIH(CSI
VIUCS)
VlO
'OH
'OL
'IH(S)
'IMS)
*CMR
<L(CRO)
Output Voltage High Logic State

Output Voltage Low Logic State
The minimum high-level voltage at the strobe input which
will allow normal operation during the threshold test
The maximum low-level voltage at the strobe input which
will result in Vo h at the output regardless of,in
put signals
The minimum input signal (ejn^l required to drive the
MTTL III gates to obtain the eQ waveform shown in
Figure 5
The maximum common-mode input voltage that will
not saturate the amplifier
The minimum common-mode input voltage that will not
break down the amplifier
The minimum high-level voltage at the capacitor restore
input required to insure that the capacitors are clamped
i.e., the input threshold voltage it greater than 10 mV
The maximum low-level voltage at the capacitor restore
input which will allow normal operation during the
threshold test
The minimum high-level voltage at a channel select in
put required to insure that the total of the base currents
of all unselected inputs is less than 1.0 fiA
The maximum low-level voltage at a channel select in
put required to insure that the total of the base currents
of all unselected inputs is less than 1.0 mA
The maximum differential-mode input voltage that will
not saturate the amplifier
Output Source Current High Logic State
Output Sink Current - Low Logic State
The current into the strobe input when the input it at a
high-level of 3.5 volts
The current into the strobe input when the input is at a
low-level of 0 volts
The minimum time between the 50% level of the trailing
edgeof a + or - 2 volt common-mode signal Ut l h . *THL
< 1 5 ns) and the 50% level of the leading edge of a
5 mV input pulse when the capacitor restore and strobe
inputs are used in a normal manner as shown in Figure 22
The minimum time between the 50% level of the leading
edge of a 50 mV input offset signal and the 50% level of
the leading edge of the capacitor restore pulse as shown
in Figure 9
L(CR)
*L(CS)
tpLH(CS)
tpHL(CS)
lDMR
tPLH(O)
tPHL(D)
LIS)
*PLH(SI
tpHL(S)
'lH(CS)
'lH(CR)
'lL(CS)
'lL(CR)
4-7
J*TLH<tOm
,n2 |tTHL

edge of the capacitor restore signal and the 50% level of
the leading edge of a 5 mV input signal as shown in
Figure 6
edge of the channel select and the 50% level of the
leading edge of a 5 mV input signal as shown in Figure 6
The delay time from the 50% level of the trailing edge of
the channel select signal to the 1.5 volt level of the
positive edgeof the output when the input to the selected
channel is held at the "1" level as shown in Figure 8
The delay time from the 50% level of the leading edge of
the channel select signal to the 1.5 volt level of the
negativeedge of the output when the input to the select
ed channel is held at the "1" level as shown in Figure 8
The minimum time between the 50% level of the trailing
edge of a + or - 1 volt differential-mode signal (ty|_H.
tju L ^ 15 ns) and the 50% level of the leading edge of
a 5 mV input pulse when the capacitor restore and strobe
inputs are used in a normal manner as shown in Figure 23
The delay time from the 50% level of the trailing edge
of a 5 mV input signal to the 1.5 volt level of the posi
tive edge of the output as shown in Figure 6
The delay time from the 50% level of the leading edge
of a 5 mV input signal to the 1.5 volt level of the nega
tive edge of the output as shown in Figure 6
edge of the strobe and the 50% level of the leading edge
of the input signal as shown in Figure 6
The delay time from the 50% level of the trailing edge
of the strobe to the 1.5 volt level of the positive edge of
the output when the input is held at the High Logic Level
as shown in Figure 7
The delay time from the 50% level of the leading edge
of the strobe to the 1.5 volt level of the negative edge of
the output when the input is held at the High Logic
Level as shown in Figure 7
The current into the channel select input when the input
is at a high-level of 3.5 volts
The current out of the capacitor restore input when the
input is at a low-level of 0 volts
The input current to a channel select input when that
input is at a high-level of 3.5 volts
The current into a channel select input when the input
isat a low-level of 0 volts
MC1444, MC1544
TYPICAL CHARACTERISTICS
(T a * + 2 5 C unless otherwise noted)
FIGURE 10 - THRESHOLD VOLTAGE versus TEMPERATURE
FIGURE 11 - THRESHOLD VOLTAGE versus POWER SUPPLIES
2.0
o
o
z
10
S
3
ae
X
>
-2 5
*25
+75
T, TEMPERATURE CC)
FIGURE 12 - THRESHOLD versus INPUT OFFSET VOLTAGE
Vio, INPUT OFFSET VOLTAGE (<nV)
FIGURE 14 - OUTPUT VOLTAGE

versus CURRENT and TEMPERATURE
Vcc. POWER SUPPLY VOLTAGE (VOLTS)
FIGURE 13 - THRESHOLD VOLTAGE versus PULSE WIDTH
PW.PULSE WtOTH (ns)

(10H LEVEL OF TRIANGLE)
FIGURE 15 - SENSE AMPLIFIER RESPONSE

versus TEMPERATURE (See Figure 3 and 6)
V[(CS). CHANNEL SELECT INPUT VOLTAGE. Pin 7 (VOLTS)
V|(CS). CHANNEL SELECT INPUT VOLTAGE. Pin 8 (VOLTS)
MC1444, MC1544
F IG U R E 22 - CO M M O N M O D E C H A R A C T E R IS T IC S
Note
The 5mV Input Signal (Differential) is superimposed on the

Common-Mode Inpul and is shown separately for reference only.
COMMON-MODE INPUT 2 V /D IV
SIGNAL INPUT '0 m V/D | V
CAPACITOR RESTORE 5 V /m v
STROBE IN P U T S V / q iv
OUTPUT 2.5 V /D |v
'
1
i
25 n5/D IV
F IG U R E 2 3 - D IF F E R E N T IA L M O D E C H A R A C T E R IS T IC S
Note: The 5mV Input Signal is superimposed on the D ifferential

Input and is shown separately for reference only.
/
D IFFE R E N TIA L INPUT 1 V /D |V
DIFFE RE NTIA L INPUT > V /D |V

SIGNAL INPUT 10 m V /D |V
CAPACITOR RESTORE 5
V/DW
SIGNAL INPUT 1 0 m V /0 |V
CAPACITOR RESTORE 5 V /D IV
STROBE INPUT 5 V /0 |V
OUTPUT 2-5 V /D IV
OUTPUT 2-5 V /O IV
MC3232A
(M ) MOTOROLA
MEMORY ADDRESS
MULTIPLEXER
AND REFRESH
ADDRESS COUNTER
MEMORY ADDRESS MULTIPLEXER

The Motorola MC3232A is an address multiplexer and refresh
counter for 16-pin 4K dynamic BAMs that require a 64-cycle refresh.
It multiplexes twelve system address bits to the six input address
pins of the memory device. The MC3232A also contains a 6-bit
refresh counter that is clocked externally to generate the 64 sequen
tial addresses required for refresh. The high performance of the
MC3232A will enhance the high speed of the fast N-channel RAMs
such as the MCM4027.
Simplifies 16-Pin 4K Dynamic Memory Design

Reduces Package Count
6-Bit Binary Counter for 64 Refresh Address
Multiplexing: Row Address/Column Address/Refresh Address
High Input Impedance for Minimum Loading of Bus:
Ip = 0.25 mA Max
Schottky TTL for High Performance Address
I nput to Output Delay
tAO D 25 ns @ C l 250 pF, 9.0 ns Max @ C l 15 pF
Second Source to Intel 3232
(Detect Zero Function Not Included and Additional
Power Fail Feature Added at Pin 13)
SCHOTTKY
SILICON MONOLITHIC
INTEGRATED CIRCUITS
L SUFFIX
CERAMIC PACKAGE
CASE 623
P SUFFIX
PLASTIC PACKAGE
Count 1 C=
Refresh 2 C=
Enable
A1 3 C=
= 3 2 4 V CC
123 Row
Enable
= 3 2 2 AS
A7 4 e =
= 3 2 1 A11
A2 5 d
ZD 20A4
A8 6 t =
ZD 19A10
AO 7 d
= )1 S A 3
AO 8 C=
= 3 1 7 A9
00
1 3 16 0 3
9 C=
15 0 4
0 2 10 c z
O l 11 c =
Gnd 1 2 C
14 0 5
13 CE*
Note: AO Through AS Are Row Addresses

A6 Through A 1 1 Are Column Addresses
*S m Pin D e finition *
TRUTH TABLE AND DEFINITIONS

Refresh
Row
Output
Enable
Enable
Refresh Address
(From Internal Counter)
Row Address
(AO through AS)
L
Column Address
(A6 through A ll)
Count Advene** Internal Refresh Counter
4-11
MC3232A
ABSOLUTE M AXIMUM RATINGS (TA 25C unless otherwise noted.)

Rating
Power Supply Voltage
Input Voltage
Output Voltage
Symbol
Value
VCC
V|
V0
-0.5 to +7.0
-0 .5 to +7.0
Output Current^
Operating Ambient Temperature
'O
TA
Storage Temperature
Junction Temperature
Ceramic Package
Plastic Package
Tstg
Tj
-0.5 to +7.0
100
"Absolute Maximum Ratings" are those

values beyond which the safety of the device
cannot be guaranteed. This is a stress rating
only and functional operation of the device
at these or any other conditions above those
indicated in the operational sections of this
specification is not implied. Exposure to
absolute maximum ratings for extended
periods may affect reliability.
Unit
V
V
V
mA
C
C
C
0 to +75
-6 5 to +150
+175
+160
ELECTRICAL CHARACTERISTICS (Unless otherwise noted, Min/Max values apply with 4.5 V < V c c < 5.5 V, 0C < T A < 75C;
typical values apply with Vcc 5.0 V, TA 25C.)
Characteristic
Input Current, Low Logic State
(V |L 0.45 V)
Input Current, High Logic State
(V |H 5.5 V)
Input Voltage, Low Logic State
Input Voltage, High Logic State
Output Voltage, Low Logic State
( I q l 5.0 mA)
Output Voltage, High Logic State
(iO H _ 1 -0mA)
Input Clamp Voltage
(l|C ~12mA)
Power Supply Current
(Vcc 5.5 V)
Symbol
Min
IL
>IH
V|L
V|H
V0 L
2.0
Typ
-0.04
-0.25
Max
Unit
mA
10
fiA
0.8
0.25
0.4
V
V
V
VOH
2.8
4.0
V |C
-0 3
-1.5
ice
75
125
mA
SWITCHING CHARACTERISTICS (Unless otherwise noted, Min/Max values apply with 4.5 V < Vcc ^ 5.5 V, 0C < TA < 75C;
typical values apply with V cc = 5.0 V, TA - 25C.)
Characteristic
Propagation Delay Times
Address Input to Output
(Load - 1 TTL, Cl 250 pF)
(Load- 1 TT L ,C l = 15pF, V c c 5 .0 V ,T A 25C)
Row Enable to Output
(Load - 1 TTL, C l 250 pF)
(Load - 1 TTL. CL = 15 pF. VCC = 5.0 V, TA - 25C)
Refresh Enable to Output
(Load - 1 TTL, CL 250 pF)
(Load - 1 TTL. Cl 15 pF, Vcc 5.0 V, TA 25C)
Count Pulse Width
Counting Frequency
Symbol
Min
Typ
Max
Unit
*
ns
AO
-
12
6.0
25
9.0
12
27
12
41
27
12
7
30
14
45
27
30
5.0
10
too
*EO
twC
ns
ns
ns
MHz
MC3232A
FIGURE 1 - AC WAVEFORMS with MCM6604 NORMAL CYCLE
Row
Enablo
Input
(AOA11)
O utput*
(0 0 -0 5 )
Refroih Enablo Low Logic Stato
FIGURE 2 - REFRESH CYCLE
FIGURE 4 - PROPAGATION DELAY versus LOAD CAPACITANCE
Row or Column Address to Output
OUTPUT CURRENT. I0L (mA>
FIGURE 3 - OUTPUT CURRENT versus

OUTPUT LOW VOLTAGE
LOAD CAPACITANCE. CL (pF)
MC3232A
PIN DEFINITIONS
A 6 -A 1 1 Inputs - Pins 8 ,4 ,6 ,1 7 ,1 9 ,2 1
Column address inputs.
CE Input Pin 13
Optional use, chip enable control pin. Left open, an
internal 50 kJ2 pullup resistor keeps this pin high and the
MC3232A is a functional replacement for the Intel 3232
(without detect zero function). As an active input, when
pulled low, all 3232A outputs go three-state. Regardless
of Pin 13 (CE) condition, when power (V q c ) '* removed,
all 3232A outputs go three-state. In addition, the refresh
address counter is reset to all 1s so that upon return of
supply power, control of refresh addressing can be returned
to the MC3232A (by pulling Pin 13 high) at a known
address (i.e., all 1s). This option is available tested by
consulting factory.
0 0 - 0 5 Outputs - Pins 9 ,1 1 ,1 0 ,1 6 ,1 5 ,1 4
Address outputs to memories. Inverted with respect
to address inputs.
Row Enable Input Pin 23

High input selects row, low input selects column
addresses of the driven memories.
Count Input Pin 1

Active low input increments internal 6-bit counter
by one for each count pulse in.
Refresh Enable Input Pin 2
Active high input which determines whether the
MC3232A is in refresh mode (H) or address enable (L).
AO-AS Inputs Pins 7 ,3 ,5 ,1 8 ,2 0 ,2 2
Row address inputs.
G n d -P in 12
Power supply ground.
V c c Pin 24
+5 V power supply input. Due to high capacitance
drive capability, a 0.1 fiF capacitor should be used to
ground along with careful V c c and Gnd Bus layout.
GENERAL 4K DYNAMIC RAM

SIMPLIFIED BLOCK DIAGRAM
MC3232A
TYPICAL APPLICATION
16K X 8-BIT MEMORY SYSTEM FOR M6800 MPU
Note:
; Numbort In parenthetlt Indlcato

port typot or vafuet fo r 16K'x t RAM*
Power-On Rctot
C ryitsl
(4 x MPU f 0)
X I ; X2
P - OR
MPU
Syttem
Clock
MC6875
I
I
R if
MC
Req
MPU
MC6800
02
Deta
But
Ref
Control
Grant
But
Address
But
Mem
Clk
2k
&
MC
Refresh
Enable
t1
A ddrett
M ultiplex
and
Rafreth
Countor
MC3232A
(MC3242A)
t2
Oelay
Circuit
t3
Memory Control
and Timing
MC3480
Row
Enable
Data
Buffer
MC6880A
t4
tS
\
32 kHz
(64 kHz)
O tcllletor
Ref C lk
RAS1 RASJ
RAS3 RAS4
CAS
R/W
(OO - 061
Address
Bus
Memory
Array
4K x 8
MCM4027
(16K x 8 )
(MCM4116)
11
4K X 8
(16K x 8 )
Data
But
IF
4K X 8
(16K x 8 )
4K X 8
(16K x 8 )
MC3242A
MOTOROLA
MEMORY ADDRESS
M ULTIPLEXER
AND REFRESH
ADDRESS COUNTER
MEMORY ADDRESS MULTIPLEXER

FOR 16K RAMS
The M otorola M C 3242A is an address m u ltip lexe r and refresh
counter fo r 16-pin 16K dynam ic RAMs that require a 128-cycle
SCHO TTKY
refresh. It m ultiplexes fourteen system address bits to the seven
S IL IC O N M O N O L IT H IC
address pins o f the m em ory device. The M C3242A also contains

a 7-bit refresh counter that is clocked externally to generate the
128 sequential addresses required fo r refresh. The high performance
o f the M C 3242A w ill enhance the high speed o f the N-channel
RAMs such as the M C M 41 16.
IN T E G R A T E D C IR C U ITS
L S U F F IX
R A M IC P A C K A G E
CASE 733
Sim plifies 16-Pin 16K Dynam ic M emory Design

Reduces Package C ount
7-Bit Binary Counter fo r 128 Refresh Address
M u ltip lexin g : Row Address/Column Address/Refresh Address

High In p u t Impedance fo r M inim um Loading o f Bus:
IF = 0.25 m A Max
S ch o ttky T T L fo r High Performance Address Input

to O u tp u t Delay
P S U F F IX
P L A S T IC P A C K A G E
CASE 710
tAC) = 25 ns @ C|_ = 250 pF

Second Source to Intel 3242
(Detect Zero Function N ot Included and A d d itio n al
Chip Enable Feature Added at Pin 15)
C ount [ T
H ]vcc
Ref En [ T
~27~] A 6
Row E n ! 3
N.C. [ T
LOGIC DIAG RAM
T o ta l
Address
Linos
A1 [ T
~24~| A 1 2
A8 [fF
A2 [ T
j2 3 | A 4
A9 [ T
~2?] A 3
~22~] A1 1
AO [ T
20| A 1 0
A7 Qo
00 [77
02 Q7
TF] 0 6
01 [7T
~ti] os
G nd [77
Note:
2 6 ]A 1 3
25] A 5
T s] 0 3
77] 04
T s ] CE*
AO Through A6 Are Row Addresses

A7 Through A 13 Are Column Addresses
See Pin D e fin itio n s
TRUTH TABLE AN D D EFINITIO NS

Refresh
Row
Output
Enable
Enable
H
X
Refresh Address
(From Internal Counter)
L
H
Row Address
(AO through A6)
L
L
Column Address
(A7 through A13)
Refresh
Enable
C o u n t Advances Inte rn al Rofresh C ounter
Seo Pin D e fin itio n s
4-16
MC3242A
ABSOLUTE M AXIM UM RATINGS (Ta 25C unless otherwise noted.)

Rating
Input Voltage
Output Voltage
Symbol
Value
vcc
-0 .5 to +7.0
-0.5 t o +7.0
V|
Vo
o
Output Current
Storage Temperature
Ceramic Package
Plastic Package
V
mA
-0 .5 to +7.0
100
ta
0 to +75
Tstg
-6 5 to +150
"Absolute Maximum Ratings" are those

values beyond which the safety of the device
cannot be guaranteed. This is a stress rating
only 8nd functional operation of the device
at these or any other conditions above those
indicated in the operational sections of this
specification is not implied. Exposure to
absolute maximum ratings for extended
periods may affect reliability.
Unit
V
V
C
C
C
Tj
+175
+150
ELECTRICAL CHARACTERISTICS (Unless otherwise noted, Min/Max values apply with 4.5 V < Vcc ^ 5.5 V, 0C < T a < 75C;
typical values apply with Vcc c 5.0 V. T A = 25C.)
-0.25
Unit
mA
10
iA
0.8
2.0
0.25
0.4
V
V
3.0
4.0
V|K
- 0.8
-1.5
ice
95
125
mA
Symbol
Min
Input Current, Low Logic State

(V||_ * 0.45 V)
IlL
Input Current, High Logic State

(V |H 5.5 V)
Input Voltage, Low Logic State
l|H
V|L
Input Voltage, High Logic State
V|H
Output Voltage, Low Logic State

0OL 5.0 mA)
Output Voltage, High Logic State
IlOH -1 .0 mA)
Input Clamp Voltage
(l|K -12m A )
(Vcc 5.5 V)
V0 L
VOH
Characteristic
Typ
-0.04
Max
SWITCHING CHARACTERISTICS (Unless otherwise noted, Min/Max values apply with 4.5 V < V c c 4 5.5 V, 0C < T a < 75C;
typical values apply with Vcc 5.0 V, T a = 25C.)
Characteristic
Address Input to Output
(Load 1 TTL, C l = 250 pF)
(Load = 1 TTL. Cl - 15 pF, V c c - 5.0 V . T A = 25C)
Row Enable to Output
(Load - 1 TTL. Cl ** 250 pF)
(Load 1 TTL. Cl = 15 pF. V c c = 5.0 V . TA = 25C)
Symbol
Min
Typ
Max
12
6.0
25
9.0
12
27
12
41
27
12
7
30
14
45
27
30
5.0
10
ns
*AO
to o
Refresh Enable to Output

(Load - 1 TTL. Cl = 250 pF)
(Load = 1 TTL. C l = 15 pF. V p c 5.0 V , TA 25C)
EO
Count Pulse Width

Counting Frequency
WC
C
Unit
ns
ns
ns
MHz
MC3242A
FIGURE 1 - AC WAVEFORMS WITH MCM4116 NORMAL CYCLE
Row
Enable
Input
(A 0 -A 1 4 )
Outputs
(0 0 -0 6 )
Refresh Enable Low Logic State
FIGURE 2 - REFRESH CYCLE
FIGURE 4 - PROPAGATION DELAY versus LOAD CAPACITANCE
Row or Column Address to Output
OUTPUT CURRENT. I0L <mA)
FIGURE 3 - OUTPUT CURRENT versus

OUTPUT LOW VOLTAGE
LOAD CAPACITANCE. CL (pF)
4-18
MC3242A
PIN DEFINITIONS
CE Input Pin 15
Optional use, chip enable control pin. Left open, an
internal 50 kft pullup resistor keeps this pin high and the
MC3242A is a functional replacement for the Intel 3242
(without detect zero function). As an active input, when
pulled low, all 3242A outputs go three-state. Regardless
of Pin 15 (CE) condition, when power ( V c c l ,s removed,
all 3242A outputs go:three-state. In addition, the refresh
address counter is reset to all Is so that upon return of
supply power, control of refresh addressing can be returned
to the MC3242A (by pulling Pin 15 high) at a known
address (i.e., all Is). This option is available tested by
consulting factory.
Count Input Pin 1

Active low input increments internal 6-bit counter
by one for each count pulse in.
Refresh Enable Input Pin 2
Active high input which determines whether the
MC3242A is in refresh mode (H) or address enable (L).
A 0 -A 6 Inputs - Pins 9 .5 ,7 ,2 1 ,2 3 ,2 7
Row address inputs.
A 7 -A 1 3 Inputs - Pins 1 0 ,6 ,8 ,2 0 ,2 2 ,2 4 ,2 6
Column address inputs.
0 0 - 0 6 Outputs - Pins 1 1 ,1 2 ,1 3 ,1 8 ,1 7 ,1 6 ,1 9
Address outputs to memories. Inverted with respect
to address inputs.
V c c " Pin 28
+5 V power supply input. Due to high capacitance
drive capability, a 0.1 (iF capacitor should be used to
ground along with careful v c and Gnd Bus layout.
Gnd - Pin 14
Power supply ground.
GENERAL 16K D Y NA M IC RAM

SIM PLIFIED BLOCK DIAG R A M
4-19
MC3242A
TYPICAL APPLICATION
Note:
Numbers In parenthesis indlceto

part typos or values fo r 16K x 1 R A M i
Power-On Reset
] _____ [
I .
P - OR
R
01
Crystal
(4 * MPU f 0 )
MPU
System
Clock
MC6875
I
I
MC
Mem
Ref
Grant
R ef
Req
MPU
MC6800
02
Data
Bus
Control
Bui
Address
But
(Plk
A 0 -A 1 1
(AO - A13)
\ 7
MC
Refrosh
Enable
tl
Address
M ultiplex
and
Refresh
Counter
MC3232A
(MC3242A)
t2
Delay
C ircuit
t3
Memory Control
and Timing
MC3480
Row
Enable
Oata
Buffer
MC6880A
t4
7 * \
t5
32 kHz
(64 kHz)
Oscillator
Re< C lk
RAS1 RAS2
RAS3 RAS4
CAS
R/W
Address
Bus
Memory
Array
4Kx8
MCM4027
(16K X 8 )
(MCM4116)
u
4K x 8
(16K x 8)
f H - it
Data
Bus
11
4K x 8
(16K x 8)
4K x 8
(16K x 8)
{1 1 3 1
4-20
MOTOROLA
MC3245
GATE-CONTROLLED
FOUR-CHANNEL
MOS CLOCK DRIVERS
QUAD TTL TO MOS DRIVER
This high-speed driver is intended as a clock (high-level)

driver for 22-pin and 18-pin dynamic NMOS RAMs and CCD
memories. It is designed to operate on nominal +5 V and
+12 V power supplies.
The channel control logic is organized so that all four
drivers may be deactivated for STANDBY operation, or single
driver may be activated for READ/WRITE operation or all
four drivers may be activated for REFRESH operation.
Control Logic Optimized for Use in MOS
RAM Systems
Output Voltages Compatible with Many Popular
MOS RAMs
TTL and DTL Compatible Inputs
High-Speed Switching
Interchangeable with Intel 3245
L SU FFIX
C E R A M IC P A C K A G E
CASE 6 20
P SU FFIX
CASE 648
PIN CONNECTIONS
TYPIC AL APPLICATIO N W ITH 4K NMOS RAM IN TTL SYSTEM
Vddi Ll
O u tp u t A 2^
Channel H T
Select A
Enable 1
Refresh r ^ r
Solect '
Channel |"g~
Select B
O u tp u t B
G nd [IT
TY PIC AL APPLICATIO N W ITH '7001 RAM AN D T T L SYSTEMS
TR UTH TA BLE
In p u ts
Address
C o n tro l
C hannel
Select
R efresh
Select
O u tp u t
Enable 1 En ab le 2 En ab le 3
I
H
1
1
L
L
1
1
1
H
L
1
I
I
i
H
1
L
L
L
L
L
H
H
M
1
1
l
L
L
H = H ig h L o gic State
L - L o w L o gic S tate
I Irre le va n t
S elects
4-21
1
I
H
1
L
L
MC3245
M A XIM U M RATINGS (T a 25C unlest otherwise noted.)

Rating
Symbol
Value
VCc
-0.8 to +7.0
Vdc
VpD
-0.5 to +14
Vdc
Output Voltage
V0
Input Voltage
Operating Ambient Temperature Range
ta
-I.O to V p o +1.0
T stn
Tj
Vdc
- 1,0 to Vqd
V|
Unit
Vdc
C
. 0 to +7B
-65 to +150
C
C
Ceramic Package
Plastic Package
175
.150

Characteristic
Symbol

Max
VCC
V dd
Min
4.75
1M
Typ
5.0
5.25
12
12.6
Ta
75
Unit
Vdc
Vdc
C
ELECTRICAL CHARACTERISTICS (Unleu otherwise noted, these specifications apply over recommended power supply end temperatore conditions. Typical values measured at T a
Characteristic
Symbol
V
VOH
(V |L " 0.8 V, I o h ~10 mA)
Output Clamp Voltage High Logic State
VOHC
(lOH 5*0 mA, V |L 0 V I
V0 L
(V|H 2*0 V, I o l " BjOmAl
Output Clamp Voltage - Low Logic State
VOLC
(V|H - 6.0 V. I o l -6.0 mA)
Input Voltage High Logic State
V |H
Input Voltage Low Logic State

Input Clomp Voltage
(IIK - -5 .0 mA)
Input Current - High Logic State
(V| - 5.0 V)
Channel Select Inputs
Refresh Select and Enable Inputs
ViL
V IK
Input Current Low Logic State

(V|L " 0 ^ 5 V) '
Refresh Select and Enable Inputs
<IL
2SC.)
Min
Typ
Max
o o - 0i
Unit
Vdc
V DD + 1-0
Vdc
0.45
Vdc
Vdc
Vdc
- 1 J0
2.0
0.8
- 1.0
Vdc
Vdc
jiA
l|H
'
10
40
mA
Power Supply Current Output High Logic State

(VCc 5.26 V, V |L - 0 V. I0 H 0 mA. V DD 12.6 V)
Power Supply Curtent Output Low Logic State
(VCC " 5.26, V |H - 5.0 V , I q l - 0 mA, V DD - 1 2 .8 V)
>CCH
d d h
CCL
DDL
4-22
23
19
29
12
-0.25
- 1 j0
30
26
mA
39
15
mA
MC3245
SWITCHING CHARACTERISTICS (Unless otherwise noted, these specifications epply over recommended power supply end temperature conditions. Typical values measured at +25C.)
Characteristic
Symbol
Min (1)
Delay Time
Output High to Low Level
Output Low to High Level
Transition Time
Typ (2)
Max (3)
(Rs " O n )
(Rs 0 ( l l
tOHL
tDLH
3.0
5.0
7.0
11
(Rs " 20 n )
(Rs 20 n )
*THL
TLH
5.0
10
17
17
25
25
(Rs 0 1 1 l
(Rs O n )
(Rs 20 n )
tpHL
PLH1
PLH2
18
27
32
32
38
Unit
ns
ns
ns
20
(1) Cl 150 pF
(2) C|_ " 200 pF
(3) C t-2 5 0 p F
CAPACITANCE* (Unless otherwise specified, Ta - +2BC. f 1.0 MHz. V| - 2.0 V. and V cc 0 V->
Characteristic
Input Capacitance
Input Capacitance
Refresh or Enable Inputs
Symbol
Min
Unit
Typ
5.0
Max
C|(CS)
8.0
PF
Cin(E)
8.0
12
PF
Periodically sampled, but not 100% tested.

FIGURE 1 - SWITCHING TEST WAVEFORMS
Input Pulso Characteristics

PRR - 1 MHz
PW 500 n$
FIGURE 2 - SWITCHING TEST CIRCUIT

To Scopo
(Input)
T o Scopo
(O utput)
Probe Capacitance
MC3459
MOTOROLA
Specifications and Applications

Inform ation
QUAD NMOS ADDRESS
LINE DRIVER
The MC3459 is designed fo r high-speed driving of the highly

capacitive Address select inputs fo r NMOS Memories. It is also useful
in numerous applications requiring a high-current M T T L N AN D
gate. It is pin-com patible w ith the popular MC7400 Quad N AN D gate.
L SU FFIX
Fast Propagation Delay Time

20 ns Typical w ith 360 pF Load
CASE 632
O u tp u t Voltages C om patible w ith NMOS Memories
Inputs C om patible in M T T L and M D TL Logic Families
O u tp u t Loading Factor 50
T O 116
|j
V
REPRESENTATIVE CIRC UIT SCHEMATIC
(1/4 of Circuit Shown)
1a
L l
In p u t
2A
Ll
O u tp u t
A
I u
I
In p u t
ID
^1
In p u t I u
1B L l
vcc
F3
InpUt | y,
2B
O u tp u t
B
<
In p u t
QUAD NMOS MEMORY ADDRESS DRIVER
I]
3
3
I---I w
Ll
Gnd | ^
In p u t
2D
O u tp u t
D
In p u t
1C
In p u t
2C
O u tp u t
C
P SUFFIX
CASE 6 46
TYPICAL OPERATION
In p u t
2.5
V /d iv
2.5
V /d iv
O u tp u t
VCC = 5 0 v
T a - 2 5 C
4-24
50
n i/ d iv
Ci * 3 60 pF
RS - 0 n
MC3459
MAXIM UM RATINGS (TA 25C unless otherwise noted.)

Rating
Input Voltage
Power Dissipation (Package Limitation
Ceramic Package @ TA = 25C
Derate above T A 25C
Symbol
Value
V cc
V)
8.5
5.5
PD
1000
6.6
1 /RflJA
Plastic Package @ T A = 25C

Derate above T A 25C
PD
1/RfljA
830
Ceramic Package @ T c = 25C

Derate above T q 25C
PD
1/RflJC
3.0
Plastic Package @ Tc 25C

PD
1/RJC

Ceramic Package
Plastic Package
Ta
Tj
T stg
6.6
20
1.8
Unit
Vdc
Vdc
mW
mW/C
mW
mW/C
Watts'
mW/C
Watts
14
mW/C
Oto 70
C
C
175
150
C
-65 to +150
ELECTRICAL CHARACTERISTICS (Unlessotherwise noted. 4.75 V < V CC < 5.25 V and 0 < TA < 70C)
Characteristic
Input Voltage - High Logic State
Input Current High Logic State
<VCC * 5.25 V .V |H = 2.4 V)
(VCC = 5.25 V. V |n = 5.5 V)
(V c c= 5.25 V .V | l = 0.4 V)
Unit
V
Min
Typ(1)
V|H
V|L
2.0
0.8
1IH1
80
2.0
/iA
mA
hL
-3.6
mA
V ie
-1.5
VOHI
VOH 2
3.2
2.4
v OC
|H2
Input Clamp Voltage

(tic -12 mA) |
(Vc c 4-75 v <V IL 0.8 V. Iq h - -6 4 0 #iA)
(Vcc = 4 75 V .V ,L = 0.8 V, l0 H -2-0 mA)
Output Clamp Voltage
(VCC= 5 .2 5 V .V |l = 0 V . I 0 C 5.0mA)
(Vcc " 4 75 V, V |H - 2.0 V, l0 L 6 40mA)
(VCc = 4 75 V, V |H = 2.0 V, l0 L 80 mA)
Power Supply Current Outputs High Logic State
(VCC =5.25 V .V |L = 0 V )
Power Supply Current Outputs Low Logic State
(VCC 5.25 V. V |H = 5.0 V)
Max
Symbol
v OL1
v OL2
'CCH
*CCL
5.8
6.75
0.3
0.7
12
18
mA
85
122
mA
V
V
SWITCHING CHARACTERISTICS (Unlessotherwise noted. VCc 5.0 V. TA 25C. CL = 3 60pF)

Typ
Max
Propagation Delay Time High to Low Logic State
tPHL
21
32
ns
Propagation Delay Time Low to High Logic State
TPLH
16
26
ns
Symbol
Characteristic
(1) Typical values measured at T A = 25C, Vcc = 5.0 V.
4-25
Min
Unit
VOH. OUTPUT VOLTAGE - HIGH IOTIC STATE (VOLTS)
FIGURE 4 - OUTPUT VOLTAGE - HIGH LOGIC STATE

mrsus OUTPUT CURRENT
(Exptndtd Scait)
4-26
V ol . OUTPUT VOLTAGE - LOW LOGIC STATE fmV)
PC. POWER CONSUMPTION (mW)

(TOTAL OF FOUR DRIVERS)
I( O
VOH. OUTPUT VOLTAGE - HIGH LOGIC STATE (VOLTS
FIGURE S - OUTPUT VOLTAGE - LOW LOGIC STATE

OUTPUT CURRENT
/
I
O
o<
o<
,o
UI
o
b*
it
8 <
5
3h
oS
S '
9 5
It* O
>
<
O<
g
0
MC3459
APPLICATIONS SUGGESTIONS
will be proportional to the ground impedance. The
impedance of the ground bus can be reduced by in
creasing its width. At least a 50 mil ground width is
recommended.
Some of the NMOS memories with TT L logic com
patible inputs do not {actually meet the T T L logic level
requirements in the input high state voltage (V jh ). There
are N-Channel MOS memories with a V | h minimum
ranging from 2.4 V to 4.0 V. The MC3459 can directly
interface with those N-Channel memories having a V |H
minimum of 3.0 V . The higher driver output levels can be
accomplished by adding a pull-up resistor to V c c or by
increasing the V c c voltage. There ar6 some N-Channel
MOS memories, such as the MCM7001, that have a supply
requirement of 7.5 V. The high maximum supply voltage
rating of the MC3459 can accommodate a 7.5 V V q c
supply without affecting its input TTL logic compatibility.
Figure 4 gives the typical V o h versus lOH characteristics
for both V c c = 5.0 V and VcC 7.5 V. An expanded
output characteristic curve of Figure 4 is illustrated in
Figure 5.
The MC3459 can be used in a variety of applications
including, high fan-out buffer (drives 50 standard TTL
loads) and low impedance transmission line driver.
A majority of the new N-Channel MOS memories have

TTL logic compatible inputs that exhibit extremely low
input current and capacitance (typically 5 pF to 10 pF).
However, in a typical memory system (Figure 6) where
some of the inputs such as Address lines have to be
common, the total parallel input capacitance can be over
300 pF. Standard TTL logic gates have insufficient current
drive capability to rapidly switch a high capacitive load; a
high speed buffer, such as the MC3459, is required.
A considerable amount of noise can be generated during
switching due to the high speed and high current drive
capability of the MC3459. The high capacitive discharge
current during the high "to low transition, plus current
spikes can result in a considerable amount of noise being
generated on the ground lead. Current spikes are due to
both the upper and lowerôutput drive transistors being
on for a short period of time' during switching. This causes
a very low impedance path between V c c an(* ground.
In order to minimize the effects of these currents, the
following layout rules should be followed:
1. The V q c supply pin of each package should be by
passed with a low inductance 0.01 pF capacitor. The'
0.01 ji F capacitor will sustain the high surge currents
required during switching.
2. There is a large amount of current out of the ground
node during switching the noise seen at this node
FIGURE 6 TYPICAL APPLICATION

16 K X N Mtmory Systsm Employing
MCM66054K RAMS
B it 2
Chip Enabl> 1
4N MCM660S RAMS
4-27
MC3461
MOTOROLA
DUAL NMOSMEMORY
SENSE AMPLIFIER
HIGH-SPEED NMOS/MECL SENSE AMPLIFIER
The MC3461 is a dual current sense am plifier w ith MECL 10,000
com patible co ntro l inputs and open em itte r com plem entary outputs.
The device is designed fo r use w ith M otorola MCM7001 or Intel
2105 NMOS 1K RAMs. A com m on latch in p u t retains inform a tio n
in the am plifier at the tim e o f latch closure. Separate channel o u t
put enables are provided to force the outputs to predetermined
states u n til a m plifier in fo rm a tio n exchange is desired.
When the latch in p u t goes to a logic " 0 " the o utputs are locked
in th e ir present state unless the o u tp u t enable is at, goes to, logic
" 1 " . In this event, the O u tp u t 1 and O u tp u t 2 remain at, o r go to,
logic " 0 " and logic " 1 " respectively.
L SU FFIX
CASE 620
Complete NMOS Sense A m p lifie r No External Components

Required
M inim um Propagation Delay
A m p lifie r Response 5.0 ns T yp
Enable Response - 2.5 ns T yp
Latch Response - 1.0 ns T yp
Power Supplies C om patible W ith M C M 7001/M EC L10.000 Systems
A m p lifie r In p u t Term ination Voltage Range from Gnd to V r e f
Su pply on MCM7001
PIN CONNECTIONS
O u tp u t
G nd.
H
[I
O u tp u t
Gl
2A
O u tp u ts A
d
Enablo
In p u t
2 A GE
In p u t
H
1A
Latch
In p u t U
V
(-5 .2 V ) H
O u tp u t
1A
APPLICATION W ITH MCM7001 MEMORY
__ A m p l. In p u t
10] T e rm in a tio n
(RT )
ee
j[]
V CC
'(7 .S V )
TR UTH TABLE
f o r la tch in p u t at lo g ic 1
In p u t
1(1) > -2 0 0
I (2) - 0 /JA
nA
1(1) - O /iA
I (2) > 2 0 0 VA
O u tp u t
Enablo
O u tp u t
1
O u tp u t
1
1
0
1
Negative C urre n ts D efinod as F lo w in g in to

Device Pin.
4-28
VCC
V ee
vT
Termination Voltage
Package Power Dissipation
Still Air
Derata above 25C
Transverse Air flow > 500 linear fpm
Derate above 25C
ELECTRICAL CHARACTERISTICS
ta
OTM
Ttmpmtun
0C
2SC
75C
6 3 -*
MC3461 Test Limits

Max
Min
mW
mW/C
mW
mW/C
inL
Vq h
Logic 0" Output Voltage
V|Hmax V|Lmin VjHAmin

-1.870
Max
V|Hma
mAdc
500
500
VlLAfTMX
Vcc
V ee
mAde
MAdC
6.12
6.12
uAdc
5 .11
5. 11
fjAdc
5.11
MAdc
5. 11
ViHAmin V|LAmsx
Vcc
9. 10
9. 10
9.10
9.10
9. 10
9.10
9.10
vee
1. 16
1. 16
1.16
1.16
1.16
1.16
9.10
Logic "V' Threshold Voltage
Vq ha
Logic 0 Threshold Voltage

Switching Timet (60Ohmload)
Propagation Oelay
TEST VOLTAGE/CURRENT APPLIED TO PINS LISTED BELOW:
7SC
Min
ice
Logic '*1** Output Voltage
0 to V cc
Oto 75
TEST VOLTAGE/CURRENT VALUE8
Under
Tert
Power Supply Drain Current
Unit
V
V
1000
6.7
2000
13.3
Pd
This device has been designed to meet the

dc specifications shown in the test table,
after thermal equilibrium has been esta
blished. The circuit is in a test socket or
mounted on a printed circuit board and
transverse air flow greater than 500 linear
fpm is maintained. Outputs are termin
ated through a 50-ohm resistor to -2.0
volts. Test procedures are shown for only
one sense amplifier. The other half is
tested in the same manner.
Value
8.5
-6.0
MC3461
M AXIMUM RATINGS (Unless otherwise noted, T A 25C)

Rating
Symbol
vOLA
Amplifier
Negative currents are defined as currents leaving the device.
-1.630
9.10
1.16
MC3461
FIGURE 1 - SWITCHING RESPONSE TEST CIRCUIT AND WAVEFORMS 9 2SC

(Other Section Tested Similarly)
VCc +7-B Vde
'D enotes equal lengths o f 50-ohm coaxial cabla. Wlra length should be < 1 /4 " fro m test p o in t to pin or BNC connector.
Amplifier Response Waveforms
Enable in put held at -1.69 Vdc

fo r A m p lifie r Response Tests.
Enable Response Waveforms
A m p lifie r Input held at + 0.6 Vdc

fo r Enable Response Tests.
MC3461
FIGURE 2 - 32K x 2 MEMORY BOARD (MECL SYSTEM)
1/2 MC3461
8 placet
Connaet to
Top Array (32K x 1)
Conn act to all M CM 7001'i
Connoct to
Bottom A rray (32K x 1)
1/3 MC10177,
12 Placat
AO
A1
A2
A3
A4
AS
AS
A7
AS
4-31
A9
0|n
D in
Board Enable A1 > ------ | e 0 QO
WEI (to top 38 devices)

WE2 (to Bottom 36 davlcot)
\
1/2 M C 3461.18 Place*
f
MCM7001, 72 Place*
l9t7OLAJ
MC3461
REPRESENTATIVE CIRCUIT SCHEMATIC

Simplifiod MC3461
MC3467
MOTOROLA
TRIPLE WIDEBAND PREAMPLIFIER

WITH ELECTRONIC GAIN CONTROL (EGC)
TRIPLE MAGNETIC TAPE

MEMORY PREAMPLIFIER
SILICON MONOLITHIC
INTEGRATED CIRCUIT
The MC3467 provides three independent preamplifiers with in

dividual electronic gain control in a single 18-pin package. Each pre
amplifier has differential inputs and outputs allowing operation in
completely balanced systems. The device is optimized for use in 9track magnetic tape memory systems where low noise and low dis
tortion are paramount objectives.
The electronic gain control allows each amplifier's gain to be set
anywhere from essentially zero to a maximum of approximately
100 V /V .
The MC3467 is intended to mate with the MC3468 read amplifier
to provide the entire magnetic tape read function.
Wide Bandwidth - 15 MHz (Typ)

Individual Electronic Gain Control
Differential Input/Output
TYPICAL APPLICATION
HIGH PERFORMANCE 9-TRACK OPEN REEL
TAPE SYSTEM
V I(EGC)
N R ZI/0
Select
P SUFFIX
L SUFFIX
PLASTIC PACKAGE
CERAMIC PACKAGE
MC3467
MAXIMUM RATINGS
(T A
2 5 C unless otherwise noted.)
Rating
Positive Supply Voltage
Negative Supply Voltage
Symbol
Value
Vcc
6.0
Unit
V
V EE
-9 .0
V I(EGC)
-5 .0 to Vcc
Input Differential Voltage
V|D
5.0
Input Common-Mode Voltage
V|C
5.0
Amplifier Output Short Circuit

Duration (to Ground)
*s
10
EGC Voltages (Pins 1,6 and 13)
Ta
0 to +70
Tstg
-6 5 to +150
Tj
+150
c
c
ELECTRICAL CHARACTERISTICS (Vcc 5-0 V, Vee 6.0 V, < ** 100 kHz, TA 0 to +70C unless otherwise noted.)
Characteristic
Power Supply Voltage Range
Operating EGC Voltage
Symbol
Min
Typ
Max
Unit
VCCR
4.75
-5 .5
5.0
- 6.0
5.25
-7 .0
VCC
V
V
V
veer
V KEGC)
Differential Voltage Gain (Balanced)

(VI(EGC) * i 25 mVp-p) (See Figure 1)
Av d
85
100
120
V /V
Differential Voltage Gain

<V I(EGC) VCC>
Av d
0.5
2.0
V /V
Maximum Input Differential Voltage

(Balanced) (TA 25C)
v IDR
0.2
VPP
Output Voltage Swing (Balanced) (Figure 1)

fej 200 mVp-p)
v OR
6.0
8.0
v pp
Input Common-Mode Range
V(CR
1.5
2.0
Differential Output Offset Voltage

(TA - 25C)
VoOD
500
mV
Common-Mode Output Offset Voltage

<TA = 25C)
VOOC
500
mV
Common Mode Rejection Ratio (Figure 2)

v K E G C )" .v C M " 1 0Vpp
(f *= 100 kHz)
(f = 1.0 MHz)
CMRR
Small-Signal Bandwidth (Figure 1)

(-3 .0 dB, eg = 1.0 mVp-p, TA 25C)
BW
dB
60
40
100
100
10
15
MHz
Input Bias Current
<IB
5.0
15
UA
Output Sink Current (Figure 5)
os
1.0
1.4
mA
Differential Noise Voltage Referred to Input (Figure 3)

<VI(EGC 0. Rs - 50 n . BW 10 Hz to 1.0 MHz, TA = 25C)
en
3.5
" V r MS
Positive Power Supply Current (Figure 4)
ice
30
40
mA
Negative Power Supply Current (Figure 4)
*EE
-3 0
-4 0
mA
12
25
Cj
2.0
pF
ro
30
Ohms
Input Resistance (TA 25C)

Input Capacitance
(TA 25C)
Output Resistance (Unbalanced)

(TA = 25C)
MC3467
FIGURE 1 - DIFFERENTIAL VOLTAGE GAIN.

BANDWIDTH AND OUTPUT VOLTAGE SWING
TEST CIRCUIT
(Channel A under test, other channels tested similarly)
FIGURE 2 - COMMON-MODE REJECTION RATIO

(Channel A under test, other amplifiers tested similarly)
5.0 V
18_
17
16
* v OD
CMRR - 20
13
V QD
_L -
10
1
-6.0 V
FIGURE 3 - DIFFERENTIAL NOISE VOLTAGE

REFERRED TO THE INPUT
FIGURE 4 - POWER SUPPLY CURRENT TEST CIRCUIT
VCc
Assume Uncorrolated N oito Sources

en (D ifferential N oito at Input) 0o v /i/lO O
FIGURE 6 - TOTAL HARMONIC DISTORTION

TEST CIRCUIT
FIGURE S'OUTPUT SINK CURRENT TEST CIRCUIT

+5.0 V
+2.0 v
S.O v
4-36
v OD
A V V,
100 V,
-5.0
< >
x>5
< o
V|, INPUT VOLTAGE (mVp.p)
-6.5
-7.0
FIGURE 9 - NORMALIZED VOLTAGE GAIN

vwsus AMBIENT TEMPERATURE
-6.0
VEE. NEGATIVE POWER SUPPLY VOLTAGE (Vdc>
-5.5
< 5
H >
\
-7.5
io
O CO
3-
S c
s
m
O
>
I, FBEQUENCY (MHi)
SO
m
,1
s
I
I
O
10
30
40
50
Ta . AMBIENT TEMPERATURE (C)
20
FIGURE 10 - NORMALIZED POSITIVE POWER SUPPLY

CURRENT vwsu* POSITIVE POWER SUPPLY VOLTAGE
n m
o
c 2;
3 . co
Ay (nwm). VOLTAGE GAIN NORMALIZED ftJB)
7
x
o
~
Is
o
a h
m3
v\
o<2
bo
<
z>
| s
X
n
(D*
3
3 '
M
sz <
I
\
MC3467
THO, TOTAL HARMONIC DISTORTION (X)
MC3467
FIGURE 13 - DIFFERENTIAL VOLTAGE GAIN versus

ELECTRONIC GAIN CONTROL VOLTAGE (V|(EQC))
FIGURE 14 - COMMON-MODE REJECTION RATIO

(CMRR) versus FREQUENCY
f. FREQUENCY (MHz)
FIGURE 15 - PHASE SHIFT versus FREQUENCY
FIGURE 16 - TYPICAL EGC INPUT CURRENT versus

EGC INPUT VOLTAGE
1.0
f, FREQUENCY (MHz)
2.0
3.0
4.0
V'(EGC). EGC INPUT VOLTAGE (Vdc)

1/3 MC3467
VCc
O utput*
T L Q1
11
V EE O
o ia i
Q13
4-38
^ |q 1 7
r 18
( L
MOTOROLA

Inform ation
MAGNETIC TAPE
MEMORY READ AMPLIFIER
LSI MAGNETIC MEMORY READ SUBSYSTEM

L SU FFIX
C A S E 726
The MC3468 READ Subsystem when used w ith the MC3467

trip le prea m p lifie r provides the interface between magnetic tape
heads and digital logic. Th is system is w ell suited fo r open-reel and
cartridge magnetic tape systems. The M C3468 perform s peak detec
tio n , and threshold detection fu n ctio ns as required fo r N R Z I, PhaseEncoded o r Group-Encoded recording formats. The device consists
o f: 1) In p u t M u ltip le x fu n c tio n , 2) Gain Stage w ith Electronic Gain
C ontrol (EGC), 3) A ctive D iffe re n tia tio n A m p lifie r, 4) Zero Crossing
D etector (ZC D ), 5) Threshold D etector A m p lifie r w ith M ultiplexed
In p u ts and 6) Threshold D etector.
Com plete R EAD F u n ctio n in One LSI Device
T w o Pair o f D iffe re n tia l Inputs A llo w Logically C ontrolled Selec

tio n o f In p u t F ilte r o r Tape Head C onfiguration
Low Recovered E rro r Rate
In p u t/O u tp u ts are Low Power S ch o ttky T T L C om patible
P SU FFIX
CASE 701 01
MC3468 TYPICAL APPLICATION AN D WAVEFORMS
Channel A In p u t
0.5 V p-p, 160 kH z
Ze ro Crossing
D e tecto r O u tp u t
P re a m p lifie r
T h ro sho ld D e tecto r
O u tp u t
4-39
MC3468
MAXIMUM RATINGS (TA - 25C unless otherwise noted)

Symbol
V ee
+7.0
- 8.0
< <
V|(EGC)
V|(T>
-5 .0 to +7.0
+1.0 to -3 .5
V
V
v O(ZCD)
V|(CS)
+7.0
+7.0 to -2 .0
< <
Unit
v O(TD)
+7.0
V|D(T)
V|Q
5l 5)
Differential Input Voltage

Threthold Amplifier
Gain Amplifier
Value
V
V
Vcc
o b
Rating
Power Supply Voltage*
Po*itive Supply Voltage
Pin Voltages
EGC Voltage (Pin 5)
Threshold Voltage
(Pin 16)
ZCD Output (Pin 15)
Channel Select A/B
Input (Pin 1)
Threthold Output TD
(Pin 17)
MAXIMUM RATINGS (continued)

Rating
Common Mode Input
Voltage
Threshold Amplifier
Gain Amplifier
Symbol
Value
Unit
V|C(T)
V |C
5.0
5.0
V
V
*S
10
ta
0 to +70
Tstg
- 6 5 to +150
150
c
c
Amplifier Output Short

Circuit Duration
(Ground Pin 11)
Operating Ambient
Temperature Range
Tj
ELECTRICAL CHARACTERISTICS (Vc c - 5.0 V. V EE = - 3.0 V, TA = 0 to +70C unless otherwise noted)

Characteristic
Figure
Symbol
Min
Typ
Max
Unit
5.25
-7 .0
45
V
V
TOTAL DEVICE
Power Supply Voltage Range @ T a * 25C
VCCR
V eer
4.75
-5 .5
5.0
- 6.0
35
30
Positive Supply Current (Vcc " +5.25 V)
7-13
Ice
Negative Supply Current ( V EE -7 .0 V)

Channel Select Input Voltage Low Logic State
7-13
>EE
V|L(CS)
V|H(CS)
2.0
Channel Select Input Voltage High Logic State

Channel Select Input Current Low Logic State
V IL(CS) "
Vcc 5.25 V)
Channel Select Input Current High Logic State
<V|H(CS) V CC 5.25 V)
'IL(CS)
'lH(CS)
45
0.8
mA
mA
V
V
-10 0
MA
10
J*A
GAIN AMPLIFIER SECTION

Voltage Gain (Unbalanced @ Max Gain)
(e; - 100 mVp i), f 1.0 kHz
1 . 14
AV
6.5
7.5
8.5
v /v
Voltage Gain (Unbalanced @ Min Gain)*

<V|(EGC) VCC. i " 800 mVp^,)
Operating EGC Current (VEq c 0 to +5.25 V)
Maximum Differential Input Voltage
(TA 25C)
Common Mode Rejection Ratio
<V|(EGC) 0. V CM 1-0 Vpp, f * 100 kHz.
T A -2 5 C )
Bandwidth
(3.0 dB, T a 25C)
Input Resistance
Channel Isolation
(f - 100 kHz, e) 800 mVp^j)
1.14
AVS
0.05
0.1
v /v
1.15
11(EGC)
6.0
mA
V|DR
0.8
Vpp
CMRR
40
80
BW
15
30
40
60
60
Input Bias Current

Input Common Mode Voltage Range
Output Resistance (Pin 11)
(TA 25C)
Output Sink Current (Pin 11)
Output Voltage Swing (Pin 11)
(f 1.0 kHz. ej - 800 mVp<l)
2,16
4
Output Offset Voltage

(Ta " 25C)
4-40
dB
MHz
k
dB
1IB
V|CR
5.0
15
1.0
rO
15
15
30
lo s v OR
1.2
2.1
2.25
3.0
mA
Vpp
V oo
400
mV
#A
V
Ohms
MC3468
ELECTRICAL CHARACTERISTICS (V^c 5.0 V, Vgg 6.0 V, TA = 0 to +70C unless otherwise noted) (Continued)
Characteristic
Figure
Symbol
Min
Typ
Max
Unit
1.0
3.0
ACTIVE DIFFERENTIATOR SECTION

Timing Distortion
(1 1.0 mA, A 1.5 Vpp, f - 100 kHz, TA = 25C)
Zero Cross Detector High Level Output Current
(V0 H * 5-5 V)
Zero Cross Detector - Low Level Output
(lOL 8.0 mA)
Differentiator Output Sink Current
(Pins 12 and 13)
Differentiator Output Resistance (Unbalanced)
(TA - 25C)
12
8
'OH (ZCD)
150
JiA
v OL(ZCD)
0.50
'O (D )-
1.0
1.4
ro(D)
20
4.25
5.0
5.75
400
V/V
mVpp
1.4
Vpp
- 2.0
- 1.0
-2 .5
MHz
mA
Ohms
THRESHOLD AMPLIFIER SECTION

Differential Voltage Gain (e, = 200 mV)
Maximum Differential Input Voltage Without
Distortion (TA 25C)
Maximum Differential Input Voltage Before
Timing Shift (TA = 25C)
Maximum Threshold Voltage (Linear Operation)
Av d
V IDR(T)
V IDR(T>
V IR(T)
Threshold Voltage Required to Disable Threshold

Comparators (V fo > 2.7 V, T A = 25C)
V I(T)
Bandwidth
(-3 .0 dB, TA = 25C)
Input Resistance
Threshold Amplifier Bias Current '
Channel Isolation Ratio

(f - 100 kHz)
Threshold Detector Output Voltage - Low Logic State

(I q l = 8.0 mA, Pin 17)
Threshold Detector Output Current High Logic State
(V o h 5-5 V. Pin 17)
10
11
BW
ri(INT)
25
50
5.0
15
k
nA
40
60
dB
v OL(T)
0.50
'OL(T)
"
150
JiA
t h c
50
VA
'lB(T)
Threshold Voltage Input Current

(Pin 16)
15
25
DESCRIPTION OF FUNCTION
Threshold Amplifier and Detector The gain stage out
put is ac coupled or differentiated into the Threshold
Amplifier multiplexer. This allows logic-controlled (TTL
compatible) selection of either of a pair of single-ended
to differential gain stages. Thus, the possibility of select
ing between a differentiated or straight capacitive
coupled signal for thresholding. The select line is the
same as for the Gain Stage multiplexing. The unbalanced
gain of the threshold amplifier is 5. An inverting input is
available for balancing the input signal to minimize the
effects of offset current. The differential outputs of the
threshold amplifier are compared to an external thresh
old in the threshold comparators. An output signal is
provided whenever the signal exceeds the threshold
setting in the positive or negative direction. The output
is open collector Schottky TTL.
The versatility of the MC3468 facilitates the design
of dual mode (NRZI/PE, Group/PE) tape drives with the
ability of dynamically switch gain, active differentiator
components, and thresholds for different recording
speeds or interchanged tapes.
Input Multiplex Input multiplexing allows logiccontrolled (TTL compatible) selection of either of a pair
of differential gain stages. Two separate tracks or one
track processed through different filter networks for dif
ferent recording formats can be selected (e.g.. Phase Encoded/NRZI, Group-Coded/PE).
Gain Stage The gain stage is controlled by Electronic
Gain Control (EGC) and differential outputs are pro
vided for the active differentiator and a single output is
available for the threshold function. The EGC range is
from essentially zero to 7.5 (unbalanced).
Active Differentiation Active differentiation requires
minimum external passive component count. The pro
cedure for selecting component values insures linear
operation and optimum zero-crossing detector per
formance for excellent noise rejection.
Zero Crossing Detector (ZCD) The zero-crossing de
tector generates an output transition corresponding to
the peak of the incoming signal to the MC3468. Careful
attention has been paid to avoid timing distortion be
tween the outputs of the active differentiator and the
inputs of the zero crossing comparator.The output is
open collector Schottky TTL.
Note: For proper operation a dc path must be provided

for all inputs of all amplifiers.
4-41
MC3468
MC3468 BLOCK SCHEMATIC
V|(QQC)
5 O - W *>
Threshold
A m plifier 2 ^
Input A
Inverting
Input
Threshold 4 O
A m plifier
Input B
MC3468
FIGURE 2 - CHANNEL ISOLATION

RATIO
(B Inputs Shown)
FIGURE 1 - VOLTAGE GAIN.

BANDWIDTH AND OUTPUT
VOLTAGE SWING
(A Input Shown)
2.0 V
5.0 V
FIGURE 3 - COMMON MODE

REJECTION RATIO (CMRR)
FIGURE 4 - INPUT BIAS CURRENT

TEST CIRCUIT
FIGURE 6 - CHANNEL SELECT

INPUT CURRENT TEST CIRCUIT
FIGURE 5 - AMPLIFIER OUTPUT

AND DIFFERENTIATOR OUTPUT
SINK CURRENT TEST CIRCUIT
+5.0 V
4-43
MC3468
FIGURE 7 - POSITIVE AND

NEGATIVE SUPPLY CURRENT
TEST CIRCUIT
FIGURE 8 - ZERO CROSS DETECTOR

OUTPUT CURRENT HIGH LOGIC
STATE TEST CIRCUIT
FIGURE 9 - ZERO CROSSING

DETECTOR OUTPUT VOLTAGE
LOW LOGIC STATE TEST CIRCUIT
VCC
FIGURE 10 - THRESHOLD DETEC

TOR OUTPUT VOLTAGE - LOW
LOGIC STATE TEST CIRCUIT
FIGURE 11 - THRESHOLD DETEC

TOR OUTPUT CURRENT - HIGH
LOGIC STATE TEST CIRCUIT
5.0 V
FIGURE 12 - TIMING DISTORTION T a 25C
4*44
5.5 V
MC3468
TYPICAL PERFORMANCE CURVES

FIGURE 13 - NEGATIVE POWER SUPPLY
CURRENT versus NEGATIVE POWER SUPPLY
VOLTAGE

versus EGC INPUT VOLTAGE
FIGURE IS - ELECTRONIC GAIN CONTROL

INPUT CURRENT versus VOLTAGE
FIGURE 16 - CHANNEL ISOLATION RATIO

versus FREQUENCY
f. FREQUENCY (Hi)
FIGURE 17 - GAIN AND PHASE versus

FREQUENCY FROM Pins 6,7 to Pins 12,13
I. FREQUENCY (Hi)
MC3468
SYSTEM PARAMETERS
The following system parameters are characteristic of
not only the device but external component values and
circuit layout. Detailed test circuits and measured
parameters are provided only as a guide to expected sys

tem performance.' These parameters are not readily
measureable on a production volume basis.
FIGURE 18 - TEST CIRCUIT FOR MEASURING PROPAGATION DELAYS

From Gain Stage Input to Zero Crossing Detector Output
(Pin 6 to Pin 16) (Subtract 8 n t from measurement fo r probo and coble delays)
V EE
2 - 1 0 (IF
Capacitances aro solid Tantalums
_
0.8 Vpp
r \ j 600 kHz
iO
( > 1
O i
i. m
JL
JL
~ so
*r
Wavetek
Model 184 "
Function
Generator
MC3468
?
-
Note: Sym m etry Is adjusted 9 50 kHz and 60 m Vpp

Adjust 100 k por Figure 21, Part II
Typical Meesurod Values: tPLH(ZCD) 40 ns

tP H U ZC D ) 60 " *
FIGURE 19 - TEST SETUP FOR MEASURING PHASE JITTER
V EE
Noto: Use of a sorias inductor In-tha d ifferentiator notwork

significantly improved phase jitte r performance.
210 UF.
TE K 476
Scope
Capacitances are solid Tantalums
121
^ \ _ t 500 kHz
-O
Wavetek
Model 164
Function
Genorator
~ 60S
X?
ZCD O utput
Pin 15
1.6
Typical Measured Valuos:
0| - 0.6 Vp-p Pins 12, 13 - 0.5%
26 mVp-p 9 Pins 12,13 - 6.0 %
Note: The Jitter w indow , t, is defined as the

3 a points on o Gussion curve.
4-46
MC3468
FIGURE 20 - TEST SETUP FOR THRESHOLD AMPLIFIER DELAY AND

THRESHOLD COMPARATOR EQUIVALENT OFFSET MEASUREMENTS
+ 100 mV
Input
Pin 2
100 kHz
Typical Measured Values: *PLH(TO) 43 n*

*PH L(TD ) 43 n*
v IO (T 5 ) 38 mV
tPHL(TO)
100 m V
Threshold
Detoctor
O utpu t
Pin 17
Notes:
1. For Delay measurements, V !> fixed at 250 m V;

fo r equivalent comparator offsot voltage measurements,
V is adjustod until Pin 17 goos low. The voltage, V , it
the equivalent offset. V | o ( t d ).
2. Somo compensation is possible using a reiistor from
Pin 3 to ground.
MC3468
FIGURE 21 - TEST SETUP FOR GAIN AND PHASE versus FREQUENCY (5 kHz to 1 MHz I
FROM INPUT TO DIFFERENTIATOR (Pin 6.7 to Pin 12.13)
Actual Test Measurements (Calibrate Instrumentation for Phase Compensation)
DESIGN SUGGESTIONS
Gain Stage Bias Current
II
One must consider supplying 15 pA of bias cur

rent to the Gain Stage when designing a filter net
work. A good design value for the equivalent
resistance from each input leg to ground is 5 kS2.
Adjusting Peak Shift to Zero (See Figure 22)

The worst peak shift observed on the ZCO output
occurs for the smallest slew rate provided by the
Active Differentiator at the ZCD inputs. In Turn,
the Active Differentiator produces the smallest
slew rate when the gain-bandwidth product ap
plied at its inputs is the smallest. Current source,
resistors, and diode imbalances will exhibit the
maximum peak shift under this condition. Using
the resistor network shown, these imbalances are
adjusted out for the worst case condition.
FIGURE 22 - PEAK SHIFT NETWORK
4-48
MC3468
MC3468 APPLICATIONS INFORMATION

MC3468 For NRZI Encoded Magnetic Tape
FCPI is maximum flux changes per inch and IPS is tape
speed in inches per second). In high-speed, low-level sys
tems, the amplitude of these read head signals is only a
few millivolts and conditioning with a preamplifier such
as the MC3467 followed by a passive bandpass filter is
required. The bandpass characteristic sets the lower 3
dB frequency below f (_ and the upper 3 dB frequency
above f^ . In most systems, the bandpass filter must do
more than filter out noise. The low-pass portion also
equalizes the read amplifier chain and differentiation
network for a linear phase versus frequency response.
Once the transfer function of this equalization filter is
known, it may be incorporated as part of the filter be
tween the preamplifier and amplifier or as part of the
differentiation network.
The American National Standard specifies that PE
data be recorded at 1600 BPI (Bits Per Inch) on operv
reel magnetic tape. Typical read/write tape speeds range
from 6.25 to 200 IPS (Inches Per Second). Cartridges
use 1600 BPI and have tape speeds of 30 IPS for read/
write. Examples 2, 3, and 4 show MC3468 designs for
PE systems.
NRZI Encoding was one of the first popular record

ing formats and is formalized as an American National
Standard for the purpose of facilitating the interchange
of magnetic tapes. Although the Phase-Encoded format
is now more widely accepted than NRZI, vast libraries of
NRZI tapes still exist. Computers will be reading these
tapes for years to come, and in some cases, re-writing
them in phase-encoded format. Thus, the ability of the
tape drive electronics to read both NRZI and PE tapes is
a feature often sought in new designs.
For NRZI recording, the magnetic surface of the tape
is magnetized to saturation in one direction or the other
each time a logical "1" is to be recorded. The magneti
zation remains unchanged for a logical "0". The result
ing signal from the read head for a typical NRZI data
stream is shown in Figure 23. The NRZI data stream con
sists of a continuum of Fourier components up to a maxi
mum frequency of 5fn, where ty is numerically equal to
one-half the maximum flux changes per second (FCPS).
For long strings of zeroes, the lowest Fourier component
could theoretically be near dc, but on a typical tape a
long interval with no "1's" is not allowed. Consequently,
most of the energy in the pulse train is around fn and
its harmonics (up to the fifth). A suitable corner fre
quency for ac coupling from the preamplifier is 60 Hz,
although for high speed systems it could be consider
ably higher (1/10 fH ). The -3 dB frequency of a low
pass filter is usually placed at a frequency greater than
fH. In most systems, this low pass filter must do more
than provide a roll-off for high-frequency transients. It
also equalizes the read amplifier chain and differentia
tion network for linear phase versus frequency response.
Once the transfer function of this equalization filter is
known, it may be incorporated either as part of the ac
coupling between the preamplifier and amplifier or as
part of the differentiation network.
The American National Standard specifies that NRZI
be recorded at 800 BPI (Bits Per Inch) on open reel mag
netic tape. Typical read/write tape speeds range from
12.5 to 300 IPS (Inches Per Second). Examples 1 and 4
show MC3468 NRZI designs.
MC3468 For Group Code Recorded (GCR) Magnetic

Tape
Basically, Group-Coded Recording (GCR) is a high
density recording scheme which uses the NRZI conven
tion for "1's" and "0's", but adds the restriction that
flux changes occur at least once in every three bit cells
(Figure 23). The read head signal resulting from mixed
data streams consists primarily of Fourier components
from f l to 3f|_ = fH and their harmonics up to the fifth.
The frequencies f|_ and fH are numerically equal to
FCPI x IPS andfCPIjc_IPS respectjve,y (where FCP, js
2
o
maximum flux changes per inch and IPS is tape speed in
inches per second). The amplitude of the read head sig
nals is only a few millivolts or less and conditioning with
a preamplifier such as the MC3467 followed by a passive
bandpass filter is required. The bandpass characteristic
sets the lower 3 dB frequency below f l and the upper
3 dB frequency above f(-|. The bandpass filter must do
more than filter out noise. The low pass portion equal
izes the read amplifier chain and differentiation network
for linear phase versus frequency response. Once the
transfer function of this equalization filter is known, it
may be incorporated as part of the filter between the
preamplifier and amplifier or as part of the differentia
tion network.
The proposed American National Standard specifies
that GCR data be recorded at 9042 FCPI (Flux Changes
Per Inch). Because of the data format, the usable data
density is 6250 BPI rather than 9042 BPI. The "6250
BPI" is a throughput specification and should not be
used in read amplifier calculations. The original GCR
concept was intended for high speed drives (200 IPS).
However, it is also being applied to lower speed (125
IPS) systems. Examples 5 and 6 illustrate the use of the
MC3468 in GCR systems.
MC3468 For Phase-Encoded (PE) Magnetic Tape

Of the numerous methods for encoding digital data
on magnetic tape, phase encoding is currently most
popular. As shown in Figure 23, data is represented by
transitions occurring in the middle of a "data cell . A
low-to-high flux transition (toward the magnetization
level representing erased tape) is defined as a logical
one" and a high-to-low transition is defined as a logical
"zero". For consecutive "one's" or "zero's" phase
transitions are introduced as needed at the "data cell"
borders. Phase transitions are not required when the en
coded data consists of "one-zero" patterns.
The read head signal resulting from mixed data
streams consists of two fundamental frequencies, fn and
f|_ which represent most of the harmonic content (with
some energy at harmonics up to the fifth). These are
numerically equal to
x IPS and PCPI^x IPS {wj,ere
4-49
MC3468
FIGURE 23 - MOST POPULAR MAGNETIC TAPE RECORDING FORMATS

B it Stream in a Trock
+M
N R ZI
(800 8 /IN .. 800 FC /IN .)
-M
+M
PE
O
M
I
z J r1
11.600 B /IN ., 3,200 FC /IN .)|+M
GCR
-M
(6,260 B /IN ., 9,042 FC /IN.)
CIRCUIT OPERATION
(See Figure 24 for component wiring and Figures 25 and
26 for Timing Diagrams)
Threshold Circuit amplifies the Gain Stage output and

compares positive and negative signals to a threshold
level. When the level is exceeded, the TD output is low.
From the waveforms, it is seen that the ZCD output
makes a transition approximately in the middle of the
period when TD is low. Wiring ZCD "anded" with TD to
the set input and ZCD "anded" with TD to the "reset"
input of the R-S type flip-flop reconstructs the data
stream encoded on the tape. This circuit works for zero
clip (zero threshold) operation, but has the disadvantage
that timing distortion results from capacitive loading.
Digital circuits for reconstructing the data stream which
utilize pipe-line delays to overcome capacitive loading
timing distortion are shown in Figure 27.
The operation of the MC3468 is similar for NR ZI, PE,

and GCR data formats. The preamplifier and filtered sig
nal isapplied differentially to either Channel A or B Gain
Stages. The Gain Stage output differentially feeds an
Active Differentiator and a single-ended output is avail
able for straight capacitive or differentiated (active or
passive) coupling into either Channel A or B inputs to
the Threshold Amplifier.
For the circuit configuration shown, the Active Dif
ferentiator output leads the input by almost 90. The
Active Differentiator output is applied to a Zero-Crossing
Detector, which goes low for positive levels and high for
negative levels, changing state at the zero crossings. The
FIGURE 24 - TYPICAL MC3468 COMPONENT HOOKUP
4-50
MC3468
FIGURE 25 - WAVEFORMS SHOWING MC3468 OPERATION FOR NRZI DATA
Mognotlzation
Lovol on Tapo
Channal A
Gain Stage
Input
A ctive
D ifferentiator
O utpu t
ji_ n _n _ rL n _ n j
LT
FIGURE 26 - TIMING DIAGRAM WAVEFORMS SHOWING MC3468 OPERATION FOR PHASE-ENCODED DATA
MC3468
FIGURE 27 - OTHER DIGITAL CIRCUITS FOR RECONSTRUCTING DATA STREAMS FROM THE MC3468
1) Dual O u tp u t C ircuit (Plpollne Delay <or Nssatfvo Edge M u tt Be the Some fo r Both Outputs)
2) Single O u tp u t C ircuit (Operation Independent o f Capacitive Loading E ffects on Delays)
Group Delay Distortion
The determination of the component values is rela

tively straight forward provided the active elements have
negligible phase characteristics in the frequency range of
operation. Below 1 MHz, the MC3467/MC3468 read
chain active elements have negligible phase characteris
tics. Although phase effects start showing above 1 MHz,
phase versus frequency is linear (constant time delay).
Other read chain configurations have a band-pass fil
ter between the preamplifier and Gain Stage. It is pos
sible to move some of the poles of the filter into the
active differentiator. The technique suggested in Figure
28 transfers poles into the active differentiator to min
imize component count. The insertion loss of the tech
nique is also less than an equalization filter ahead of the
READ amplifier.
The ultimate purpose of the magnetic read amplifier

chain in Figure 28 is to produce a digital signal with
transitions corresponding to the peaks of a read head sig
nal. Because the active and passive elements in the chain
exhibit phase characteristics, there will be a "pipe-line"
delay between peaks at the read head and the digital out
put from the zero-crossing detector. Variations in this
delay with frequency or amplitudes cause timing distor
tion which translates directly into increasing error rates.
The primary consideration in the read chain implementa
tion is to equalize the read chain for almost flat delay
over the frequencies and amplitudes of required opera
tion. Figure 28 depicts one of several possible read chain
configurations which can be equalized for best-flat time
delay performance.
MC3468/69 Peak Ootector Section
4-52
MC3468
Determining R d, Cq, end L q For the Active

Differentiator
Also, solving o>c:
For the equalized read chain shown in Figure 28, Cq ,

R q and L q are determined respectively in that order.
The phase characteristics of the active elements are as
sumed to be negligible.
An active differentiator is formed by R d . C q and Lq
coupling the emitters of a differential amplifier having
current sources lo D ,n each leg. If a differential voltage
AyEp cos cot is applied to the Active Differentiator, the
resulting current through R q and C q is:
2AVEP
(
/
I --------------------- --------coslcot arctanl ------ ) >
for R j,
Rt C d
RT
Assuming the output impedance of Q1 and Q2 com

bined is 40 Ohms,
RD
-4 0
WCCD
where u>c ~ 3 cjh.

As shown in Table 1, the addition of an inductor, L q ,
significantly improves phase linearity versus frequency
as well as providing a roll off for high frequency noise.
This optimum solution requires the following relation*
ships:
2
RT
Rt Cd
rearranging.
Ld1
Ld
RT2 C q
^ For optimum zero-crossing detector performance,

dl/dt should be as large as possible at zero-crossing.
Motorola guarantees a minimum lo (D ) f
mA.
TABLE 1 - PHASE LINEARITY (CONSTANT TIME

DELAY) PERFORMANCE FOR RC venus RLC ACTIVE
DIFFERENTIATOR NETWORK
where 2AvEp is the product of the differential input to

the Gain Stage Ep and its unbalanced gain, Av.
where R j is the total of R q and the output impedances
of Q1 and Q2. The combined output impedances of Q1
and Q2 is 40 Ohms.
Rd
Rq
For best zero crossing detector performance, it is es

sential that I be maximized. A design value of I which
results in good noise performance and minimum peak
shift is 900 m icroamperes. 1
2AV Ep Cd 03 = 900 x 10~6
Rearranging the equation for I,

Cd
CJC ,
This condition is approximated for * - a <oc *

RTCD
3coh (where <oh is the maximum applied frequency of
appreciable Fourier content).
The peak value of I (i.e., 2AV Ep C q cj) is important.
As I approaches 10(D)* tt*e transistor Q2 turns off 'and the
waveform at Pin 12 distorts. The circuit no longer be
haves as a differentiator and peak distortion results.
cD
ow v
900 x 1 0 -6
2Av En CO
4-53
cd
3w h
u
wc
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
+45.00
48.01
+51.34
+55.01
+59.04
+63.43
+68.20
+73.30
+78.69
+84.29
Ad
O)
wn
AS
+3.01
+3.33
+3.67
+4.03
+4.39
+4.77
+5.10
+5.39
+5.60
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
+8.49
+17.65
+27.26
+37.03
+46.69
+56.04
+6S.00
+73.68
+81.87
+8.49
+9.16
+9.61
+9.77
+9.66
+9.35
+8.86
+8.58
+8.29
MC3468
Threshold Considerations
The threshold circuitry is used in read after write sys
tems to insure that good data was written, to set up gain
during an ID burst, and sometimes to indicate a mini
mum signal voltage for invalid data. Optimum threshold
ing requires a large swing at the threshold amplifier in
puts. A good design value for V i n t a fe 1-0 Vp-p, and
should not exceed 1.4 Vp-p. If it does, a timing shift re
sults. Internal clipping is provided for all signals greater
than 400 mVp-p. The distortion resulting from clipping
has no effect on thresholding because only peaks are
clipped.
As shown in Figure 24, the Gain Stage output at Pin
11 is ac coupled to the threshold amplifier so that volt
age offsets do not influence thresholding. An attenuator,.
R1/R2, is often required in the ac coupling networks be
cause the gain stage output is between 1.6 Vp-p and 2.4
Vp-p for optimum zero-crossing-detector performance.
Gain H ugo >

Pin 11
R3 should be less than 1 k fi to minimize the effects of

Threshold Comparator Bias Current O th C = 50 pA ). A
0.1 fiF decoupling capacitor is required for transients.
The following circuits are useful for multi-channel
and/or dynamic threshold switching applications.
To
Pin 16
o f Each.
Device
V lN TA r -i T r 2 V
Base Line Shift in PE Systems

The magnitude of R1 should be less than 5 k2 to
minimize the effects of Threshold Amplifier Bias current
(IfH A = 15 nA). Also, R1 + R2 must be greater than 3
k fi because the minimum output sink current d o s) *
the Gain Stage is 1.5 m A; A resistance equal to R1
should be wired to ground from the - leg of the Thresh
old Amplifier (minimize offset bias current effects).
Note that only the selected amplifier input contributes
to bias current Each output of the Threshold Amplifier
is 5 V |N T /\, and is applied to its resepctive Threshold
comparator. Each comparator sees 2.5 V |N JA - Thresh
olding is based on a percentage of the nominal voltage
applied to the comparators, 2.5 V | n j /\. Both positive
and.negative references are derived from Vgg as follows:
In phase-encoded recording, the read signal may not

make symmetrical transitions about the zero bias level.
A lower amplitude signal with a low frequency compo
nent is often superimposed. Although a highpass filter
attenuates some of this component, its frequency is
often close to the 3 dB frequency of the filter and may
be only 6 dB down from signal amplitudes. This base
line shift has no. adverse effects on the performance of
the Active Differentiator. However, the Threshold De
tector is sensitive to the unequal signal peaks. Signal-tonoise ratio can be improved by performing a passive
differentiation into the Threshold Amplifier. With the
corner frequency, fc , placed at fj., the fL signal is at
tenuated - 3 dB; the f h 2 f l signal is for all practical
purposes unattenuated. Figure 29 shows the 45 phase
lead introduced by passive differentiation. Note that this
technique is not directly applicable to high thresholds
because the ZCD transitions fall outside the thresholding
window. However, the threshold window can be delayed
to overcome this drawback.
V - 0.707 (2A V Ep) 9 f u (+46 Pha*o Lead)
R 3 + R4
(V EE) +25JJA * R3
' 2 .6 V |N T A x%
V IN T A
1
R2
O-------- K ^ - ^ W V -
2CTRC
2n(R1 + R2)C
MC3468
The design of the attenuator, R1/R2, follows as de

scribed previously. Example 3 shows a typical applica
tion of passive differentiation to overcome base-line
shift.
FIGURE 29 - RESULTING OPERATION FOR PASSIVE
DIFFERENTIATION INTO THRESHOLD AMPLIFIER
I
V IN TA
(+46 shift)
5. Keep all signal runs as short as possible. The lead on

Pin 15 will radiate and can couple back into the
active differentiator. This will result in excessive
phase jitter. The tell-tale behavior is a ringing at Pin
11 corresponding to the transitions at Pin 15. To
overcome this coupling problem, keep the lead on
Pin 15 short and isolated from the other Input/Output
lines to the MC3468. Preferably, put it over or next
to a ground plane. For long distance runs, use a
twisted pair or coaxial cable.
When evaluating the device for phase jitter and fre
quency response, a special test jig should be designed to
reduce ground loops and coupling caused by instrumen
tation. Instrumentation test set-ups must be calibrated
at each test frequency and differential equipment util
ized where required. A valid evaluation of the perform
ance of any read amplifier chain requires considerable
care and thought.
FIGURE 30 - POWER AND GROUND DISTRIBUTION FOR

MC3468 PRINTED CIRCUIT BOARD LAYOUT
ra_rL_n__TL
Board Layout and Testing Considerations
An LSI package has many input/output pins in close
proximity, some carrying high level signals and others
low level signals. As carefully as the on-chip isolation of
the devices connected to these pins is implemented by
the manufacturer, the coupling of signals or noise be
tween external wires is under the control of the end-user
who designs the integrated circuit into a piece of equip
ment. The designer should be familiar with the following
layout procedures which will optimize the performance
of the device. See Figure 30.
1. Build all circuits on printed circuit boards (including
breadboards). Transmission line theory for flat con
ductors in a plane quite convincingly proves that
coupling is far less than for round conductors in 3dimensions.
2. Use a ground plane under the IC and over as much of
the printed circuit board surface as possible without
exceeding practical limits.
3. Avoid signal runs under the IC, also avoid parallel runs
of 1 inch or greater on the opposite or same side of
board.
4. Use monolithic ceramic 0.1 fiF capacitors for de
coupling power supply transients. One from V q c t0
ground and one from V e e to ground for each IC
package. Keep lead lengths to V* inch or less and place
in close proximity to the IC.
Nots: Oottod L in a i O utline G round Plano

on Back Sldo of Printed C ircu it Board
MC3468
EXAMPLES
Epp - 0 .2 Vp-p @320 kHz

0.4 Vp-p @ 160 kHz
Example #1 (Sea Figure 24 for Component Hookup)
Threshold: 25% of minimum voltage peaks
Tape Drive Type: Open Reel

Encoding: NRZI
Recording Density. 800 BPI (800 FCPI)
Tape Speed: 200 IPS
Signal into Gain Stage
The voltage from the Gain Stage is designed for 1.6 Vp-p at
Pin 11.
1 6 " Au
A =4
^
jr-r
0.4
w
Epp - 0.3 to 0.6 Vp-p @ 80 kHz
Set the EGC for a gain of 4, unbalanced.
Threshold: 25% of minimum voltage peak*
The maximum p-p voltage to the Threshold Amplifier, V / n t A
The voltage from the Gain Stage it designed for 1.6 Vp-p at
Pin 11.
is designed for 1 Volt. The required attenuation factor is
1.6
0 .6 '
1.6
VlNTA .
R1
1
V 0 R 1 + R2 = 1.6
2.7
Set the EGC for a gain of 2.7, unbalanced.
R1 + R2 > 3 kR and R1 < 5 kR (See text)

These constraints are satisfied when R1 s 4.7 kR and R2 s 3
kR. This is an optimum solution for a minimum coupling capaci
tor value. Now consider the minimum voltage applied to the
Threshold Amplifier.
The maximum p-p voltage to the Threshold Amplifier, V | n t a is designed for 1 Volt. The required attenuation factor is r-r-
1.6
V )N T A _
R1
_ 1
V o " R1 + R2 ** 1.6
V|NTA(MIN) " ' f j x 4 * -2 0.5 Vp-p
R1 + R2 > 3 kR and R1 < 5 kR (See text)
The threshold comparator reference voltage, V r , is set at 25% of

2-5 V|NTA(MIN)
V r - 0.25 x 2.5 x 0 5 a 300 mV
These constraints are satisfied when R1 = 4.7 kR and R2 = 3 kR.

This is an optimum solution for a minimum coupling capacitor
value.
Now consider the minimum voltage applied to the Threshold
Amplifier
-3 0 0 x 10~ 3
R3
( - 6)
R3 + R4
R3 < 1 kR (See text)

V INTA(MIN)
2.7 x 0.3 = 0.5 Vp-p.
Let R3 = 470 R; then R4 ar 10 kR
The threshold comparator reference voltage, V r , is set at 25% of
The values of R q and C q are determined from the equations

given in the text.
2 -5V|NTA(MIN)
V r 0.25 x 2.5 x 0.5 a 300 mV
-3 0 0 x 10,3 _
9 0 0 x 1 0 -6
Av Ep
900x 10~6
4 x 0.4 x 2n x 160 x 10^
CD a 560 pF
R3 < 1 kR (See text)
Assume fc = 3fn
Let R3 = 470 R; then R4 & 10 kR
RD
The values of Rq and Cq are determined from the equations

given in the text! '
300 x 10-6
CD r 2AU r
-p w
900x 1 0-6
2AV Epp
R3
( - 6)
R3 + R4
1
WCCD
-4 0
300 x 10~ 6
Av Epp uf
2ir x 3 x 320 x 103 x 5.6 x 10~ 10
-4 0
Rq = 295 ohms 40 a 250 R
______ 900 x 1 0-6

' 2.7 x 0.6 x 2ir x 80 x 103
R t 2 Cd (295)2 x 5 6 0 x 1 0 -1 2
Ld ------j ----- --------------2--------------- 24 iH
Cq as 1000 pF
Example #3 (See Figure 24 for Component Hookup)
Assume fc 3f
Same as Example #2, but consider base-line shift.

R = w CCD 40 2ir x 3 x 80 x 103 x 10~9 ~ 40
In addition to ac coupling between the Gain Stage and Threshold,

a passive differentiation is performed to attenuate the lower fre
quencies producing base-line shift. This improves signal-to-noise
ratio. The corner frequency is chosen at f |_ = 160 kHz where the
attenuation is 0.707 (3 dB) and the phase angle is +45.
Rq " 670 - 40 a 600 R

r T2 c D
(670)2X 1 0 -9
__ __
LD = ----- =----- --------------=--------- = 224 iH
1
2nC (R1 + R2)
160 x 103
For C - 200 pF

Encoding: Phase-Encoded
Recording Density: 1600 BPI (3200 FCPI)
Tape Speed: 200 IPS
Signal Into Gain Stage
R1
R1
R 1+R 2
1.6x0.707
R2 * 5 kR
0.9
Let R1 4.7 kR, then R2 470 R
4-56
MC3468

Encoding: Dual Mode (Phsse-Encoded/NRZI)
Recording Density: 1600 BPI (3200 FCPI) for PE mode and
800 BPI (800 FCPI) for NRZI mode
Tape Speed: 200 IPS
ferentiation for base-line shift or straight ac) into the Threshold

Amplifier, end Threshold setting are similar to the previous ex
amples. For Group-coded data the EGC setting can be electroni
cally locked during the ID burst in conjunction with Threshold
setting. (See Figure 32.)
Values for Co end R q
Same as Examples 1 and 2
900 x 10 -6
D 2AV Epcj
Threshold: 25% of minimum voltage peaks

NOTE: Consider base-line shift for PE mode.
This t 8pe drive performs either the NRZI or the PE functions of
Examples #1 and #3, under control of the SEL A/B line. Using
the Gain Stage and Threshold Amplifier Channel A, Channel B
inputs, the hook-up for a single track is implemented as shown
in Figure 31. Note that an electronic switch is required for Gain
switching when the mode is changed. This particular design did
not require the threshold voltage to be switched, although in a
typical system it probably would be.
It is necessary to electronically switch differentiator compo
nents. A low impedance MOSFET switch is shown.
Encoding: Group Code
Recording Density: 6250 BPI, 9042 FCPI
Tape Speed: 200 IPS
900 x 1 0 -6
________900 x 1 0 -6
Av Epp w
5.3 x 0.3 x 2 ir x 300 x 103
Cq * 300 pF
Assume fc 3f|^
R w cCd " 40 " 2n x 3 x 900 x 103 x 300 x 10~ 12 ~ 40
Rq 200 - 40 - 160 Ohms
R t 2 Cq
(200)2 x 300x 10- 12
..
Lq j ---- --------------2------------

Same as Example #5 except 125 IPS tape speed.
Epp 0.3 Vp-p @565 kHz
Epp - 0 .6 Vp-p @ 188 kHz
Epp - 0.1 Vp-p @ 900 kHz = fH
C o 3 0 0 p F ,R o - 2 5 0 n
Epp = 0.3 Vp-p @ 300 kHz = f L
Lo 12.6 jiH
Considerations for setting Gain Stage EGC, coupling (passive dif
FIGURE 31 - MC3468 COMPONENT HOOKUP FOR DUAL MODE PE/NRZI EXAMPLE #4

N R Z I/ P E M o doSo loct
200 pH
-B
R01<
1 ,0 j i F 4 .7 k '
Vcc
v<*c
Vgg m 6 Vdc *
- -
- -
MOSF6T
On Resistance, On fo r N R ZI)
I t .
MC3468
FIGURE 32 - APPLICATIONS CIRCUITS

Digital Attenuator for Setting MC3468 Gain Stage
Automatically During ID Burst
vCc
vo vc c A
Ro
R 14
(To EGC of MC3468

Gain Stage)
4-58
MOTOROLA
Advance Specifications and

Applications Inform ation
FLOPPY DISK READ AMPLIFIER
MC3470
FLOPPY DISK
READ AM PLIFIER SYSTEM
SILICON MONOLITHIC
INTEGRATED CIRCUIT
The M C3470 is a m o n o lith ic READ A m p lifie r System fo r

obtaining digital in fo rm a tio n fro m flo p p y disk storage. It is designed
to accept the d iffe re ntia l ac signal produced by the magnetic head
and produce a digital o u tp u t pulse th a t corresponds to each peak
o f the in p u t signal. The gain stage am plifies the in p u t waveform and
applies it to an external filte r netw ork, enabling the active d iffe r
e ntia tor and tim e dom ain filte r to produce the desired outp ut.
Combines A ll the A ctive C ircu itry To Perform the Floppy Disk

Read A m p lifie r F unction in One C ircuit
Guaranteed M axim um Peak S h ift o f 5.0%
P SU FFIX
CASE 7 0 1 0 1
TY PIC AL APPLICATION
F ilte r N e tw o rk
A ctive
D iffe re n tia to r
A na lo g In p u ts
T h is it advance In fo rm a tio n and s p e cifica tio n s are subject to change w ith o u t n otice.
MC3470
ABSOLUTE MAXIMUM RATINGS [Non I I I T a

Retina
- 2 S C )
Symbol
Value
Power Supply Voitaoe (Pin 1 1 )
Vcci
7 JO
Vdc
Power Supply Voltage (Pin 18)
VCC2
V|
16
-0 .2 to +7 JO
Vdc.
Vdc
-0 .2 to +7.0
Oto +70
-6 5 to +150
150
Vdc
C
C
C
Input Voltage (Pins 1 and 2)

Output Voltage (Pin 10)
Storage Temperature
Plastic Package
Note 1:
vo
ta
Tstg
Tj
Unit
"Absolute Maximum Ratings'* are those values beyond which the safety of
the device cannot be guaranteed. They are not meant to imply that the
devices should be operated at these limits. The table of "Electrical Charac
teristics" provicej conditions for actual device operation.

Rating
Symbol
Value
Unit
Vcc
+4.75 to +5.25
Vdc
ta
O to+70
ELECTRICAL CHARACTERISTICS (TA 0 to +70C, V jg i 4.75 to 5.25 V, Vcc 2 1 * 14 V unless otherwise noted)
|
Characteristic
GAIN AMPLIFIER SECTION
Differential Voltage Gain
(f - 200 kHz, V|D - 5.0 mV(RMS)
Input Bias Current
Figure
Symbol
Output Voltage Swing Differential
Typ
Max
Unit
AV d
80
100
120
v /v
Mb
viCM
-1 0
-2 5
jiA
- 0.1
1.0
^D
25
mVp-p
voD
3.0
4.0
8.0
2.8
100
4.0
250
Vp-p
mA
mA
k ll
ro
15
BW
5.0
CMRR
50
50
dB
60
dB
V qo
0.4
v CO
3.0
V
V
15
pV(RMS)
>0
4
os
Small Signal Input Resistance (T a 25C)

Small Signal Output Resistance, Single-Ended
(TA - 25C, Vc c i 5.0 V. Vcc2 12 V
Bandwidth, -3 .0 dB (viD - 2.0 mV(RMS), TA - 25C,
V c c i 5.0 V, Vcc2 12 V)
Common Mode Rejection Ratio (TA * 25C, f - 100 kHz,
AV D 40 dB, vin - 200 mVp-p. Vc c i 5.0 V.
V CC2 12 V)
V c c i Supply Rejection Ratio (TA 25C, Vcc2 12 V,
4.75 < VCC1 < 5.25 V, AV D ^ dB)
Vcc2 Supply Rejection Ratio (TA 25C, V c c i 5.0 V,
10 V < VCC2 < 14 V, AV D - 40 dB)
Differential Output Offset (TA 25C, vio vjn 0 V)
Common Mode Output Offset (v;p V|n 0 V,
Differential and Common Mode)
Differential Noise Voltage Referred to Input
(BW - 10 Hz to 1.0 MHz, TA - 25C)
Min
Input Common Mode Range Linear Operation

(5% max THD)
Differential Input Voltage Linear Operation
(5% max THD)
Output Source Current, Toggled
Output Sink Current, Pins 16 and 17
22
4-60
MHz
dB
MC3470
ELECTRICAL CHARACTERISTICS (continued)(TA 0 to +70C, V q c i " 4.75 to 5.25 V, Vqc 2 ~ 10 to 14 V uniat* otherwise noted)
|
ACTIVE DIFFERENTIATOR SECTION

Differentiator Output Sink Current, Pin* 12 and 13
(V o d " V c c 1>
Peak Shift (f - 250 kHz, vi0 - 1.0 Vp-p, i^ p 500 *A.
Figure
Symbol
>OD
7 ,8
PS
Min
1.0
Typ
1.4
Max
Unit
mA
S.O
where PS - 1/2 tp s l- I tps2 x 100%,
tpsi + tps2
VCC1 5.0 V, VCC 2 " 12 V)

Differentiator Input Resistance, Differential
HD
30
kn
roD
40
VOH
2.7
10
V0 L
0.5
1 1 ,1 2
1 1 ,12
*TLH
20
*THL
1A.B
ns
nt
500
Et1
85
1 1 ,1 2
t2
150
12,13
Et2
85
Differentiator Output Refinance, Differential

(TA 25C)
DIGITAL SECTION
Output Voltage High Logic Level, Pin 10 (V ^ci 4.75 V,
Vcc2 12 V, I q h -0 .4 mA)
Output Voltage Low Logic Level, Pin 10 (V c ci 4.75 V,
VCC2 " 12 V, I o l 8-0 mA)
Output Rite Time, Pin 10
Output Fall Time, Pin 10
Timing Range Mono #1 ( t iA artd t j g)
Timing Accuracy Mono #1
(t1 * 1 .0 u* - 0.625 R1C1 + 200 nt)
IR 1 6.4 kn. Cl 200 pF)
Accurancy guaranteed for R1 in the range
1.5 kn < R1 < 10 k n and C1 in the range
150 pF < Cl < 680 pF.
Note: To minimize current tran*ient*. C l should
be kept as small as is convenient.
Timing Range Mono #2
Timing Accuracy Mono #2
(t2 = 200 ns <0.625 R2C2)
(R2 ** 1.6 kn, C2 D 200 pF)
Accuracy guaranteed for 1.5 kn < R2 < 10 kn,
100 pF < C2 < 800 pF
13
12,13
25
4000
115
1000
115
ns
%
nt
%
MC3470
MC3470 CIRCUIT SCHEMATIC
MC3470
FIGURE 2 - VOLTAGE GAIN. BANDWIDTH.

OUTPUT VOLTAGE SWING
FIGURE 1 - POWER SUPPLY CURRENTS.

CC1 AND l(X 2
18
17
16
V|n(A) >51
'CC2
18
- 0 V CC2
17
-O v017
16
- O v 0 16
2.5 iiF
4
15
15
14
14
13
13
12
12
11
10
AV
vo16 ~ vo17
wlr>
ZfZ. 200 pF
= C 2 0 0 pF
200 _
11
P*='
10
-WV>
1.6 k
-< *>
" V CC1
- V CC1
200
pF
cci
FIGURE 4 - AMPLIFIER OUTPUT SINK CURRENT,

PINS 16 AND 17
FIGURE 3 - AMPLIFIER INPUT BIAS CURRENT. I|B

<IB1
fr ,
&
i
18
18
17
17
16
16
16
15
14
14
13
13
12
12
11
11
10
>VCC2
200 p F :
200 pF
7
8
200:7 :
pF
10
-OVcci
200^
pF
-V W
1.6 k
V W J
1.6 k
VW '
"f
O V cci
MC3470
FIGURE 5 - AMPLIFIER COMMON MODE

REJECTION RATIO, CMRR
wln lt \ J ) >51
18
17
16
15
14
13
12
FIGURE 6 - DIFFERENTIATOR OUTPUT SINK CURRENT,

PINS 12 AND 13
~ V CC2
2.5 ItF
ZZZ200 pF
200 :
pF
CMRR - 20 I oqiq Wlnn~

1?
100 VV
|n
f - 100 kHz
11
10
vln - 200 mVpp
-OVCci
1.6 k
------------------w v --6.4 k
NOTE: Measurement* mey bo made with voctor voltmeter hp
8405A or equivalent at 1.0 MHz to guarantee 100 kHz
performance.
FIGURE 8 - PEAK SHIFT, PS
FIGURE 7 - PEAK SHIFT, PS

See Flguro 8 fo r O utpu t Waveform
V |n 1.0 Vpp
f - 250 kHz
Test schematic on Figure 7

1
18
17
16
15
14
- o V CC2
ôut
Pin 10
1.5 V
f - 250 kHz
C1
200 pF
13
12
11
10
'CAP
0 1 ( lF
- t p s i-
vln 1-0 V p|
H( -
^ tpsitps2
2 tpsiTtps2
C2:
200
pF
1.6 k
-v w
R 1
4-64
MC3470
FIGURE 10 - DATA OUTPUT VOLTAGE LOW, PIN 10
FIGURE 9 - DATA OUTPUT VOLTAGE HIGH, PIN 10
200 pF
_L
-O VCC2
18
17
18
17
16
16
15
16
14
14
13
13
12
12
11
10
11
10
-OVCC2
200 pF :
200 pF
vw
6.4 k
FIGURE 11 - DATA OUTPUT RISE TIME, tTLH

DATA OUTPUT FALL TIME, tTHL
TIMING ACCURACY MONO #2, ET2
FIGURE 12 - TIMING ACCURACY, Eti AND Ef2

DATA OUTPUT RISE AND FALL TIMES, tTLH AND tTHL
V jn shown on Figure 13
V jn i i tamo as shown on Figura 13, to tt tchematic on Figuro 12
C 1^ 20 0p F
C2Z
200
pF
18
17
16
15
14
13
12
11
10
1 .6 k
4-65
>VCC2
MC3470
FIGURE 13 - TIMING ACCURACY MONO #1. Et l

*TLH *TH L < 10 n*
f " 280 k H i
SOS D uty Cycle
Test Schematic on Figure 12
Et i B - ! T O X100*
FIGURE 14 - AMPLIFIER OFFSET DECOUPLING
IMPEDANCE. PINS 3 AND 4
Ra + ra and A y w ith Roxt SOO t l
Vinn
BOO <
18
17
16
- 250 kHz
V | " 5 mV(RMS)
'O U tR
(O )
Rg
4
15
14
13
2.5 pF
v out
V|n
200 p F ;
7
12
11
10
200 p F ;
r + Ft -
-O V cci
'
I
soon
Z\ VSOUtR
7 7 )/
ICC<N>. NORMALIZED POWER SUPPLY CURRENT
FIGURE IS - NORMALIZED POWER SUPPLY CURRENT

(ICC/'CC 2BC) versus TEMPERATURE

(A y/A v 2BC) versus TEMPERATURE
1.0*
1.02
1.00
0.S8
038
4-66
AV/AV(MI0), NORMALIZED VOLTAGE GAIN
t;(N). NORMALIZED OUTPUT PULSE WIDTH
MC3470
Riff, EFFECTIVE EMITTER RESISTANCE (n)
to
-z~
o
31
-s
'C 'c
M N
sS
in
so
s s
*
O)
-vl
Avr (N). NORMALIZED VOLTAGE GAIN
p
o
t1/t||26C), NORMALIZED TIME DELAY
> T
sB
*
n
(II n o
|r
l< t f *
a
Is
VOLTAGE GAIN,
tl
2 o
FIGURE 20 - NORMALIZED
on (diffarential noito at Input) ooy/2/10 0
NOTE: Attumo uncorrolatod nolto tourcot
s 5
3
5
30 5
ma
MC3470
APPLICATION INFORMATION
The MC3470 is designed to accept a differential ac
input from the magnetic head of a floppy disk drive and
produce a digital output pulse that corresponds to each
peak of the ac input. The gain stage amplifies the input
waveform and applies it to a filter network (Figure 23a),
FIGURE 23a - BLOCKING CAPACITORS USED TO
ISOLATE THE DIFFERENTIATOR
14
16
MC3470
Gain Stage
Ita g ^
MC3470
D ifferentiator
F ilter
----- O I
o
18
enabling the active differentiator and time domain filter

to produce the desired output.
FILTER CONSIDERATIONS
The filter is used to reduce any high frequency noise
present on the desired signal. Its characteristics are dic
tated by the floppy disk system parameters as well as the
coupling requirements of the MC3470. The filter design
parameters are affected by the read head characteristics,
maximum and minimum slew rates, system transient
response, system delay distortion, filter center frequency,,
and other system parameters. This design criteria varies
between manufacturers; consequently, the filter con
figuration also varies. The coupling requirements of the
MC3470 are a result of the output structure of the gain
stage and the input structure of the differentiator, and
must be adhered to regardless of the filter configuration.
The differentiator has an internal biasing network on
each input. Therefore, any dc voltage applied to these
inputs will perturbate the bias level. Disturbing the bias
level does not affect the waveform at the differentiator
inputs, but it does cause peak shifting in the digital output
(Pin 10). Since the output of the gain stage has an associ
ated dc voltage level, it, as well as any biasing introduced
in the filter, must be isolated from the differentiator via
series blocking capacitors. The transient response is mini
mized if the blocking capacitors C and C' are placed
before the filter as shown in Figure 23a. The charging and
discharging of C and C' is controlled by the filter termina
tion resistor instead of the high input impedance of the
differentiator.
The filter design must also include the current-sinking
capacity of the amplifier output The current source in
the output structure (see circuit schematic pins 16
and 17) is guaranteed to sink a current of 2.8 mA. If the
current requirement of the filter exceeds 2.8 mA, the cur
rent source will saturate, the output waveform will be
distorted, and inaccurate peak detection will occur in
the differentiator. Therefore, the total impedance of the
filter must be greater than Zmjn as calculated from

_ (E pA yp)max
m,n "
2.8 mA
where Ep is the peak differential input voltage to the

MC3470.
TRANSIENT RESPONSE
The worst-case transient response of the read channel
occurs when dc switching at the amplifier input causes its
output to be toggled. The dc voltage changes are a con
sequence of diode switching that takes place when control
is transferred from the write channel to the read channel.
If the diode network is balanced, the dc change is a
common mode input voltage to the amplifier. The switch
ing of an unbalanced diode network creates a differential
input voltage and a corresponding amplified swing in the
outputs. The output swing will charge the blocking
capacitor resulting in peak shifting in the digital output
until the transient has decayed. Eliminating the differential
dc changes at the -amplifier input by matching the diode
network or by coupling the read head to the amplifier via
FET switches, as shown in Figure 23b, will minimize the
filter transient response.
FIGURE 23b - FET SWITCHES USED TO COUPLE THE R/W
HEAD TO THE MC3470
Power
Two of the advantages FET switches have over diode

switching are:
1. They isolate the read channel from dc voltage
changes in the system; therefore, the transient
response of the filter does not influence the system
transient response.
2. The low voltage drop across the FETs keeps the
input signal below the amplifier's internal clamp
voltage; whereas, the voltage dropped across a diode
switching network adds a dc bias to the input signal
which may exceed the clamp voltage.
AMPLIFIER GAIN
For some floppy systems, it may become necessary
to either reduce the gain of the amplifier or reduce the
4-68
MC3470
signal at the input to avoid exceeding the output swing

capability of the amplifier. The voltage gain of the ampli
fier can be reduced by putting a resistor in series with
the capacitor between pins 3 and 4 (Figure 14). The
relationship between the gain and the external resistor is
given by
crossing detection of the current waveform. Since the

capacitor shifts the current 9 0 from the input voltage,
the comparator performs peak detection of the input
voltage.
The following terms will be used in determining the
value of C to be used in the differentiator:
Ep A peak differential voltage applied to MC3470
amplifier input.
AV p _
Rext
t
a V r 2<re + Re)
Ep sin <ot ^ voltage waveform applied to MC3470

amplifier input (for purposes of discussion,
assume a sine wave).
where A y g voltage gain with the external resistor = 0,

A \ / r ^ voltage gain with the external resistor in,
êxt ~
external resistor, and
A v d differential voltage gain of input amplifier.
re + Re ^ the resistance looking into pin 3 or pin 4.
vjn(t) ^ differential voltage waveform applied to the

differentiator inputs.
Thus,
s EpA vD s'n a,t (Note: The filter is assumed to

be lossless.)
(re + Rg).
R ext= 2
A plot of (re + Re) versus temperature is shown in

Figure 21. Figure 20 shows the normalized voltage gain
versus temperature with the external resistor equal to
500 ohms.
ic(t) ^ current through capacitor C q .

RO output resistance of Q1 (Q2) at pin 12 (13).
If v;n(t) = EpAvDs'n<Jt> then the current through the
capacitor C q is given by
ic(t) = C D A vD EptJC0SCJt
ACTIVE DIFFERENTIATOR
The active differentiator in the MC3470 (simplified
circuit shown in Figure 24), is implemented by coupling
FIGURE 24 - ACTIVE DIFFERENTIATOR NETWORK
and V o lt) = 2R cC D A vD Epw csw tAccurate zero crossing detection of V o (t) [peak
detection of v;n(t)] occurs when the current waveform
ic(t) crosses through zero in a minimum amount of time.
This condition is satisfied by maximizing current slew
rate. For a given value of to, the maximum slew rate
occurs for the maximum value of ic or cos tot = 1. There
fore,
ic = Cq A v d EpCJ
The MC3470 current-sourcing capacity will determine
the maximum value ic; therefore, Cq must be chosen such
that the maximum ic occurs at the maximum A v D Epu
product.
c
icmax
_
1 mA
(A v D Epw )max
the emitters .of a differential amplifier with a capacitor

resulting in a collector current that will be the derivative
of the input voltage,
I = Cdv/dt
If the output voltage is taken across a resistor through
which the collector current is flowing, the resulting volt
age will be the derivative of the input voltage.
(120)(EpO>)max
If the peak value specified for ic is exceeded, the

current source d o in Figure 24) will saturate and distort
the waveform at pins 12 and 13. Consequently, the
differentiator will not accurately locate the peaks and
peak shifting will occur in the digital output.
The effective output resistance Ro of Q1 (Q2) will
create a pole (as shown in Figure 25) at 1 /2 Ro C d - If
this pole is ten times greater than the maximum operating
frequency (<Omax)> the phase shift approaches 84.
Locating the pole at a frequency much greater than
10 (omax needlessly extends the noise bandwidth thus:
2Ro ---------------- .
Cd 10 Wmax
dvjn(t)
dt
V Q is applied to a comparator which will provide zero
V 0 = 2Ric = 2RC
If Ro is not large enough to satisfy this condition, a series
4-69
MC3470
Using this value for L gives:
FIGURE 2B - RESPONSE OF DIFFERENTIATOR

USING ONLY C0
RC0
'V
Cd
1 0 V r\
Solving for R gives:

R
5 CQ(Omax
The total resistance (R) is the effective output resis

tance (Ro) plus the resistor added in the differentiator
(R d )- Values of 6 from 0.3 to 1 produce satisfactory
results.
PEAK SHIFT CONSIDERATIONS
Peak shift, resulting from current imbalance in the
differentiator, offset voltage in the comparator, etc., can
be eliminated by nulling the current in the emitters of
the differentiator with a potentiometer as shown in
Figure 27.
resistor can be added so that

R = 2Rq + Rd
1
CD 10 w max
To further reduce the noise bandwidth, a second pole

can be added (as shown in Figure 26) by putting an
FIGURE 27 - PEAK SHIFT COMPENSATION
FIGURE 26 - COMPLETE RESPONSE OF DIFFERENTIATOR
The potentiometer across the differentiator components

is adjusted until a symmetrical digital output cycle is
obtained at pin 10 for a sinusoidal input with the mini
mum anticipated Epw product.
inductor in series with the resistor and the capacitor.
The values of R and L are determined by choosing the
center frequency ( g j 0 ) and the damping ratio (5) to meet
the systems requirements where
Wo = - =
V lcd
f_
RCp
2y / L C S
V lc5
where C q is chosen for maximum ic as shown previously.
Solving for L gives:
100 Cotwmax)^
DESIGN EQUATIONS FOR ONE-SHOTS

As shown in Figure 28, the MC3470 input waveform
may have distortion at zero crossing, which can result in
false triggering of the digital output. The time domain
filter in the MC3470 can be used to eliminate the distor
tion by properly setting the period (t j) of the one-shot
timing elements on pins 6 and 7. The following equation
will optimize immunity to this signal distortion at zero
crossing of the read head signal.
The timing equation for the time domain filter's oneshot is:
ti R iC iK i+ T 0
where 1 B 0.625, T c 200 ns.
Actual time will be within 15% of t i due to variations
in the MC3470.
If A T is the maximum period of distortion (see Figure
4-70
MC3470
FIGURE 28 - WAVEFORMS THROUGH THE READ CIRCUIT
A m pllflor
In p u t Signal
O u tp u t of
Ons-Shot ( t^ l
,[t | ,
Tim e Domain
F ilter Ouput
Digital
Output
T 2 f
__n__ n
28), then choose t i such that
where T --------.
4f(max)
The width of the digital output pulse t2 (pin 10) is
determined by
t2 = R2C2K2
where K2 110.625.
Actual pulse width will be within 15% of t2 due to
variations in the MC3470.
To preserve the specified accuracy of the MC3470,
R1. R2< C i, and C2 should remain in the ranges shown in
the Electrical Characteristics. Also, to minimize current
transients, it is important to keep the values of C1 and C2
as small as is convenient. For tt = 1 jus and t2 = 200 ns,
suggested good values for the capacitors are
Ci - 250 pF
C2 160 pF
BOARD LAYOUT AND TESTING CONSIDERATIONS
An LSI package has many input/output pins in close
proximity, some carrying high level signals and others
low level signals. As carefully as the on-chip isolation
of the devices connected to these pins is implemented by
n ____ n
J X
the manufacturer, the coupling of signals or noise between

external wires is under the control of the end-user who
designs the integrated circuit into a piece of equipment.
The designer should be familiar with the following layout
procedures which will optimize the performance of the
device. See Figure 29.
1. Build all circuits on printed circuit boards (including
breadboards). Transmission line theory for flat conductors
in a plane quite convincingly proves that coupling is far
less than for round conductors in three dimensions.
2. Use a ground plane under the IC and over as much
of the printed circuit board surface as possible without
exceeding practical limits.
3. Avoid signal runs under the IC. Also avoid parallel
runs of 1 inch or greater on the opposite or same side
of board.
4. Use monolithic ceramic 0.1 /iF capacitors for
decoupling power supply transients: one from V c c i to
ground and one from V q C2 to ground for each IC
package. Keep lead lengths to 1/4 inch or less and place
in close proximity to the IC.
5. Keep all signal runs as short as possible.
When evaluating the device for phase jitter and fre
quency response, a special test jig should be designed
to reduce ground loops and coupling caused by instru
mentation. Instrumentation test setups must be calibrated
MC3470
at each test frequency and differential equipment

utilized where required. A valid evaluation of the per
formance of any read amplifier chain requires considerable
care and thought.
FIGURE 29 - POWER AND GROUND DISTRIBUTION FOR

MC3470 PRINTED CIRCUIT BOARD LAYOUT
VCc2
V CC1
O O O O O O
o o o o \ o /o O O O
I
{2 & 2 -0
O O O O O O
o o o o \ o / o *o o o
9
1
NOTE: Oottod lin n outltno ground piano

on back sldo of prlntod circuit board.
<g>
MOTOROLA
Specifications and
Applications Inform ation
DYNAMIC
MEMORY CONTROLLER
MEMORY CONTROLLER FOR 16 PIN 4K, 16K

AND 64K DYNAMIC RAMs
The m em ory co n tro lle r chip is designed to greatly sim plify the
interface logic required to co n tro l the popular 16 pin m ultiplexed
dynam ic NMOS RAMs in a microprocessor system such as the
M 6800. The co n tro lle r w ill generate, on command from the m icro
processor, the proper tim in g signals required to successfully transfer
data between the microprocessor and the NMOS memories. The
c o n tro lle r, in co n ju n ction w ith an oscillator, w ill also generate the
necessary signals required to insure th a t the dynam ic memories are
refreshed fo r the retention o f data.
L SU FFIX
CASE 6 23
G reatly S im p lify the M PU -Dynam ic Mem ory Interface
Reduce Package C ou n t and System Access/Cycle Tim es 30%
C hip Enable fo r Expansion to Larger W ord Capacity
S C H O TTK Y M O N O L IT H IC
Generate 1 o f 4 RAS Signals fo r an O p tim u m 16K /64K

M em ory System
High In p u t Impedance fo r M inim u m Loading o f MPU Bus
S ch o ttky T T L Technology fo r High Performance
Useful w ith 4K and 16K and Future Expanded D ynam ic RAMs
P SU FFIX
CASE 6 49
BLO C K D IA G R A M
PIN CONNECTIONS
M C 3232A /
M C 32 42 A
MC
M C t1 t2 t3 t4 t5
Several m e tho d s m ay bo e m p lo ye d to generate the re q uired tim e delay:
1. O no shots
2. H igh fre q u e n cy co un ters
3. High fro q u o n c y s h ift registers
4. D elay lines
5. Signals fro m MPU C lock
[I
EK c
tld
t2 (J
] CE
tsE
57] Ref
t4 (T
20J Ref Request
te[T
19]
C lk
Ref G ra n t
R/W In
(T
nT] A 1 2/14
R ef En
[7
TT] A 1 3 /1 5
R o w E n [T
i l ] RAS 1
R/W O u t [ hT
RAS 2
CAS E l
G nd
QF
Soo Pin D e scrip tio ns
4-73
] MC
] RAS 3
13] ft AS 4
MC3480
ABSOLUTE MAXIMUM RATINGS (Note 1)

Rating
Symbol
Value
vcc
7 JO
-0 .5 to +7.0
-0 .5 to +7.0

Input Voltage
V|
Output Voltage
v0
ta
0 to +70
Storage Temperature
Tstn
Tj
-65 to +150

Ceramic Package
Plastic Package
Unit
Vdc
Vdc
Vdc
c
c
c
175
150
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the
device cannot be guaranteed. They are not meant to imply that the devices should
be operated at these limits. The table of "Electrical Characteristics'* provides
conditions for actual device operation.
RECOMMENDED OPERATING CONDITIONS_______________________

Rating
Symbol
Value
Unit
Vcc
+4.50 to +5.50
0 to +70
Vdc
C

ta
ELECTRICAL CHARACTERISTICS (Unless otherwise noted specifications apply over recommended power supply and temperature
ranges.)
Symbol
Min
Typ
Max
Unit
V|L
08
V|H
2.0

(V|L 0.5V
lL
250
|iA
IH
40
mA
Characteristic
(Vjn 2.7 V)
(V|H " 5.5 VI
Input Clamp Voltages

(IIK 18 mA)
(lOL * 24 mA for RAS, CAS. and R/W)
(lOL 8.0 mA for Row En, Ref En, MC, Ref Req)
(lOH * 1 mA for RAS, CAS, end R/W)
(lOH *0-4 mA for Row En, Ref En, and MC)
lOH -0 .2 mA for Ref Req
(Note: Ref Req output has internal 5.0 k
resistive pullup to Vcc.)
100
V|K
-1.5
as
FIGURE 1 - TYPICAL tpT1J.and4 (HIGH TO LOW) versus

LOAD CAPACITANCE - RAS, CAS and R/W
300
400
3.0
2.4
2.4
65
40
-10
-55
mA
mA
>OS
200
0.5
V
V0 H
CL, LOAO CAPACITANCE (pF)
V
V
ICC
100
VOL
Power Supply Current During R/W or Refresh

During Idle
Output Short-Circuit Current
(V ql 0 V for Row En, Ref En, and MC)
500
MC3480
SWITCHING CHARACTERISTICS
(Unleu otherwise noted. 4.5 < Vcc < 5.5 V. and 0 < TA < 70C
Symbol
Min
Typ
Max
tPLH(WC)
tPHL(WC)
*PT1
, PT2
*PT3
*PT4
1PT5C
PT5R
PTSW
tPT5ER
*PT5E
tPTSF
tpcQ
tPGS
Characteristic
19
30
30
25
22
10
20
14
17
40
35
45
45
42
40
58
65
48
46
27
43
tPTQ
22
60
tPTI
PT2
tPT3
tPT4
*PT5C
*PT5R
PT5W
tPTSER
PT5E
PT5F
10
30
35
25
25
35
35
45
65
48
46
33
18
16
17
16
22
ns
Propagation Delay Times (AC Load, 15 pF All Outputs)

t i to RAS
t2 to Row En
t3 to CAS
t4 to R/W
t5 to C A ?
to WES
to R/W
to Row En (Refresh)
to Row En (R/W)
to Refresh En
16
8.0
8.0
14
14
22
30
25
22
ns
Setup Times (Full AC Load All Pins)

Ref Clk before Ref Grant
A12, A13 before ti
R/W Input before t4
CE before t 1
Ref Grant before t1
tsu(RC)
*su(A)
*su(R/W)
35
tsu(RG)
10
33
20
25
th(A)
15
tsu(CE)
ns
Hold Times (Full AC Load All Pins)

A12.A13 after t5
CE after ti
R/W after t4
MC Rising after t1 Rising
th(R/W)
th(MC)
Minimum Delay Times (Note 2 Full AC Load All Pins)

t i Low to High to t2 Low to High
t i Low to High to t4 Low to High
t2 Low to High to t3 Low to High
t3 Low to High to t5 Low to High
*d(1 - 2 l
*d(1-4)
*d(2-3)
*d(3-5)
30
30
30
*WL(t)
'WH(t)
<W(MC)
tW(RG)
30
30
30
M inim um Putse W idths

t i through t5
Unit
ns
Propagation Delay Times (Full AC Load All Outputs)

MC to MC Low to High
MC to RC High to Low
t i to RAS
t2 to Row En
t3 to CAS
t4 to R/W
t5 to CE5
to RAS
to R/W
to Row En (Refresh)
to Row En (R/W)
to Refresh En
Ref Clk to Ref Req
Ref Grant to Row En 'I
to Ref En J
t 1 to Fief tteq (Ref only)
*h(CE)
0
0
30
ns
ns
Low
High
MC
Ref Grant
25
Note 2: If delay* between t i 15 ere less than the minimum specified, the succeeding outputs may not switch.
AC LOADS (Note 3)
R/W and CAS Outouts
RAS Outoutt
MC, Row En, Ref En, and Ref Req Outputs
450 dF to Gnd*
1SO dF to Gnd*
15 pF to Gnd*
Includes probe and jig capacitance.

NOTE 3: All outputs can drive larger capacitive loads than those shown
with a small decrease in speed. See Figure 1.
4-75
MC3480
PIN DESCRIPTION TABLE

No.
Name
RAS1
RAS2
RAS3
RAS4
Function
16
15
14
13
Row Address Strobe pins which connect to each of the dynamic RAMs to latch in row address on memory chips.
Decoded to 1 of 4 during R/W cycle. All 4 go low during refresh cycle.
CAS
R/W Out *
11
10
Column Address Strobe pin which connects to each dynamic RAM to latch in column address.
This pin signals the dynamic RAM whether the RAM is to be read from or written into.
Row En
Row Enable output which goes to the MC3232A (MC3242A). It signals the Address Multiplexer that the lower half
(Row Addresses) or the upper half (Column Addresses) of the address lines are to be multiplexed into the dynamic
RAM address inputs. A Logic 1 on this output indicates the Row Addresses, and a Logic 0 indicates Column Addresses.
Ref En
Refresh Enable output. A Logic 1 signals the Address Multiplexer that a refresh cycle is to be done, and a Logic 0
indicates that address multiplexing should be done.
CE
R/W In
22
7
A13 (A15)
A12 (A14)
17
18
MC
23
rac
n
t2
t3
t4
t5
2
3
4
5
Chip Enable Input. A Logic 1 on this pin disables all chip functions, except that of Refresh and the MC output. CE must
be low during tl low to high transition to initiate R/W cycle. Once t1 is initiated, the cycle is independent of CE.
The Read/Write input pin receives information from the M6800 MPU as to the direction of data exchange in the
dynamic RAM. It transmits a Logic 0 to the R/W output for a Write Cycle and a Logic 1 for a Read Cycle.
Upper Order Address lines from the M6800. These two inputs decode to four signals controlling the four RAS outputs.
A14 and A15 apply to 16K RAMs.
Memory Clock input from MC6875 clock or other signal source. The rising edge of MC must'occur after the rising
edge of tl to avoid aborting the refresh cycle. When MC rises, it resets an internal flag that will terminate refresh at the end
of the current cycle. Failure to reset the flag forces the 3480 to refresh every cycle thereafter. MC can be connected to
t2 or t3 in noncritical applications.
The buffered complement output of MC. It is a buffered output which may be used to drive the circuitry creating the
time delays used on inputs t1 through t5.
These pins use external timing inputs to sequentially select the outputs to be enabled. They are positive-edge triggered
inputs. Assuming a Read/Write cycle is to be executed, a positive edge on t l forces a logic 0 on one of the four RAS
outputs as determined by the A12/14, A13/15 inputs. After a delay, a positive edge on t2 causes Row En to go to a
Logic 0, providing address-multiplexing information to the MC3232A or MC3242A. t3 enables the CAS output and it
goes low. t4 enables the R/W output and it goes low, assuming the R/W input was low. t5 resets all the outputs to a
Logic 1 (with the exception of MC, Ref En, and Ref Req). The inputs t l, t2, t3, and t5 are daisy-chained, so they must
be sequentially driven to obtain the desired output signals. t4 can be driven at any time after t l .
Ref Clk
21
Ref Req
20
Ref Grant
19
Vcc
Gnd
24
Through the Refresh Grant input, the MC6875 initiates a refresh cycle. This input is positive-edge triggered and is
enabled only after the Ref Req pin has gone low. This allows the MC3480 to discern between a Refresh Grant or a
DMA Grant even though they appear on the same line. When employing both dynamic memory (refresh) and DMA
in a microprocessor-based system with a combined Refresh/DMA Request control on the clock, provision must be
made for holding off a DMA request during a refresh period (and visa versa). If this provision is not made, clock
stretching (cycle stealing) will continue indefinitely and dynamic microprocessor data will be lost. The positive edge
on Ref Grant causes Row En output to go low and Ref En output to go high. This signals the MC3232A (MC3242A)
that a refresh address is required. The refresh cycle occurs with the succeeding pulses on tl -tS. A positive edge on tl
causes Ref Req to go high and all the RAS outputs to go low. A positive going edge on t2 causes no change in the
outputs, since it controls the address multiplexing (Row En) during the Read/Write cycles. There is no output change
when t3 and t4 go high because no CAS or R/W signal is needed during refresh. A positive edge on t5 resets the RAS
and Row En to a Logic 1 state, and Ref En to a Logic 0 state, ready for the next Read/Write cycle.
+5.0 V supply. A 0.1 mF capacitor is recommended to bypass pin 24 to ground.
12
System Ground.
The 32 kHz (64 kHz) Refresh Clock signals this pin that another refresh cycle is required. It is a positive-edge triggered
input, and upon triggering, the Ref Req pin goes to a Logic 0.
The Refresh Request output acts as an input to the MPU system, requesting a refresh cycle. This output has
a 5 kn pullup resistor to the Vcc *UPP*V to allow wire-ORing if desired.
These outputs are designed to drive the highly capacitive inputs of multiple dynamic RAMs/(150 pF for RAS outputs, and 4S0 pF for CAS
and R/W outputs). Consequently, these outputs have no short-circuit limit and must be handled accordingly. Good high capacitance load
driving techniques'usually include a 10 n or greater series damping resistor. It is highly recommended that this be done on RAS. CAS and
R/W outputs of the MC3480. The effect of these series damping resistors on rise and fall times must be included in timing considerations.
NOTE: All other outputs are LS/TTL totem-pole configuration unless otherwise noted.
MC3480
TIME DELAY INFORMATION

TIMING REQUIREMENT CONSTRAINTS
Minimum is determined by MPU Address Delay (>a d )< plus RAM Row Address Set-Up Time (tASR)' minus MC3480
Propagation Delay (tpxi).
Minimum is determined by RAM Row Address Hold Time (tRAH) minus the minimum MC3232A/3242A Row Enable to
Output Delay ft()O M IN >Minimum is determined by RAM Column Address Set-Up Time (t^sc minimum) P'ut maximum MC3232A/3242A Row
Enable to Output Delay (tooiMAXlNo Minimum
A tl
At2 - At1
At3 At2
At4 - At3
At5 - At3
Minimum is determined by RAM minimum CAS Pulse Width (tcAS^ or Access Time from CAS Uc a c ) p,u* Dflta Set-Up Time
of MPU (tDSR).
Minimum is determined by the RAM minimum Write Pulse Width (tyyp).
AtS At4
Note: Also required in computing time delays are the various delays incurred by the particular delay scheme used; i.e., delays between
4 x fo. 2 x fo. and fQ from the MC687S which are used as inputs or the gate delays of the gates used in Figures 6A through SC.
TYPICAL APPLICATION
Note:
Numbors In parenthesis indlcato

part typo* or values fo r 16K x 1 BAM *
Power-On Retet
P-OR
01
X I, X2
Crystal
(4 x MPU f 0 )
MPU
Syttem
Clock
MC687S
MPU
MC6800
C i
<t>2
I
MC
(Mem
Clk)
Data
But
Ref
Control
Grant
Bus
Rat
Req
Address
Bus
A12, A13 (A 14, A1S)
1
iz
MC
Rofroth
Enablo
t1
Addrets
M ultiplex
and
Refresh
Counter
MC3232A
(MC3242A)
t2
Oelay
C ircuit
t3
Memory Control
and Timing
MC3480
AO -A 11
\ X (A0~ A13>
Row
Enablo
i z
Oata
Buffer
MC6880A
rS
7 \
t4
ts
32 kHz
<64 kHz)
Oscillator
Ref Clk
S A S i RAS2
RAS3 RAS4
CA
R/W
A d dro tt
But
0 0 -0 5
<00-06>
Memory
Array
4K x 8
MCM4027
(16K x 8)
(MCM6616)
u
4K x 8
(16K x 8)
Data
But
IZ
4K x 8
(16K x 8)
4-77
4K x 8
(16K x 8)
MC3480
FIGURE 2 - READ/WRITE TIMING CYCLE

-R/W C ycle-
*iu(cE)
-tMcE)
Ce
Ref Grant
PAAJ In R
1.8 V
*u(R /W )-
.+-1.6 V
h(R/W>
A12/A 14
<13) (15)
h(A)~
Sy$
Clk
~**u(A)
_ tW H (t|
*W L(t)
" m
V M k
a 7 L . /m
/m
' Noto: tyy|_(t ) and ty^H It) typical all t inputs.
- j f 1.6 V
*d(1-2)
* ^ * * ////////////A
*d(2-3)
V / / / / / / / / / / y m . &___ /
*d(1-4)----------
WE23MZMBL
7W/////////M
W ///M
/////////
7ZZL.
-*d (3 -5 )-
m
PT1-
*P T 6 R -
-*PT3
RAS
*PT6C-
9
X
2.4
,0 . V
PT2*PT4 -
*PT5W
*PT5E
NOTE 4: A lthough t l and CE arc shown a t d o n 't car* after their respective m inim um hold tim e t, t l
may rite again after the Initial rWnoedge In e R/W cycle o n ly If c E It low. Bringing t l high
a second tim e during a cycle when CE It high w ill Im properly term inate the cycle.
4-78
MC3480
FIGURE 3 - REFRESH TIMING CYCLE
Refrath Cycle-
CE
*u(RG )*
-< W (R O )*'
'tu (R C ) - >
p^TTZ
Rof Grant -
^
R
R/W
A 1 2/A 14
(13) (16)
-*W(MC)
S yt C lk /M C *PLH (M C )^
-* p h l {KSc )
?*
MC
. <WH|t) .
*W L(t)
CL
2
1.5 V
/
Note:
|_<t) Bn<S*W H(t) 'VP '601 0,1 * ln Pu ,-
TL
IW/////A * *w m m m m /////////m
7 m 2
W //////A 777T/.7k i v 'V ////////////7777///M
*4 7
m
tB
PCO
/,
R efR eq 1
j f i1.5 V
PTQ
RAS
V
*PT1
Hlsh
CAS
Low
Read
R/W O ut
.tp os
Row En
^
t PT6ER-
1.5 V
H i^
MC3480
APPLICATIONS INFORMATION
GENERAL DESCRIPTION
systems, the timing signals required can be directly

obtained from those available from the microprocessor. In
systems requiring high speed memory/microprocessor
cycle times, timing input t1-t5 can be obtained using
delay lines or a range of techniques as shown in Figures 4
thru 8. It is only necessary to maintain the time delay
relationships shown under time delay information.
The MC3480 uses five general timing inputs in place of

a master clock with on-chip timing generation. This gives
the system designer optimum flexibility in interfacing
with the various microprocessor families and dynamic
memories that are available. In simpler slow speed
FIGURE 4 - UNIVERSAL TIME DELAY USING MC687S
READ /W RITE CYCLE
T V ?
2 N 5
o j> I
MC3480
RAM
C ontroller
tl
It2
RAS 1
RAS 2 0
o
,3 ^ 3
0
t4
CAS o
tS
R/W o
i _ MC Row o
En
MC
Rof
En
NOTE: t4 can bo tied to t3 Instead of 2fp,

giving a longer w rlto pulse w idth.
4-80
MC3480
BA
FIGURE 6 - ALTERNATE TIME DELAYS USING MC6875

(Rsad/Writo Cycle Shown)
79
MC3480
RAM
C ontroller
UoH
tl
R A S fl
t2 R AS 2
RAS 3
t3
RAS 4
t4
CAS
tb
R/W
MC Row
En
MC
Ref
En
0
o
0
0
o
o
Gete MC7400
From MC687S
Gete*-MC7400
4-81
MC3480
FIGURE SC - ALTERNATE TIME DELAYS USING MC6875
REAO/W RITE CYCLE
From MC6875
NOTE: MC o f MC3480 is delayed by

tw o gota dolayt after t i to
satisfy MC after t i Hold Tima,
h IM C I'
MC3480
FIGURE 6 - ONE SHOT TIME DELAY METHOD
tt
t2
MC3480
RAM C ontrollor
Q
CD
t i RAS 1
,2 RAS 2
RAS 3
t3
RAS 4
ti
t4
t2
MC
MC
Cd
CAS
R/W
Row
En
Rof
En
Memory Clock
From MC6875
o r Suitablo
Clock Signal
CD
13 X
2 MC9602S
NOTE: t4 can bo tiod to t3 and tho
4th 1-shot can bo used
olsowhere.
MC3480
FIGURE 7 - DELAY LINE TIME DELAY METHOD
READ/W RITE CYCLE
MC3480
RAM Controller
tl
RAS 1
t2 RAS 2
t3 RAS 3
RAS 4
t4
CAS
tS
X
Memory Clock
From MC687S
or Sultoblo
Clock Signal
MC
MC
R/W
Row
En
Ref
En
NOTE: t4 can be tied to t3 and the

4th delay element cen bo
eliminated.
MC3480
FIGURE 8 - DELAY LINE TIME DELAY (ALTERNATE METHOD)
READ /W RITE CYCLE
Memory Clock
NOTE: MC o f MC3480 is dolayod by

tw o gato delays after t l to
satisfy MC after t l Hold Tlmo.
'h(M C )-
REFRESH CONSIDERATIONS
The MC3480/MC3232A (MC3242A) memory control
system can be used with either cycle steal or transparent
refresh methods. Figure 9 shows one transparent tech
nique employing refresh during 0 2 low in an M6800
microprocessor-based system. Using this technique requires
that the memory be capable of completing a Read/Write
Cycle and a Refresh Cycle sequentially during the M6800
cycle. The minimum cycle time at the time of printing for
dynamic multiplexed RAMs is 320 ns, therefore limiting
the microprocessor to 1.56 MHz operation. The D flipflops of Figure 9 produce a trigger at the beginning of
both 01 and 02. For a 1.0 MHz system, the t1 - t 5 inputs
should be adjusted for the following delays:
the four monostables. For the 1.0 MHz system, it would

require either two 5 tap delay lines with 50 ns per tap or a
10 tap line with 50 ns/tap. For use with a 600 kHz
system, a delay line with 5 taps of 150 ns each could be
used. For this case:
RAS falls at 150 ns
Row En falls at 300 ns
CAS, R/W falls at 450 ns
t5 rises at 750 ns
Figure 10 shows typical refresh oscillator configurations
for both 32 kHz(fREFm in for4K) and 64 kHz (fREFmin
for 16K). In the case of transparent refresh, if the designer
is not concerned with power consumption, the refresh
oscillator may be eliminated and the Ref Clk input con
nected to the MC input yielding a refresh every 01.
For DMA operation combined with cycle stealing
refresh, care must be taken not to allow a DMA request
during a Refresh Request/Grant period and to hold off a
refresh during a DMA operation. See comments under pin
descriptions. Pin 19.
RA falls at 150 ns (triggered by t l )

Row En falls at 250 ns (triggered by t2)
CAS, R/W falls at 300 ns (triggered by t3)
t5 rises at 500 ns.
A delay line could be used to generate t1-t5 in place of
4-85
MC3480
FIGURE 9 - EXAMPLE OF 2 LOW METHOD OF HIDDEN REFRESH

USING MC3480 A ND4K RAMS
Row
En
Ref
En
Count
32 kHz
Otc.
Row En
A13
R/W
CE
MC
Ref En
Ref Clk
A12
A12
-I
c
a
3
3
2
RAS 1
A13
R/W In
RAS~2
RAS 3
CE
MC
MC3480
I to Dynamic M amorlet
RAS 4
CAS
Ref Req
1 Ref G rot
MC t l
R/W O ut
t2
t3
t4
tB
MC8602
IT
#1 a
R
T~
CD
6 V
y
D
JT
#2
C
_TL
p
+5 V
MC8S02
CD
Thl invertor can bo allm lnatad and tha clock

Input of " D " F lip-Flop # 2 connoctad to MC
on tha MPU But. Tha Inverter It usad to
provldo m inim um loading of the MC line when
m ultiple connections are made to that line In e
largo tyttem .
4-86
MC3480
FIGURE 10 - SUGGESTED 32 kHz OSCILLATORS
LM311
MC75140
OSCILLATOR USING ANY CMOS INVERTER
MC14SS OSCILLATOR (32 kHz COMPONENTS SHOWN)
32 or 64 kHz X T A L
^ B u ffo r
I
O utput
(32 or 64 kHz)
Rb = 9.0 k
C 1 - 0.001 ItF
4-87
MOTOROLA

Inform ation
M6800 TWO-PHASE
CLOCK G EN ERATO R/DRIVER
M6800 CLOCK GENERATOR
S C H O TTK Y M O N O L IT H IC
Intended to supply the non-overlapping 01 and <j>2 clock signals

required by the microprocessor, this clock generator is com patible
w ith 1.0, 1.5, and 2.0 MHz versions o f the MC6800. Both the
oscillator and high capacitance driver elements are included along
w ith numerous o ther logic accessory functions fo r easy system
expansion.
S ch o ttky technology is em ployed fo r high speed and PNP-buffered
inputs are employed fo r NMOS co m p a tib ility . A single +5 V power
supply, and a crystal or RC netw ork fo r frequency determ ination
P SUFFIX
CASE 648
are required.
Typical MPU System with Bus Extenders

L SUFFIX
CASE 6 20
PIN CONNECTIONS
l Vcc
MPU 01
E x t In
4 x fo
4-88
Rosot O u tp u t
l MPU 0 2
2 x fo
M em ory
Ready
Bus 0 2
I P ow or-O n Reset
G ro un d
I M e m o ry Clock
I D M A /R o f G rant
i D M A / R if Req
MC6875
ABSOLUTE M A XIM U M RATINGS (Unless otherwise noted TA 25C.)

Rating
Input Voltage
Ceramic Package
Plastic Package
Ceramic Package
Plastic Package
Symbol
Value
V cc
V|
+7.0
+5.5
ta
0 to +70
Unit
Vdc
Vdc
C
C
T$tg
-65 to +150
-55 to +125
C
Tj
175
150

Rating
Symbol
Value
VCc
+4.75 to +5.25
Unit
Vdc
ta
0 to +70
Characteristic
MPU ^1 and 0 2 Outputs
(Vcc = 4-75 V, loHM "200 pA)
(Vcc 5.25 V, loHMK +5- mA)
Bus 0 2 Output
(Vcc = ^-75 V, lOHB 10 mA)
(Vcc * 5.25 V, loHBK +s- mA)
4 x fo Output
(VCC 4.75 V, V |H 2.0 V, l 0 H4X - 500 "A*
2 x fo, DMA/Refresh Grant and Memory Clock Outputs
(Vc c 4.75 V, I o h -500 iA)
Reset Output
(VCC = 4.75 V, V IH - 3.3 V, I q h R -100 mA)
MPU 01 and 02 Outputs
(VCc = 4-75 V, l0 LM - +200 iA)
(Vcc = 4 -7S v <*OLMK " *5.0 mA)
Bus 02 Output
(Vcc =
V, loLB " ^ 8 mA)
(Vcc ^-75 V, lOLBK 5-0 mA)
4 x fo Output
(Vcc 4.75 V, V|L = 0.8 V, loL4X 16 mA)
2 x fo, DMA/Refresh Grant and Memory Clock Outputs
(Vcc = 4.75 V. I o l 16 mA)
Reset Output
(Vcc 4-75 V, V |L 0.8 V, IOL r - 3.2 mA)
Ext. In, Memory Ready and DMA/Refresh Request Inputs
Symbol
Min
Typ
If
(Unless otherwise noted specifications apply over recommended power supply and temperature ranges.
Typical values measured at V c c 5 0 v and TA 25C.)
VCC -0 .6
Max
Unit
VCC + 1 0
V
2.4
v OH4X
VOH
2.4
2.4
v OHR
2.4
v OLM
v OLMK
0.4
v OLB
v OLBK
v OL4X
V 0L
v OLR
v OHB
VOHBK
V cc + 1
V
- 1.0
V
-
0.5
- 1.0
V
0.5
0.5
0.5
V|H
2.0
VlL
OS
2.8
3.6
V
V

Input Thresholds Power-On Reset Input (See Figure 2)
Output Low to High

Output High to Low
Input Clamp Voltage
(VCC 4.75 V, l|C - -5.0 mA)
(VCC = 4.75 V, V |H 5.0 V)
Power-On Reset
(Vcc 5* V, V | h r * 5.0 V)
(VCC 5.25 V ,V | L - 0 .5 V)
Power-On Reset Input*
(Vcc 5.25 V , V | l * 0.5 V)
V ILH
V|HL
0.8
1.4
V IC
- 1.0
<IH
25
mA
|HR
50
PA
'IL
-250
mA
-250
mA
'ILR
4-89
MC6875
OPERATING DYNAMIC POWER SUPPLY CURRENT

Characteristic
Power Supply Currents
(VCC - 5.25 V. fosc 8.0 MHz. V|L - 0 V, V |H 3D V)
Normal Operation
(Memory Ready and DMA/Refresh Request Inputs at
High Logic State)
Memory Ready Stretch Operation
(Memory Ready Input at Low Logic State;
DMA/Refresh Request Input at High Logic State)
DMA/Refresh Request Stretch Operation
(Memory Ready Input at High Logic State;
DMA/Refresh Request Input at Low Logic State)
Symbol
Min
Typ
Max
Unit
>CCN
150
mA
*CCMR
135
mA
>CCDR
135
mA
(These specifications apply whether the Internal Oscillator (see Figure 9) or an External Oscillator is used (see Figure 10).
Typical values measured at V c c ~ 5.0 V, T /\ - 25C, fo - 1.0 MHz (see Figure 8).
|
Characteristic
Symbol
Min
Typ
Max
Unit
MPU 01 AND 02 CHARACTERISTICS

Output Period (Figure 3)
Pulse Width (Figure 3)
( f o - 1.0 MHz)
( f o - 1.5 MHz)
(fo - 2.0 MHz)
*o
PWM
Total Up Time (Figure 3)

( f o - 1.0 MHz)
(fo 1.5 MHz)
(fo 2.0 MHz)
Delay Time Referenced to Output Complement (Figure 3)
Output High to Low State (Clock Overlap at 1X) V)
Delay Times Referenced to 2 x fo (Figure 4 MPU 02 only)
Output Low to High Logic State
Output High to Low Logic State
Transition Times (Figure 3)
UPM
500
400
230
180
900
600
440
ns
ns
ns
*PLHM
ns
PLHM2X
tpHLM2X
85
70
ns
ns
tTLHM
*THLM
25
25
ns
nt
BUS 02 CHARACTERISTICS
Pulse Width Low Logic State (Figure 4)
( f o - 1.0 MHz)
( f o - 1.5 MHz)
(fo - 2.0 MHz)
Pulse Width High Logic State
(fo - 1.0 MHz)
(fo - 1.5 MHz)
(fo - 2.0 MHz)
Delay Times (Referenced to MPU 01) (Figure 4)
(fo IX) MHz)
(fo - 1.5 MHz)
(fo - 2.0 MHz)
(CL - 300 pF)
(Cl " 100pF)
Delay Times (Referenced to MPU 02) (Figure 4)
ns
tPWLB
430
280
210
ns
PWHB
450
295
235
480
320
240
25
tPLHBM2
tPHLBM2
-30
+25
+40
tTLHB
tTHLB
20
20
ns
tPLHBMI
tPHLBMI
20
ns
ns
ns
ns
MC6875
SWITCHING CHARACTERISTICS (continued)______________

Characteristic
MEMORY CLOCK CHARACTERISTICS

Delay Timet (Referenced to MPU 02) (Figure 4)
Delay Timet (Referenced to 2 x fo) (Figure 4)
Symbol
_________ __________ __________ _________

|
Min
Typ
Max
_________
Transition Timet (Figure 4)

Output Low to High State
Output High to Low State
Unit
+25
+40
nt
ns
65
85
nt
nt
*TLHC
*THLC
25
25
nt
nt
*PLH2X
tPHL2X
50
65
ns
nt
220
tPLHCM
tPHLCM
-60
'PLHC2X
*PHLC2X
_____________
2 x fo CHARACTERISTICS
Oetay Timet (Referenced to 4 x fo) (Figure 4)
Delay Time (Referenced to MPU 01) (Figure 4)
( f o - 1.0 MHz)
(fo - 1.5 MHz)
nt
tPHL2XM1
365

TLH2X
'THL2X
25
25
ns
ns
4 x fo CHARACTERISTICS
DelaV Times (Referenced to Ext. In) (Figure 4)
tPLH4X
PHL4X
50
30
ns
ns
Transition Time (Figure 4)

*TLH4X
*THL4X
25
25
ns
ns
Set-Up Timet (Figure 5)

Low Input Logic State
High Input Logic State
<SMRL
tSMRH
55
75
nt
ns
Hold Time (Figure 5)

HMRL
10
ns
DMA/REFRESH REQUEST CHARACTERISTICS

Set-Up Times (Figure 6)
High Input Logic State
tSDRL
SDRH
65
75
nt
ns
Hold Time (Figure 6)

l HDRL
10
ns
Delay Time Referenced to Memory Clock (Figure 6)

tPLHG
*PHLG
-15
-25
+25
+ 15
ns
ns

*TLHG
THLG
25
25
ns
ns
1000
ns
250
ns
100
50
ns
ns
MEMORY READY CHARACTERISTICS
DMAJtREFRESH GRANT CHARACTERISTICS
RESET CHARACTERISTICS
Delay Time Referenced to Power-On Reset (Figure 7)
*PLHR
PHLR
*TLHR
l THLR
DESCRIPTION OF PIN FUNCTIONS

o 4 h fo
2a Ip
DMA/RIF REQ
- A free rum** oe6Ktor n four times tfw MPU clock rateuseful tar a lyiim sync h n I. BUS#2
- Anoutputnonwfty m ptw* wit* MPU #2 ho**nMC8T26Atrpedrwecepetelirv.
- Atreerunninf osgttatofaiTwotimestf*eMPUctockret*.
o MEMORY CiOCX - An output nomineBy in M m wtth ltfU}wMck free run* during rslreshn q m i cyds
- An asynchronous input weed to frww de ItfU docks in tfte #1 Im^ , #2 low tut* lor PONIRON RtSlt - A SchMtt tngjer input wfticfc controls React. A capacitor to round nqumd to Ml the
dynamic memory >efietf>or cyclettoal DMA (Direct Msmory Access),
dwfid time oomtant. Internal 80 k resistor to Vq. See Qtmnl Owfn ^mjwtiBm tor
____
Manual Raeat Operation.
o RfF GRAMT
- A tywlvonoui output gnd to syndtrortio 9m refre* or DMA operation to 9m U
MEMORY REAOY - An nyndwonMi taput wed to fro*** the MPU c*ockin*e+1 Ion#9hirsute for slow o KISET
- An output to the MPU end I/O dmeai.
memory interface.
XI. X2
- Provision to attach a series resonant crystal or RC network.
o fttPU#1
- Capefeteof drMflf the#1 end#2 inputson two MCGdOOs.
o xT tN
- Allows drMnf by an external TTL sifnal to synchroniM the MPU to an external system.
UPU42
4-91
MC6875
FIGURE 1 - BLOCK DIAGRAM
4 x fo
2 x fo
?(4)
? ( 5)
_ ( 1>
f Rf l
T Q
T Q
1(9)
E xt
In
Memory Clock
R (1 5 )
M smory Ready O
___________ (
(6 )
O Q
S
27
T O
s a
- > 0 ^ 0 BUS 0 2
'- = C |
s a
Reset (14)
O utput O
n o
s a
r*
VCc
MPU 01
-O MPU 0 2
(13)
-p
10)
O M A /R ofrojh O
Roquest
90 k
- C
R Q
(11)
O O MA/Refrm h
Grant
Pin 16 - +5.0 V o lti

Pin S - Gnd
Power-On Reset O ( 12)
FIGURE 2 - TYPICAL HYSTERESIS CHARACTERISTIC

OF RESET FUNCTION
FIGURE 3 - TIMING DIAGRAM FOR

MPU 01 AND 02
V0. OUTPUT VOLTAGE IVOLTS)
1
1
VfT * 5.0 V
25>
C
T
i1
Cl-------------- ------- ------- ------- ------- -------------- ------- ------0

1.0
2.0
3.0
4.0
5.0
V|. INPUT VOLTAGE (VOLTS). P0WER-0N RESET PIN
*THLM 2
V q v " 1*0 v " Clock Ovorlep
mcoturemont point
MC6875
FIGURE 4 - TIMING DIAGRAM FOR NON-STRETCHED OPERATION

{Memory Ready and DMA/Refresh Request held high continuously)
Ext. In Input Voltage: 0 V to 3.0 V, f 8.0 MHz, Duty Cycle SOX, t r | , H E X *THLEX " 6.0 R*
OM A/Rofroth Grant
(Low)
4-93
MC6875
FIGURE S - TIMING DIAGRAM FOR MEMORY READY STRETCH OPERATION

(Minimum Strrtch Shown)
Input Voltag*: 3.0 to 0 V. tjH LM R *TLHMR 5.0 m
MPU 01
v cc
"'PWMR '
Vcc
M e m o ry
Clock
OMA/Refreth Grant
1.8 V j *
tpwMR ~
(Low)
4-94
1.5 V
MC6875
FIGURE 6 -T IM IN G DIAGRAM FOR DMA/REFRESH REQUEST STRETCH OPERATION

(Minimum Stretch Shown)
Input Vottag*: 3.0 to 0 V. tXHLDR TLHDR s- "*
4-95
MC6875
FIGURE 7 - POWER ON RESET

Input Voltage: 0 to 5.0 V. f 100 kHz Pulse Width "1 .0 M, *JLH *THL 2S ns
FIGURE 8 - LOAD CIRCUITS

For MPU 01 and MPU <7>2
For Bus <t>2
T o Sc op e
Inp u t
T o O u tp u t
Pin
"o
-w v RLH
20 k
, AM d io d e s are 1 N 9 1 6
o r e q u iv a le n t
MPU 01 C L - 35 pF, R q - 20 n
MPU 02 C L - 70 pF, R q - 15 n
For 4 x fo, 2 x fo. Memory Clock and DMA/Refresh Grant
For Reset Output
* L o a d capacitanco includot fixtu re and prob o capacitance
4-96
MC6875
GENERAL
The MC6875 Clock Generator/Driver should be located
on the same board and within two inches of the MC6800
MPU. Series damping resistors of 10-30 ohms may be
utilized between the MC6875 and the MC6800 on the 01
and 02 clocks to suppress overshoot and reflections.
The V c c Pin fpin *16) of the MC6875 should be
bypassed to the ground pin (pin 8) at the package with a
0.1 /uF capacitor. Because of the high peak currents
associated with driving highly capacitive loads, an ade
quately large ground strip to pin 8 should be used on the
MC6875. Grounds should be carefully routed to minimize
coupling of noise to the sensitive oscillator inputs. Unnec
essary grounds or ground planes should be avoided near
pin 2 or the frequency determining components. These
components should be located as near as possible to the
respective pins of the MC6875. Stray capacitance near
pin 2 or the crystal, can affect the frequency. The can of
the crystal should not be grounded. The ground side
of the crystal or the C of the R-C oscillator should be con
nected as directly as possible to pin 8.
Unused inputs should be connected to V c c or ground.
Memory Ready, DMA/Refresh Request and Power-On
Reset should be connected to V c c when not used.
The External Input should be connected to ground
when not used.
Af0, FREQUENCY CHANGE (X)
FIGURE 9 - TYPICAL RC FREQUENCY verms VOLTAGE
ô. FREQUENCY CHANGE (*)
FIGURE 10 - TYPICAL RC FREQUENCY

versus TEMPERATURE
OSCILLATOR
A tank circuit tuned to the desired crystal frequency
connected between terminals X j and X 2 as shown in
Figure 12, is recommended to prevent the oscillator from
starting at other than the desired frequency. The 1kft
resistor reduces the Q sufficiently to maintain stable
crystal control. Crystal manufacturers may recommend a
capacitance (C l) to be used in series with the crystal for
optimum performance at series resonance.
See Figures 9 and 10 for typical oscillator temperature
and V cc supply dependence for R -C operation.
TA. TEMPERATURE CC)
C, CAPACITANCE (pF)
FIGURE 11 - TYPICAL FREQUENCY versus
5 6 7 8 9
)0
4 X fo, FREQUENCY (MHz)
4-97
MC6875
TA B LE 1 - OSCILLATOR COMPONENTS
TANK CIRCUIT
PARAMETERS
APPROXIMATE
CRYSTAL PARAMETERS
CTS KNIGHTS
400 REIMANN AVE.
SANDWICH, IL
60648
(81SI786-8411
McCOY ELECT. CO.

WATTS a CHESTNUTS STS.
MT. HOLLY SPRING, PA
TYCO CRYSTAL PRODUCTS

3940 W. MONTECITO
PHOENIX, A2
(717) 488-3411
(602) 272-7948
PF
RS
Ohms .
Co
PF
Cl
mpF
fo
MHz
10
ISO
15-75
3-6
12
4.0
MP-04A
* 390 pF
113-31
4.7
82
8-45
4-7
23
8.0
MP-080
47 pF
113 -32
lt
(*H
cT
150-3260
150-3270
Inductors may Im obtained from: Collcrtft, Cry, I t 00013 (312) 0392381

FIGURE 13
To precisely time a crystal to desired frequency, a

variable trimmer capacitor in the range of 7 to 40 pF
would typically be used. Note it is not a recommended
practice to tune the crystal with a parallel load capaci
tance.
The table above shows typical values for C j and L j,
typical crystal characteristics, and manufacturers' part
numbers for 4.0 and 8.0 megahertz operation.
The MC6875 will function as an R-C oscillator when
connected as shown in Figure 13. The desired output
frequency (M01) is approximately:
Formula
320
C in picofarads
4 x fo a*:
C (R+ .27) + 23
R in K ohms
4 x fo in Megahertz
(See Figure 11)
a solid V o l output level until V c c has reached 3.5 to

4.0 V. During this time transients may appear on the
dock outputs as the oscillator begins to start. This
happens at approximately Vpc a 3 V. A t some Vcc level
above that, where Reset Output goes low, all the clock
outputs will begin functioning normally. This phenom
enon of the start-up sequence should not cause any
problems except possibly in systems with battery back-up
memory. The transients on the clock lines during the
time the Reset Output is high impedance could initiate
the system in some unknown mode and possibly write
into the backup memory system. Therefore in battery
backup systems, more elaborate reset circuitry will
be required.
_____________
Please note that the Power-On Reset input pin of the
MC6875 is not suitable for use with a manual MPU reset
switch if the DMA/Ref Req or Memory Ready inputs are
going to be used. The power on reset circuitry is used to
initialize the internal control logic and whenever the
input is switched low, the MC687S is irresponsive to
the DMA/Ref Req or Memory Ready inputs. This may
result in the loss of dynamic memory and/or possibly
a byte of slow static memory. The circuit of Figure 14
is recommended for applications which do not utilize the
DMA/Ref Req or Memory Ready inputs. The circuit of
Figure 15 is recommended for those applications that do.
FIGURE 14 - M A N U A L RESET FOR APPLICATIO NS NOT USING
DM A/REFRESH REQUEST OR MEM ORY R E AD Y INPUTS
VCc
Rotot
14
It would be desirable to select a capacitor greater than

15 pF to minimize the effects of stray capacitance. It is
also desirable to keep the resistor in the 1 to 5 k Q,
range. There is a nominal 270 2 resistor internally at
X i which is in series with the external R. By keeping
the external R as large as possible, the effects due to
process variations of the internal resistor on the frequency
will be reduced. There will, however, still be some
variation in frequency in a production lot both from
the resistance variations, external and internal, and
process variations of the input switching thresholds.
Therefore, in a production system, it is recommended
a potentiometer be placed in series with a fixed R
between X i and X2____
POWER-ON RESET
As the power to the MC6875 comes up, the Reset
Output will be in a high impedance state and will not give
40
8
8
s
Manual Rasat Switch

FIGURE 15 - M A N U A L RESET FOR SYSTEMS USING
DY NA M IC RAM OR SLOW STATIC RAM IN CONJUNCTIO N
WITH M EMORY R EAD Y OR DM A/REFRESH REQUEST INPUTS
4-98
MC6880A
MC8T26A
(M ) MOTOROLA
This device may be ordered under

either of the above type numbers.
QUAD THREE-STATE BUS TRANSCEIVER

This quad three-state bus transceiver features both excellent MOS
or MPU c o m p a tib ility , due to its high impedance PNP transistor
inp u t, and high-speed operation made possible by the use o f Schottky
diode clamping. Both the - 4 8 m A driver and 20 m A receiver o u t
puts are short-circuit protected and em ploy three-state enabling inputs.
The device is useful as a bus extender in systems em ploying the
M 6800 fa m ily or other comparable MPU devices. The m axim um
inp u t current o f 200 juA at any o f the device inp u t pins assures
proper operation despite the lim ite d drive capability o f the MPU
chip. The inputs are also protected w ith S chottky-barrier diode
clamps to suppress excessive undershoot voltages.
The M C 8T26A is identical to the N E 8T 26A and it opeiates from
a single +5 V supply.
High Impedance Inputs
Single Power Supply
QUAD THREE-STATE
BUS TRAN SCEIVER
M O N O L IT H IC S C H O TTK Y
IN T E G R A T E D C IR CU ITS
J
L S U F F IX
CASE 620
High Speed S ch o ttky Technology
Three-State Drivers and Receivers
C om patible w ith M6800 Fam ily Microprocessor
P S U F F IX
CASE 648
M IC R O P R O C E S SO R BUS E X T E N D E R A P P L IC A T IO N
(Clock)
02
G N D *5 V 01
P IN C O N N E C T IO N S - M C 6 8 8 0 A
M C 8T26A
---- 1 Recotvor
1 * | O u tp u t
To] Bus 3
---- - D river
9 | In p u t
4-99
MC6880A, MC8T26A
MAXIMUM RATINGS (TA 25C unleu otherwise noted.)

Rating
Symbol
Value
VCC
8.0
Vdc
Input Voltage
V|
S.S
Vdc
Ceramic Package
Plastic Package
Tj
ta
Storage Temperature Rangs
Tstg
Unit
C
175
150
0 to +75
-65 to+150
C
UC
ELECTRICAL CHARACTERISTICS (4.75 V < Vcc < SJS V and 0C < T a < 75C unless-otherwise noted.)
Characteristic
Input Current - Low Logic State
(Receiver Enable Input, V||_(r e ) - 0.4 V)
(Driver Enable Input. V||_(DE) * 0.4 V)
(Driver Input. Vj(_(Dl 0.4 V)
(Bus (Receiver) Input. V| |_(b) 0 -4 V)
Input Disabled Current Low Logic State
(Driver input, V|(_(q ) = 0.4 V)
Symbol
Min
'lL(RE)
'lL(DE)
* 1LID)
'IL(B)
'IL(D) DIS
Input Current-High Logic State

(Receiver Enable Input, V | h (RE) * 5.25 V)
(Driver Enable Input, V | h ( q e ).= 5.25 V)
(Driver Input. V | h ( q ) 5.25 V)
(Receiver Input, V | h ( b ) 5.25 V)
11HIRE)
'IH(DE)
'IH(D)
>IH(B)
Input Voltage - Low Logic State

(Receiver Enable Input)
(Driver Enable Input
(Driver Input)
(Receiver Input)
(Driver Enable Input)
(Driver Input)
(Receiver Input)
Output Voltage - Low Logic State
(Bus Driver) Output, Io l (B) 48 mA)
(Receiver Output, >OL(R) = 20 mA)
Output Voltage - High Logic State
(Bus (Driver) Output, lo H ( B ) "
(Receiver Output, lo H ( R ) -2 .0 mA)
(Receiver Output, I o h (R ) -1 0 0 iiA, Vcc 5.0 V)
Typ
Max
-200
-200
-200
-200
mA
-25
MA
IiA
Unit
25
25
25
100
v 1LIRE)
VIL(DE)
VIL(D)
V|L(B)
_
-
0.85
0.85
0.85
0.85
V IH(RE)
V IH(DE)
V|H(D)
V IH(B)
2.0
2.0
2.0
2.0
v OL(B)
vOL(R)
0.5
0.5
v OH(B)
v OH(R)
2.4
2.4
3.5
3.1
3.1
-
_
-
100
100
mA
Output Disabled Leakage Current - High Logic State

(Bus Driver) Output, Vqh(B) 3 2-4 V)
(Receiver Output, V q h (R) 2.4 V)
'OHL(B)
'OHL(R)
Output Disabled Leakage Current Low Logic State

(Bus Output, V q l (B) 0.5 V)
(Receiver Output, V o l (R) 0-5 V)
'OLL(B)
'OLL(R)
-10 0
-10 0
mA
V|C(DE)
V|C(RE)
VIC(D)
- 1.0
- 1.0
- 1.0
'OS(B)
'OS(R)
-50
-30
mA
cc
-150
-75
87
Input Clamp Voltage

(Driver Enable Input I| d (d e ) 12 mA)
(Receiver Enable Input l|C(RE) " +12 mA)
(Driver Input l|C(D) 12 mA)
Output Short-Circuit Current, Vcc * 5-25 V <11
(Bus (Driver) Output)
(Receiver Output)
<VCC - 5.25 V)
(1) Only one output may be short-circuited at a time.
4 -1 GO
mA
MC6880A, MC8T26A
SWITCHING CHARACTERISTICS (Unless otherwise noted, specifications apply at T/^ 25C and V j c 5.0 V)
Symbol
Figure
Min
Max
Unit
Propagation Delay Time from Receiver (Bus) Input to

High Logic State Receiver Output
Propagation Delay Time from Receiver (Bus) Input to
Low Logic State Receiver Output
Propagation Delay Time from Driver Input to
High Logic State Driver (Bus) Output
*PLH(R)
14
ns
tPHL(R)
14
ns
*PLH(D)
14
ns

Low Logic State Driver (Bus) Output
*PHL(D)
14
ns
Propagation Delay Time from Receiver Enable Input to

High Impedance (Open) Logic State Receiver Output
Propagation Delay Time from Receiver Enable Input to
Low Logic Level Receiver Output
tPLZ(REI
15
ns
tPZL(RE)
20
ns
Propagation Delay Time from Driver Enable Input to

High Impedance Logic State Driver (Bus) Output
tPLZ(DE)
20
ns
Propagation Delay Time from Driver Enable Input to

Low Logic State Driver (Bus) Output.
tPZL(DE)
25
ns
Characteristic
FIGURE 1 - TEST CIRCUIT AND WAVEFORMS FOR PROPAGATION DELAY FROM

BUS (RECEIVER) INPUT TO RECEIVER OUTPUT, t p L H ( R ) AND t p H L (R )
4*101
MC6880A, MC8T26A
FIGURE 2 - TEST CIRCUIT AND WAVEFORMS FOR PROPAGATION DELAY TIME FROM
DRIVER INPUT TO BUS (DRIVER) OUTPUT. tpLH(D) AND tpHL(D)
Input
Input Pula Frequency 10 MHz
Duty Cycto - 50%
Output
RECEIVER ENABLE INPUT TO RECEIVER OUTPUT. t p L Z ( R E ) AND t PZL(RE)
4-102
MC6880A, MC8T26A
FIGURE 4 - TEST CIRCUIT AND WAVEFORMS FOR PROPAGATION DELAY TIMES FROM
DRIVER ENABLE INPUT TO DRIVER (BUS) OUTPUT. tpLZ(DE) AND tpZL(DE)
Input
O utput
FIGURE 5 - BIDIRECTIONAL BUS APPLICATIONS
Racaivar
O utputs
Racaivar
O utputs
Orivar
Inputs
Drivar
Inputs
Drivar
E nab la
4-103
MC6881
MC3449
MOTOROLA

TRIPLE BI-DIRECTIONAL BUS SWITCH
The M C 6881/3449 is a three channel, non-inverting, bi-directional
Bus Extender. It is designed to a llow the bi-directional exchange o f
T T L level digital in fo rm a tio n between a selected pair o f ports in a
three p o rt netw ork. A ll three ports o f each channel may be forced to
a high impedance co nd itio n through that channel's Enable input.
Port pair selection and listener/talker status fo r the three channels
is determined through the C on tro l and Select inputs. A ll inputs are
PNP buffered, M6800 F am ily com patible, and protected w ith
Schottky-B arrier diode clamps to suppress undershoot voltages.
BI-DIRECTIONAL
BUS EXTENDER/SW ITCH
A summary o f M C 6881/3449 features include:
Three Channels
N on-Inverting Data Exchange
Bi-Directional Operation
A ctive Pull-Up w ith Three-State Capability
T T L C om patible
High Speed S ch o ttky Technology
P S U F F IX
P L A S T IC P AC K A G E
CASE 648
L S U F F IX
CASE 620
TRU TH TABLE
Single Power Supply
Enable
Select
C o n tro l
Data F lo w
2 * 3
3 *2
1 *3
3 -0
X - D o n 't Care
4-104
High Im pedance
MC6881, MC3449
MAXIMUM RATINGS (Unless otherwise noted TA - 25C.)

Symbol
Value
Unit

Input Voltage
vcc
Vdc
V|
7.0
5.5
ta
0 to +70
Tstg
-65 to +150
c
c
Rating
Junction Temperature Range

Ceramic Package
Plastic Package
Vdc
Tj
175
150
ELECTRICAL CHARACTERISTICS (VCq 4.75 to 6.25 Volts and Ta 0 to +70C unlew otherwise noted.)
Characteristic
(V|L " 0.4 V)
(V |H - 2.7 V)
(V |H 5.25 V)
Input Ctamp Voltage
(l|C " -1 8 m A )
(lOL - 8 .0 mA)
(lOH -400 mA)
Output Disabled Leakage Current
(V0 Z " 0.4 V)
(V 0 2 " 2.7 V)
(Voz " 5.25 V)
Output Short Circuit Current
Crosstalk Current Low Logic State
(V|h 2.4 V on Node 3. opposite node selected
V | l " 0 4 V on node tested)
Crosstalk Current High Logic State
(V ||, Oil V on Node 3, opposite node selected
V | h 2.4 V on node tested).
(V|H 2.4 V, Vcc = 5.25 V)
Symbol
Min
-
Typ
Max
Unit
0.8
Vdc
V|L
V|H
2.0
Vdc
lU
-100
MA
40
Vdc
>iA
'IH
VlC
100
-IS
VoL
**
OS
VOH
2.7
-40
40
-20
-55
mA
XL
-4 0
jjA
'XH
40
*i A
70
mA
*PLH
tPHL
30
24
tN
DIS
18
MA
'OZ
100
os
ice
SWITCHING CHARACTERISTICS (Vcc 5-0 V and T/y 25C unless otherwise noted.)
Propagation Delay Times Nodes 1 ,2 ,3
Low-to-High Output
High-to-Low Output
Enable Delay Times
Disabled to High or Low-Logic State
High or Low-Logic State to Disabled
Select Delay Times
Third-State to High or Low-Logic State
High or Low-Logic State to Third-State
Control Delay Times
Third-State to High or Low-Logic State
High or Low-Logic State to'Third-State
ns
ns
-
10
25
25
25
25
ns
*ON
*OFF
ns
ON
tOFF
MC6881, MC3449
PROPAGATION DELAY TIME TEST CIRCUITS AND WAVEFORMS

FIGURE 1 - NODE TO OUTPUT
To 'Scop*
(Output)
V Cc
Enable Gnd
^5,1 k
Generator
1N916
S e le c t - V |H
or
C ontrol - Gnd
Equivalent NcKfo2. 0pen
130 pF!
Total Including
Probe*, etc.
f - 1.0 MHz
D uty Cycle 50%
Propagation Delay - Node 1 to 3 Shown; - 3 to 1, 2 to 3 and 3 to 2 To*tod Similarly.
* T L H - t T H L " 5- n*
Nodo 1
Input
0 V
Vo h O utput
*PLH
Input Pul*o C haracterlttlct

*PHL
VO L-
1 1.0 MHz, 50% D uty Cycle
1.5 V
t T L H " t T H L 5-0 n*
A ll voltage* referenced to Gnd.
FIGURE 2 - THIRD-STATE
To 'Scopo
(O utput)
1N914
or
Equivalent
15 pF :
Pulte
Generator
V CC
f - 1.0 MHz
D uty Cycle 50%
*T L H " TH L B- n*
Nodo 3 thown under te tt;

Other* totted ilm ltarly.
TEST TABLE
4-106
Control
Select
V |L
V |L
V |H
V |H
Enable
Pulte
Pulte
Node 1
Test
V il
V |H
*EN /*D IS
* e n / * d is
MC6881, MC3449
FIGURE 3 - TIMING DIAGRAM
4 -1 07
Note 1: Data I* transmitted to o nly 1 o f the 3 ports. Which p o rt acts as an o u tp u t doponds
on logic state o f the select and control pins when the channel is enabled.
Note 2: A port choson to act as the o u tp u t is oither high or low, depending on the logic
state o f the p o rt choson to be the input.
Note 3: Tho arrow indicates the diroction o f data flo w . Each buffe r is non-inverting, so
data maintains the same logic stote through the buffer.
Note 4: *ON * tf>0 tim e fro m th ird state to active (high or low) state;
tQ F F 11 tlm o fro m active to th ird state.
TRUTH TABLE
Enable
Select
C ontrol
Data Direction (Note 3)
X
0
0
1
1
X
0
1
0
1
A ll Ports are High-Z

Port 2 -Port 3
Port 3 - Port 2
Port 1 -* Port 3
Port 3 - Port 1
0
0
0
0
MC6881, MC3449
FIGURE 4 - TYPICAL l0 L * * * V q l
TYPICAL APPLICATION
FIGURE S - TWO MPUs SHARING A COMMON MAIN-MEMORY
ADDRESS AN D
4-108
MC6882A/MC3482A
MC6882B/MC3482B
<> MOTOROLA

either o f the above type numbers.
Advance In fo rm atio n
OCTAL THREE-STATE
B U FFER/LATCH
OCTAL THREE-STATE BUFFER/LATCH

This series o f devices combines
desirable in bus-oriented systems: 1)
fo u r features usually found

High impedance logic inputs
in s u re
th a t
these devices do
n o t seriously
load
the
bus; 2) Three-state logic configuration allows buffers n o t being
utilize d
to
be effe ctive ly
removed fro m the bus; 3) S chottky
technology allows fo r high-speed operation;
4) 48
mA
drive
capability.
Inverting and N on-Inverting Options o f Data
SN74S373 F unction Pinouts
Eight Transparent Latches/Buffers in a Single Package
Full Parallel-Access fo r Loading and Reloading
Buffered C ontrol Inputs
A ll Inputs Have Hysteresis to Improve Noise Rejection
High Speed 8.0 ns (Typ)
Three-State Logic C onfiguration
Single +5 V Power Supply Requirement
C om patible w ith 74S Logic or M6800 Microprocessor Systems
High Impedance PNP Inputs Assure M inimal Loading o f the Bus
IN P U T E Q U IV A L E N T
C IR C U IT
O U T P U T E Q U IV A L E N T
C IR C U IT
4-109
MC6882A, B, MC3482A, B
M AXIM UM RATINGS H a 25C unless othgrwiso notad.)

Rating
Symbol
Value
Vcc
8.0

Input Voltage
Storage Temperature RangeOperating Junction Temperature
Plastic Package
Ceramic Package
5.5
0 to +75
-6 5 to +160
V|
Ta
Tftn Tj
Unit
Vdc
Vdc
C
~*C
C
150
175
ELECTRICAL CHARACTERISTICS (Unless otharwise noted, 0C < T A < 7 5 C and 4.7S V < Vcc < S . 2S V)
Characterbtie
Input Voltage High Logic Stata
(Vcc 4.75 V ,T A -2 5 C )
Symbol
Min
Typ
Max
V |H
2.0
Unit
V
V|L
- '
0.8
IH
40
fxA
IL
-2 50 *
*iA
V0 H
2A
VOL
Input Voltage Low Logic Stata

(V cc " 4.75 V .T a -2SCJ
(VCC 5.25 V, V |H - 2.4 V)
Input Current Low Logic Stata
(Vcc " 5.25 V. V |L - 0.6 V ,V |L (OE) 0.5 V )
Output Voltage High Logic Stata
(VCC 4.75 V, Iq H -2 0 mA)
(lOL 48 mA)
Output Current High Impedance State
(VCC 5.25 V. V0 H - 2.4 VI
(Vcc 5.25 V. V0 L " 0.6 V)
(Vcc 5.25 V, V q 0) (only one output can be shorted at a time)
MC6882A/MC3482A
(VCC 5.25 V)
MC6882B/MC3482B
Input Clamp Voltage
(Vcc 4.75 V. 1|K -1 2 mA)
0.5
100
-100
os
-3 0
-8 0
-130
mA
cc
130
150
mA
V IK
- 1.2
|iA
oz
SWITCHING CHARACTERISTICS (Vcc * 5.0 V, T a * 2SC unlew othcrwiia noted.)

Characteristics
MC6882A/
MC3482A
Symbol
Min

Data to Output
Low to High
CL 50pF
Cl 250 pF
Cl - 375 pF
CL - 500 pF
High to Low
Cl *50 pF
CL 250 pF
Cl 375 pF
CL 500 pF
Latch Disable (Low to High)
to Output
Low to High
Cl - S 0 p F
High to Low
CL 50pF
(CL 20 pF)
High Output Level to High Impedance
Low Output to High Impedance
High Impedance to High Output
High Impedance to Low Output
MC6882B/
MC3482B
Max
Typ
Min
Typ
Unit
Max
ns
tPLH(D)
10
21
12
20
tPHL(D)
8.0
17
10
18
ns
*PLH(L)
-
17
22
19
17
7.0
18
7.0
18
8.0
12
IS
9.0
tPHL(L)
ns
tPHZ(OS)
*PLZ(0E)
tPZH(SE)
tPZL(GE)
4-110
MC6882A, B, MC3482A, B
AC SETUP CHARACTERISTICS (VCc S.0 V. TA 25C unless otherwise noted.)

Characteristic
MC6882B/
MC3482B
MC6882A/
MC3482A
Symbol
Unit
Min
Typ
Max
Min
Typ
Max
Setup Time
(Data to Negative Going Latch Enable)
tsu(D)
ns
Hold Time
(Data to Negative Going Latch Enable)
h(D)
11
11
ns
Minimum Latch Enable Pulsa Width

(High or Low)
*W(L)
is
15
ns
PIN CONNECTIONS AND TRUTH TABLES
MC6882A/MC3482A
MC8882B/MC3482B
j
J
O utput r j "
Enablo L _
2 0 ] V CC
o u tp u t r r
Enoble 1__
20]
v cc
O ut 1 ^
T 9] O ut 8
Out 1 ^
19]
O ut 8
In 1 [ 7
18] In 8
In 1 [ T
In 2 [*4~
T t ] In 7
In 2 | T
O ut 2 ^
T 7 | O ut 7
Out 2 Q T
O ut 3 |~6*
i s ] O ut 6
O ut 3 [~i~
18] In 8
T T j In 7
S'
T j ] Out 7
T i ] O ut 6
In 3 [~7
l l | In 6
In 3 p 7
14]
In 4 ^
13| In 5
In 4 [ T
1 3] In 5
O ut 4 ^
O ut 5
O ut 4 1~9*
T 2 ] O ut 6
7 7 | Latch
Gnd [To
111 Latch
12 ]
Gnd [To
k h
In 6
Output
Enable
Latch
Input
Output
Output
Enable
Latch
Input
Output
0
1
0
1
0
1
0
X
X
X
Qo
Z
0
1
0
X
0
1
X
X
Qo
z
MC6882A, B, MC3482A, B
FIGURE 1 - TEST CIRCUIT FOR SWITCHING CHARACTERISTICS
FIGURE 2 - WAVEFORMS FOR PROPAGATION DELAY

TIMES DATA TO OUTPUT
--------- 3 V
To Scope
O utput
To Scopo (Input)
Input or
Closod for
*PLZ(5E ). tP Z L(oE ) only
*5 V
---
1k
WV*
10 k
Cj_ Includes Probe and
Jig Capacitance
Input
*PHUD)-
*W r-0
1N3064
or Equivalent
PulM
Generstorl
1.5V
1.5 V
-tP LK (O )
V qh
O utput
MCS382A/MC3482A
VOL
tP L H (D )-
O utput
MC6882B/MC3482B
Closed for
*PHZ(OE),*PZH(6E) only
-*P H L (D )
v OH
Input Pulse Conditions

*TH L 1 *TLH < 5 ns
1-1.0 MHr
FIGURE 3 - WAVE FORMS FOR AC SETUP AND

LATCH DISABLE TO OUTPUT DELAY

TIMES - OUTPUT ENABLE TO OUTPUT
MC6885/MC8T95
MC6886/MC8T96
MC6887/MC8T97
MC6888/MC8T98
(M ) MOTOROLA
HEX TH R EE-STATE BUFFER INVERTERS

This series o f devices combines three features usually found
desirable in bus-oriented systems: 1) High impedance logic inputs
insure th a t these devices do n o t seriously load the bus; 2) Three-state
logic co nfig u ra tion allows buffers not being utilize d to be effectively
removed from the bus; 3) S ch o ttky technology allows high-speed
operation.

HEX THREE-STATE
B U FFER /IN VER TER S
The devices d iffe r in th a t the non-inverting M C8T95/M C6885

and inverting M C 8T96/M C 6886 provide a tw o -in p u t Enable w hich
controls all six buffers, w hile the non-inverting MC8T97/M C6887
and inverting M C 8T 98/M C 6888 provide tw o Enable inputs one
c o n tro llin g fo u r buffers and the other co ntro llin g the remaining
tw o buffers.
The units are w ell-suited fo r Address buffers on the M6800 or
sim ilar m icroprocessor application.
High Speed 8.0 ns (Typ)

Three-State Logic C onfiguration
Single +5 V Power Supply Requirement
C om patible w ith 74LS Logic or M 6800 Microprocessor Systems
High Impedance PNP Inputs Assure M inim al Loading o f the Bus
INPUT EQ UIV A LE N T
CIRC UIT
MICROPROCESSOR BUS EXTENDER APPLICATION

(C lo ck)
G N D +5 V 01
02
OUTPUT EQ U IVA LEN T

C IRC UIT
4-113
MC6885-88, MC8T95-98
PIN CONNECTIONS AND TRUTH TABLES

MC688S/MC8T9S
Enable
MC6886/MC8T96
W ------
----------
-------- W -----------
Enable
1 3 v cc
Input A f T
75] Enable 2
O utput A [~3~
14| Input F
Input S [ 7
Input A
O utput A
13] O utput F
Input B
12] Input E
O utput B a
Input C
To] Input O
O utput C [ T
Gnd fa~
Enable 2
O utput B
77] O utput E
Input C fT *
O utput C
Gnd
~9*| O utput O
E
E
E
E
E
E
E
E
16] VCC
7 i ] Enable 2
14]
In p u tF
13]
O utpu t F
12 ]
Input E
77] O utput E
i p ] Input O
T | O utpu t O
Enable 1
Input
O utput
Enable 2
Enable 1
Input
O utput
L
L
H
L
H
L
H
X
X
X
L
H
L
L
L
H
H
L
L
H
L
H
L
H
X
X
X
Z
Z
Z
L
L
L
H
H
Z
z
z
MC6887/MC8T97
MC6888/MC8T98
------
- \ J --------i f ] v cc
Enable 4 [T *
- O
On
Enable 4
Input A [ T
rO
O utput A [ T
15]
Enable 2
Input B [*4~
O utput A
O utput F
12 ]
O utput B |~6~
&
O utput C ^
Input E
Input
Output
L
H
X
L
H
Z
L
H
Z
X
&
13] O utput F
12 J Input E
77] O utput
Gnd | jT
Enable
L
L
H
Rating
Input Voltage
Symbol
Value
V cc
V|
ao
5.5
ta

Plastic Package
Ceramic Package
Tsta
Tj
0 to +75
*65 to +150
150
175
4-114
~fl~| O utpu t O
Input
Output
L
H
X
H
L
Z
MAXIMUM RATINGS (T A 2SC unless otherwise noted.)

ip ] Input O
O utput C [ T
- Low Logic State

High Logic State
T hird (High Impedance) State
Irrelevant
7 s] Enable 2
14] Input F
Input C J T
S I O utput O
L
L
H
[7
O utput B [ T
I p ] Input 0
Enable
r O
Input B |~4~
771 O utput E
Gnd [ T
is] vcc
Input A [ 7
14] in put F
Input C ^
H
L
Unit
Vdc
Vdc
C
C
C
MC6885-88, MC8T95-98
ELECTRICAL CHAR ACTERISTICS (Unlaw otherwise noted. 0C < T A < 75C and 4.75 V < V Cc < 5 .2 5 V)
Symbol
Min

(Vc c - 4.75 V. T a 25C)
V|H
2.0

(VCC - 4.75 V. TA 25CI
(VCC * 5-25 V, V |H 2.4 V)
(Vcc 5 25 V. V |L = 0.5 V, V |L(E) 0.5 V)
Input Current High Impedance State
(VCC * 5.25 V. V |L(|) 0.5 V. V IH(E|- 2-0 V)
Vcc * 4-75 V. Iq h '5-2 mA)
(lOL 48 mA)
Output Current - High Impedance State
VCC * 5.25 V. V0 H 2.4 V)
(VCC 5 25 V. V0 L 0.5 V)
(VCC 5.25 V. V 0 = 0)
(only one output can be shorted at a time)
(VCC * 5 25 V)
MC8TS5. MC8T97. MC6885. MC8887
MC8T96, MC8T98, MC8886. MC6888
VlL
Characteristic
>IH
Unit
Max
TVP
0.8
40
(iA
-400
-40
<iA
"
>IL
'
'IH(E)
"
VOH
2.4
VOL
0.5
V
(iA
'o z
'OS
40
-40
-40
-80
- II S
65
59
98
89
-1.5
1.5
-1.5
mA
mA
Ice
Input Clamp Voltage

(VCC 4.75 V. l|C = -12m A)
Vic
Output Vcc Clamp Voltage

(Vcc 0. IOC * 12 mA)
Output Gnd Clamp Voltage
( V c c 0. l o c *12mA)
Voc
Voc
5.5
Input Voltage
(If - 1.0 mA)
V|
SWITCHING CHARACTERISTICS (Vcc S.O V TA - 25C unlew otherwise noted.)

&IC8T96/88
MC6886/88
MC8T9S/97
MC688S/87
Characteristic
Propagation Delay Time High to Low State
. (Cl 50 pF)
<CL 250 pF)
(Cl "3 75 pF)
(Cl 500 pF)
Propagation Delay Time Low to High State
(Cl 50 pF)
(CL - 250 pF)
(Cl * 375 pF)
<CL - 500 pF)
Transition Time High to Low State
<CL - 250 pF)
(CL - 37S pF)
(Cl 500 pF)
Transition Time Low to High State
(CL " 250 pF)
(CL " 375 pF)
(Cl 500 pF)
Symbol
Min
Typ
Max
Min
Typ
Min
3.0
-
16
12
4.0
-
11
20
IS
18
23
22
3.0
-
25
33
42
10
3.0
-
Unit
nt
*PHL
----
ns
tRLH
13
- -
22
28
35
10
13
IS
28
38
53
RS
*THL
-
10
11
14
32
42
60
RS
TLH
-
4-115
MC6885-88, MC8T95-98
SWITCHING CHARACTERISTICS (Vcc *S.O V . T a * 25C unlaw otherwise noted.)

MC8T95/97
MC6885/87
Characteristic
MC8T96/88
MC6886/88
Symbol
Min
Typ
Max
Min
Typ
Max
Unit
Propagation Delay Time High State to Third State

(Cl - 5.0 pF)
PHZ(E)
3.0
10
3.0
10
ns
Propagation Delay Time - Low State to Third State

(Cl 5.0 pF)
Propagation Delay Time - Third State to High State
(CL 50pF)
tPLZ(E|
3.0
12
5.0
16
ns
PZH(E)
8.0
25
7.0
22
ns
PZL(E)
12
25
11
24
ns
Propagation Delay Time - Third State to Low State

(CL 5 0 p F )

TIMES INPUT TO OUTPUT
FIGURE 1 - TEST CIRCUIT FOR SWITCHING CHARACTERISTICS
V------------------ 3 V
To Scope
O utput
To Scope (Input)
1.5 V
r l. 5 V
------ 0 V
*PLH4
----- ' v OH
Open fo r tp 2 H (E ) Test Only
Input or
-14
cL
Pulse
GoneratorT
JL
P H L -
5 V
W r-O
O utput
200
MC8T90, MC6888
MC8T98 or MC6888
1N3064
or Equivalent
- 1 .5 V
V0 L
---- W Sr
1.0 k \ , Open fo r
J * IP Z LfE ) Test Only
C|_ Includes Prol

Jig Capacitance
1.5 V
*P LH
Output
MC8T9S, MC6885
MC8T97 or MC6887
- J
' 1.5 V
*PHL
VOL
Input Pulse Conditions

*TH L *TLH ** 10 n*
I - 1.0 MHz
FIGURE 3 - WAVEFORMS FOR PROPAGATION DELAY TIMES - ENABLE TO OUTPUT

3.0 V
Enable
*PZL(E)
E) J
O utput
VOL
3 .0 V
Enable
0O utput
Vq l
*PLZ(E)
-3 .0 V
Enable
1.5 V
0
*PZH(E1"
- VOH
jh
H Hlgh-Loglc State, L Low-Logic State, Z - High Impedance State
4-116
V0 H
r - 1.5 V
O utput
MC6885-88, MC8T95-98
FIGURE 4 - ADDRESS MULTIPLEXER FOR 16-PIN 4K NMOS MEMORY
4-117
MC6889
MOTOROLA
MC8T28
NON-INVERTING
QUAD THREE-STATE BUS TRANSCEIVER
This quad three-state bus transceiver features both excellent MOS
or MPU co m p a tib ility , due to its high impedance PNP transistor
inp u t, and high-speed operation made possible by the use o f Schottky
diode clamping. Both the -4 8 m A driver a n d -2 0 m A receiver outputs
are sh ort-circu it protected and em ploy three-state enabling inputs.
The device is useful as a bus extender in systems em ploying the
M6800 fa m ily or other comparable MPU devices. The maxim um
in p u t cu rren t o f 200 ^ A at any o f the device inp u t pins assures
proper operation despite the lim ite d drive capability o f the MPU
chip. The inputs are also protected w ith Schottky-barrier diode
clamps to suppress excessive undershoot voltages.
Propagation delay times fo r the driver p o rtio n are 17 ns maximum
w hile the receiver p o rtio n runs 17 ns. The MC8T28 is identical to
the N E8T28 and it operates fro m a single +5 V supply.
Single Power Supply
High Speed S chottky Technology
Three-State Drivers and Receivers
C om patible w ith M 6800 F am ily Microprocessor
N on-Inverting
NON-INVERTING
BUS TRAN SCEIVER
M O N O L IT H IC S C H O TTK Y
P S U F F IX
CASE 648
M ICR O PRO CESSO R BUS E X T E N D E R A P P L IC A T IO N

(C lock)
G N D *5 V 01
02
PIN C O N N E C T IO N S - M C 6889
M C 8T28
4-118
MC6889, MC8T28
MAXIMUM RATINGS (Ta * 2^C unless otherwise noted.)

Rating
Input Voltage
Ceramic Package
Plastic Package
Symbol
Value
Unit
Vcc
V|
8.0
Vdc
5.5
Vdc
C
Tj
Ta
Tstg
175
150
Oto +75
-65 to+150
C
bc
ELECTRICAL CHARACTERISTICS (4.75 V < V c c < 5-25 v and 0C < T a < 7SC unless otherwise noted.)
Characteristic
(Receiver Enable Input, V||_(RE) * 0.4 V)
(Driver Enable Input, V||_(q E) * 0.4 V)
(Driver Input, V|L(D) " 0.4 V)
(Bus (Receiver) Input, V||_(b ) 0.4 V)
Input Disabled Current Low Logic State
(Driver Input, V | l ( d ) 0.4 V)
Symbol
Min
Typ
Max
Unit
iL(RE)
'IL(DE)
'IL(O)
'IL(B)
-200
-200
-200
-200
liA
-25
MA
mA
'lL(D) DIS
Input Current-High Logic State

(Receiver Enable Input, V | h (RE) 5.25 V)
(Driver Enable Input, V | h (d E)- 5.25 V)
(Driver Input, V | h (D) * 5.25 V)
(Driver Enable Input
(Driver Input)
(Receiver Input)
'IH(RE)
'lK(DE)
'IH(D)
25
25
25
VlL(RE)
VlL(DE)
v lC(D)
V|L(B)
0.85
0.85
0.85
0.85

(Driver Enable Input)
(Driver Input)
(Receiver Input)
V IH(RE)
V|H(DE)
V|H(D)
V|H(B)
2.0
2.0
2.0
2.0
0.5
0.5
2.4
2.4
3.5
3.1
3.1
-
100
100
>i A
mA

(Bus Driver) Output, loL(B)
mA)
(Receiver Output, loL(R) 20 mA)
(Bus (Driver) Output, Iq h (B) -1 0 mA)
(Receiver Output, Iq h (R) -2 .0 mA)
(Receiver Output, I o h (R) " 100 mA, V cc 6.0 V)
v OL(B)
VOL(R)
v OH(B)
VOH(R)
Output Disabled Leakage Current - High Logic State

(Bus Driver) Output, V q h (B) 2.4 V)
(Receiver Output. V o h (R) 2.4 V)
'OHL(B)
'OHL(R)
Output Disabled Leakage Current Low Logic State

(Bus Output, V o l (B) 0.5 V)
(Receiver Output. V o l (R) 0.5 V)
'OLL(B)
'OLL(R)
-100
-100
V|C(DE)
V|C(RE)
V|C(D)
- 1.0
- 1.0
- 1.0
'OS(B)
'OS(R)
ice
-50
-30
-150
-75
mA
110
mA
Input Clamp Voltage

(Driver Enable Input l|D(DE) 12 mA)
(Receiver Enable Input l|C(RE) +12 mA)
(Driver Input l|C(D) 12 mA)
Output Short-Circuit Current, Vcc * 6.25 V
(Bus (Driver) Output)
(Receiver Output)
(VCC - 5.25 V)
(1) Only one output may be short-circuited at a time.
4-119
MC6889, MC8T28
SWITCHING CHARACTERISTICS (Unless otherwise noted. Vcc 6.0 V and TA * 25C)

Characteristic
Max
Unit
PLH(R)
tPHUR)
17
17
ns
Propagation Delay TimeDriver (C|_ 300 pF)
PLH(D)
*PHL(D)
17
17
ns
Propagation Delay Tlme-Enable (Cl 30 pF)

Receiver
tPZL(R)
PLZ(R)
23
18
ns
Propagation Delay Time-Raceivsr (Cl 30 pF)
Driver Enable (Cl 300 pF)
Symbol
tPZL(D)
tpLZ(D)
Min
_
-
FIGURE 1 - TEST CIRCUIT AND WAVEFORMS FOR PROPAGATION DELAY FROM

BUS (RECEIVER) INPUT TO RECEIVER OUTPUT, t p L H ( R ) AND tpHL(R)
28
23
MC6889, MC8T28
DRIVER INPUT TO BUS (DRIVER) OUTPUT, t p L H ( D ) AND tpHL(D)
Input
Input Pulls Frequency 10 MHz
D u ty Cycle 50%
O utput
RECEIVER ENABLE INPUT TO RECEIVER OUTPUT. t p L Z ( R E ) AND t PZL(RE)
In p u t Pul to Frequency 5.0 MHz

D u ty Cycle - 50%
4-121
MC6889, MC8T28
FIGURE 4 - TEST CIRCUIT AND WAVEFORMS FOR PROPAGATION DELAY TIMES FROM
DRIVER ENABLE INPUT TO DRIV 6R (BUS) OUTPUT. tpL2(DB) AND tpzL(DE)
FIGURE S - BIDIRECTIONAL BUS APPLICATIONS
Driver
E nab Is
4-122
R c c th u r
Enabl*
MC6890
MOTOROLA
FO R CO M P LETE D A T A
S E E P A G E 8 61
P ro d u c t P r e v ie w
BUS-COMPATIBLE
8-BIT MPU D-TO-A CONVERTER
The MC6890 is a self-contained, bus-compatible, 8-bit

(0.19% accuracy) D-to-A converter system capable of interfac
ing directly with 8-bit microprocessors.
Available In both commercial and military temperature
ranges, this monolithic converter contains master/slave
registers to prevent transparency to data transitions during ac
tive enable; a laser-trimmed, low-TC, 2.5 V precision bandgap
reference; and high-stability, laser-trimmed, thin-film resistors
for both reference input and output span and offset control.
A reset pin provides for overriding stored data and forcing lout
to zero.
1 / 2 LSB N on lin e a rity

A vailable in M ilita ry Tem perature Range
D irect Data Bus Link

Low Power: 130 m W Typ
Fast S ettlin g Tim e: 140 ns Typ
S ingle Enable: 10 ns M ax Data Hold
Time
S elf-C ontained 2 .5 -V Precision Laser-Trim m ed Voltage
Reference (M ay A lso Be Used Externally)
Reset Pin to O verride Data

O u tp u t Voltage Ranges: +5.0, +10, +20, or
2 .5 , 5 .0 , 1 0 V olts
8 -B IT
B U S -C O M P A T IB L E
M PU DAC
L SU FFIX
CASE 732
PIN C O NN EC TIO NS
(MSBI 07 [7
0 6 (T
0 5 (T
77] Rel In
D4 (T
77] Analog Gnd
03 (7
E ] 20 V Span
D2 (T
TT] 10 V Span
Ref Out
01 [7
T ] lout
DO [ 7
l Bipolar
i l l Offset
Roset [7
77] Enable
Digital Gnd [To
4-123
El vcc
77] V EE
MOTOROLA

Inform ation
QUAD MOS CLOCK DRIVER
QUAD MOS CLOCK DRIVER
OR HIGH-VOLTAGE, HIGH-CURRENT NAND DRIVER
SILICON M O N O LIT H IC
IN TE G R A T E D C IR CU ITS
The MC75365 is intended fo r driving the highly capacitive A d

dress, C ontrol and Tim ing inputs on a variety o f MOS RAMs such as
the "1 1 0 3 " and " 7 0 0 1 " types. It is designed to operate from the
M T T L 5.0 V power supply and the VgS and VgB power supplies
used w ith the memories in most applications. Operation is re
commended at V q C3 VCC2 + 3 V, but the part is useable over a
w ide latitude o f supply voltages. V cC 2 may t>e tied dire ctly to
V cC 3 ' n many conditions.
Pin Compatible w ith Intel 3207 and Interchangeable w ith T. I.
SN75365
M TT L and M D T L Compatible, Diode-Clamped Inputs
Two Common Enable Inputs per Gate Pair
Low Standby Power Consum ption Transient
Capable o f D riving High Capacitive Loads
Fast Switching Operation
L S U F F IX
C E R A M IC P AC KA G E
CASE 620
P S U F F IX
P LA S T IC P AC KA G E
CASE 648
PIN C O N N E C TIO N S
TRU TH TABLE
IN P U T
1
O U TP U T
H
L
1
1
H
1
L
1
H
1
1
L
L
H
H
H
Whore:
H
High Logic State
L & L o w Logic State
I I Irre le van t
4-124
MC75365
TYPICAL APPLICATION
with "1103" Type 1 K RAM
5 .0 V
19.5 V
16 V
5.0 V
M A X IM U M RATINGS (T ^ = 25C unless otherwise noted)

Symbol
Value
Unit
Vcci
VCC2
V CC3
V|
-0.5 to 7.0
-0.5 to 25
-0.5 to 30
5.5
Input Differential Voltage (see Note 1)
V|D
5.5
Power Dissipation (Package Limitation)

Ceramic Package @ T ^ = 25C
Derate above T /\ * 25C
Pd
RflJA
1000
6.6
raW
mW/C
mW
mW/C
Rating
Input Voltage
Plastic Package @ T/^ 25C

Derate above T/v 25C
PD
830
Ceramic Package @ T q = 25C

Derate above T c m25C
Pd
t/R o je
3.0
Plastic Package @ T q = 25C

pd
20
1.8
1/RgjC
14
Watts
mW/C
0 to 70
ta
Ceramic Package
Plastic Package
Tj
Tstg
6.6
Watts
mW/C
C
175
150
-65 to +150
Note 1. This is the differential voltage between any two inputs to any single gate.

Characteristic
Difference between V q c 3 end V c c 2

Operating Temperature Range
Symbol
Min
Typ
Max
Unit
V CC 1
VCC2
VCC3
V C C3VCC2
4.75
4.75
VCC2
5.0
5.25
24
28
0
0
4.0
10
70
Ta
4-125
20
24
MC75365
ELECTRICAL CHARACTERISTICS (Unless otherwise noted T a 25PC, Vqc 1 - 5.0 V, V c c 2 " 20 V, V cc3 24 V,
Cl = 200 pF, Rq 24n, See Figures 1 and 2.)
Characteristic
Symbol
Min
Typ*
Max
Unit
V|H
2.0
VlL
v ie
0.8
Input Clamp Voltage

( l|C -12m A )
1.5
1.0
mA
40
80
-1.0
-2.0
-1.6
-3.2
Input Current Maximum Input Voltage

(V |H 5.5 V)
>IH1

(V |n (1) 2.4 V)
<V|H (2) or V |H (3) 2.4 V)
1IH 2

(V||_(1> = 0 .4 V)
(V |L (2) or V |L C3> = 0.4 V)
il
MA
mA
-

(VCC3 VcC2 + 3 0 V, V| L - 0.8 V. I q h = -100 jiA)
(VCC3 V CC2 + 3-0 V, V|i_ - 0.8 V, I q h -10 mA)
(VCC3 VcC2- V IL 0.8 V, I q h "50 #<A)
(VCC3 = VcC2> V IL 0.8 V, I q h "10 mA)
(V | l 0 V, lo c 20 mA)
(V|H 2.0 V, Io l 10 mA)
(15 V < V cc3 < 28 V, V |H 2.0 V. I q l 40 mA)
Power Supply Currents Outputs High Logic State
(Vcci 5-25 V, VCC2 " 24 V. VCC3 28 V.
V ||. 0 V, Iq h = 0 mA)
V
v OH1
VOH2
VOH3
v OH4
Voc
Power Supply Currents - Output Low Logic State

(V c c i 5.25 V, VcC2 24 V, VcC3 28 V
V|H " 5.0 V, I o l 0 0 mA)
Power Supply Currents Standby Condition
(Vcci 0 0 V, VCC2 24 V. VCC3 24 V
V|H 5.0 V , I q l 0 0 mA)
VCC2 -0.1
V cc2 -0.9
VCC2 -0 '7
V CC2 -1
-
V CC2 +1-8
V
V
VOLI
V0 L2
>CC1(H)
4.0
-2.2
2.2
47
2.5
25
0.25
0.5
0.15
0.25
0.3
0.5
mA
>CC2(H)
'CC3(H)
(Vcci 5.25 V. VCC2 24 V, VCC3 24 V

V |L " 0 V, loH 0 mA)
VCC2 O-3
VCC2 -1-2
V cc2 1 0
VCC 2 "2^
-
>CC2(H)
<CC3(H)
8.0
-3.2/+0.25
3.5
0.25
0.5
mA
CCUL)
>CC2(L)
'CC3ID
31
16
>CC2(S)
>CC3(S)
mA
Typical Values at 25C, V c c i " 5.0 V. VCC2 = 20 V and VCC3 24 V
SWITCHING CHARACTERISTICS (Unless otherwise noted T a 11 25C. VCC1 5.0 V, V CC2 20 V, VCC3 24 V.
C|_ = 200 pF ,R q 24n, See Figures 1 and 2.)
Characteristic
Symbol
Min
Delay Time, Low to High State Output

Delay Time, High to Low State Output
PLH
1PHL
tDLH
DHL
10
10
-
Transition Time, Low to High State Output

Transition Time, High to Low State Output
*TLH
*THL
Propagation Delay Time, Low to High State Output

Propagation Delay Time, High to Low State Output
Typ
31
30
Max
Unit
48
46
ns
11
10
20
18
ns
20
20
33
33
ns
VOH. OUTPUT VOLTAGE - HIGH

LOGIC STATE (VOLTS)
v o l . o utput v o lta g e
- low
LOGIC STATE (VOLTS)
Ioi_, OUTPUT CURRENT - LOW LOGIC STATE (mA)

Vo h . OUTPUT VOLTAGE - HIGH
LOGIC STATE (VOLTS)
f, FREQUENCY (MHz)
MC75365

versus OUTPUT CURRENT

versus OUTPUT CURR ENT
MC75365

FIGURE 7 - PROPAGATION DELAY TIME LOW TO HIGH STATE OUTPUT
versus AMBIENT TEMPERATURE
FIGURE 8 - PROPAGATION DELAY TIME HIGH TO LOW STATE OUTPUT

versus AMBIENT TEMPERATURE
40
40
cl
200 iF
cl
-200 pF
i 30
Cl 50 )F
Cl 50 pF
<
S
< 1
a
5 5
Vci 1 5 . IV \ CC2 = 20 V
VCC3 * 24 V
Rd *
vcc 1 - s.c V V :c2 s o v

VCC3 24 V
HD = 240
Ml
I
0
20
I
40
I
60
20
T a . AMBIENT TEMPERATURE (C)
II II
40
60
80
Ta . AMBIENT TEMPERATURE <C)
FIGURE 9 - PROPAGATION DELAY TIME

LOW TO HIGH STATE OUTPUT
versus V CC 2 SUPPLY VOLTAGE
PLH. PROPAGATION DELAY TIME

-OW TO HIGH STATE OUTPUT (ns)

HIGH TO LOW STATE OUTPUT
versus V CC2 SUPPLY VOLTAGE
VCC2. SUPPLY VOLTAGE (VOLTS)
FIGURE 11 - PROPAGATION DELAY TIME LOW TO HIGH LOGIC STATE

versus LOAD CAPACITANCE
PLH. PROPAGATION DELAY TIME-LOW

TO HIGH STATE OUTPUT (ml
FIGURE 12 - PROPAGATION DELAY TIME HIGH TO LOW STATE OUTPUT

versus LOAD CAPACITANCE
4-128
MC75365
APPLICATIONS SUGGESTIONS
R0JC - thermal resistance, junction to case
R0CA~ thermal resistance, case to ambient
R0JA ~ thermal resistance, junction to ambient.
POWER CONSIDERATIONS
Circuit performance and long-term circuit reliability are
affected by die temperature. Normally, both are improved
by keeping the integrated circuit junction temperatures
low. Electrical power dissipated in the integrated circuit
is the source of heat. This heat source increases the
temperature of the die relative to some reference point,
normally the ambient temperature. The temperature in
crease depends on the amount of power dissipated in the
circuit and on the net thermal resistance between the
heat source and the reference point. The basic formula
for converting power dissipation into junction temper
ature is:
Power Dissipation for the MC75365 MOS Clock Driver:

The power dissipation of the device (P q ) is dependent
on the following system requirements: frequency of op
eration, capacitive loading, output voltage swing, and
duty cycle. The variation of power dissipation with
frequency and load capacitance for the MC75365 is
illustrated in Figure 6. The power dissipation, when
substituted into equation (2), should not yield a junction
temperature, T j, greater than Tj(m ax) at the maximum
encountered ambient temperature. Tj(m ax) is speci
fied for two integrated circuit packages in the maximum
ratings section of this data sheet.
With these'maximum junction temperature values, the
maximum permissible power dissipation at a given
ambient temperature may be determined. This can be
done with equations (1) and (2) .and the maximum
thermal resistance values given in Table 1 shown on
the following page.
T j = T a + PD (R0JC + R0CA)
or
T J T A + Pd (R0JA>
(2)
where
T j = junction temperature
T a = ambient temperature
Pq = power dissipation
4-129
MC75365
TABLE 1 - THERMAL CHARACTERISTICS

OF "L " AND "P PACKAGES
PACKAGE TYPE
(Mounted in Socket)
RfljC <C/W)
Still Air
RflJA (C/W>
Still Air
TYP
MAX
"L" (Ceramic Package)
150
*'P" (Plastic Package)
ISO
This gives approximately a 60% increase in maximum

power dissipation over the power dissipation which is
allowable with no heat sink.
MAX
100
100
TYP
50
27
70
40
FIGURE 1 4 - CASE TEMPERATURE RISE ABOVE

AMBIENT versus POWER DISSIPATED USING
NATURAL CONVECTION
If the power dissipation determined by a given system

produces a junction temperature in excess of the recom
mended maximum rating for a given package type, some
thing must be done to reduce the junction temperature.
ThWe are two methods of lowering the junction tem
perature without changing the system requirements.
First, the ambient temperature may be reduced suf
ficiently to bring T j to an acceptable value. Secondly,
the RflCA term can be reduced. Lowering the RflCA
term can be accomplished by increasing the surface1
area of the package with the addition of a heat sink or by
blowing air across the package to promote improved
heat dissipation.
Heat Sink Considerations:
PO. POWER OISSIPATEO (WATTS)
Heat sinks come in a wide variety of sizes and shapes that

will accomodate almost any IC package made. Some of
these heat sinks are illustrated in Figure 13.
Forced Air Considerations:
FIGURE 13 - THERMALLOY* HEAT SINKS
As illustrated in Figure 15, forced air can be employed to

reduce the R0j a term. Note, however, that this curve is
expressed in terms of typical RflJA rather than maximum
R0JA- Maximum R0JA can be determined in the fol
lowing manner:
From Table 1 the following information is known:
(a)
(b)
Since:
6012B
M a n u fa c tu re d by T h e rm allo y Co. o f Toxa*.
<3)
R0CA = R0JA - R0JC
(4)
Therefore, in still air

R0CA(typ) = 100C/W - 27C/W = 73C/W
From Table 1, R0JA(max) for the ceramic package

with no heat sink and in a still air environment is
150C/W .
For the following example the Thermalloy 6012B type
heat sink, or equivalent ischosen. With this heat sink, the
R0 CA for natural convection from Figure 14 is 44C/W.
From Table 1 Rgjc(m ax) = 50C/W for the ceramic
package.
Therefore, the new R 0 JA (m ax) with the
6012B heat sink added becomes:
R flJA(m ax) = 50C/W + 44C/W = 94C/W .
Thus the addition of the heat sink has reduced R0JA
(max) from 150C/W down to 94C/W . With the heat
sink, the maximum power dissipation by equation (2)
at T a 55 +70C is:
175C - 70 C
R0JA R0JC + R0CA

Then:
6007A
PD =
RflJA(tYP) = 100C/W
Rfl jc (ty p ) = 27C/W
From Curve 1 of Figure 14 at 500 LFPM and eq

uation (4),
R0CA(tYP) - 53C/W - 27C/W = 26C/W .
Thus R0CA(tVP) has changed from 73C/W (still air) to
26C/W (500 LFPM), which is a decrease in typical
R0CA tv a ratio of 1:2.8. Since the typicai value of
R0CA was reduced by a ratio of 1:2.8, R0 CA(max> of
100C/W should also decrease by a ratio of 1:2.8.
This yields an R0CA(ma*) at 500 LFPM of 36C/W .
Therefore, from equation (3):
R0JA(max) = 50C/W + 36C/W = 86C/W .
Therefore the maximum allowable power dissipation at
500 LFPM and T a a +70C is from equation (2):
= 1.11 watts.
175C - 70C
+94C/W
PD =
4-130
86C/W
= 1.2 watts.
MC75365
Given data from Table 1:

typical RflJA = 100C/W
typical RflJC = 27C/W
From Curve 2 of Figure 15, RgJA(typ) 's 75C/W for a
PC mount and no air flow. Then the typical R flC A 's
75C/W - 27C/W = 48C/W . From Table 1 the typical
value of RflCA f r socket mount is 100C/W 27C/W
= 73C/W . This shows that the PC board mount results
in a decrease in typical R0CA by a ratio of 1:1.5 below
the typical value of R 0C A in a socket mount. Therefore,
the maximum value of socket mount RflCA f 100C/W
should also decrease by a ratio of 1:1.5 when the device
is mounted in a PC board. The maximum RflCA be
comes:
FIGURE IS - TYPICAL THERMAL RESISTANCE (Rflj A) OF

"L " PACKAGE versus AIR VELOCITY
201----------L---------1----------1---------- 1---------- ---------- ---------- ----------
200
400
600
800
1000
1200
1400
1600
100C/W
R0CA = ------------ --- 66C/W for PC board mount
1.5
AIR VELOCITY (LINEAR FEET PER MINUTE)
Heat Sink and Forced A ir Combined:

Some heat sink manufacturers provide data and curves of
R0CA f r still a'r ancl forced air such as illustrated in
Figure 16.
For example the 6012B heat sink has an
R0CA 17C/W at 500 LFPM as noted in Figure 15.
From equation (3):
Max R fljA = 50C/W + 17C/W = 67C/W
From equation (2) at T a = +70C
175C - 70C
Pn = -------------------- 1.57 watts.
67C/W
FIGURE 16 - THERMAL RESISTANCE R0CA
versus AIR VELOCITY
Note from Table 1 and Figure 15 that if the 16-pin

ceramic package is mounted directly to the PC board
(2 oz. cu. underneath), that typical R#j a is considerably
less than for socket mount with still-air and no heat sink.
The following procedure can be employed to determine
the maximum power dissipation for this condition.
Therefore the maximum RflJA for a PC mount is from

equation (3).
Rfl j a 50C/W + 66C /W = 116C/W .
With maximum R0JA known, the maximum power dis
sipation can be found.
If T a ** 70C then from
equation (2) the maximum power dissipation may be
found to be 905 mW.
In most cases, heat sink manufacturer's publish only
R0CA socket mount data.
Although data for PC
mounting is generally not available, this should present
no problem. Note in Figure 15 that an air flow greater
than 250 LFPM yields a socket mount R0j a approxi
mately 6% greater than for a PC mount. Therefore, the
socket mount data can be used for a PC mount with a
slightly greater safety factor. Also it should be noted
that thermal resistance measurements can vary widely.
These measurement variations are due to the dependency
of R0CA of the Wpe environment and measurement
techniques employed. For example, R0CA would be
greater for an integrated circuit mounted on a PC board
with little or no ground plane versus one with a sub
stantial ground plane. Therefore, if the maximum cal
culated junction temperature is on the border line of
being too high for a given system application, then
thermal resistance measurements should be done on the
system to be absolutely certain that the maximum
junction temperature is not exceeded.
MOTOROLA
DUAL MECL-to-MOS
DRIVER
DUAL MECL-to-MOS DRIVER
The M C 75368 is a dual M ECL-to-M O S driver and interface c ircuit.

The device accepts standard M ECL 10,000 and IBM groundedreference ECL input signals and creates high-current and high-voltage
o u tp u t levels suitable fo r driving MOS circuits. Specifically, it may
be used to drive address, co n tro l, and tim ing inputs fo r several types
o f MOS RAMs. The device may also be used as a M E C L-to-M T TL
translator.
The M C 75368 is o ptim ized fo r higher voltage capability.
L SUFFIX
CASE 632
T O -116
Dual M ECL-to-MO S Driver

Dual M E C L-to-M T T L Driver
Versatile Interface C ircu it fo r Use Between MECL and HighC urrent, High-Voltage Systems
FIGURE 1 - TYPIC AL APPLICATIO N WITH 7001 1K NMOS RAM
O u tp u t Enable
A2
M C 75 36 8
A3
I
I L
P S U F F IX
CASE 646
Data
O u tp u t
(M EC L
M a trix of
7001
1 0 .0 0 0 )
FUNCTION TABLE
Input Voltage Conditions
W rite Enable
Latch
Enable
Differential
(M ore p ositive o f
A o r B) -C
( V , D > 150 m V )
M C 34 61 Dual Sense A m p lifie r
Logic Level
Output
A B C
L
H
H
H
L
H
L
H
L
(-1 5 0 m V < V 1D <

150 m V )
X X X
(V ,D < -1 5 0 m V)
H high logic level, L = lo w lo gic level,

X irre le va n t
4-132
L
In d e te r
m inate
H
MC75368
MAXIMUM RATINGS (Unless otherwise noted, voltages measured with respect to GND terminals, T a 25C.)
Value
Symbol
Rating
Unit
Vcci
VCC2
-0.5 to 7.0
-0.5 to 22
Vdc
Vdc
VCC3
-0.5 to 30
-8.0 to 0.5
-0.5
Vdc
-8.0 to 0.5
5.5
-5.0
Vdc
Vdc
Vdc
V ee
Most Negative of V^ci. VCC2>or VCC3 v*ith

respect to Vee
Input Voltage
Inter-Input Voltage! 1)
Most negative Input Voltage with respect to Vee
V, - VEE

Ceramic Package @T a *25C
Derate above T a " 25C
Plastic Package @T a 25C
Derate above Ta 25C
Ceramic Package @Tp 25C
Derate above T(; = 2BC
Plastic Package @Tg 2SC
Derate above Tq 2SC
Pd
1/Roja
Pd
1/RflJA
Pd
1/R0JC
Pd
1/Rejc

Tstg
V|
Vdc
Vdc
1000
6.6
830
6.6
3.0
20
1.8
14
mW
mW/C
mW
mW/C
Watts
mW/C
Watts
mW/C
C
C
Oto 70
-65 to 150
ta
(1) With respect to any pair of inputs to either of the input gates.

Characteristic
Power Supply Voltages -
Symbol
Vcci
Vcc2
VCC3
VCC3' VCC2
vee
ta
Min
4.75
4.75
VCC2
0
-4.68
0
Max
5.25
22
28
10
-5.72
70
Unit
V
V
V
V
V
C
-0.7
V | h -150
-
V
mV
mV
mV
Typ
5.0
20
24
4.0
-5.2
DEFINITION OF INPUT LOGIC LEVELS

Input Voltage High Logic State (Any Input) (1)
Input Voltage Low Logic State (Any Input) (1)
Input Differential Voltage High Logic State (2)
Input Differential Voltage - Low Logic State 42)
V|H
VlL
V|DH
V|DL
-1.5
vee
150
-150
(1) The definition of these Logic Levels use Algebraic System of notation.
(2) The input differential voltage is measured from the more positive inverting input (A or B) with respect to the non-inverting
input (C) of the same g8te.
4-133
MC75368
ELECTRICAL CHARACTERISTICS (Unless otherwise noted, specifications apply over recommended power supply and temperature
ranges. Typical values measured at
Vcci 5-0 V, VEE-5.2 V, T a 25C and VcC2 20,
V C C 3 -2 4 V .1
Characteristic
(Vcc3 " VCC2 + 3- V, V io l
-150 mV, l0H -100 nA)
(Vcc3 Vgc2 + 3 0 v < v IOL
-150 mV, Ioh * -10 mA)
(VcC3 Vcc2* V|DI_ -150 mV,
OH -50 fiA)
VCC3 VCC2* V |d l -150 mV,
OH "10 mA)
(V id h 150 mV, Io l 10 mA)
(V|oh 150 mV, Io l 30 mA)
10 V < Vcc3 < 22 V
10 V < VCC2 < 28 V
(V|DH - 500 mV, loc * 20 mA)
(VEE = -5.72 V, V|L " -5.72 V,
V|H -0.7 V)
(V|H -0.7 V, V|l -2.0 V)
<VEE = -5.72 V. V|H -0.7 V.
V|L -5.72 V)
Power Supply Current Both Outputs
High Logic State
(VCC 5.25 V, VCC2 - 22 V,
VCC3 26 V
VEE 5.72 V,
V |L (A) and (B) " 2 0 V,
T V|H(C) -0 7 V, IOH 0)
Power Supply Current Both Outputs
Low Logic State
(VCC1 - 5.25 V, VCC2 22 V.
VCC3 28 V, V ee -5.72 V,
V|H(A)and (B)-"0.7 V,
V|L{C) -2.0V , lO L-0 )
Min
Typ
Max
VoHI
VCC2' 0.3
VCC2 0.1
V0 H2
VCC 2-1 2
VCC2 0.9
--
VOH3
VcC2 * I-0
VcC2 0.7
v OH4
VCC2-2.3
VCC2"1
v OL1
V0 L2
0.15
0.3
0.2
-
0.4
V0 C
IlH
300
800
IL1
IL2
-10
-100
'CCI(H)
21
CC2(H)
CC3IH)
'EE(H)
'CCI(L)
13
24
mA
CC2(LI
0.5
1.0
mA
>CC3(L)
4.0
7.0
-38
mA
mA
Power Supply Current Stand By

Condition
(VCCi = 0 V, VCC2 " 22 V,
VCC3 - 22 V, VEE - 0 V,
V|H(A) and (B) 0.7 V,
V|L(c) -2.0 v, iq l o)
V
V
V
: n ;.
-1.1
0.6
-21
-21
'EE(L)
Power Supply Current - Both Outputs

High Logic State
<VCC1 - 5.25 V. VCC2 m22.V,
VCC3 22 V, VEE - -5.72 V,
V|L(A)and (B) -2.0V ,
v ih(c) "~o.7 v, io l o)
Unit
V
Symbol
VCC2+1-5 V
38
+0.25
! .
1.0
-38
UA
jiA
.
mA
mA
mA
mA
0.25
mA
0.25
mA
CC2l|s)
0.25
mA
CC3IS)
0.25
mA
CC2(H)
CC3(H)
4-134
MC75368
SWITCHING CHARACTERISTICS (Unless otherwise noted, V CC1 - 5.0 V. VEE - -S.2 V, TA - 25C and VCC2 - 20 V.)
Symbol
Characteristic
Delay Time - Low to High Output Logic Level
(VCC 3 = 2 4 V )
(VCC3 2 0 V )
Typ
Max
12
13
24
25
13
15
24
26
19
20
30
30
Min
Unit
ns
*DLH
-
"
Delay Time - High to Low Output Logic Level

<VCC3 24 V)
(VCC3 20 V)
DHL
Transition Time, Low-to-High Output Logic Level

(VCC 3 2 4V )
(VCC3 = 20 V)
*TLH
Transition Time, High-to-Low Output Logic Level

(V c c 3 24 V)
(VCC3 20 V)
THL
Propagation Delay Time, Low-to-High Logic Level

(VCC3 * 24 V)
(VCC3 = 20 V)
*PLH
Propagation Delay Time, High-to-Low Logic Level

(VCC3 " 24 V)
(VCC3 20 V)
*PHL
ns
4
ns
20
18
33
30
31
33
54
55
33
33
57
56
ns
ns
-
FIGURE 3 SWITCHING TIMES WAVEFORM
FIGURE 2 - SWITCHING TIMES TEST CIRCUIT
To Scops
(Inp ut) -1.3 V
ns
To Scope (Output)
V C C 2*3 0 V T
Output
(Vcc3 " VCC2>
(Includes Probe
and Jig
_L
Capacitance)
Output
The pulse generator has the
follow ing characteristics:
(Vcc3 " Vqc2 +
V)
VOL
PRR - 1 MHz. zQ BO n .
D uty Cycle - 50%
4-135
MC75368
APPLICATIONS INFO RM A TIO N ,

MODES OF OPERATION
FIGURE 4 - POSITIVENOR GATE
FIGURE S - DIFFERENTIAL MECL LINE RECEIVER

C A and/or B
C
= D ~
C o t V BB
INPUTS
A B C
CONFIGURATION
FUNCTION TABLE
CONFIGURATION
Y- C
FUNCTION TABLE
INPUTS
A B
C
A and B connoctcd
together
OUTPUT
Y
v B8
H
X
X V BB
H V BB
H H
L L
L H
L L
H L
L L
A not usod but

connected low
H
L
L
B not usod but

connectod low
OUTPUT
Y
L
H
L
H
L
H
L
H
L
H
L
H
H High Laval, L Low Lavol, X Irrolovant

V BB - Roforenco Supply voltago fo r MECL 10,000.
FIGURE 7 - USE OF DAMPING RESISTOR TO REDUCE

OR ELIMINATE OUTPUT TRANSIENT OVERSHOOT IN
CERTAIN MC7S368 APPLICATIONS
FIGURE 6 - NON-INVERTING GATE
c- D
Y - C
y
MOS
System
FUNCTION TABLE
INPUTS
CO NFIG UR ATION
A and B at V BB
A at V BB,
B connoctod low
B ot VBB,
A connoctod low
OUTPUT
Y
1
1
V BB V BB L
v Bb vBB h
L
H
I
I
Vbb
V BB
L
H
1
1
L
L
8 C
VB B L
V BB H
1
1
__ __
L
H
Note:
Rq
1
J
1 0 n to 30R (optional)
required V qq voltage source may be obtained from

MECL 10,000 Series devices such as the MC10115 line
receiver, or by connecting the output of a MECL 10,000
gate, like the MC10102, to the respective out-of-phase
inputs (as an example connect pins 4 and 5 to 2 of the
MC10102 to obtain a VgB reference voltage).
When driven differentially, the MC75368 may be used
as a differential MECL line receiver, without the need for
the V bb reference voltage.
Undesirable output transient overshoot due to load or
wiring inductance and the fast switching speeds of the
MC75368 can be eliminated or reduced by adding asmall
amount of series resistance. The value of this damping
resistance is dependent on specific load characteristics
and switching speed but typical values lie in the range of
10 to 30 ohms. This is illustrated in Figure 7.
The need for four separate power supplies V c c iVCC2<

VcC3 and V e e can be avoided in many cases by tying
VcC2 to VcC3- However, performance advantages can be
obtained by connecting either one or both V q C3 pins to an
additional power supply of higher voltage than V q c 2- Both
VcC3 P>ns do not have to be held at the same voltage. For
MECL-to-TTL level converter applications both V q C2 and
VcC3 are generally connected to a +S.0 V power source.
By providing two out-of-phase (A and B) inputs and
one in-phase (C) input, each gate can be used as positive
NOR, or as a inverting or non-inverting gate. This
flexibility is achieved by connecting an externally supplied
MECL 10,000 Series reference supply voltage (V b b ) t0
the appropriate input as shown in Figures 4 thru 6. An
unused out-of-phase input should be tied low or connected
to the other out-of-phase input of the same gate. The
4-136
<8>
MMH0026
MMH0026C
MOTOROLA

Inform ation
DUAL MOS CLOCK DRIVER
. . . designed fo r high-speed d riving of highly capacitive loads in a
MOS system.
Fast Transition Times 20 ns w ith 1000 pF Load
High O u tp u t Swing 20 V o lts
High O u tp u t C urrent Drive 1.5 Amperes
High R epe titio n Rate 5.0 to 10 MHz Depending on Load
M T T L and M D T L C om patible Inputs
Low Power C onsum ption when in MOS 0 State 2.0 mW
+5.0 -V o lt O peration fo r N-Channel MOS C o m p a tib ility
DUAL MOS
CLOCK DR IVER
G SU FFIX
M E T A L PACKAGE
CASE 601
TO-99
(T o p V ie w )
L SU FFIX
CASE 632
TO-116
NC C
D VCC
NCC
] NC
OUTPUT AC
NC C
IN P U T A C
T Y P IC A L OPERATION
(R s = 10 n . C L = Cin - 1000 pF, f *> 1.0 MHz,
PW = 500 ns, V CC = 0 V, V EE = -2 0 V)

KM M M

WUBM
nc
] OUTPUT B
D NC
D IN P U T B
NC[
] NC
V e e II
3 NC
P1 SU FFIX
PLASTIC PACKAGE
CASE 626
IMMH0026C Only)
U SU FFIX
CASE 693
+5.0 V
0 V
nnuu
(T o p V lo w )
100 n s /D IV .
4-137
MMH0026, MMH0026C
MAXIMUM RATINGS (T a
+2SC unlaw otherwise noted.)
Rating
Differential Supply Voltage
Input Current
Input Voltaae
Peak Output Current
Symbol
Value
Unit
Vcc-V ee
ll
V,
+22
Vdc
mA
Vdc
A
'Ook
Tj
Ta
MMH0026
MMH0026C
T*tg
+100
V e e + 5.5
1.5
+175
+175
U.L
-5 5 t o +125 -5 5 to +125
0 to +70
0 to +70
+150
PI
0 to +70
-65 to +150 -6 5 to +150 -65 to +150
ELECTRICAL CHARACTERISTICS (V cc-V ee " 10 V to 20 V, CL - 1000 pF, TA - -5 5 to+125Cfor MMH0028and Oto+70C

for MMH0026C for min and max values; T a +25C for all typical values unless otherwise noted.)
Characteristic
Symbol
Min
Typ
Max
Unit
_
Logic "1" Level Input Voltage
Vdc
V ee + 2.0 V e e + 1.5
V|H
Vo V e e + i .o vdc
Logic " I Level Input Current
mA
10
15
>IH
V, V e e 2.4 vdc, V o V e e + i-o vdc
Logic 0" Level Input Voltage
Vdc
V e e + o.6 v e e + o.4
V|L
V o - V c c - 1 0 Vdc
Logic 0" Level Input Current
-0.005
-10
mA
>IL
V, - V ee 0 Vdc, V o Vcc -1 .0 Vdc
Logic "0" Level Output Voltage
Vdc
v OH
Vc c +5.0 Vdc, V e e -1 2 Vdc, V| - -11.6 Vdc
4.0
4.3
V, - V e e 0.4 Vdc
v c c -1 0
Vcc 0.7
Logic "1 " Level Output Voltage
Vdc
V0 L
Vcc " S.O Vdc, V EE -1 2 Vdc. V| - -9.6 Vdc
-11.5
-1 1
V| - V e e 2.4 Vdc
v E E + 0.5 V e e + 1-0
"On" Supply Current (N otel)
30
mA
40
'CCL
V c c Vee 20 vdc. V| Vee 2.4 vdc
"Off" Supply Current
10
100
MMH0026C
VA
'CCH
V c c - Vee 20 vdc, V, Vee v
500
MMH0026
SWITCHING CHARACTERISTICS (V c c -V e e - 10 V to 20 V, CL = 1000 pF, TA 25C)

Propagation Time
High to Low
Low to High
Transition Time (High to Low)
VCC-V EE * 20 Vdc. CL = 250 pF
V cc-V ee - 20 vdc, c L = 500 pF
V c c -V ee - 20 vdc, c L = 1000 pF
Transition Time (Low to High)
V c c -V ee 20 vdc, c L - 250 pF
V c c -V ee " 20 vdc, c L 500 pF
Vcc -V e e 20 Vdc, C l - 1000 pF
(Figure 2)
(Figure 3)
(Figure 2)
(Figure 3)
tPHL
PLH
*THL
(Figure 2)
(Figure 2)
(Figure 3)
(Figure 2)
(Figure 3)
*TLH
(Figure 2)
(Figure 2)
(Figure 3)
(Figure 2)
(Figure 3)
Note 1: Tested w ith one output on at a time.
4-138
5.0
7.5
11
12
13
12
15
30
20
36
10
12
28
17
31
5.0
12
ns
15
ns
18
40
35
50
ns
16
35
25
40
MMH0026, MMH0026C
TEST CIRCUIT
FIGURE 2 - AC TEST CIRCUIT AMD WAVEFORMS
FIGURE 3 - AC TEST CIRCUIT AND WAVEFORMS
4-139
MMH0026, MMH0026C
(Vcc + 20 V, VgE 0 V. T a * +2SC unless otherwise noted.)
FIGURE 4 - INPUT CURRENT versus INPUT VOLTAGE
FIGURE 6 - SUPPLY CURRENT versus TEMPERATURE

1
9.0
----
DUTY CYCLE 20%
l|. INPUT CURRENT (mA)
Cl * I pF
,V|C-Vee
+20 V
V :c- v e e -
-25
0
+25
+50
T, TEMPERATURE (C|
+75
+100
+125
PW. OUTPUT PULSE WIDTH (nil
FIGURE 6 -O P T IM U M INPUT CAPACITANCE

versus OUTPUT PULSE WIDTH
Cl. LOAD CAPACITANCE (pF)
FIGURE 8 -PROPAGATION DELAYTIMES

versusTEMPERATURE
FIGURE 0 - TRANSITION TIMES versusTEMPERATURE
tp. PHOPAOATION OELAYTIME
VCC-VEE-20V
c l * itnopF
------T HL
------T
-75
.4-140
-50
-25
0
+25
+50
T, TEMPERATURE (C)
+75
+100
+125
MMH0026, MMH0026C
TYPICAL CHARACTISTICS (continued)

(Vcc + 20 V. Vgg 0 V, T a +25C unless otherwise noted.)
FIGURE 11 - PROPAGATION DELAY TIME versus
TEMPERATURE FOR 46 VOLT DC-COUPLED
OPERATION (See Figure 4J
ty. TRANSITION TIME (in)
FIGURE 10 - TRANSITION TIME versus TEMPERATURE

FOR 5 VOLT DC-COUPLED OPERATION (See Figure 4.)
+25
+50
T. TEMPERATURE (0C)
+75
FIGURE 12 - DC-COUPLED SWITCHING RESPONSE

versus R[ (See Figure 4.)
tTHL
. Cl * 1000 pF
Cin* 510 pF ____
V ee = OV
VCC* 1 /V
t.TIME(m)
FIGURE 13 - DC-COUPLED SWITCHING versus Cj

(See Figure 4.)
TLH
1PHL
IPIH
0 '
4.0
6.0
Rj, RESISTANCE (kn)
FIGURE 16 - AC POWER DISSIPATION versus

FREQUENCY (SINGLE DRIVER)
Po. DC POWER DISSIPATION (nW)
FIGURE 14 - MAXIMUM DC POWER DISSIPATION

versus DUTY CYCLE (SINGLE DRIVER)
Cjn. CAPACITANCE (pF)
f. FREQUENCY (MHi)
MMH0026, MMH0026C
OPERATION OF THE MMH0026
The complete circuit. Figure 1, basically creates Dar

lington devices of transistors 0 7 , 0 4 and 0 2 in the
simplified circuit of Figure 16. Note in Figure 1 that
when the input goes negative with respect to V e e > diodes
D7 through D10 turn "on" assuring faster turn "off" of
transistors 01 , 02, 0 6 and 07. Resistor R6 insures that
the output will charge to within one VgE voltage drop
of the V c c supply.
The simplified schematic diagram of MMH0026, shown

in Figure 16, is useful in explaining the operation of the
device. Figure 16 illustrates that as the input voltage level
goes high, diode D1 provides an 0.7-volt "dead zone"
thus ensuring that' Q2 is turned "on" and Q4 is turned
"off" before Q7 is turned "on". This prevents undesirable
"current spiking" from the power supply, which would
occur if Q7 and 0 4 were allowed to be "on" simul
taneously for an instant of time. Diode D2 prevents
"zenering"nf 0 4 and provides an initial discharge path
for the output capacitive load by way of 02.
SYSTEM CONSIDERATIONS
As the input voltage level goes low, the stored charge in

0 2 is used advantageously to keep Q2 "on" and 0 4 "off"
until 0 7 is "off". Again undesirable "current spiking" is
prevented. Due to the external capacitor, the input side
of Cjn goes negative with respect to VÊ causing 0 9 to
conduct momentarily thus assuring rapid turn "off"
of 07.
Overshoot:
In most system applications the output waveform of the
MMH0026 will "overshoot" to some degree. However,
"overshoot" can be eliminated or reduced by placing a
damping resistor in series with the output The amount
of resistance required is given by: Rs = 2 /U C l where
L is the inductance of the line and Cl. is the load capac
itance. In most cases a series of damping resistor in the
range of 10-to-50 ohms will be sufficient The damping
resistor also affects the transition times of the outputs.
The speed reduction is given by the formula:
FIGURE 16 - SIMPLIFIED SCHEMATIC DIAGRAM

(Rf.: Figure 1)
tT H L ** tTLH a 2.2 Rs C l (R s *the damping resistor).

Vcc
Crosstalk:
The MMH0026 is sensitive to crosstalk when the output
voltage level is high (V o ** V cc)- With the outpgt in the
high voltage level state, 0 3 and 0 4 are essentially turned
"off". Therefore, negative-going crosstalk will pull the
output down until 0 4 turns "on" sufficiently to pull the
output back towards V cc- This problem can be min
imized by placing a "bleeding" resistor from the output
to ground. The "bleeding" resistor should be of suf
ficient size so that 0 4 conducts only a few milliamperes.
Thus, when noise is coupled, 0 4 is already "on" and the
line is quickly clamped by 04. Also note that in Figure 1
D6 clamps the output one diode-voltage drop above V c c
for positive-going crosstalk.
Power Supply Decoupling:
The decoupling of V c c and Vgg is essential in most
systems. Sufficient capacitive decoupling is required to
supply the peak surge currents during switching. A t least
a 0.1-fiF to 1.0-/1F low inductive capacitor should be
placed as close to each driver package as the layout will
permit.
Input Driving:
For those applications requiring split power supplies
(V e e < GND), ac coupling, as illustrated in Figure23,
should be employed. Selection of the input capacitor
size is determined by the desired output pulse width.
Maximum performance is attained when the voltage at
4-142
MM HO026, MMH0026C
APPLICATIONS INFORMATION (continued)
TABLE 1 - THERMAL CHARACTERISTICS

OF "G". "L". "P I", AND "U " PACKAGES
the input of the MMH0026 discharges to just above the

device's threshold voltage (about 1.5 V ). Figure 6 shows
optimum values for Cjn versus the desired output pulse
width. The value for C;n may be roughly predicted by:
PACKAGE TYPE
(Mounted in Socket)
Cjn = (2 x 10 3 ) (PWo)(1)
For an output pulse width of 500 ns, the optimum value
for Cjn is:
Cin = (2 x 10 3) (500 x 1(T9)= 1000 pF.
If single supply operation is required (VE 8 GND), then
dc coupling as illustrated in Figure24cari be employed.
For maximum switching performance, a speed-up capac
itor should be employed with dc coupling. Figures 12
and 13 show typical switching characteristics for various
values of input resistance and capacitance.
'
R0JA (C/W)
Still Air
RgJC (C/W>
Still Air
MAX
TYP
MAX
TYP
"G" (Metal Package)
220
175
70
40
"L" (Ceramic Package)
1S0
ioo
50
27
"P i" (Plastic Package)
150
100
70
40
"U" (Ceramic Package)
150
100
50
27
FIGURE 17 - MAXIMUM POWER DISSIPATION w a i t

AMBIENT TEMPERATURE (As related to package)
POWER CONSIDERATIONS
Circuit performance and long-term circuit reliability are
affected by die temperature. Normally, both are improved
by keeping the integrated circuit junction temperatures
low. Electrical power dissipated in the integrated circuit
is the source of heat. This heat source increases the
temperature of the die relative to some reference point,
normally the ambient temperature. The temperature in
crease depends on the amount of power dissipated in the
circuit and on the net thermal resistance between the
heat source and the reference point The basic formula
for converting power dissipation into junction temper
ature is:
T j = T a + Pd ( r 0JC+ R.0CA)
Ta . AMBIENT TEMPERATURE (<>C)
(2)
or
Power Dissipation for the MMH0026 MOS Clock Driver:
With these maximum junction temperature values, the

maximum permissible power dissipation at a given
ambient temperature may be determined. This can be
done with equations (2) or (3) and the maximum thermal
resistance values given in Table 1 or alternately, by using
the curves plotted in Figure 17. If, however, the power
dissipation determined by a given system produces a
calculated junction temperature in excess of the recom
mended maximum rating for a given package type, some
thing must be done to reduce the junction temperature.
The power dissipation of the device (Pq ) is dependent

on the following system requirements: frequency of op
eration, capacitive loading, output voltage swing, and
duty cycle. This power dissipation, when substituted into
equation (3), should not yield a junction temperature,
T j, greater than Tj(max) at the maximum encountered
ambient temperature. Tj(m ax) is specified for three
integrated circuit packages in the maximum ratings
section of this data sheet
There are two methods of lowering the junction tem

perature without changing the system requirements.
First, the ambient temperature may be reduced suf
ficiently to bring T j to an acceptable value. Secondly,
the R0 CA term can be reduced. Lowering the R0CA term
can be accomplished by increasing the surface area of the
package with the addition of a heat sink or by blowing
air across the package to promote improved heat
dissipation.
T j T a + Pd <R0JA);
; where
T j = junction temperature
T a = ambient temperature
Pp = power dissipation
R#JC - thermal resistance, junction to case
R0CA thermal resistance, case to ambient
RflJA - thermal resistance, junction to ambient.
(3)
MMH0026, MMH0026C

The following examples illustrate the thermal consider
ations necessary to increase the power capability of the
MMH0026.
using the previous formulas and constants, a new safe

operating area can be generated for any output voltage
swing and duty cycle desired.
Assume that the ceramic package is to be used at a

maximum ambient temperature (T a ) of +70C. From
Table 1:R0JA(max)B 150C/watt, and from the max
imum rating section of the data sheet: Tj(max) = +175C.
Substituting the above values into equation (3) yields a
maximum allowable power dissipation of 0.7 watts. Note
that this same value may be read from Figure 17. Also
note that this power dissipation value is for the device
mounted in a socket.
Note from Figure 18, that with highly capacitive loads,

the maximum switching frequency is very low. The
switching frequency can be increased by varying the
following factors:
Next, the maximum powdr consumed for a given system

application must be determined. The power dissipation
of the MOS clock driver is conveniently divided into *
dc and ac components. The dc power dissipation is
given by:
Pdc = (V c c V EE> x HCCL) x (Duty Cycle)
(4)
V c c - VEE
where IcCL 40 mA (---------------- ).

20 V
Note that Figure 14 is a plot of equation (4) for three
values of (V c c ~VEE)- For this example, suppose that
the MOS clock driver is to be operated with V c c = +16 V
and V e e = GND and with a 50% duty cycle. From
equation (4) or Figure 14, the dc power dissipation (per
driver) may be found to be 256 mW. If both drivers
within the package are used in an identical way, the total
dc power is 512 mW. Since the maximum total allowable
power dissipation is 700 mW, the maximum ac power
that can be dissipated for this example becomes:
(a)
(b)
(c)
decrease T a
decrease the duty cycle
lower package thermal resistance (R0ja )
In most cases conditions (a) and (b) are fixed due to

system requirements. This leaves only the thermal re
sistance R0JA that can be varied.
Note from equation (2) that the thermal resistance is
comprised of two parts. One is the junction-to-case
thermal resistance (R0jc) and the other is the case-toambient thermal resistance (R0CA)- Since the factor R0JC
is a function of the die size and type of bonding employed,
it cannot be varied. However, the R0CA term can b*
changed as previously discussed, see Page 7.
FIGURE 18 - LOAD CAPACITANCE versus FREQUENCY

FOR "L PACKAGE ONLY
(Both driver* used in identical way)
Pac = 0 .7 - 0 .5 1 2 = 188 mW
The ac power for each driver is given by:
Pac= <VCC - V E E ) 2 x f x C L
where f - frequency of operation
C|_ - load capacitance (including all strays and
wiring).
(5)
Figure 16 gives the maximum ac power dissipation versus

switching frequency for various capacitive loads with
V c c = 16 V and V E = GND. Under the above con
ditions, and with the aid of Figure 15, the safe operating
area beneath Curve A of Figure 18 can be generated.
Since both drivers have a maximum ac power dissi
pation o f 188 mW, the maximum ac power per driver
becomes 94 mW. A horizontal line intersecting all the
capacitance load lines at the 94 mW level of Figure 15
will yield the maximum frequency of operation for each
of the capacitive loads at the specified power level. By
Heat Sink Considerations:

Heat sinks come in a wide variety of sizes and shapes that
will accomodate almost any 1C package made. Some of
these heat sinks are illustrated in Figure 19. In the
previous example, with the ceramic package, no heat sink
and in a still air environment, R0JA(max)was 150C/W.
For the following example the Thermalloy 6012B type
heat sink, or equivalent, is chosen. With this heat sink, the
R0CA for natural convection from Figure 20 is 44C/W.
From Table 1 R0jc(max) = 50C/W for the ceramic
MMH0026, MMH0026C

FIGURE 1 9 -TH ER M ALLO Y* HEAT SINKS
Forced Air Considerations:'

As illustrated in Figure 21, forced air can be employed to
reduce the R0j a term. Note, however, that this curve is
expressed in terms of typical RflJA rather than maximum
R0JA- Maximum RflJA C^n be determined in the follow
ing manner:
package. Therefore, the new R0jA(m ax) with the 6012B

heat sink added becomes:
R0JA(max) = 50C/W + 44C/W = 94C/W.
Thus the addition of the heat sink has reduced RflJA(max)
from 150C/W down to 94C/W. With the heat sink, the
maximum power dissipation by equation (3) at T a +70C is:
From Table 1 the following information is known:

(a) R0JA (typ )B 1OOC/W
(b) R0JC(typ) = 27 C/W
175C 70C
. _
Pn = --------------------- =1, 11 watts.
94C/W
This gives approximately a 58% increase in maximum
power dissipation. The safe operating area under Curve C
of Figure 18 can now be generated as before with the aid
of Figure 15 and equation (5).
Since:
R0JA= R0JC + R(JCA
(6 )
R0CA = R0JA - RflJC
(7)
Then:
Therefore, in still air

FIGURE 20 - CASE TEMPERATURE RISE ABOVE
AMBIENT versus POWER DISSIPATED USING
NATURAL CONVECTION
RflCA(typ) 100C/W - 27C/W = 73C/W

From Curve 1 of Figure 21 at 500 LFPM and eq
uation (7),
RflCA(typ) = 53C/W - 27C/W = 26C/W.
Thus R0 CA(typ) has changed from 73C/W (still air) to
26C/W (500 LFPM), which is a decrease in typical R0CA
by a ratio of 1:2.8. Since the typical value of R0CA was
reduced by a ratio of 1:2.8, R0CA(max) of 100C/W
should also decrease'by a ratio of 1:2.8.
This yields an R0CA(max) at 500 LFPM of 36C/W.
Therefore, from equation (6 ):
RflJA(max) - 50C/W + 36C/W = 86C/W.
Therefore the maximum allowable power dissipation at
500 LFPM and T a * +70C is from equation (3):
175C - 70C
PD = --------- -----------a 1.2 watts.
+86C/W '
Pq , POWER DISSIPATED (WATTS)
4-145
MM H0026, MMH0026C

As before this yields a safe operating area under Curve E
in Figure 18.
FIGURE 21 - TYPICAL THERMAL RESISTANCE (RejA* OF

"L" PACKAGE varus AIR VELOCITY
v
V
1
1
1
x
P ICKAGE MOUNTING #1 BARNES SO CKET OR EQUIV_
PRINTED Cl RCUIT BOARD
4" * 6" * 0.002' -2 0 2 .C U .
k- e
i t
UJ
60
as
o
_ tL
AIR FI QWDIRC
\# 1
#2
Note from Table 1 and Figure 21 that if the 14-pin

ceramic package is mounted directly to the PC board
(2 oz. cu. underneath), that typical R&JA is considerably
less than for socket mount with still air and no heat sink.
The following procedure can be employed to determine a
safe operating area for this condition.
Given data from Table 1:
typical
< 3<
x
RflJA
100C/W
typical :R0JC= 27C/W
S o
Raj A 100PI :/WATT)

R#JC * 27C/WATT f --------------1
200
1
1
400
GOO
800
1000
1200
AIR VELOCITY (LINEAR FEET PER MINUTE)
1400
1600
As with the previous examples, the dc power at 50% duty

cycle is subtracted from the maximum ajlowable device
dissipation (Pq ) to obtain a maximum Pac. The safe
operating area under Curve D of Figure 18 can now be
generated from Figure IS and equation (S).
Heat Sink and Forced Air Combined:
From Curve 2 of Figure 21, R0jA(tVP) 's 75C/W for a

PC mount and no air flow. Then the typical RflCA is
75C/W - 27C/W = 48C/W. From Table 1 the typical
value of RflCA for socket mount is 100C/W - 27C/W =
73C/W. This shows that the PC board mount results in
a decrease in typical RflCA by a ratio of 1:1.5 below the
typical value of RflCA 'n a socket mount. Therefore, the
maximum value of socket mount RflcA of 100C/W
should also decrease by a ratio of 1:1.5 when the device
is mounted in a PC board. The maximum RflcA becomes:
100C/W
RflCA = ------------ = 66C/W for PC board mount
1.5
Therefore the maximum Rq ja for a PC mount is from
equation (6).
Some heat sink manufacturers provide data and curves of

R0CA for still air and forced air such as illustrated in
Figure 22. For example the 6012B heat sink has an
R0CA = 17C/W at 500 LFPM as noted in Figure 22.
From equation (6):
RflJA = 50C/W + 66C/W = 116C/W.

With maximum R0JA known, the maximum power dis
sipation can be found and the safe operating area de
termined as before. See Curve B in Figure 18.
Max R0j a = 50C/W + 17C/W = 67C/W

From equation (3) at T>\ = +70C
CONCLUSION
In most cases, heat sink manufacturer's publish only
R0CA socket mount data. Although R0CA data f r pC
mounting is generally not available, this should present
no problem. Note in Figure 21 that an air flow greater
than 250 LFPM yields a socket mount R0JA approxi
mately 6% greater than for a PC mount. Therefore, the
socket mount data can be used for a PC mount with a
slightly greater safety factor. Also it should be noted that
thermal resistance measurements can vary widely. These
measurement variations are due to the dependency of
R0CA on the type environment and measurement tech
niques employed. For example, R0CA would.be greater
for an integrated circuit mounted on a PC board with little
or no ground plane versus one with1a substantial ground
plane. Therefore, if the maximum calculated junction
temperature is on the border line of being too high for a
given system application, then thermal resistance measure
ments should be done on the system to be absolutely
certain that the maximum junction temperature is not
exceeded.
175C - 70C
Pn -------- ---------- 1.57 watts.
67C/W
FIGURE 22 -TH E R M A L RESISTANCE R9CA
versus AIR VELOCITY
4-146
MMH0026, MMH0026C
TYPICAL APPLICATIONS
FIGURE 23 - AC-COUPLED MOS CLOCK DRIVER
V|
VO
Vcc " t5 V
3D
- O
Two-Phase ^
Clock to
Shift Rogisters
M TTL
MC7400
Series Gate*
V Ee - - 1 2 V
Pint not shown ora not connected.
FIGURE 24 - DC-COUPLED RAM MEMORY ADDRESS

OR PRECHARGE DRIVER (POSITIVE-SUPPLY ONLY)
Vcc
V|
Vo
_L
To Address
Lines On
'1 '
1103 Type
Memory System
Or Equiv
r o lt ]
L -w v -1
C|n
t C h H(T r f e i
M TTL
Rin
MC7400
L jV W J
Serios Gates
I
?
Pins not shown are not connected.
4-147
DRIVERS/RECEIVERS
Temperature Range
Commercial '
M ijitary
AM26LS31
DS8641
MC8T13 /
8T23
M C 8T14/
8T24
M C 26S10/11
MC75S110
M C 1411,
1 2 ,1 3 ,1 6 *
M C I4 7 2
M C1488
MC1489, A
MC3437
MC3438
M C 3 44 0A /
41 A /4 3
MC3446A
MC3447
M C3448A
M C 3 4 5 0 /5 2
MC3453
M C 3 48 1/85
MC3486
MC3487
MC3488A, B
M C 3 4 9 0 /9 4
M C 3 4 9 1 /9 2
M C 7 51 07/10 8
M C 7 51 25/12 7
M C 7 5 1 2 8 /1 2 9
MC75140P1
MC75325
M C75450
M C75451-454
M C 75461-464
M C 7 5 4 9 1 /9 2
S N 7 54 31/4 32
SN75451BP454BP
Page
Quad RS-422 Line with 3-State Outputs ...................................... 5-3
Quad Unified Transceiver ................................................................. 5*6
Dual Line Drivers ...............................................................................
5-9
Triple Line Receivers with Hysteresis.............................................

Quad Open-Collector Bus Transceivers .........................................
Dual Line D r iv e r ..................................................................................
5-12
5-16
5-19
Peripheral Driver A r r a y s ....................................................................

Dual Peripheral Positive "NAND" D river.........................................
Quad MDTL Une D riv er......................................................................
Quad MDTL Line Receivers..............................................................
Hex Bus R e c e iv e r................................................................................
Quad Bus Transceiver........................................................................
5-25
5-29
5-32
5-38
5-44
5-47
Quad Interface Bus Transceivers ....................................................

Quad General Purpose Interface Bus Tranceiver..........................
Bidirectional Instrumentation Bus Tran sceiver.............................
Quad 3-State Bus Transceiver..........................................................
Quad MTTL Compatible Line D r iv e r ................................................
MTTL Compatible Quad Line D r iv e r ................................................
Quad Single Ended Line Driver .......................................................
Quad R S -422/423 Line Receiver.....................................................
Quad Line Driver with 3-State Outputs .........................................
Dual RS-423/232C D rivers...............................................................
7-Digit Gas-Discharge Display Drivers ...........................................
8-Segment Visual Display D r iv e rs ..................................................
Dual Line Receivers ...........................................................................
7-Channel Line R eceivers.................................................................
8-Channel Line Receivers............................ ...................................
Dual Line R e c e iv e r.............................................................................
Dual Memory Drivers .......................................................................
Dual Peripheral Positive "AND" D riv e r...........................................
Dual Peripheral D rivers..............................................................
Dual High-Voltage Peripheral D rivers..............................................
Multiple Light-Emitting Diode Drivers ...........................................
Dual Peripheral D rivers.....................................................................
5-5 0
5-54
5-57
5-63
5-68
5-75
5-79
5-80
5-83
5-87
5-90
5-96
5-103
5-108
5-112
5-116
5-1 20
5-126
5-131
5-135
5-140
5-146
M C55325
Dual Peripheral D rivers...................................................................... 5-147
industrial
5-2
MOTOROLA
<8>
QUAD RS-422 LINE DRIVER

WITH THREE-STATE OUTPUTS
QUAD LINE DR IVER WITH NAND ENABLED

TH R EE-STATE OUTPUTS
T h e M o to r o la A M 2 6 L S 3 1 is a quad d iffe re ntia l line driver

intended fo r dig ita l data transmission over balanced lines. It meets
all the requirements o f E IA Standard RS-422 and Federal Standard
1020.
The A M 26LS31 provides an enable/disable fu n ctio n com m on to
all fo u r drivers as opposed to the sp lit enables on the MC3487
RS-422 driver.
The high impedance o u tp u t state is assured during power down.
Full RS-422 Standard Compliance
S in g le + 5 V Supply
Meets Full V q = 6.0 V, V c c = 0 V, l o < 100 n A Requirement
O u tp u t S hort C ircu it Protection
C om plem entary O utputs fo r Balanced Line Operation
High O u tp u t Drive C apability
Advanced LS Processing
PNP Inputs fo r MOS C o m p a tib ility
D SU FFIX
C E R A M IC PAC KAG E
CASE 62 0
T ill
ll t
P SU FFIX
P LASTIC P A C KAG E
CASE 648
D R IV E R BLO C K D IA G R A M
In p u t
TR UTH TABLE
O u tp u t
C o ntrols
Input
Control
Inputs
(E/E)
Non-Inverting
O utput
Inverting
O utput
H
L
X
H /L
H /L
L/H
H
L
Z
L
H
Z
L
H
X
Z
5-3
= Low Logic State

= High Logic State
= Irrelevant
= Third-State (High Impedance)
AM26LS31
ABSOLUTE MAXIMUM RATINGS

Rating
Symbol
Value
Unit
VCC
8.0
Vdc
Input Voltage
V|
Vdc

Operating Junction Temperature Range
Ceramic Package
Plastic Package
ta
5.5
0 to +70
C
C
Tj
175
150
-65 to +150
Tsto
'"Absolute Maximum Ratings" are those values beyond which the safety of the device cannot
be guaranteed. They are not meant to imply that the devices should be operated at these limits.
The 'Table of Electrical Characteristics" provides conditions for actual device operation.
ELECTRICAL CHARACTERISTICS (Unless otherwise,noted specifications apply 4.75 V < Vcc ^ 6.25 V and 0C < T a ^ 70C.
Typical values measured at Vc c 5.0 V, and TA = 25C.)
Characteristic
Symbol
Min
Max
0.8
VlL
V|H
2.0
Unit
Vdc
Vdc

(V jl 0.4 V)
IL
-360
JiA

(V |H 2.7 V)
(V | h 7.0V)
Input Clamp Voltage
(l|K -1 8 mA)
*IH
-
+ 20
+ 100
V(K
-1 .5

(iO L 20mA)
Vo l
0.5

(lOH "20 mA)
VOH
2.5
'OS
-3 0
-150
mA
-2 0
+20
+100
-100
10.4
2.0

(V|n 2.0 V) 2
Output Leakage Current Hi-Z State
(V q l 0 5 V. V||_(E> 0-8 V . V |H(E) 2-0 V)
IVoH 2.5 V, V|L(E) 0.8 V, V |H(gj " 2 0 V)
'O(Z)
Output Leakage Current - Power OFF

fVOH 6J) V , V c c -O V )
(V o l -0.25 V. V c c * 0 V |
Output Offset Voltage Difference1
Output Differential Voltage 1
'O(off)

(Output Disabled)^
nA
**A
MA
Vos-VOS
VT
Vt - V T
Output Differential Voltage Difference 1
Typ
'CCX
V
V
V
mA
10.4
60
80
1. See EIA Specification RS-422 for exact test conditions.

2. Only one output may be shorted at a time.
3. Circuit in three-state condition.
SWITCHING CHARACTERISTICS (V qc 5.0 V, Ta * 25C unless otherwise noted.)

Characteristic
High to Low Output
Low to High olitput
Symbol
Min
Typ
Max
tPHL
tPLH
20
20
6.0
30
35
40
45
Output Skew
Propagation Delay - Control to Output
(Cl 10 pF. RL - 75 n to Gnd)
(Cj_ io pF, R l 180 n to Vcc>
(Cl 30 pF, R l 75 n to Gnd)
(Cl 30 pF, r l 180 n to Vcc)
Unit
ns
ns
ns
tPHZ(E)
'PLZ(E)
. PZH(E)
*PZL(E
5-4
AM26LS31
FIGURE 1 - THREE-STATE ENABLE TEST CIRCUIT

AND WAVEFORMS
To Scope (Inp ut)
3.0 V or Gnd
Input
To Scope
O utput
0
Pulte generator characteristics
Inv
O utput
s.
Zc SO f t
O penfor1t p jH IE ) Test Only
rx = k
P B R < 1 .0 M H l
Non-lnv
O utput
Enablo
50% D uty Cyclo

*TLH . l T H L < 6 ns
Pulse
Generator
::50
H(_ Seo Test Table
C l Includes Probe and Jig Capacitance. See Test Table
----------------3.0 V
Control
Input
(Enable)
Contol
Input
(Enablo)
3 V
5
<PZUE>
V o l
-0 V
PZH(E)
FIGURE 2 - PROPAGATION DELAY TIMES INPUT TO

OUTPUT WAVEFORMS AND TEST CIRCUIT
v q h
Scope
(O u tp u t)
Scope
(Input)
Inv
Output
Pulse
Generator
Non-lnv
O utput
Pulse generator characteristics

Z - 50 n
C L - 30 pF
3.0 V
Enable
PRR < 1.0 MHz

50% D uty Cycle
Cj_ Includes Probe and Jig Capacitance
5-5
MOTOROLA
QUAD UNIFIED TRANSCEIVER

Consists o f fo u r pair o f drivers and receivers w ith the o u tp u t of
each driver connected to the in p u t o f its mating receiver. These
devices are intended fo r use in bus organized data transmission
system em ploying term inated 120 f2 lines. A disable fu n ctio n con
sisting o f a tw o -in p u t NOR gate is provided to co ntro l all fo u r
drivers. Up to 27 driver/receiver pairs can share a comm on line.
Receiver In p u t Threshold Is N ot A ffecte d by Temperature
Open C ollector D river O u tp u ts A llo w Wire-OR
T T L Com patible Receiver O utputs and Disable and Driver Inputs
Driver Propagation Delay = 15 ns
Receiver Propagation Delay = 20 ns
Guaranteed M inim um Bus Noise Im m u n ity = 0.6 V
Low Bus Term inal C urrent (Supply On or O ff) = 30 f i A typ
QUAD UNIFIED BUS

TRAN SCEIVER
J SUFFIX
CASE 620
FIGURE 1 - TY PIC AL APPLICATION
N SUFFIX
CASE 6 48
To C o m p ute r o r Peripherals
TR UTH TABLES
DRIVER SECTION
RECEIVER SECTION
Bus
O utput
V|H (R ) > 1 7 V
V IL(R ) < 1-3 v
L
H
Disable 1 Disable 2 In p u t
Where: L - Low Logic State

H = High Logic State
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
Bus
H
L
H
H
H
H
H
H
M A X IM U M R A TIN G S (T^ = 25C unless otherwise noted.)

Rating
Supply Voltage
Input and O utput Voltage
Plastic
Ceramic
Symbol
Value
V cc
7.0
Vdc
V O -V |
5.5
Vdc
Tj
150
175
U nit
ta
0 to +70
T stg
-65 to +150
5-6
DS8641
ELECTRICAL CHARACTERISTICS (Uniats otherwise noted, specification* apply for 0 < T/\ < 70C and 4.75 < Vcc ^ 5 25
Symbol
Characteristic
Disable Input Voltage High Logic State
Disable Input Voltage Low Logic State
V|H(DA)
Driver Input Voltage High Logic State
V IH(D)
Driver Input Voltage Low Logic State
V IL<D)
V IL(DA)
Receiver Input Threshold Voltage High Logic State

(V | l (D) 0.8 V, lOL(R) 16 mAv OL(R) < 0 .4 V)
Receiver Input Threshold Voltage - Low Logic State
<V|L(D) V >'OH(R) -4 0 0 mA, V o h (R) > 2.4 Vi
Disable Input Current High Logic State
<V|H(D> 2.4 V .V ,H (D A )- 2.4 V)
V|H(D) = 5-5 v - V IH(DA) 6.6 V)
V ILH(R)
Min
2.0
Typ
Max
Unit
2.0
1.50
0.8
0.8
1.70
1.50
V IHL(R)
V
V
1.30
>IH(DA)
-
Driver Input Current High Logic State

<V|H(DA) 2.4 V. V|H(D) " 2.4 V)
40
MA
1.0
mA
40
1.0
mA
mA
-1.6
mA
-1.6
mA
'lH(D)
-
W|H(DA) 5 5 V' V IH(D) 5-5 V)

Disable Input Current Low Logic State
'IL(DA)
IV|L(DA) 0 4 V - v 1t_(D) 0-4 V)

Driver Input Current Low Logic State
(V|L(D) - 0.4 V .V ,U 0 A ) - 0.4 V)
Bus Current
<V|L(DA) 0.8 V, V | l (D> 0-8, V|H(BUS) 4.0 V)
(Vcc = 5-25 V)
(V c c -O V )
Bus Voltage Low Logic State
{V |L (D A ) 0.8 V, V | h (D) " 2.0 V, IjjUS " 50 mA)
Receiver Output Voltage High Logic State
IVlLIDA) 0 8 V, V | l (D) 0.8 V, V|L(BUS) -5 v OH(R) -400 mA)
Receiver Output Voltage Low Logic State
IV|L(DA) -8 V, V | l (D) 0.8 V, V | h (BUS) 4 0 V.
>OL(R) 16 mA)
Receiver Output Short Circuit Current (Note 1)
V|L(DA) 0.8 V. V | l (D) 0.8 V, V |L(BUS) 0.5 V.
VCC " 5.25 V)
'IL(D)
MA
bus
V L(BUS)
v OH(R)
2.4
ice
<V|L(DA) V . V , h ( d ,- 2 .0 V >
Input Clamp Diode Voltage (TA - 2 5C)
('l(DA) l|(D) 'BUS "12 niA)
V|
0.4
-55
mA
50
70
mA
-1.0
-1.5
Typ
19
Max
Unit
30
ns
15
23
ns
17
25
ns
-18
100
100
0.7
0.25
v OL(R)
'OS(R)
30
2.0
0.4
'
NOTE 1: Only one output at a time.
SWITCHING CHARACTERISTICS (TA - 25C, Vcc - 5.0 V unless otherwise noted.)

Characteristic
Propagation Delay Tima from Disable Input to
High Logic Level Output
Symbol
lPLH(DA)
Min
-
Propagation Delay Time from Disable Input to

Low Logic Level Output
tPHUDA)

Progpgation Delay Time from Drive Input to
Propagation Delay Time from Bus 1nput to
Propagation Delay Time from Bus Input to
tPLH(D)
*PHL(D)
9.0
15
ns
tPLH(R)
20
30
ns
tPHUR)
18
30
ns
5-7
DS8641
FIGURE 2 - DRIVER AND DISABLE TEST CIRCUIT AND WAVEFORMS
To Scopo
(Output)
To Scops
(Input)
3 V
Disable
Input
1 8 V<DA) 0 V
V0 H
O utput
v OL
l PLH(DA)-*
FIGURE 3 - RECEIVER TEST CIRCUIT AND WAVEFORM

To Scope
(Inp ut)
t o Scope
(O utput)
+5- V

(1/4 Shown)
5-8
-*PHL(O A)
MCST13
MC8T23
(M ) MOTOROLA
DUAL LINE DRIVERS

SILIC O N M O N O L IT H IC
DUAL LINE DRIVERS
The M C 8T13 and M C8T23 are designed to drive transmission

lines w ith impedances o f 50 2 to 500 12. The MC8T23 specifically
meets all o f the in p u t/o u tp u t requirements of the IBM System
360/System 370 specifications (IBM Specification GA 22-6974-0).
High O u tp u t Drive Capability

10 = -7 5 m A (M in) @ V o = 2.4 V - MC8T13
10 = -5 9 .3 m A (M in) @ V o = 3.11 V - MC8T23
High Speed Operation

t P L H = l P H L = 20 ns (Max) w ith 50 2 Load
M T T L and M D T L C om patible Inputs
U ncom m itted E m itte r O u tp u t Structures Permit Party-Line

Operation
CZ)
L S U F F IX
CASE 620
Designed to Operate w ith MC8T14 or MC8T24 Line Receivers
Outputs are S h o rt-C ircu it Protected
Equivalent to SN75121 and SN75123 Respectively.
P S U F F IX
P LA S T IC P AC K A G E
CASE 648
PIN C O N N E C T IO N S
~\J~
TR U TH TABLE
In p u ts
1
H
X
H
X
34
H
X
H
X
O u tp u t
X
H
X
H
H
H
A ll O ther
C o m b in atio ns
H = High Log ic State
L L o w Log ic State
X = Irre le van t
5-9
MC8T13, MC8T23
MAXIMUM RATINGS (T a +25C untan otherwise noted.)
Rating
Symbol
Value
v Cc
7.0
Vdc
V|
s.s
Vdc

Input Voltage
Unit
Output Voltage
vo
7.0
Vdc
Power Dissipation @ T A = +25C

Derate above 25C
PD
1000
6.7
mW
mW/C
Ta
0 to +75
Tstg
-65 to +150

Storage Temperature Renge
ELECTRICAL CHARACTERISTICS (Unless otherwise noted. 4.75 V < V Cc < 5 .2 5 V and 0C < T A < 7S C )
MC8T23
MC8T13
Characteristics
Symbol
Min
Typ
Max
Min
Typ
Max
V|L
0.8
0.8
Input Volt8ge High Logic State
V|H
2.0
2.0

(V|i_= 0.4 V)
'IL
-0.1
-1.6
-0.1
-1.6
mA

(V |H = 4.5 V)
'IH I
__
40
40
*iA
(V |H = 5.5 V, VC C 5.0 V)
*IH2
10
10
mA
v l (clamp)
-1.5
-1.5
v OH1
2.4
Input Clamp Voltage

( l | - - 1 2 mA. V c c 5.0 V)
Unit

(V|H * 2.0 V. I q h -75 mA)
(V c c - 5.0 V. V |H - 2.0 V, l0 H -59.3 mA)
(TA = 25^C)
Output Current High Logic State
(V |H - 4.5 V . V c c " 5.0 V. V 0 2.0 V, T A 25C)
Output Current Low Logic State
(V |L 0.8 V. V0 0.4 V)
(V|i_ 0.8 V, V 0 - 0.15 V)
2.9
v OH2
'OH
-100
-250 -100
*OL1
-800
3.11
-250
mA
>OL2
Output Reverse Leakage Current Low Logic State

(V |L = O V .V 0 = 3.0 V)
(V|L 0 V , V 0 *> 3.0 V. V CC - 0 V)
Output Shon-Circuit Current
(V|H * 4.5 V, VCC - 5.0 V , V 0 - 0 V . TA - 25C)
OR1
>OR2
80
500
'OS
Power Supply Currents

(lO 0 mA)
Outputs Low Logic State, V | l 0.8 V
Outputs - High Logic State, V |n - 2.0 V
_
-240
'CCL
'CCH
IiA
#*A_
40
MA
-30
-30
mA
60
28
60
28
mA
Max
Unit
i A
mA
SWITCHING CHARACTERISTICS (VCC " 5.0 V, T A 25C unless otherwise noted.) Figure 1
MC8T13
Symbol
Characteristic
Propagation Delay Time Low to High Level Output
(R L 3 7 n ,C L ;i5 p F )
(RL 3 7 n . C L =1 0 00 p F )
(R L 5 0 n ,C |_ - 15pF)
(RL * * 5 0 n ,C L * 100pF)
*PLH
Propagation Delay Time High to Low Level Output

(R|_ 37 n . C L - 15pF)
(R|_= 37 n , C L 1000 pF)
(R L 5 0 H ,C i_ = 15pF)
(RU 50 , CL 100pF)
*PHL
Typ
Max
Min
Typ
11
22
20
50
-
8.0
20
20
50
ns
-
12
20
20
35
12
15
20
ns
-
5-10
MC8T23
Min
25
MC8T13, MC8T23
FIGURE 1 - SWITCHING TEST CIRCUIT AND WAVEFORMS
To Scope
To Scopo
In p u t Pulte W idth
200 os, SOX Duty Cycle
FIGURE 2 - REPRESENTATIVE SCHEMATIC DIAGRAM

(1/2 Shown)
FIGURE 3 - TYPICAL OUTPUT CURRENT

versus OUTPUT VOLTAGE
1.0
2.0
3.0
Vo. OUTPUT VOLTAGE (VOLTS)
5-11
4.0
5.0
MC8T14
MC8T24
MOTOROLA
TRIPLE LINE RECEIVERS

WITH HYSTERESIS
IN TE G R A T E D C IR C U IT
TRIPLE LINE RECEIVERS WITH HYSTERESIS

. . . specifically designed to meet the in p u t/o u tp u t specifications for
IBM 360/370 Systems (IBM specification GA 22-6974-0). Each
receiver incorporates hysteresis to provide high noise im m unity and
also high inp u t impedance to minim ize loading on the related driver.
Each Channel Can Be Independently Strobed
High Speed - tp|_H = tp H L = 20 ns
Inp u t Gating Provided on Each Line
Operates on a Single +5.0 V Power Supply
F u lly C ompatible w ith M T T L or M D TL Logic Systems
In p u t Hysteresis Results in High Noise Im m unity
16
( top view)
CASE 620
P S U F F IX
P L A S T IC P AC K A G E
CASE 648
PIN C O N N E C TIO N S
Goto
I----In p u t 1A I ^
In p u t 2 A
Receiver |---In p u t B I 3
S trobe I---In p u t B L i .
In p u t 1B I 5
Goto
(
In p u t 2B
LL
O u tp u t
b
r~
LL
Gnd H E
TRU TH TABLE
O u tp u t
In p u ts
Receiver S trobe Gate 1 Gate 2
X
L
H
X
H
X
X
H
X
L
X
L
H
X
L
L
X
X
Whero:
H - Hiflh Logic State
X * D o n 't Care
5-12
H
X
X
X
L
L
L
L
H
H
H
H
MC8T14,MC8T24
M A X IM U M RATINGS I T ^ * 25?C unless otherwise noted.)

Unit
Symbol
Value
V cc
7.0
Vdc
Receiver Input Voltage

( V c c 0)
V |(R )
7.0
6.0
Vdc
Rating
V|(S) or (G)
5.S
Vdc
Output Voltage
v0
7.0
Vdc
Output Current
Ceramic Package
Derate above 25C
*100
mA
PD
1000
6.7
mW
mW/C
830
6.7
mW
mW/C
Strobe or Gate Input Voltage
Plastic Package
Derate above 25C
Ceramic Package
Plastic Package
Tj
175
150
Ta
0 to +75
Tstfl
-65 to +150
ELECTRICAL CHARACTERISTICS (Unless otherwise noted, 4.75 < Vcc < S.2S V and 0C < T A < 7SC)
MCBT24
MC8T14
Unit
Symbol
Min
Typ
Max
Min
Typ
Max
Gate or Strobe Input Voltage High Logic State
V|H(G )or (S)
2.0
2.0
Gate or Strobe Input Voltage Low Logic State
V|L(G )or (S)
0.8
0.8
0.8
-
1.7
0.2
0.4
0.7
Vdc
Characteristic
Receiver InputVoltage High Logic-State
V IH(R)
2.0
Receiver Input Voltage Low Logic State
V IL(R)
Receiver Input Hysteresis (1)

(VCC " 5.0 V, T A = 25C, V ,L(G) = 0, V IH (S) " 4.5 V)
Input Clamp Voltage
(V cc = 5.0 V ,T A = 25C, l| * -1 2m A ) (Strobe or Gate Inputs)
Input Breakdown Voltage
(V cc = 5.0 V, l| = 10 mA) (Strobe or Gate Inputs)
V H(R)
0.3
0.5
V IC(G) or (S)
1.5
1.5
V HG) or (S)
5.5
5.5
0.17
-0.1
40
40
-1,6
-0.1
2.6
2.6
-
3.5
3.5
-
2.6
2.6
3.4
3.4
0.4
0.4
0.4
0.4
-50
-100
-50
-100
60
72
60
72
Receiver Input Current High Logic State

V|H(R) = 3 .8 V )
<V|H(R> = 3.11 V)
V IH(R) = 7-o v >
<V IH(R) ** 6.0 V, V c c = 0 VI
Gate or Strobe Input Current High Logic State
<V|H(S) = 4.5 V , V IH (R ) 3.11V)
<V|H(G) = 4-5 V)
Gate or Strobe Input Current Low Logic State
IV|L(G) or (S) -4 V, V |L(R) - 0 V)
<V IH(R) = 2.0 V, V|H(S| 2.0 V, V | l (Q) " 0.8 V, l<)H ** -8 0 0 //A)
V IH(R) 0.8 V, V|L(S) 0.8 V, V | l (G) 0-8 V, Io h -8 0 0 *A)
<V IH(R) = 1-7 V, V | H(S) 2-0 V, V tL(G) 0-8 V. 'OH 8 0 0 mA)
(V|H(R) 0 7 v V |l(s ) 0.8 V, V||_(G) 0.8 V, I<j h -800 ji A)
(V IL ,R> = 0.8 V, V |H(S) " 2.0 V, V |U(G) 0.8 V, I q l 16 "iA)
v IL (R ) 0 - 8 V .V | l (S ) 0 .8 V , V | h (G ) 2.0 V. I q l 16mA)
<V|L(R) 0.7 V. V IH (S) " 2.0 V. V tL(G) *> 0.8 V. I0 l - 16 mA)
<V|L<R) 0-7 v ' V|L(S) 0 8 V. V|H(G ) - 2 0 V, l0 L - 16 mA)
Output Short-Circuit Current 12)
<V|H(R) 3.8 V , V|i_(G) = 0 V, V |US) 0. VCC 5.0 V. TA = 25C)
<V|H(R) = 3.11 V. V | l (G) - 0 V. V |L($) - 0 V. V CC - 5.0 V, T A - 25C)
(VCC 5.25 V. T a 25C)
mA
'IH(R)
0.17
5.0
5.0
MA
'IH(G) or (S)
lL(G) or (S)
40
40
- ! -1.6
mA
V
VOH
Vo l
mA
os
ice
Vdc
mA
(1) The Input Hysteresis is defined as the difference the input voltage at which the output begins to go from the high logic state to the low logic
state and the input voltage which causes the output to begin to go from the low logic stete to the high logic state.
(2) Only one output may be shorted at a time.
5-13
MC8T14,MC8T24
SWITCHING CHARACTERISTICS IV q ; S.O V, T a 2SC unless otherwise noted.)

MC8T14, MC8T24
Parameter
Symbol
Min
Typ
Max
Propagation Delay Time Receiver Input to High Logic State Output
PLH(R)
20
30
ns
Propagation Delay Time Receiver Input to Low Logic State Output
tpHL(R)
20
30
ns
Propagation Delay Time Strobe Input to High Logic State Output
PLH(S)
ns
Propagation Delay Time Strobe Input to Low Logic State Output
*PHL(S)
ns
Propagation Delay Time Gate Input to High Logic State Output
'PLH(G)
ns
Propagation Delay Time Gate Input to Low Logic State Output
tPHL(G)
ns
Unit
FIGURE 1 - RECEIVER PROPAGATION DELAY TIMES tpLH(R) and tpHL(R) TEST CIRCUIT AND WAVEFORMS
T o Scope
To Scope
In p u t Pulse W idth 200 ns

D u ty Cycle 50%
FIGURE 2 - GATE AND STROBE PROPAGATION DELAY TIME TEST CIRCUIT AND WAVEFORMS
T o Scope
'I 'U M S I
O utput
T r1.5 V
1.6 S / r
V
J|r 1.S '
VOL
In p u t Pulse W idth 200 ns
D uty Cycle 50 ns
*TLH *THU < s- "*
5-14
*PHLCG)
MC8T14,MC8T24
FIGURE 3 - TYPICAL RECEIVER HYSTERESIS

CHARACTERISTIC
Vo. OUTPUT VOLTAGE (VOLTS)
FIGURE 4 - HYSTERESIS TEST CIRCUIT
V|. INPUT VOLTAGE (VOLTS)
5-15
MC26S10
MC26S11
MOTOROLA
QUAD OPEN-COLLECTOR
BUS TRAN SCEIVERS
QUAD OPEN-COLLECTOR BUS TRANSCEIVERS

These quad transceivers are designed to mate S ch o ttky T T L or
SC H O TTK Y
NMOS logic to a low impedance bus. The Enable and Driver inputs
are PIMP buffered to ensure low in p u t loading. The Driver (Bus) o u t
p u t is open-collector and can sink up to 100 m A at 0.8 V, thus the

bus can drive impedances as low as 100 2. The receiver o u tp u t is
active pull-up and can drive ten S ch o ttky T T L loads.
A n active-low Enable controls all fo u r drivers allowing the outputs
o f d iffe re n t device drivers to be connected together fo r party-line
operation. The line can be term inated at both ends and still give
considerable noise margin at the receiver. Typical receiver threshold
is 2.0 V.
Advanced S ch o ttky processing is utilize d to assure fast propaga
tio n delay times. Tw o ground pins are provided to improve ground
current handling and allow close decoupling between V c c ar|d
ground at the package. Both ground pins should be tied to the
ground bus external to the package.
Driver Can Sink 100 m A at 0.8 V (Max)
PNP Inputs fo r Low -Logic Loading
Typical Driver Delay = 10 ns
Typical Receiver Delay = 10 ns
S ch o ttky Processing fo r High Speed
Inverting Driver MC26S10
L SU FFIX
CASE 620
P SU FFIX
CASE 648
PIN CONNECTIONS
N on-Inverting MC 26S11
TYPIC AL APPLICATION
Receiver r
O u tp u t a I-----
-Tr| Receiver
----- O u tp u t.C
D rivor i
In p u t a I----D river
In p u t B
Receiver
r ^ n D rive r
----- ' In p u t D
yjji Receiver
-----1O u tp u t D
In v e rte r on M C 26S11 o n ly .
TRUTH TABLE
26S10
26S11
Enable
H
L
H
X
Y
5-16
Bus
Driver
Input
Receiver
Output
Low Logic State

High Logic State
Irrelevant
Assumes condition controlled
by other elements on the bus
MC26S10, MC26S11
M A X IM U M R A T IN G S (TA = 25C unless otherwise noted.)

Rating
Symbol
Input Voltage
Input Current
Output Voltage High Impedance State
Output CurrentBus
Output CurrentReceiver
Storage Temperature
Ceramic Package
Plastic Package
Value
Unit
Vcc
V|
-0.5 to +7.0
Vdc
-0.5 to +5.5
'I
v o (Hi-z)
'o(B)
-3.0 to +5.0
Vdc
mA
'o(R)
ta
Tstg
Tj
V
mA
mA
C
C
C
-0.5 to Vcc
200
30
0 to +70
-65 to +150
175
150
ELE C TR IC A L C H A R A C TE R IS T IC S (Unlessotherwise noted Vcc ~ 4.75 t0 5.25 V and TA = 0 to +70C.

Typical values measured at Vcc 5.0 V and T a 25C.)
Characteristic
Typ
Symbol
Min
V |L
(Driver and Enable Inputs)
(Driver and Enable'lnputs)
V|H
Input Clamp Voltage

(Driver and Enable Inputs)
(l|K -18 mA)
(V | l - 0.4 V)
(Enable Input)
(Driver Inputs)
V|K
Input Current High Logic State (V m 2.7 V)

(Enable Input)
(Driver Inputs)
*IH
2.0
Max
Unit
0.8
-1.2
mA
lL
Input Current Maximum Voltage

(V i h i 5.5 V)
(Enable or Driver Inputs)
Driver Output Voltage Low Logic State
(I q l = ^0 mA)
(lO L = 70niA)
(lOL 100 mA)
Driver (Bus) Leakage Current
(VOH 4.5 V)
(V0 L = 0.8 V)
Driver (Bus) Leakage Current
(VCC = 0 V ,V OH = 4.5 V)
Receiver Input High Threshold
<V|H(E) 2.4V>
Receiver Input Low Threshold
(V|H(E) 2.4 V)
(I q l 20 mA)
(OH " -1.0 mA)
Receiver Output Short-Circuit Current (Note 1)
Power Supply Current Output Low State
(V IL K O V )
MC26S10
MC26S11
-0.36
-0.54
20
30
mA
100
lH 1
VOL(D)
-
0.33
0.42
0.51
0.5
0.7
0.8
*01 (D)
100
-50
100
mA
VjH (R )
2.25
2.0
VTL(R)
2.0
1.75
v OL(R)
0.5
VOH(R)
2.7
3.4
'OS(R)
-18
-60
45
70
80
mA
'O(D)
ice
N O T E 1: O n e o u tp u t sh ortod at a timo. D u ra tio n n ot to excood 1.0 second.
17
mA
V
mA
mA
MC26S10, MC26S11
SWITCHING CHARACTERISTICS (Vcc 5.0 V, T /\ 25C unless otherwise noted.)

Characteristic
Driver Input to Output
Enable Input to Output
Bus to Receiver Output
Symbol
Min
*PLH(D)
tPHL(D)
lPLH(E)
tPHL(E)
tPLH(R)
tPHL(fl)
Rise and Fall Time of Driver Output
*TLH(D)
tTHL(D)
4.0
2.0
MC26S10
Typ
Max
Min
Typ
Max
Unit
10
10
15
15
12
12
19
19
ns
14
13
18
18
15
14
20
ns
10
10
15
15
10
10
15
15
ns
10
4.0
10
4.0
ns
MC26S11
4.0
2.0
20
SWITCHING WAVEFORMS AND CIRCUITS
FIGURE 1 - DATA INPUT TO BUS OUTPUT (DRIVER)

V Cc
Pulso
Generator
FIGURE 2 - ENABLE INPUT TO BUS OUTPUT (DRIVER)

V CC
Enable
In p u t
D river
Pulse
G enorator
O utput
FIGURE 3 - BUS INPUT TO RECEIVER OUTPUT

V CC
T o S c o p #
(O u tp u t)
1N 916
VO H Orivsr
O utput
(In p u t) V q l *
V
'P H L ( R )
VOHRecciver
O u tp u t
VO L-
E quivalent
M------I S p F (Total)
*P L H (R )
Scopo
(Inp u t)
<3
J.
5-18
SO pF
(Total)
V cc
MOTOROLA
MC75S110
MONOLITHIC DUAL LINE DRIVERS
The M C75S110 dual line driver features independent

channels with common voltage supply and ground termi
nals. Each driver circuit provides a constant output current
that switches to either of two output terminals subject to
the appropriate logic levels at the input terminals. Output
current can be switched "off (inhibited) by appropriate logic
levels at the inhibit inputs. Output current is nominally
twelve milliamperes for the M C75S110.
The inhibit feature permits use in party-line or data-bus
applications. A strobe or inhibitor, common to both drivers,
is included to increase driver-logic versatility. With output
current in the inhibited mode, lO(off) is specified so that
minimum line loading occurs when the driver is used in a
party-line system with other drivers. Output impedance of
the driver in inhibited mode is very high (the output
impedance of a transistor biased to cutoff).
All driver outputs have a common-mode voltage range
of -3.0 volts to +10 volts, allowing common-mode voltage
on the line without affecting driver performance.
Insensitive to Supply Variations Over the Entire
Operating Range
MTTL Input Compatibility
Current-Mode Output (12 mA Typical)
High Output Impedance
High Common-Mode Output Voltage Range
(-3.0 V to +10 V)
Inhibitor Available for Driver Selection
O UTPUTS
V CC
IV
12
IN H IB IT
IN P U T
V EE
DUAL LINE DRIVERS

Wmm
141) DICII II || u u
L S U F F IX
CASE 632
pT f T T in
P S U F F IX
CASE 6 46
(T O -1 16)
O U TP U TS
2Z
2Y
TRUTH TABLE
IN H IB IT O R
IN P U TS
L O G IC IN P U TS
A
L or H
L or H
L
L or H
H
B
L or H
L Or H
L or H
L
H
OUTPUTS
V
2
D
L or H
L or H
H
L
H
H
H
H
H
L
H
L o w o u t p u t re p re s e n ts th e " o n " s ta te .
H ig h o u t p u t re p re s e n ts th o " o f f " s ta te .
L O G IC
IN P U T S
IN H IB IT
IN P U T S
L O G IC
IN P U TS
5-19
H
L
MC75S110
MAXIMUM RATINGS (TA - 0 to +70C unless otherwise noted.)

Ratings
Symbol
Value
Unit

(See Note 1)
Vcc
VEE
+7.0
-7.0
Volts
Logic and Inhibitor Input Voltages

(See Note 1)
V in
5.5
Volts
VOCR
-5.0 to +12
Volts
1000
3.85
mW
mW/C
Common-Mode Output Voltage Range

(See Note 1)
Plastic and Ceramic Dual In-Line Packages
Derate above T a " +25C
Pd
0 to +70
ta

Ceramic Dual In-Line Package
Plastic Dual In-Line Package
C
C
T stg
-65 to +150
~o5 to +150
RECOMMENDED OPERATING CONDITIONS (See Notes 1 and 2.)

Characteristic
Positive
Negative
Symbol
Min
Norn
Max
Unit
VCC
VEE
+4.75
-4.75
+5.0
-5.0
+5.25
-5.25
Volts
v OCR
0
0
Volts
+10
-3.0
Note 1. These voltage values are in respect to the ground terminal.

Note 2. When using only one channel of the line drivers, the other channel should be
inhibited and/or its outputs grounded.
DEFINITIONS OF INPUT LOGIC LEVELS*

Characteristic
High-Level Input Voltage (at any input)
Low-Level Input Voltage (at any input)
Symbol
Test Fig.
Min
Max
Unit
V|H
1.2
2.0
5.5
Volts
0.8
Volts
1.2
V|L
* The algebraic convention, where the most positive limit is designated maximum, is used with
Logic Level Input Voltage Levels only.
MC75S110
ELECTRICAL CHARACTERISTICS (TA 0 to +70C unless otherwise noted.)

Characteristic a a
High-Level Input Current to 1A, IB, 2A or 2B
Symbol
Test Fig.
i h l
(V cc = Max, V EE = Max, V m ^ = 2.4 V I*

(Vcc = Max, V EE = Max. V |H l = v c c Maxi
Low-Level Input Current to 1A, 1B, 2A or 2B
Min
MC75S110
Typ s
Max
Unit
40
1.0
MA
mA
-3.0
40
1.0
-3.0
80
2.0
-6.0
12
15
mA
(Vcc = Max, VEE = Max, V|L(_ 0.4 V)

High-Level Input Current into 1C or 2C
(VCC = Max. V EE = Max, V|H, = 2.4 V)
(Vcc = Max, VEE = Max, V|Hj Vcc Max)
lH|
Low-Level Input Current into 1C or 2C

(V cc = Max, V EE 3 Max,V|L| = 0.4 V)
lL|
High-Level Input Current into O

(Vcc = Max. VEE = Max, V|H| 2.4 V)
(V cc = Max, V EE = Max, V|Hj Vcc Max)
lH|
Low-Level Input Current into D

(VCC Max, VEE = Max, V|(_| 0.4 V)
'IL|
Output Current ("on" state)

(V c c = Max, V EE = Max)
(Vcc = Min, V EE = Min)
!0(on)
Output Current ("off state)

(Vcc = Min, V EE = Min)
'O(off)
Supply Current from Vcc (with driver enabled)

(V ,L l = 0.4 V .V , h , = 2.0 V)
'CC(on)
Supply Current from V EE (with driver enabled)

(V |L l = 0.4 V. V |H| =2.0 V)
'EE(on)
Supply Current from Vcc (with driver inhibited)

(V| LL 0.4 V, V)L| =0.4 V)
ICC(off>
Supply Current from VEE (with driver inhibited)

(V |L l = 0.4 V, V |L| =0.4 V)
*EE (off)
2
mA
mA
mA
nA
mA
mA
mA
6.5
>iA
-
100
mA
28
35
-41
-50
21
-41
-50
mA
mA
mA
AII typical values are at Vcc a +5.0 V, VEE -5.0 V.

o s F o r conditions shown as Min or Max, use the appropriate value specified under recommended
operating conditions.
SWITCHING CHARACTERISTICS (VCC - +5.0 V. VEE = -5.0 v. T A = +25C.)

Characteristic
Symbol
Test Fig.
Min
Typ
Max
9.0
9.0
15
15
PLHL
PHLL
Propagation Delay Time from Inhibitor Input C or D
to Output Y or 2 (R l = 50 ohms. Cl 40 pF)
ns
5
*PLH|
PHL|
Unit
ns
Propagation Delay Time from Logic Input A or 8 to

Output Y or 2 (R|_ = 5 0 ohms, C|_ 40 pF)
16
13
25
25
MC75S110
TEST CIRCUITS
FIGURE 1 - V ,H. V |L. I| H.
Vcc
>| L
V Eg
i_ _ _ l
'O(on)
Soa
Table
V |L <
'O(off)
/
OUTPUT
1Y o r 2Y
OUTPUT
1Z o r 2Z
ALL INHIBITOR
INPUTS
Open
V lH ,
V "-L
VCc
V|H,
,|H L
4.5 V
V |H|
Gnd
Gnd
'" L
Gnd
V |H ,
Gnd
Gnd
>
LOGIC INPUTS
NOT UNDER TEST
TEST AT ANY
LOGIC INPUT
OUTPUTS
_>
NOTES:
H
(Soa N ote 1)
L
(See N ote 1)
L
(See N ote 1)
H
(See N ote 1)
1. Low o u tp u t represents tho " o n " state, high o utp u t represents tho " o f f * ctato.
2. Each input it tested separately.
3. Arrow s indicata actual direction o f current flo w .
FIGURE 2 - V |H, V |L. IIH< l | L

V CC
V EE
J__. I
TEST AT ANY
INHIBITOR INPUT
V |H ,
V ,L ,
INHIBITOR INPUTS
NOT UNDER TEST
OUTPUT
1Y or 2Y
V |H ,
Open
H(Soo N ote 1)
LISee N ote 1)
V ><-L
V ,H U
Open
LISeoN ote 1)
H ISeeN ote 1)
ALL LOGIC
INPUTS
v <l l
OUTPUT
IZ o r 2Z
V Cc
H(Soe N oto 1)
H(See Note 1)
H(Soe N ote 1)
H(Soo Noto 1)
Gnd
Gnd
Gnd
Gnd
IH,
Gnd
V CC
4.5 V
'I L ,
Gnd
Gnd
5-22
MC75S11Q
TEST CIRCUITS (continued)

FIG U RE 3 - iQ (on)
Vcc
O(oH)
V EE
Arrow * Indicate actual direction

of currant (low.
TEST TABLE__________________________
TEST
G round all o u tp u t pins
n o t under test.
'O (on)
'O (on)
'O (o ff)
at output
1Y or 2Y
at o utp u t
1Z o r 22
at o utput
1Y or 2Y
LOGIC INPUTS
1A o r 2A
IB o r 2B
IN H IBITO R INPUTS
1C o r 2C
D
V| L
V |L
V |H
V )L
V(H
V lL
V lH
V lH
V|H
V lH
V lH
V|H
V|H
V |H
V lH
V|H
V |L
V |H
V lL
V |H
V lH
Either
state
V iL
V lL
V |H
V iL
V |H
V lL
'O (o ff)
at output
I Z o r 22
V |L
V lL
V |H
'O (oH )
at o utput
1Y. 2Y . 1Z, o r 2Z
Either
state
FIGURE 4 Iqc and IÊ

V CC
V EE
TEST TABLE
lc c ( n>
'EE(on)
iCC<offl
ig g to ff)
5-23
TEST
Drlvor
Driver
Driver
Driver
enablod
enabled
in hibited
inhibited
A L L LOGIC
INPUTS
A L L IN H IB IT O R
INPUTS
V lL
V lL
V lL
V iL
V lH
V |H
V |L
V iL
MC75S110

FIGURE 5 - PROPAGATION DELAY TIMES TEST CIRCUIT AND WAVEFORMS
NOTES:
1. Tha pulse genorators have the follow ing characteristics: z 50 i l . t r = t f = 10 5 ns, t p i 500 ns, PRR 1 M H i,
tp 2 * 1 m** PRR " 500 kHz.
2. C|_ includes probe and Jig capacitance.
3. For sim plicity, only one channel and the in hibito r connections are shown.
i*4
MC1411
MC1412
MC1413
MC1416
MOTOROLA
HIGH-VOLTAGE, HIGH-CURRENT
DARLINGTON TRANSISTOR ARRAYS
(ULN2001 A)
(ULN2002A)
(ULN2003A)
(ULN2004A)
PERIPHERAL
DRIVER ARRAYS
The seven NPN Darlington-connected transistors in these arrays

are well suited fo r driving lamps, relays, or p rin te r hammers in
a variety o f industrial and consumer applications. Th e ir high break
dow n voltage and internal suppression diodes insure freedom from
IN T E G R A T E D C IR CU ITS
problems associated w ith inductive loads. Peak inrush currents

to 600 m A perm it them to drive incandescent lamps.
The MC1411 device is a general-purpose array fo r use w ith
D T L , T T L , PMOS, or CMOS Logic. The MC1412 contains a zener
diode and resistor in series w ith the in p u t to lim it input current
fo r use w ith 14 to 25 V o lt PMOS Logic. The MC1413 w ith a 2.7 kf2
series in p u t resistor is well suited fo r systems u tilizin g 5 V o lt T T L
o r CMOS Logic. The MC1416 uses a series 10.5 kJ2 resistor and
is useful in 8 - 1 8 V o lt MOS systems.
P SUFFIX
CASE 6 48
M A X IM U M R A TIN G S (T a = 25C and rating apply to any one device in the

package unless otherwise noted.)
L SUFFIX
Symbol
Value
Unit
O utput Voltage
v0
50*
Input Voltage (Except MC1411)
V|
30
Collector Current Continuous
500
mA
Base Current Continuous
25
mA
uc
Rating

ta
0 to +85
T stg
-5 5 to +150
Tj
150
Maximum Package Power Dissipation (See Thermal Inform ation Section)

Higher voltage selection available. See your local representative.
CASE 6 2 0
PIN CONNECTIONS
EEE(7 -
D EVIC E CROSS-REFERENCE LISTIN G

9665
9666
9667
9668
- SN75476 - U L N 2 0 0 1 A
- SN75477 - U L N 2 0 0 2 A
- SN75478 - U L N 2 0 0 3 A
U LN 2 0 0 4 A
- order
- order
- order
order
MC141 IP
MC1412P
MC1413P
MC1416P
5-25
EEEE-
- O
t r
- >
i >
-E
t t
;- - 3
- 3
MC1411, MC1412, MC1413, MC1416
ELECTRICAL CHARACTERISTICS (TA - 25C unlaw otherwise noted)

Characteristic
Output Leakage Current
<Vo 5 0 V .T A -+ 7 0 C )
*(V q 50 V, TA - +25C)
*<V0 - 50 V. TA +70C, V| 6.0 V)
*(V 0 - 50 V, TA - +70C, V | = 1.0 V)
Symbol
All Types
All Types
MC1412
MC1416
Collector-Emitter Saturation Voltage

(iC 350 mA, I q - 5 00 mA)
(lc - 200 mA, I b - 350 mA)
(lC -1 0 0 mA. Ib 250 mA)
Input Current On Condition
IV| " 17 V)
(V| - 3.85 V)
<V| 5.0 V)
( V | 12 V)
Input Voltage On Condition
IVCe 2.0 V, lC D 300 mA)
(VCE - 2.0 V, IC - 200 mA)
(VCe - 2.0 V , IC -2 5 0 mA)
(V c e - 2-0 V, lC - 300 mA)
(VCE " 2.0 V, lC 125 mA)
(VcE 2.0 V, lC 200 mA)
Vc e 2.0V . IC 275 mA)
<Vc e " 2 .0 V , I c 350 mA)
Input Current Off Condition
(lC 500 jiA, T a +70C)
DC Current Gain
(VCB fa2^)V, 1C = 350 mA)
Typ
Max
100
50
500
500
1.1
055
0 35
1.6
1.3
1.1
0.85
0.93
0.35
1.0
1.3
1.35
OS
1 j45
mA
11(on)
MC1412
MC1413
MC1416
MC1416
V|(on)
MC1412
MC1413
MC1413
MC1413
MC1416
MC1416
MC1416
MC1416
Unit
|iA
v CE(sat)
13
2.4
2.7
3.0
5.0
6.0
7.0
8.0
'Hoff)
50
100
hFE
1000
*iA
_
MC1411
Input Capacitance
Turn-On Delay Tima
(50% E| to 50% Eq )
Turn-Off Delay Tima
(50% E| to 50% E0 )
Clamp Dloda Leakage Current
(VR - 5 0 V )
Min
<CEX
TA - +25C
T a +70C
Clamp Dloda Forward Voltage

dp -3 5 0 mA)
C|
15
0.25
30
1.0
PF
*on
t 0ff
02 5
1j0
iu
>R
50
100
MA
Vf
IS
2.0
Higher voltage selections available, contact your local representative.
TYPICAL PERFORMANCE CURVES - T a 25C

FIGURE 2 - OUTPUT CURRENT mr*us INPUT CURRENT
OUTPUT CURRENT (mA)
FIGURE 1 - OUTPUT CURRENT varsus INPUT VOLTAGE
5-26
MC1411, MC1412, MC1413, MC1416
TYPICAL CHARACTERISTIC CURVES - T
2SC (continued)
FIGURE 4 - INPUT CHARACTERISTICS - MC1412
*C. COLLECTOR CURRENT (mA)
FIGURE 3 - TYPICAL OUTPUT CHARACTERISTICS
FIGURE 6 - INPUT CHARACTERISTICS - MC1416
I|. INPUT CURRENT (mA)
FIGURE 6 - INPUT CHARACTERISTICS - MCI413
FIGURE 7 - MAXIMUM COLLECTOR CURRENT

versus DUTY CYCLE
(AND NUMBER OF DRIVERS IN USE) - CERAMIC or PLASTIC
5-27
MC1411, MC1412, MC1413, MC1416
REPRESENTATIVE CIRCUIT SCHEMATICS
1 O P In g
f^ -O P in 9
5-28
MC1472
MOTOROLA
DUAL PERIPHERAL
POSITIVE "NAND" DRIVER
DUAL PERIPHERAL-HIGH-VOLTAGE
POSITIVE "NAND" DRIVER
The dual driver consists o f a pair o f PNP-buffered A N D gates

connected to the bases o f a pair o f high-voltage NPN transistors.
They are sim ilar to the M C 75452 drivers b u t w ith the added advan
tages o f: 1) 70 V o lt ca p a b ility 2) o u tp u t suppression diodes and
3) PNP buffered inputs fo r MOS co m p a tib ility . These features make
the MC1472 ideal fo r m ating MOS logic or microprocessors to
lamps, relays, p rin te r hammers and incandescent displays.
300 m A O u tp u t C ap a b ility (each transistor)
70 V d c Breakdown Voltage
Internal O u tp u t Clamp Diodes
Low In p u t Loading fo r MOS C o m p a tib ility (PNP buffered)
U SU FFIX
P1 SU FFIX
CASE 6 9 3
CASE 626
CROSS REFERENCE
U DN -5712 - SN75475 - MC1472
M A X IM U M R A TIN G S (TA 25C , Note 1).
Value
Unit
Supply Voltage
7.0
Volts
Volts
Rating
Input Voltage
5.5
O utput Voltage
80
Volts
Clamp Voltage
80
Volts
O utput Current (Continuous)
300
mA

Ceramic Package
Plastic Package
+175
+150

Note 1:
-65 to +150
"M axim um Ratings" are those values beyond which the safety of the device
cannot be guaranteed. They are not meant to im ply that the device should
be operated at these lim its. The "Table o f Electrical Characteristics" pro
vides conditions for actual device operation.
RECO M M END ED O P E R A TIN G C O N D ITIO N S

Symbol
Min
Max
U nit
Vcc
4.5
5.5
Volts
Operating Am bient Temperature
ta
70
O utput Voltage
v0
vc
0
vcc
v0
70
Volts
70
Volts
Rating
Supply Voltage
Clamp Voltage
5-29
TR UTH TABLE
A
H ("O F F " S TATE)
H ("O F F " S TATE)
H ("O F F " S TATE)
L ("O N " S TATE)

H L o g ic Ono
L Log ic Zo ro
MC1472
ELECTRICAL CHARACTERISTICS Unless otherwise noted min/max limits apply accross the 0C to 70C temperature range with
4 5 V V c c 1 5J6 V. All typical values are for TA 25C .V cc 5 Volts.
Characteristic
Symbol
Min
V|H
2.0
5.5
Vdc
V|L
0.8
Vdc
'IL
-0.3
-0.15
mA
40
20

(V | l 0.4V)
A Input
B Input
(V |H = 2.4V)
A input
B Input
(V|H 5.5V)
A Input
B Input
>IH
Typ
Max
Unit
200
100
-1.5
MA
Input Clamp Voltage

(lie - -12mA)
V |C
Output Leakage Current High Logic State

(V(j = 70V, See test Figure)
'OH
100
MA
VOL
0.4
0.7

(I q l 100 mA)
(l0 L 300 mA)
Output Clamp Diode Leakage Current
(Vc 70V, See test Figure)
>OC
100
IiA
Output Clamp Forward Voltage

(IpC 300 mA See test Figure)
V FC
1.7
15
70
mA

(All Inputs at V | h )
(All Inputs at V||_)
cc
NOTE: All currents into device pins are shown as positive, out of device pins as negative. All voltages referenced to ground unless otherwise
noted.
SWITCHING CHARACTERISTICS VCc 5.0V. T A 25C

Symbol
Min
Typ

Output High to Low
Output Low to High
Characteristic
*PHL
PLH
Output Transition Time

Output High to Low
Output Low to High
*THL
*TLH
5-30
Max
Unit
1.0
0.75
0.1
0.1
MS
MC1472
TEST CIRCUITS
Q
V |H a V (L
Per T ru th Tablo
n i
' k. 1
1k- 4
3
4
v cc
Vcc
VOL
VOL(^v)
r
OL
r- 1
* vcc
4
Vp<v)
_ L M fc I
Vcc
5
T
SWITCHING TEST CIRCUIT AND WAVEFORM

+80 V
5-31
ToScopo
<g>
MOTOROLA
MC1488
QUAD MDTL LINE DR IVER

RS-232C
QUAD LINE DRIVER
The MC1488 is a m o n o lith ic quad line driver designed to inter

face data term inal equipm ent w ith data com m unications equipm ent
in conformance w ith the specifications o f El A Standard No. RS-232C.
Features:
Current Lim ite d O u tp u t

10 m A ty p
Power-Off Source Impedance

300 Ohms min
Simple Slew Rate C ontrol w ith External Capacitor
Flexible Operating Supply Range
C om patible w ith A ll M otorola M D T L and M T T L Logic Families
L S U F F IX
P S U FF IX
CASE 6 32
TO -116
CASE 646
P IN C O N N E C T IO N S
------- W -------
C IR C U IT SCHEM ATIC
(1/4 OF CIRCUIT SHOWN)
5-32
MC1488
M A X IM U M R A TIN G S (T^ +25C unless otherwise noted.)

Symbol
Rating
Vcc
vee
Input Voltage Range
V|R
Output Signal Voltage
v0
Power Derating (Package Limitation,Ceramicand Plastic Dual-In-Line Package)

Vdc
Vdc
15
Vdc
1000
6.7
mW
mW/C
ta
0 to +75
Tstg
-6 5 to +175
ELEC TR IC A L C H A R AC TER ISTIC S IV g o = +9.0 1% Vdc, V e e = -9 .0 1% Vdc.

Characteristic
Unit
+15
-1 5
- 1 5 < V |R < 7.0
PD
1/RtfJA
Derate above TA = +25C
Value
= 0 to +75C unless otherwise noted.)
Figure
Symbol
Min
Typ
Max
Unit
Input Current Low Logic State ( V||_ = 0)
Ml
1.0
1.6
mA
Input Current - High Logic State (V | h = 5.0 V)
'IH
10
v OH
(V |L = 0.8 Vdc, R L = 3.0 k fi, V c c +9 0 Vdc, Vgg = -9 0 Vdc)
+6.0
+7.0
(V |L = 0.8 Vdc, R l = 3.0 k , V c c +13-2 Vdc, V e e = -13.2 Vdcl
+9.0
+10.5
-6.0
-7.0
-9.0
-10.5

(V|H = 1.9 Vdc, R L = 3.0 k n , V c c = +9 vdc>V e e = -9.0 Vdc)
Vdc
v OL
<V|H = 1.9 Vdc, Ri_ 3.0 k n , V c c = +13-2 vdc- V e e = "13-2 Vdc)
MA
Vdc
Positive Output Short-Circuit Current (1)
>OS+
+6.0
+10
+ 12
Negative Output Short-Circuit Current (1)
>0S-
-6.0
-10
-12
mA
Output Resistance (V c c = V EE 0. I v o | = 2.0 V)
ro
300
Ohms
Positive Supply Current (R| = oo)

(V |H = 1-9 Vdc, Vc c = +9.0 Vdc)
cc
mA
mA
-
+15
+20
(V il = 0.8 Vdc, V c c = +9 0 Vdc)
+4.5
+6.0
(VjH = 1.9 Vdc, Vcc " + , 2 Vdc)
+ 19
+25
(V (L = 0.8 Vdc, Vc c D +12 Vdc>

(V |H = 1.9 Vdc, V c c +15 Vdc)
+5.5
_
+7.0
(V | l 0.8 Vdc, VCc +15 Vdc)
+12
-13
-17
-1 5
mA
mA
<V|H = 1.9 Vdc] V e e - -12 Vdc)
-18
-23
mA
(V|i_ 0.8 Vdc, V e e - 12 vdc>
-1 5
(V ,H 1.9 Vdc, V e e -15 Vdc)
-34
MA
mA
(V |L = 0.8 Vdc, V e e - -15 Vdc)
-2.5
Negative Supply Current (Rj_ oo)

(V |H 1.9 Vdc, V e e " "9.0 Vdc)
e e
(V lL = 0.8 Vdc, V EE -9.0 Vdc)
Power Consumption
(V c c 9.0 Vdc, VgE -9 0 Vdc)
(V c c * 12 Vdc, V e e -1 2 Vdc)
+34
mA
mW
Pc
333
576
SW ITCHING C H A R AC TER IS TIC S (V c c - +9.0 1% Vdc, V EE = -9.0 1% Vdc, T A = +25C.)

Propagation Oelay Time (i| = 3.0 k and 15 pF)
*PLH
275
350
Fall Time
<Z| = 3.0 k and 15 pF)
l THL
45
75
ns
Propagation Oelay Time
(z| 3.0 k and 15 pF)
*PHL
110
175
ns
Rise Time
(zi 3.0 k and 15 d F)
tT I H
55
100
ns
(1) Maximum Package Power Dissipation may be exceeded if all outputs are shorted simultaneously.
5-33
ns
MC1488
CHARACTERISTIC D E FIN ITIO N S
FIGURE 1 - INPUT CURRENT

+9 V
FIGURE 2 - OUTPUT VOLTAGE
-9 V
+9 V
FIGURE 3 - OUTPUT SHORT-CIRCUIT CURRENT

vcc
-9 V
FIGURE 4 - OUTPUT RESISTANCE (POWER-OFF)
vee
FIGURE S - POWER-SUPPLY CURRENTS
FIGURE 6 - SWITCHING RESPONSE
Vcc
3k
1
--------1 5tcp .Fc
^
+3 V 1.5 V -
*in
tPHL
v0-
PIH
A . SOS
tTHL
TLH
tTHL <nd tTLH Mniuted 10% to 90%
vee
5-34
VO
SLEW RATE (VOLTS/ut)
VCC. VEE. POWER SUPPLY VOLTAGE (VOLTS)
T, TEMPERATURE CC)
i s
3
*
5 S
mc
? S
I?
- I
z
.o O
3 H
> m
O 3
IT) TJ
ID
>
-i
c
n
IQ. OUTPUT CURRENT (mA)
Ln
MC1488
FIGURE 13 - POWER-SUPPLY PROTECTION

TO MEET POWER-OFF FAULT CONDITIONS
The Electronic Industries Association (EIA) has released the
RS232C specification detailing the requirements for the interface
between data processing equipment and data communications
equipment. This standard specifies not only the number and type
of interface leads, but also the voltage levels to be used. The
MC1488 quad driver and its companion circuit, the MC1489
quad receiver, provide a complete interface system between DTL
or TTL logic levels and. the RS232C defined levels. The RS232C
requirements as applied to drivers are discussed herein.
The required driver voltages are defined as between 5 and 15volts in magnitude and are positive for a logic "0" and negative for
a logic " 1 These voltages are so defined when the drivers are
terminated with a 3000 to 7000-ohm resistor. The MC1488 meets
this voltage requirement by converting a DTL/TTL logic level into
RS232C levels with one stage of inversion.
The RS232C specification further requires that during transi*
tions, the driver output slew rate must not exceed 30 volts per
microsecond. The inherent slew rate of the MC1488 is much too
FIGURE 12 - SLEW RATE versus CAPACITANCE

FOR Is c 10 mA
would be excessive. Therefore, if the system is designed to permit
low impedances to ground at the power-supplies of the drivers, a
diode should be placed in each power-supply lead to prevent over
heating in this fault condition. These two diodes, as shown in
Figure 13, could be used to decouple all the driver packages in a
system. (These same diodes will allow the MCI 488 to withstand
momentary shorts to the 25-volt limits specified in the earlier
Standard RS232B.) The addition of the diodes also permits the
MC1488 to withstand faults with power-supplies of less than the
9.0 volts stated above.
The maximum short-circuit current allowable under fault con
ditions is more than guaranteed by the previously mentioned
10 mA output current limiting.
Other Applications
C. CAPACITANCE IpFI
fast for this requirement. The current limited output of the device
can be used to control this slew r8te by connecting a capacitor to
each driver output. The required capacitor can be easily determined
by using the relationship C lo s * A T/AV from which Figure 12 is
derived. Accordingly, a 330-pF capacitor on each output will
guarantee a worst case slew rate of 30 volts per microsecond.
The interface driver is also required to withstand an accidental
short to any other conductor in an interconnecting cable. The worst
possible signal on any conductor would be another driver using a
plus or minus 15-volt, 500-mA source. The MC1488 is designed to
indefinitely withstand such a short to all four outputs in a package
as long as the power-supply voltages are greater than 9.0 volts (i.e.,
v C C >9 -0 V; V g E ^ -9 .0 V). In some power-supply designs, a loss
of system power causes a low impedance on the power-supply out
puts. When this occurs, a low impedance to ground would exist at
the power inputs to the M C I488 effectively shorting the 300-ohm
output resistors to ground. If all four outputs were then shorted
to plus or minus 15 volts, the power dissipation in these resistors
The MC1488 is an extremely versatile line driver with a myriad

of possible applications. Several features of the drivers enhance
this versatility:
1. Output Current Limiting this enables the circuit designer
to define the output voltage levels independent of power-supplies
and can be accomplished by diode clamping of the output pins.
Figure 14 shows the MC1488 used as a OTL to MOS translator
where the high-level voltage output is clamped one diode above
ground. The resistor divider shown is used to reduce the output
voltage below the 300 mV above ground MOS input level limit.
2. Power-Supply Range as can be seen from the schematic
drawing of the drivers, the positive and negative driving elements
of the device are essentially independent and do not require match
ing power-supplies. In fact, the positive supply can vary from a
minimum seven volts (required for driving the negative pulldown
section) to the maximum specified 15 volts. The negative supply
can vary from approximately -2.5 volts to the minimum specified
15 volts. The MC1488 will drive the output to within 2 volts of
the positive or negative supplies as long as the current output limits
are not exceeded. The combination of the current-limiting and
supply-voltage features allow a wide combination of possible out
puts within the same quad package. Thus if only a portion of the
four drivers are used for driving RS232C lines, the remainder could
be used for DTL to MOS or even DTL to OTL translation. Figure 15
shows one such combination.
MC1488
FIGURE 14 - MDTL/MTTL-TO-MOS TRANSLATOR
FIGURE 15 - LOGIC TRANSLATOR APPLICATIONS
+ I2 V
. rMRTL
on i l u
OUTPUT
u iru
* -0.7 V to +3.7 V
T
MOTL
MTTL'
INPUT
MOS OUTPUT
(WITH VSS-GNO)
- O
8
-12 V
i+3.0V-
m
T T
A +5V
_____
MOTL OUTPUT
-0.7 V to +5.7 V
MHTL OUTPUT
-0.7 V to 10 V
V -------- O f
AMr
k
^T Y '
7
0 14
MOS OUTPUT
-10 V to O V
<8>
MOTOROLA
MC1489L
MC1489AL
QUAD MDTL
LINE RECEIVERS
RS-232C
QUAD LINE RECEIVERS
SILIC O N M O N O LIT H IC
The MC1489 m o n o lith ic quad line receivers are designed to in te r
face data term inal equipm ent w ith data com m unications equipment
in conformance w ith the specifications o f El A Standard No. RS-232C.
In p u t Resistance 3.0 k to 7.0 kilohm s

Inp u t Signal Range - 30 V o lts
In p u t Threshold Hysteresis B u ilt In
Response C ontrol
a) Logic Threshold S hifting
b) Inp u t Noise F iltering
L SUFFIX
C E R A M IC P AC K A G E
CASE 632
T O -116
P S U FF IX
P LA S T IC P AC K A G E
CASE 646
In p u t A [ T
Rojponse r
C o n tro l A I
O u tp u t A :
C o n tro l D
TT| O u tp u t
To] In p u t C
Responso
C o n tro l C
~8~| O u tp u t C
5-38
MC1489L, MC1489AL
M A X IM U M R A TIN G S (TA = +25C unless otherwise noted)

Symbol
Valua
Unit
Vcc
10
Vdc
Input Voltage Range
V|R
30
Vdc
Output Load Current
'L
20
mA
pd
1000
6.7
mW
mW/C
ta
0 to +75
Tstg
-65 to +175
6c
c
Rating
Power Dissipation (Package Limitation, Ceramic and Plastic Dual In-Line

Package)
Derate above TA +25C
1/ffjA

5
ELECTRICAL CHARACTERISTICS (Response control pin is open.) (V cc +5.0 Vdc 1%, T a = 0 to +75C unless otherwise noted)
Figure
Symbol
Min
Positive Input Current
(V | h +26 Vdc)
(V |n o +3.0 Vdc)
>IH
3.6
0.43
Negative Input Current
(V||_ -2 5 Vdc)
(V |L - -3.0 Vdc)
IL
-3.6
-0.43
V|H L
Characteristics
Input Turn-On Threshold Voltage

(TA +25C, V0 L * 0.45 VI
Unit
8.3
mA
-8.3
mA
1.95
1.5
2.25
0.75
0.75
Vdc
1.0
1.75
MC1489
MC1489A
Input Turn-Off Threshold Voltage

(TA = +25C, VOH 2 .5 V. I|_ = -0.5 mA)
Max
Typ
Vdc
V|LH
MC1489
MC1489A
0.8
1.25
1.25
Output Voltage High
(V m 0.75 V , l|_ * -0.5 mA)

(Input Open Circuit, l|_ -0.6 mA)
VOH
2.6
2.6
4.0
4.0
5.0
5.0
Vdc
Output Voltage Low
(V | l 3.0 V, I I 1 0 mA)
VOL
0.2
0.45
Vdc
os
'cc
Pc
3.0
mA
20
26
mA
100
130
mW

(V |H +5-0 Vdc)
Power Consumption
(V jh +5.0 Vdc)
SWITCHING CHARACTERISTICS (VCc - 5.0 V d c IX , TA - +25C)

(R L = 3.9 kn>
tPLH
25
85
ns
Rise Time
(R L 3.9 k)
*TLH
120
175
ns
(R L 39 0 n >
tPHL
25
50
ns
Fall Time
(R L = 390 n )
*THL
10
20
ns
5-39
MC1489L, MC1489AL
TEST CIRCUITS
FIGURE 3 - OUTPUT SHORT-CIRCUIT CURRENT
FIGURE 4 - POWER-SUPPLY CURRENT
V cc<
FIGURE 5 - SWITCHING RESPONSE
FIGURE 6 - RESPONSE CONTROL NODE
VR
_L
1/4
MCI489A
RESPONSE NOOE
C. capacitor it lor nois filtering.

R. rejistor is (or threshold shilling.
Ct * 15 pF (otil putsitic uptcitinct. wtiich includes
prob *nd writing cipniunce
5-40
>V0
MC1489L, MC1489AL
(Vcc 5.0 Vdc, T a +25C unless otherwise noted)
FIGURE 8 - M C I489 INPUT THRESHOLD
VOLTAGE ADJUSTMENT
11. INPUT CURRENT (mA)
Vi, INPUT VOLTAGE (Vdc)
Vin. INPUT VOLTAGE (VOLTS)
FIGURE 10 - INPUT THRESHOLD VOLTAGE

versus TEMPERATURE
Vo. OUTPUT VOLTAGE (Vdc)
FIGURE 9 - MC1489A INPUT THRESHOLD

VOLTAGE ADJUSTMENT
T. TEMPERATURE <C)
FIGURE 11 - INPUT THRESHOLD versus

POWER-SUPPLY VOLTAGE
V|Hl MC1489A
V|LH MC1489 _
----- V|LH AC1489A
4.0
8.0
VCC. POWER SUPPLY VOLTAGE (Vdc)
8-41
MC1489L, MC1489AL
General Information
rejection. The MC1489 input has typical turn-on voltage of 1.25
volts and turn-off of 1.0 volt for a typical hysteresis of 250 mV.
The M C I489A has typical turnon of 1.95 volts and turn-off of
0.8 volt for typically 1.15 volts of hysteresis.
Each receiver section has an external response control node in
addition to the input and output pins, thereby allowing the design
er to vary the input threshold voltage levels. A resistor can be
connected between this node and an external power-supply- Fig
ures 6, 8 and 9 illustrate the input threshold voltage shift possible
through this technique.
This response node can also be used for the filtering of highfrequency, high-energy noise pulses. Figures 12 and 13 show
typical noise-pulse rejection for external capacitors of various sizes.
These two operations on the response node can be combined
or used individually for many combinations of interfacing appli
cations. The MC1489 circuits are particularly useful for interfacing
between MOS circuits and M OTL/M TTL logic systems. In this
application, the input threshold voltages are adjusted (with the
appropriate supply and resistor values) to fall in the center of the
MOS voltage logic levels. (See Figure 14)
The response node may also be used as the receiver input as
long as the designer realizes that he may not drive this node with
a tow impedance source to a voltage greater than one diode above
ground or less than one diode below ground. This feature is
demonstrated in Figure 15 where two receivers are slaved to the
same line that must still meet the RS-232C impedance requirement.
The Electronic Industries Association (EI A) has released the RS-232C

specification detailing the requirements for the interface between
data processing equipment and data communications equipment.
This standard specifies not only the number and type of interface
leasts, but aim the voltage levels to be used. The MC1488 quad
driver and its companion circuit, the MC1489 quad receiver,
provide a complete interface system between DTL or TTL logic
levels and the RS-232C defined levels. The RS-232C requirements
as applied to receivers are discussed herein.
The required input impedance is defined as between 3000 ohms
and 7000 ohms for input voltages between 3.0 and 25 volts in
magnitude; and any voltage on the receiver input in an open circuit
condition must be less than 2.0 volts in magnitude. The MC1489
circuits meet these requirements with a maximum open circuit volt
age of one V qe (Ref. Sect. 2.4).
The receiver shall detect a voltage between -3 .0 and -2 5 volts
as a logic "1" and inputs between +3.0 and +25 volts as a logic "0"
(Ref. Sect. 2.3). On some interchange leads, an open circuit or
power "O FF" condition (300 ohms or more to ground) shall be
decoded as an "O FF condition or logic "1" (Ref. Sect. 2.5). For
this reason, the input hysteresis thresholds of the MC1489 circuits
are all above ground. Thus an open or grounded input will cause
the same output as a negative or logic "1" input.
Device Characteristics
The MC1489 interface receivers have internal feedback from the
second stage to the input stage providing input hysteresis for noise
FIGURE 13 - TURN ON THRESHOLD versus CAPACITANCE

FROM RESPONSE CONTROL PIN TO GND
FIGURE 12 - TURN ON THRESHOLD versus CAPACITANCE

FROM RESPONSE CONTROL PIN TO GND
too
1000
too
10.000
tooo
PW, INPUT PULSE WIDTH (ns)
PW. INPUT PULSE WIDTH (ns)
5-42
10,000
MC1489L, MC1489AL
FIGURE 14 - TYPICAL TRANSLATOR APPLICATION MOS TO DTL OR TTL
FIGURE 15 - TYPICAL PARALLELING OF TWO MC1489.A RECEIVERS TO MEET RS-232C
5-43
MOTOROLA
HEX BUS R ECEIVER WITH INPUT HYSTERESIS
HEX BUS
R ECEIVER
These high-speed bus receivers are useful in bus organized data

transmission systems em ploying term inated 120 2 lines. The receivers
feature in p u t hysteresis to obtain im proved noise im m u n ity . The
receivers low in p u t current requirem ent allows up to 27 drive r/
receiver pairs to share a com m on bus. A pair o f Disable Inputs are
provided. These Disable Inputs along w ith the receiver outputs are
M T T L com patible.
(to p vlaw)
B u ilt in receiver hysteresis
Receiver in p u t threshold is n o t affected by temperature
Propagation delay tim e 20 ns (Typ)
D ire ct Replacement fo r DS8837
L SUFFIX
CASE 620
FIGURE 1 - TYPIC AL APPLICATION
120 f t
Data Bus
P SUFFIX
f>X-
CASE 648
1/6
: 437
mc
1/4
M C 3438
1 /4
M C 3438
PIN CONNECTIONS
T o C o m p ute r o r Peripherals
In p u t 4 [ jT
M A X IM U M R A T I NGS (T ^ = 25C unless otherwise noted.)

Rating
Symbol
Value
U nit
V cc
7.0
Vdc
Input Voltage
V|
5.5
Vdc
Power Dissipation
Derate above 25C
PD
625
3.85
mW
mW/C
ta
O to 70
T stg
-65 to +150
Supply Voltage

TRUTH TABLE
Input
O
5-44
Disable
L
H
1
1
L
H
Output
H
L
L
L
O - < 1.05 V
I - > 2 .5 V
H = H igh Log ic S tato
L * L o w L o g ic Stata
MC3437
ELECTRICAL CHARACTERISTICS (Unless otherwise noted, specifications apply for 0 < T a < 70C and 4.75 V < Vcc < 5 .2 5 V.)
Symbol
Min
Typ
Max
Unit

fV/UDA) -8 v - *OL '6 mA, V0 L < 0 .4 V)
V ILH(R)
1.80
2.25
2.50
Receiver Input Threshold Voltage Low Logic State

<V IL(DA) 0-8 v - 'OH * -4 00 mA, V0 H > 2 .4 V)
V|HL(R)
1.06
1.30
1.55
15
1.0
50
50
-
Charactertstic
Receiver Input Current

(V|(R) = 4.0 V, VCC= 5.25 V)
(V|(R) = 4.0 V ,V CC= 0 V )
mA
'l(R)
Disable Input Voltage High Logic State

(V|(R) = 0.5 V, V q l < 0 .4 V, Iq l " 16 mA)
V IH(DA)
2.0

(V |(R ) = 0.5 V, V q h > 2 .4 V, Iq h -400 jiA)
V|L(DA)
0.8

(V|(R) = 0.5 V, V | l (DA) 0 8 v >OH " -400*1 A)
VOH
2.4

(V|(R) B 4.0 V, V | l (DA) O' v *OL 18 mA*
VOL
0.25
0.4
80
2.0
mA

(V|H(DA) = 2.4V)
<V|H(DA) 5.5 V)
lH(DA)
Disable Input Current Low Logic State

<V,(R, = 4.0 V ,V ,L(D A ) 0.4 V)
'lL(DA)
-3.2
mA

(V|,R) 0.5 V, V ,L(DA) = 0V, V CC - 5.25 V)
os
-18
-55
mA

<V|(R) = 0.5 V, V | l ( q A) 0 V)
ice
45
70
mA
Input Clamp Diode Voltage

MR) -12 mA, l|(DA) - -12 mA,
V|
-1.0
-1.5
mA
SWITCHING CHARACTERISTICS (TA 2SC, VCc 5.0 V unless otherwise noted.)

Symbol
Min
Typ
Max
Unit
Propagation Delay Time from Receiver Input to

High Logic State Output
tPLH(R)
20
30
ns
Propagation Delay Time from Receiver Input to

Low Logic State Output
*PHL(R)
18
30
ns

High Logic State Output
*PLH(DA)
9.0
15
ns

Low Logic State Output
PHL(DA)
4.0
15
ns
Characteristic
MC3437
FIGURE 2 - SWITCHING TIMES TEST CIRCUIT AND WAVEFORMS

6.0 V
D in b l o
IDA)
FIGURE 3 - TYPICAL HYSTERESIS

(1/6 Shown)
5-46
<g>
MOTOROLA
QUAD BUS
TRAN SCEIVER
QUAD BUS TRANSCEIVER

Consists o f fo u r pair o f drivers and receivers w ith the o u tp u t of
each driver connected to the in p u t of its mating receiver. These
devices are intended fo r use in bus organized data transmission
system e m ploying term inated 120 f i lines. The receivers feature
hysteresis to im prove noise im m u n ity . A disable fu n ctio n consisting
of a tw o -in p u t NOR gate is provided to co ntro l all fo u r drivers.
Receiver in p u t threshold is n o t affected by temperature
Receiver in p u t hysteresis - 1.0 V (Typ)
Open co lle cto r driver outputs a llo w wire-OR
M T T L com patible receiver outputs and disable and driver inputs
Driver propagation delay 20 ns
Receiver propagation delay - 20 ns
D irect replacement fo r DS8838
(to p view )
L SU FFIX
CASE 6 20
P SUFFIX
CASE 648
FIGURE 1 - TYPIC AL APPLICATION
120 n
Data Bus
>1
U
1/6
M C 3437
1/4
M C 3438
1/4
M C 3438
T o C o m p u te r o r P e rip h e ra ls
TRUTH TABLES
DR IVER SECTION
Disable 1 Disable 2 Input
M A X IM U M R A T IN G S (T ^ = 25C unless otherwise noted.)

Rating
Supply Voltage
Input and O utput Voltage
Power Dissipation
Derate above 25C
Symbol
Value
Unit
vCc
7.0
Vdc
v 0 .v .
5.5
Vdc
Pd
625
3.85
mW
mW/C
ta
0 to +70
T stg
-65 to +150
L
L
H
L
L
L
L
H
H
L
L
H
H
L
H
H
H
H
H
H
RECEIVER SECTION
Bus
Output
V IH (R ) > 2 -5 v
V ,l (R )< 1 .0 5 V
L
H
W here:
L L o w L og ic S tate
H " H igh L o g ic State
5-47
Bus
L
H
L
H
L
H
L
H
MC3438
ELECTRICAL CHARACTERISTICS (Unless otherwise noted, specifications apply for 0 < T A <
Characteristic
70C and 4.75 < Vqq < 5 .2 5 V.)
Symbol
Min
Typ
Max
Unit
Disable Input Voltage - High Logic State

1VIH(D) = 2.0 V, V|H(BUS) 4- v . I b u s O O O mA)
V|H(DA)
2.0

(V|H(D) = 2.0 v , VIL(BUS) < - 7 v . 'BUS= 50 mA)
VlL(DA)
0.8

V IL(DA) -8 V, I b u S 50 mA, V |L(BUS) < 0-7 v >
V IH(D)
2.0

<V IL(DA) 0.8 V, V |H( b US) 4.0 V, IfluS < 100 jiA)
V|L(D)
0.8

*VIL(D) = 0-8 v . 'OL(R) 6 mA, V o l (R) < 0 -4 V)
V ILH(R)
1.80
2.25
2.50
Receiver Input Threshold Voltage Low Logic State

<VIL(D) = 0.8 V, lOH(R) -4 00 mA. V o H(R) > 2 .4 V)
V IHL(R)
1.05
1.30
1.55
'IH(DA)
-
40
1.0
mA
mA
40
1.0
MA
mA
W|H(D) 2 4 V- V IH(DA) * 2.4 V)

<VIH(D) 5.5 V, V|H{DA) " 5.5 V)
Driver Input Current High Logic State
<V|H(DA) = 2.4 V ,V |H (D )-2 .4 V)
'IH(D)
<V|H(DA) 5-5 V, V |H(D) 5.5 V)

Disable Input Current - Low Logic State
<V|L(DA) " 0.4 V, V |L(D) " 0.4 V)
'lL(DA)
-1.6
mA
Driver Input Current Low Logic State

(V|t_(D) = 0.4 V, V |L(DA) 0.4 VI
'IL(D)
-1.6
mA
Bus Current
<V|L(DA) 0.8 V, V | l (D) 0.8. V |H(BUS) 4-0 V)
(VCC 5 25 VI
(V c c 0 V )
'BUS
-
20
2.0
100
100
Bus Voltage Low Logic State

*V|L(DA) " 0.8 V. V|H(D) 2.0 V. lBus 50 mA)
V L(BUS)
0.4
0.7

<V|L(DA) 0.8 V, V |L(o) - 0.8 V. V |L(BUS) -5 V,
'OH(R) -4 00 pA)
v OH(R)
2.4

<V|L(DA) = 0-8 V, V|L(D) 0.8 V, V|H(BUS) = 4 0 v .
'OL(R) = 16 mA)
v OL(R)
Receiver Output Short Circuit Current

*V|L(DA) 0-8 V, V |L(D) - 0.8 V, V |L(BUS) = 0.5 V,
VCC 5.25 V)
'OS(R)
-18

<V|L(DA) 0 V, V |H(D) " 2.0 V)
'CC
V|
MA
V
V
0.25
0.4
-55
mA
50
70
mA
-1.0
-1.5
l'l(DA) = '1(D) 'BUS * - 12 mA)

SW ITC HING C HA R AC TER ISTIC S (T a 25C, Vgc 5- V unless otherwise noted.)
Characteristic
Min
Typ
Max
Unit

*PLH(DA) -
Symbol
19
27
ns

*PHL(DA)
15
27
ns
Propagation Delay .Time from Driver Input to

High Logic LevAl Output
PLH(D)
17
25
ns

*PHL(D)
9.0
20
ns

'PLH(R)
20
30
ns

*PHL(R)
18
30
ns
5-48
MC3438
FIGURE 2 - ORIVEH AND DISABLE TEST CIRCUIT AND WAVEFORMS

To Scope
(Output)
To Scope
(Input)
3V
DItable
Input
(DA) 0 V
V0 H
Output
VOL
tPLH(DA)_*
,* _tPHL(DA)
Driver
Input
Output
FIGURE 3 - RECEIVER TEST CIRCUIT AND WAVEFORM

To Scope
(Input)
To Scope
(Output)
+s- V
Receiver
Output
Driver
Input
But
Putt
Generator
r7 to r(H H
A?
>
1/4 MC3438
1N016 or
Equlv 3 I
'TMBpF 4
DItable
Inputs
1.0
2.0
3.0
V|(fi). RECEIVER INPUT VOLTAGE (VOLTS)

(1/4 Shown)
5-49
MC3440A
MC3441A
MC3443
MOTOROLA
QUAD INTERFACE
BUS TRANSCEIVERS
QUAD GENERAL-PURPOSE INTERFACE

BUS (6PIB) TRANSCEIVERS
SILICON MONOLITHIC
INTEGRATED CIRCUITS
The MC3440A, MC3441A, MC3443 are quad bus transceivers

intended for usage in instruments and programmable calculators
equipped for interconnection into complete measurement systems.
These transceivers allow the bidirectional flow of digital data and
commands between the various instruments. Each of the transceiver
versions provides four open-collector drivers and four receivers
featuring input hysteresis.
The MC3440A version consists of three drivers controlled by
a common Enable input and a single driver without an Enable input.
Terminations are provided in the device.
The MC3441A differs in that all four drivers are controlled by
the common Enable input. Again, the terminations are provided.
The MC3443 is identical to the MC3441A except that the ter
minations have been omitted. As such it is pin compatible, and
functionally equivalent to the SN75138. It does offer the advantage
of receiver input hysteresis.
Receiver Input Hysteresis Provides Excellent Noise Rejection
Open-Collector Driver Outputs Permit Wire-OR Connection
Tailored to Meet the Proposed Standards Set by the IEEE

and IEC Committees on Instrument Interface (488-1978)
Terminations Provided (except MC3443 version)
Provides Electrical Compatibility with General-Purpose

Interface Bus
P SUFFIX
PLASTIC PACKAGE
CASE 648
Output and
Termination p~
Gnd
Output and
Termination
Gnd^
MAXIMUM RATINGS (Ta - 25C unless otherwise noted.)

Rating
Symbol
Value
Unit
Vcc
V|
7.0
Vdc
6.5
150
830
6.7
Vdc
mA
mW
mW/C
C
C
Input Voltage
Driver Output Current
Power Dissipation {Package Limitation)
Derate above 2SC
'O(D)
PD

Ta
T*tg
0 to +70
-65 to +150
TYPICAL APPLICATION - GPIB MEASUREMENT SYSTEM

Output Gnd
Instrument
A
(with QPIB)
Programmabta
Calculator
(with GPIB)
Inttrumant
B
(with GPIB)
- T - - Bu
Termination
16 LtflM Total
5-50
Logic Gnd
MC3440A, MC3441A, MC3443
ELECTRICAL CHARACTERISTICS (Unless otherwise noted,4.5 V < V q q < S.S V and 0 < TA < 70C. typical values are at
___________________________________ TA 2 5 C .V c C S.0V)_____________ __________________________________________________
Characteristic
DRIVER PORTION
Symbol
Min
Typ
Man
Unit
VIH(DI
V IL(D)
2.0
input Current - High Logic State

(V|H *2 .4 V )
'IH(D)
11L (D)
V IK(D)
Output Voltage - High Logic State (1)

(MC3440A, 3441A only)
*VIH(S) 2 4 v or V IL(DI 0-8 VI
MC3443
<V|H(SI - 2.0 V, V |L(E) 0.8 V. I o l (D) 48 mA)
MC3440A, 3441A
,v IH(OI * 2.0 V. V | l (E) 0.8 V, Iq l (O) 100 mA)
VOH(D)
25
v OL(D)
0.4
0.5
0.80
Output Leakage Current - MC3443 Only

*VIH(E) 2.0 V or V |LID( 0.8 V)
'OH(D)
250
pA

(V |L 0.4 V, Vcc 5.0 V, TA = 2SC)
Input Clamp Voltage
(l|K --1 2 m A I
MC3443
MC3440A, 3441A
V
V
0.8
40
mA
-1.6
-0.26
mA
-1.5
V
V
RECEIVER PORTION
Input Hysteresis
Input Threshold Voltage - Low to High Output Logic State
< V c c -5 .0 V .T A - 25C)
Input Threshold Voltage - High to Low Output Logic State
(VCC 5.0 V, TA 25C)
(VIL(R) 0-8 v - *OH(R( -400 jjA)
MC3440A, 3441A
<V IH(R 2.0 V, lO L(R ) '6 mA)
MC3443
(V| l (R) 0.8 VI (Only one output may be shorted at a timel
400
580
mV
V|LH(RI
0.8
0.98
V IHL(R)
1.56
2.0
VOH(R)
2.4
v OL(R)
'OS(RI
-20
0.5
0.4
-55
mA
BUS TERMINATION PORTION (Dow not apply to MC3443)

Bus Voltage (V||_(d ) 0.8 V)
(lBUS -1 2 mA)
(No Lo8d)
V BUS
Bus Current
(V|L(D) 0-8 V, VguS ^ 5.0 V)
(V |L (D) - OS V. V BUS < 5.5 V)
(V i u d ) OJB V. V BUS 0 5 V)
(VCc - 0. 0 < V BUS< 2.75 V)
bu s
V
-
-1.5
3.70
2.5
-3.2
+0.04
2.50
.
mA
0.7
-1.3
-
(MC3440A, 3441A only)
TOTAL DEVICE POWER CONSUMPTION

*VIH(D) 2.4 V, V |L(E) 0 VI
30
'cc
mA
75
56
SWITCHING CHARACTERISTICS (VCc - S OV. TA 25C)

Symbol
Characteristic
DRIVER PORTION
Propagation Delay Time from Driver Input to Low Logic St8te Bus Output
Propagation Delay Time from Driver Input to High Logic State Bus Output
Propagation Delay Time from Enable Input to Low Logic State Bus Output
Propagation Delay Time from Enable Input to High Logic State Bus Output
RECEIVER PORTION
Propagation Delay Time from Bus Input to High Logic State Receiver Output
Propagation Delay Time from Bus Input to Low Logic State Receiver Output
(1) 12 k resistor from the bus terminal to V c c required on the MC3443 version.
5-51
MC3441A.3441A
Min | Typ | Max
MC3443
Min | Typ | Max
PHL(D
13
17
30
30
PLH(D)
PHL(E)
25
25
40
40
16
15
30
30
..n m E i
tPLH(R)
tPHL(R)
13
17
25
Unit
ns
25
25
25
32
32
ns
ns
ns
15
15
22
22
ns
ns
MC3440A, MC3441A, MC3443
GENERAL PURPOSE INTERFACE BUS APPLICATION
GPIB SIGNALS:
8 L in * Data B in : DI01 0108
S General In te rru p t Tranafer Control But:
REN Remote Enable
SRQ Service Request
EOI End o r Identify
A T N A tte n tio n
I PC Interface Clear
5-52
3 Data Byte T rantfer Control But

O AV - Data Valid
N R FD N o t Ready fo r Data
NOAC N o t Data Accepted
16 T otal Signal Line*
MC3440A, MC3441A, MC3443
RECEIVER INPUT (BUS) TO OUTPUT
3.0 V
Input
60%.'
0v
*-*P L H (R )
V oH *
O utput
VOL-
DRIVER AND COMMON ENABLE INPUTS TO OUTPUT (BUS)
Driver Input
OV
60K
tP H U D )-
\
tPLHID)
V 0 H --------O utput
VOL--------3.0 V -----Enable Input

0 V ------t PLH(E)~
VOHO utput
VOL'
MC3443 only.
M C3440A/3441A U M t 100 SI.

CHARACTERISTICS
1
ta*
25C
5 2.0
0.5
1.0
V|. INPUT VOLTAGE IVOLTS)
5-53
t P H U E )
MC3446A
MOTOROLA
QUAD GENERAL-PURPOSE INTERFACE

BUS (GPIB) TRAN SCEIVER
The M C 3446A is a quad bus transceiver intended fo r usage in
instrum ents and programmable calculators equipped fo r interconnec
QUAD IN TERFACE
BUS TR AN SCEIVER
tio n in to com plete measurement systems. This transceiver allows the

bidirectional flo w o f digital data and commands between the various
instrum ents. The transceiver provides fo u r open-collector drivers and
fo u r receivers featuring hysteresis.
Tailored to Meet the IEEE Standard 488-1978 (D igital Interface

fo r Programmable In strum entation) and the Proposed I EC
Standard on Instrum ent Interface
Provides Electrical C o m p a tib ility w ith General-Purpose Interface

Bus (GPIB)
MOS C om patible w ith High Impedance Inputs
Driver O u tp u t Guaranteed O ff During Power Up/Power Down
P SU FFIX
L ow Power - Average Power Supply C urrent = 12 m A
Term inations Provided
TY PIC AL M EASUREM ENT SYSTEM APPLICATION
16 Llno T o ta l
5-54
CASE 648
MC3446A
MAXIMUM RATINGS (Ta * 2SC unless otherwlw noted.)

Rating
Input Voltage
Symbol
Velue
Vcc
7.0
Vdc
V|
6.6
Vdc
'O(D)
Tj
160
mA
160
ta
Oto +70
Tstg
-66 to +160
C
C
Unit
(Unless otherwise noted, 4.5 V < V c c ^ 6.6 V and 0 < TA < 70C, typical values are at T a " 25C, V c c 6-0 V)
I
Characteristic
Symbol
Min
DRIVER PORTION

(V ,L - 0.4 V, VCC - 5.0 V, T a - 25C)
Input Clamp Voltage
(l|K -12 mA)
Output Voltage High Logic State (1)
<V IH(S) 2.4 V or V , h (D) 2.0 V)
lv lL(S) 0<8 v <V IL(D) 0.8 V, loL(D) 48
Input Breakdown Current
(V ,(d ,- 5 .S V)
2.0
Max
Unit
OS
V
V
5.0
40
mA
-0.2
-0.25
mA
V IK(D)
-1.5
v OH(D)
2.5
3.3
3.7
v OL(D)
0.5
'lB(D)
1.0
mA
400
-
mV
V|H(D)
V|L(D)

(V | h 2.4V I
Typ
<IH(D)
'lL(D)
RECEIVER PORTION
Input Hysteresis
2.0
-
0.5
4.0
14
mA
V|LH(R)
Input Threshold Voltage High to Low Output Logic State
V|HL(R)

<V IH(R) 2-0 V, lOH(R) -400jiA)
v OH(R)
0.8
2.4
v OL(R)
'OS(R)
<V IL(R) 0 8 v - 'OL(R) 8 0

(V| h |R) 2.0 V) (Only one output may be shorted at a time)
625
1.66
1.03
Input Threshold Voltage Low to High Output Logic State
BUS LOAD CHARACTERISTICS

Bus Voltage
<V|H(E) 2.4 V)
('BUS - 12 mA)
V (BUS)
2.5
3.3
Bus Current
(V|H(D) 2-4 V ,V BUS> 5 .0 V )

(V |H (D ) 2.4V , VBu s -0 .5 V )
(V b u s < 5 .5 V )
(Vcc - 0 ,0 V < V BUS < 2.75 V)
'(BUS)
0.7
-1.3
-
3.7
-1.5
-3.2
2.5
0.04
12
32
19
40
V
mA
TOTAL DEVICE POWER CONSUMPTION

mA
ice

(All Drivers OFF)
(Atl Driven ON)
SWITCHING CHARACTERISTICS (Vqc S O V. TA 2 S C ) ____________________ ___________ ___________ __________

Characteristic
Symbol {
Min
Typ
Max
Unit
DRIVER PORTION
Propagation Delay Time from Driver Input to Low Logic State Bus Output
Propagation Delay Time from Driver Input to High Logic State Bus Output
Propagation Delay Time from Enable Input to Low Logic State Bus Output
Propagation Delay Time from Enable Input to High Logic State Bus Output
RECEIVER PORTION
Propagation Delay Time from Bus Input to High Logic State RecelverOutput
Propagation Delay Time from Bus Input to Low Logic State ReceiverOutput
5-55
tPHL(D)
50
PLH(D>
PHL(E)
tPLH(E)
' -
40
50
50
*PLH(R)
*PHL(R)
50
40
ns
ns
ns
ns
ns
ns
MC3446A
FIGURE 1 - TEST C IR C U IT AND WAVEFORMS FOR PROPAGATION D E LAY TIME FROM

RECEIVER INPUT (BUS) TO OUTPUT
T o Scope
In p u t
50%
0 V ----------
\
<PLH(R)
v OH
O u tp u t
- P H L(R )
15
v O L -----------
FIGURE 2 - TEST C IRC UIT AN D WAVEFORMS FOR PROPAGATION D E LAY TIME FROM
DRIVER AN D COMMON ENABLE INPUTS TO OUTPUT (BUSI
j . u v ----------------/
D river In p u t crl(w /
o r Enable
5 0 % -|
0 V -------------- '
- 'P H L (D )
'P L H ( D ) -
VoH -------O u tp u t
JP 7 7
V q l ---------
* Includes Probe and Jig Capacitance

CHARACTERISTICS
FIGURE 4 - T Y PIC AL BUS LOAD LINE
1
ta-
25C
Non-Shaded Area
Conform! to Paragraph
3 5.3 ol IEEE
Standard 488-1978
0.5
1.0
1.5
2.0
VflUS-BUS VOLTAGE (VOLTS)
5-56
<8>
MOTOROLA
MC3447
Advance Information
OCTAL BIDIRECTIONAL
BUS TRANSCEIVER
WITH
TERM INATION NETWORKS
BIDIRECTIONAL INSTRUMENTATION
BUS (GPIB) TRANSCEIVER
This bidirectional bus transceiver is intended as the interface
between T T L or MOS logic and the IEEE Standard Instrumentation
Bus (488-1975, often referred to as GPIB). The required bus termi
nation is internally provided.
Low power consumption has been achieved by trading a minimum
of speed for low current drain on non-critical channels. A fast
channel is provided for critical ATN and EOI paths.
Each driver/receiver pair forms the complete interface between
the bus and an instrument. Either the driver or the receiver of each
channel is enabled by a Send/Receive input with the disabled output
of the pair forced to a high impedance state. The receivers have
input hysteresis to improve noise margin, and their input loading
follows the bus standard specifications.
Low Power Average Power Supply Current 30 mA Listening

75 mA Talking
Eight Driver/Receiver Pairs
Three-State Outputs
Receiver Hysteresis 600 mV (Typ)
Fast Propagation Times 1 5 -2 0 ns (Typ)
TT L Compatible Receiver Outputs
Single + 5 Volt Supply
Open Collector Driver Output with Terminations
Power Up/Power Down Protection (No Invalid
Information Transmitted to Bus)
No Bus Loading When Power is Removed From Device
Required Termination Characteristics Provided
Rating
Input Voltage
Symbol
Value
VCc
V|
7JD
5.5
'O(D)
Tj
150
150
ta
0 to +70
-6 5 to +150
Tstg
L SUFFIX
CERAMIC PACKAGE
CASE 623
P 3 SUFFIX
PLASTIC PACKAGE
CASE 724
0 0
PIN ASSIGNMENTS
ENcc
S/H (0 )fT
Data o [ T
--------- T - 23] Bus 0
Onto t l~3~
Data 21*4"
Data' 31~S~
MAXIM UM RATINGS (T^ 25C unless otherwise noted)

SILICON MONOLITHIC
INTEGRATED CIRCUIT
Unit
Vdc
cPn
---------= F -
Bus 2
TF| Bus 4
---------T - Is ]B u s 6
- < y f - 17 ]S /R (1-4 )
6C
C
U fH
--------- T -
161Bu s 6
--------- T
1s 1 b u s 7
U -
TYPICAL MEASUREMENT
SYSTEM APPLICATION
Instrument
A
(W ith GPIB)
2l l
---------T - 20] Bus 3
--------- T
ifcH
Vdc
mA
--------- T 22] Bus 1
14]s/^ <71
i51Bu*
1 Gnd
Programmable
Calculator
(With GPIB)
vCc
Instrum ent
Bus Indicates
(W ith GPIB)
16 L in n Total
This Is advance inform ation and (pacifications are subject to change w ith o u t notico.
5-57
o BUS
Termination*
MC3447
FIGURE 4 - SEND/RECEIVE INPUT TO D ATA OUTPUT (RECEIVER)
C l 15 pF (In clu de s Jig

and P robe Capacitance)
Pulso
G enerator
t f L H ' T H L = ^ 5 .0 ns ( 1 0 - 9 0 )
D u ty C ycle = 50%
V q , OUTPUT VOLTAGE (VOLTS)
FIGURE 5 - TY P IC A L RECEIVER HYSTERESIS

CHARACTERISTICS
FIGURE 6 - TY PIC AL BUS LO AD LINE
vcc 3Uv
25C
0.5
1.0
1.5
VBUS. BUS VOLTAGE (VOLTS)
FIGURE 7 - SUGGESTED PRINTED CIRCUIT BOARD LA YO U T USING MC3447s AN D MC68488

1O
O
M C 68 48 8
O
O
2 MC3447S
5-60
MOTOROLA
MC344SA
BIDIRECTIONAL INSTRUMENTATION
BUS (GPIB) TRANSCEIVER
This bidirectional bus transceiver is intended as the interface
between T T L or MOS logic and the IEEE Standard Instrum entation
Bus (4 8 8 -1 9 7 8 , often referred to as GPIB). The required bus
QUAD THREE-STATE
BUS TR AN SCEIVER WITH
TERMINATION NETWORKS
te rm ina tio n is intern a lly provided.
Each driver/receiver pair form s the com plete interface between

the bus and an instrum ent. Either the driver or the receiver o f each
channel is enabled by its corresponding Send/Receive input w ith
the disabled o u tp u t o f the pair forced to a high impedance state. An
additional optio n allows the driver outputs to be operated in an
open c o lle c to r!!) o r active pull-up co nfiguration. The receivers have
inp u t hysteresis to im prove noise margin, and their input loading
follow s the bus standard specifications.
Four Independent D river/Receiver Pairs
Three-State O utputs
Receiver Hysteresis 600 m V (Typ)
Fast Propagation Times 1 5 -2 0 ns (Typ)

T T L C om patible Receiver O utputs
Single +5 V o lt Supply
Open C ollector Driver O u tp u t O p tio n ^ )
Power Up/Power D ow n Protection
No Bus Loading When Power Is Removed From Device
Required Term ina tio n Characteristics Provided
iu
L SU FFIX
CASE 6 20
..W f f lill
ill u
P SUFFIX
CASE 648
(No Invalid In fo rm a tio n Transm itted to Bus)
(1) Selection of the "Open C ollector" configuration, in fact, selects an open collector device
w ith a passive pull-up load/term ination which conforms to Figure 7. IEEE 488-1978
Bus Standard.
M A X IM U M R A TIN G S (T a = 25C unless otherwise noted)

Symbol
Value
Unit
V CC
7.0
Vdc
V|
5.5
Vdc
Driver O utput Current
'O(D)
150
mA
Tj
150
ta
0 to +70
T stg
-6 5 to +150
Rating
Input Voltage
TYPIC AL MEASUREMENT
SYSTEM APPLICATION
T] V CC
E
ec.
Data A E
1SInnd/R
put D
~T ~ x
B ut A
~i~| Data D
E
P ull-U p
J
^
ut D
Enable
1 . ] PBull-U
L
p
In p u t A-B
1 Enable
But B E
In p u t C-D
A % Data B
E
S end/R ec.
t T ] D8t* C
In p u t B E
I S end/R ec.
G nd
_^J In p u t C
E
S end/R ec.
In p u t A
In stru m e n t
(W ith G PIB)
TRUTH TABLE
P rogram m able
C a lcu lato r
(W ith G PIB)
But
D a ta
Bu
A c tiv e P u ll-U p
D a ta
8u*
O p an C ol.
5-63
C o m m e n t*
Enable
X D o n *! Cara
16 L in o * T o ta l
In fo . F lo w
S cn d /R e c.
D ata
MC3448A
(Unless otherwise noted 4.76 V < V c c < 6.26 V end 0 < T A < 70C; typlcel values are at T a 26C, VpC ~ 6.0 V)
Characteristic
Bus Voltage
(Bus Pin Open)(V|(s/R) " 0.8 V)
"(BUS) -1 2 mA)
Bus Current
(5.0 V < V ( b (js ) < 6.5 V)
(V(BUS) 0.6 V)
(VCC - 0 V. 0 V < V(BUS) < 2.75 V)
Receiver Input Hysteresis
(V|(s /R )-0 J B V )
Symbol
Min
Typ
Max
V (BUS)
V|C(BUS)
2.76
3.7
-1.5
mA
'(BUS)
2.6
-3.2
+0.04
0.7
-1.3
400
600
'
V|LH(R)
V|HL(R)
13
0.8
1.6
1.0
v OH(R)
2.7
VOL(R)
>OS(R)
Unit
V
mV
V
Receiver Input Threshold

(V|(s/R) 0 3 V, Low to High)
(V|(s/R) 0.8 V, High to Low)
fv KS/R) " 0 3 V, l o H ( R ) " -800 iA. V(gus) * 2.0 V)
<V I(S/R) 0.8 V, l O L ( R ) 16 mA. V(BUS) " OS V)
Receiver Output Short Circuit Current
<V I(S/R) " 0.8 V. V(BUS) " 2.0 V)
<V|<S/R )-2.0V)
<V |(S /R )-2.0V )
Driver Input Current Data Pins
< V |(S /R )-V |(E,- 2 . 0 V )
(0.5 < V |(D) < 2.7 V)
(V|( d ) 5.5 V)
Input Current Send/Receive
(OS < V|(s/R) < 2.7 V)
fV |(S /R )-5 .5 V )
V
0.5
-15
-7 5
mA
V|H(D)
2.0
V IL(D)
OS
*A
>1(0)
'IB(D)
-200
40
200
l(S/R)
iBIS/R)
-100
20
100
'l(E)
'IB(E)
-200
V IC(D)
20
100
-1.5
v OH(D)
2.5
v OL(D)
0.5
OS(D)
-30
-120
mA
'CCL
>CCH
63
106
85
125
tPLHID)
l PHL(D)
16
17
tPLH(R)
tPHL(R)
25
23
Input Current Enable

(0.5 < V|(E) < 2.7 V)
(V|{E) 5.5 V)
MA
Driver Input Clamp Voltage

<V US/R) * 2.0 V. l | c ( D ) " -18 mA)
Driver Output Voltage High Logic State
<V I(S/R) " 2 0 V. V | h (D) 2.0 V. V|H(E) - 2.0 V. Iq h " -5 2 mA)
Driver Output Voltage Low Logic State (Note 1)
<V HS/R) 2-0 V , loL(D) 48 mA)
<V I(S/R) " 2.0 V, V|H(D) 2.0 V. V |H(E) " 2.0 V)
(Listening Mode All Receivers On)
(Talking Mode All Drivers On)
mA
SWITCHING CHARACTERISTICS (Vpc ~ 5.0 V. TA - 25C unless otherwise noted)

Propagation Delay of Driver
(Output Low to High)
(Output High to Low)
Propagation Delay of Receiver
ns
ns
NOTE 1. A modi (lestion of the IEEE 488-1978 Bus Standard changes V q l (D) fro(n 0-4 to 0.5 V maximum to permit the use of
Schottky technology.
5-64
MC3448A
S W ITC H IN G C H A R A C TE R IS T IC S (continuad) (Vcc " &0 V. TA - 25C unless otherwise notad)

Characteristic
Symbol
Propagation Delay Tima Send/Receive to Data

Logic High to Third State
Third State to Logic High
Logic Low to Third State
Third State to Logic Low
Propagation Delay Time Send/Receive to But
Logic High to Third St8te
Third State to Logic High
Logic Low to Third St8te
Third State to Logic Low
tPHZ(R)
'PZH(R)
tPLZ(R)
tPZL(R)
PHZ(O)
<PZH(D)
tPLZ(D)
tPZL(D)
Turn-On Time Enable to Bus

Pull-Up Enable to Open Collector
Open Collector to Pull-Up Enable
POFF(E)
'PON(E)
Min
Typ
__
Max
Unit
ns
30
30
30
30
ns
30
30
30
30
ns
30
20
PROPAGATION DELAY TEST CIRCUITS AND WAVEFORMS

FIGURE 1 - BUS INPUT TO DATA OUTPUT (RECEIVER)
To Scop*
(O utput)
+ 5.0 V
3.0 V
O utput
f - 1.0 MHz
t jL H " *T H L ^ *0 n* d O -9 0 )
D uty Cycle 50%
FIGURE 2 - DATA INPUT TO BUS OUTPUT (DRIVER)

T o Scope
(O utput) 2.3 V
Driver Input
or Enable
Data
Pulse
* - P H L (D )
PLH(D)O utput
30 pF
VQH
2.0 V
0.8 V-
VOL
f - 1.0 MHz
Include* Jig
and Probe Capacitance
t j L H * t^ H L ^ 5.0 n* (1 0 -9 0 )
D u ty Cyclo - 50%
Pull-Up Enable
FIGURE 3 - SEND/RECEIVE INPUT TO BUS OUTPUT (DRIVER)
4 ^1.5 V
Y
tPZH(D)
O utput
High to Open
O utput
t o w to Open
/-V qh
t2 .0 V
/
tpH Z(D )
r 0.8 V
>----------v OL
3^10%
+ tP LZ(D )
----"
tp z L (D )
f 1.0 MHz
*TLH *TH L " ^ 5.0 n* (1 0 -9 0 )
D uty Cycle - 60%
5-65
MC3448A
FIGURE 4 - SEND/RECEIVE INPUT TO D A TA OUTPUT (RECEIVER)
O u tp u t
High to Open
tP L Z (R )
C l 15 pF (In clu de s Jig
and Probe Capacitance)
iP Z L tR )
f - 1.0 M H z
tT L H * T H L ** 5 0 ns ( 1 0 -9 0 )
O u ty C ycle 50%
FIGURE 5 - ENABLE INPUT TO BUS OUTPUT (D R IVER)

T o Scope
tjL H l T H L
5 0 ns (1 0 -9 0 )
D u ty C ycle - 50%
FIGURE 6 - TY PIC AL RECEIVER HYSTERESIS

CHARACTERISTICS
FIGURE 7 - TY PIC AL BUS LOAD LINE
4.0
3.0
1.0
<
o
o
5.0
T a = 25C
0
0
0.5
1.0
1.5
2.0
V|, INPUT VOLTAGE (VOLTS)
V BUS.BUS VOLTAGE (VOLTS)
5-66
MC3448A
FIGURE 8 - SIMPLE SYSTEM CONFIGURATION

B V
5-67
<8>
MOTOROLA
MC3450
MC3452
QUAD LINE R EC EIV E R S

WITH COMMON TH R EE-STA TE
STROBE INPUT
IN T E G R A T E D C IR C U IT S
QUAD MTTL COMPATIBLE

LINE R ECEIVER S
The M C 3450 features fo u r MC75107 type active pullu p line
receivers w ith the a dd itio n o f a com m on three-state strobe input.
When the strobe in p u t is at a logic zero, each receiver o u tp u t state is
determined b y the d iffe re n tia l voltage across its respective inputs.
W ith the strobe high, the receiver o u tp u ts are in the high impedance
state.
The MC3452 is the same as the M C3450 except that the o utputs
are open colle cto r w h ich perm its the im plied " A N D " fu n c tio n .
The strobe in p u t on b oth devices is buffered to present a strobe
loading fa cto r o f o n ly one fo r all fo u r receivers and inverted to
provide best co m p a ta b ility w ith standard decoder devices.
Receiver Performance Identical to the Popular

M C 75107/M C 75108 Series
Four Independent Receivers w ith C ommon Strobe In p u t
Im plied " A N D " C ap a b ility w ith Open C ollector O utputs
Useful as a Quad 1103 typ e M em ory Sense A m p lifie r
L S U F F IX
CASE 620
P S U F F IX
CASE 6 48
TRUTH TABLE
OUTPUT
INPUT
STROBE
V |D >
+25 m V
L
H
O ff
O ff
-2 5 m V <
L
H
V |D < + 2 5 mV
O ff
V ID <
-2 5 m V
L
H
L
H
Z
I
5-68
MC3450 MC3452
O ff
= L o w Log ic State
= H igh Log ic Stato
= T h ird (H igh Im pedance) State
= Ind e te rm in a te State
MC3447
FIGURE 8 - SIMPLE SYSTEM CONFIGURATION

5 V
T/R 1
DBO
T /R 2
D87
___
DO
D7
R/W
RS0
RS2
Tb o
AO
MC6802
or
MC6800
MPU
182
A1B
IB4
IRQ
IRQ
186
DAC
EOT
Tf c
MC68488
GPIA
SRQ
181
183
185
187
NOTE 1: Although the MC3447 transceiver*
are non-inverting, the 488-1978 b u t c elloutt
appear Inverted w ith roipect to the MC68488
pin designations. This is because the 488-1978
Standard is defined fo r negative logic, w hile ell
M6800 MPU components make use o f positive
logic form at.
RFD
ATN
REN
5-61
MC3447
FIGURE 9 - SUGGESTED PIN DESIGNATIONS FOR USE WITH MC68488

MC8848S
Connactioni
A
MC68488
Connections
MC3447 Pin Dasionations
T /R 2
V cc
S/R (0)
24
V CC
V Cc
V CC
OAV
SRQ
Data 0 0
23
BusO
DA V
SRQ
?B0
Ib i
Data 1
22
B u ll
DIO 1
DIO 2
?B2
TB3
Data 2
21
But 2
DIO 3
DIO 4
TB4
IBS
O ata3
20
Bus 3
D IO S
DIO 6
Tbs
IB7
Data 4
DIO 7
D IO S
RFO
Data 5
Octal
19
GPIB
Tr*n*elvor 18
Bus 4
DAC
Bus 5
NOAC
NRFD
T/R 2
T /R 2
S/R (6)
17
S/R (1 -4 )
T/R 2
T/R 2
EOT
ATN
Data 6
16
Bus 6
EOI
ATN
if c
REN
Data 7
10
IB
Bus 7
IFC
REN
T/R 1
Gnd
S/R (6)
11
14
S/R (7)
Gnd
Gnd
Gnd
Gnd
Logic Gnd
12
13
Bus Gnd
Gnd
Gnd
5-62
MC3450, MC3452
M A XIM U M RATINGS (TA * Oto +70PC unless otherwise noted.)

Rating
Symbol
Value
Unit
VC C.VEE
7.0
Differential-Mode Input Signal Voltage Range
V|DR
Common-Mode Input Voltage Range
VICR
V I(S)
6.0
S.O
Vdc
Vdc
Vdc
5.5
Vdc
1000
6.6
mW
mW/C
1000
6.6
mW
mW/C
Strobe Input Voltage

Derate above T a +25C
PD

Derate above T a +2SC
ta
T stg
0 to +70
-65 to +150
RECOMMENDED OPERATING CONDITIONS (Ta 0 to +70Pc unless otherwise noted.)

Characteristic
Output Load Current
Symbol
Min
Typ
Max
Unit
VCc
VEE
+4.75
-4.75
+5.0
-5.0
+5.25
-5.25
Vdc
16
+5.0
V|DR
-5.0
V|CR
V|R
-3.0
-5.0
'OL
Differential-Mode Input Voltage Range

Input Voltage Range (any input to Ground)
mA
Vdc
+3.0
Vdc
+3.0
Vdc
ELECTRICAL CHARACTERISTICS (Vcc +5 0 Vdc, Vee ' -5 0 Vdc, T a 0 to +70C unless otherwise noted.)
MC34S2
MC3450
Characteristic
High Level Input Current to Receiver Input
Low Level Input Current to Receiver Input
High Level Input Current to Strobe Input
V|H(S) +2-4 V
V|H(S) +5.25 V
Low Level Input Current to Strobe Input
V|H(S) +0-4 v
High Level Output Voltage
Symbol
<IH(I)
'IL(I)
<IH(S)
Fig.
7
8
Min
-
Max
75
-10
Min
-
Typ
-
40
1.0
-1.6
Max
75
-10
Unit
mA
mA
5
-
'I LIS)
VOH
2.4
High Level Output Leakage Current

Low Level Output Voltage
>CEX
VOL
3
3
Short-Circuit Output Current

Output Disable Leakage Current
os
'off
'CCH
6
g
4
>EEH
High Logic Level Supply Current from Vcc

High Logic Level Supply Current from V e e
Typ
-
-18
-
0.4
-1.6
-
40
-70
40
1.0
UA
mA
mA
Vdc
mA
250
0.4
mA
Vdc
mA
45
60
45
60
mA
-17
-30
-17
-30
mA
SWITCHING CHARACTERISTICS (Vc c +5.0 Vdc. VEE - -S.0 Vdc, TA +25C unless otherwise noted.)
NSC3450
Characteristic
Symbol
MC34S2
Min
Typ
Max
Min
Typ
Max
Unit
25
25
ns
High to Low Logic Level Propagation Delay

Time (Differential Inputs)
tPHL(D)
Fig10
Low to High Logic Level Propagation Delay

Time (Differential Inputs)
*PLH(D)
10
25
25
ns
Open State to High Logic Level Propagation

Delay Time (Strobe)
High Logic Level to Open State Propagation
Delay Time (Strobe)
Open State to Low Logic Level Propagation
Delay Time (Strobe)
Low Logic Level to Open State Propagation
Delay Time (Strobe)
High Logic to Low Logic Level Propagation
Delay Time (Strobe)
Low Logic to High Logic Level Propagation
Delay Time (Strobe)
tPZH(S)
11
21
ns
tPHZ(S)
11
18
ns
tPZL(S)
11
27
ns
tPLZ(S)
11
29
ns
tPHL(S)
12
25
ns
<PLH(S)
12
25
ns
5-69
MC3450, MC3452
FIGURE 2 - CIRCUIT SCHEMATIC

(1/4 Circuit Shown)
TEST CIRCUITS
FIGURE 3 - lCEX* v OH> AND V0 L
TEST TABLE
VI
MC3450 MC3452
3.975 V
-3.0 V
3.978 V
'CEK
4.0 V
3.0 V 3.0 V
VOL 3.979 V -3.975 V
V4
V2
V3
MC34S0 MC3452 MC3450 MC3462 MC3450 MC3492
If
3.0 V
34) V
ONO
0.4 mA
-3.975 V
-3.0 V
ONO
3.0 V
3.0 V
ONO
-3.975 V
OND
-3.0 V
3.975 V 3.975 V ONO
ONO 3.0 V 3.0 V
lOcnA
3.0 V -3.0 V -3.0 V -3.0 V
ONO
ONO
CteMMl A ihowA undm tMt. Otbr cdamwH art m u d thnOarly.
FIGURE 5 - 11HIS) AND l | L(S)
FIGURE 4 - IcCH AND l EEH
V IU 8 )
5-70
JQ
MC3450, MC3452
FIGURE 7 - l | H
FIGURE 6 - I q s
Channal AC) shown undar ta tt, othar channals ara tattad

similarly. Davicas ara tattad w ith V I from +3.0 V to -3.0 V.
Only ona output thortad at a tlmo.
FIGURE 9 - l0ff
FIGURE 8 - l | L
Channal A (-) shown undar tatt, othar channals ara tattad

similarly. Davieas ara tattad w ith V I from +3.0 V to -3.0 V.
Output of Channal A shown undar tatt. othar outputs ara

tastad similarly for V I 0.4 V and +2.4 V.
FIGURE 10 - RECEIVER PROPAGATION DELAY tp |.H (D )AND *PHL(D)
200 m V ---------- V
Ein
tpHUD)
Eo
VOL
Output of Channal B shown undar ta tt, othar chcnnals ara tattad similarly.
81 at " A " for MC3482
SI at " B " for MC34S0
CL - 15 pF total for MC34S2
CL SO pF total for MC34S0
5-71
E|n waveform charactaristics:

*TLH Bn<1 *T H L < 1 0 n s maaturad 10% to 90%
PRR - 1.0M H I
Duty Cycla 500 ns
MC3450, MC3452
FIGURE 1 1 -STR OB E PROPAGATION DELAY TIMES tPLZ(S) tPZL(s) tPHz(S)and <PZH(S>
PLZS
<PZL(S)
'PHZ(S)
*PZH(SI
VI
V2
SI
S2
cL
100 mV
100 mV
GND
GNO
GNO
GNO
100 mV
100 mV
Clo ted
Clotad
Cloted
Open
Cloted
Open
Cloiad
Cloted
IS pF
SO pF
IS pF
SO pF
C L includet jig and probe capacitance.

E[n waveform characterittict:
*TLH Qnd *THL <
n* meaturad 10 % to 90%.
PRR * 1.0 MHz
Duty Cycle 50%
other channel! are tetted timftarly.
3.0 V50%
Ein
0 V-
*PHZ(S)<
*PLZ(S) <
*PHZ(S)
Vq h Eo
. VOh -0.5 V
asI.S V
>
tPZL(S)<
- *PZH(S)
*PZH(S)<
EO
VOL
^1.5 V
FIGURE 12 - STROBE PROPAGATION DELAY tpLH(S) AND tpHL(S)
+3.0 V -------------
Em
0V PLH(S)
VOH------------Eo
VOL-
<PHL(S)
f 71
E|n waveform charactarittici:

'T L H "i* ' T H L < 1 0 m m m uied 10 % to 90%
PRR - I.O M H i
Duty Cycle BOO nt
5-72
MC3450, MC3452
APPLICATIONS INFO RM A TIO N

FIGURE 13 - IMPLIED "AND" GATING
FIGURE 14 - BIDIRECTIONAL DATA TRANSMISSION
V ref
The threo-*tato capability of the M C 3 4 5 0 permit*

bidirectional date transmission a* illustrated.
The M C 3 4 5 2 can be utod for addre** decoding at Illustrated

above. A ll outp ut* of the M C 3 4 5 2 are tied together through a
com m on resistor to +5.0 volt*. In thlt configuration the M C 3 4 5 2
provides the " A N D " function. A ll oddresae* have to be truo
before the output will go high. T h i* schcmo eliminate* tho need
for an " A N D " gate and enhance* cpeod throughput for addret*
decoding.
FIGURE 16 - WIRED OR" DATA SELECTION USING

THREE-STATE LOGIC
FIGURE IS - SINGLE-ENDED UNI-BUS* LINE RECEIVER

APPLICATION FOR MINICOMPUTERS
DATA
OUTPUT
DATA
L IN E S 4
RECEIVERS
The M C 34 50 /34 52 can be utad for tingle-endod e* well a*

differential line receiving. Fo r tingle-ended lino receiver appli
cation*, such a* are encountered in m inicomputer*, the con
figuration shown In Figure 15 can be used. The voltage aource.
which generetet V ref, should be designed so that tho V r#f
voltage I* halfway between V Q H (m in ) and Voi_(inex). Th
m axim um input overdrive required to guarantee a given logic
*tete i* extremely small. 2 5 m V maximum. T h i* low-input over
drive on henee* differential noise im m unity. A lto the high-input
Impedance of the line receiver permit* m any receiver* to be
pieced o n e (Ingle line w ith m inim um load effect*.
1/2 M C 40 07
C IR C U IT
6*73
MC3450, MC3452
APPLICATIONS INFO RM A TIO N (continued)
FIGURE 17 - PARTY-LINE DATA TRANSMISSION SYSTEM

WITH MULTIPLEX DECODING
5-74
MOTOROLA
M TTL COMPATIBLE QUAD LINE DRIVER
QUAD LINE DRIVER WITH

COMMON INHIBIT INPUT
The M C3453 features fo u r M C 75110 typ e line drivers w ith a

com m on in h ib it in p u t. When the in h ib it inp u t is high, a constant
o u tp u t current is switched between each pair o f o u tp u t term inals in
response to the logic level at th a t channel's inp u t. When the in h ib it
is low, all channel o u tp u ts are nonconductive (transistors biased to
cu t-o ff). This m inim izes loading in party-line systems where a large
number o f drivers share the same line.
Four Independent Drivers w ith C ommon In h ib it Input
-3 .0 V o lts O u tp u t Com m on-M ode Voltage Over Entire Operating

Range
Improved D river Design Exceeds Performance of Popular M C 75110
FIGURE 1 - PA RTY -LIN E D A TA TRANSMISSION SYSTEM WITH

M U LTIPLEX DECODING
L S U F F IX
CASE 620
P S U F F IX
CASE 648
TR UTH TA BLE
(positive logic)
IN H IB IT
INPUT
On
Off
On
O ff
Off
Off
O ff
O ff
L L o w Logic Laval
H - H igh Log ic Laval
5-75
OUTPUT
CURRENT
LOGIC
INPUT
MC3453
MAXIMUM RATINGS (Ta * 0 to +70C unlew otherwise noted.)

Ratings
Symbol
Value
Unit
Vcc
VEE
+7.0
-7.0
Volts
Vin
5S
VOCR
-5.0 to +12
Volts
Volts

Logic and Inhibitor Input Voltages
Common-Mode Output1Voltage Range
Plastic and Ceramic Dual In-Line Packages
PD
1000
6.6
Oto +70
mW
rrfW/C
T stg
-(5 to +150
Nom
+5.0
-5.0
Max
+6.25
-5.25
Unit
Volts
ta

Plastic and Ceramic Dual In-Une Packages
RECOMMENDED OPERATING CONDITIONS (See Notes 1 and 2.)

Characteristic
Positive
Negative
Symbol
Min
VCC
VEE
+4.75
-4.75
Volts
Vq c r
0
0
+10
-3.0
Symbol
Min
Max
Unit
V|H
2.0
0
5.5
Volts
Note 1. These voltage values are in respect to the ground terminal.

Note 2. When not using all four channels, unused outputs must be grounded.
DEFINITIONS OF INPUT LOGIC LEVELS*

Characteristic
High-Level Input Voltage (at any input)
Low-Level Input Voltage (at any input)

0.8
Volts
VlL
*The algebraic convention, where the most positive limit is designated maximum, is used with Logic Level Input Voltage Levels only.
ELECTRICAL CHARACTERISTICS (TA - 0 to +70C unless otherwise noted.)

Characteristic##
Symbol
High-Level Input Current (Logic Inputs)

(Vcc Max. VEe " Max, V |H, - 2.4 V)
(Vcc Max, V e e " Max V | h l Vcc Max)
Low-Level Input Current (Logic Inputs)
(V c c M3*. V e e Max, V | t L - 0.4 V)
i.h l
High-Level Input Current (Inhibit Input)

(VCC " Max, V EE Max, V |H| * 2.4 V)
(Vcc Max, V ee " Max, V|H| - Vcc Max)
Low-Level Input Current (Inhibit Input)
(Vcc Mx* VEE Max, V| Lj - 0.4 V)
>IH|
Output Current ("on" state)

(Vcc Max, V e e Max)
(VCC * Min, VEE - Min)
Output Current ("off" state)
(Vcc Min. V e e - Min)
Supply Current from Vcc (with driver enabled)
(V |L l 0.4 V .V i h , - 2.0 V)
'O(on)
i l l
Min
Typ#
Max
Unit
40
1.0
-1.6
mA
mA
mA
40
1.0
-1.6
mA
mA
hL,
'O(off)
mA
mA
15
6.5
11
11
5.0
100
fiA
35
50
mA
'CC(on)
Supply Current from V e e (with driver enabled)

(V|LL 0.4 V. V |H, - 2.0 V)
<EE(on)
65
90
mA
' Supply Current from Vcc (with driver inhibited)

(V ,Ll - 0.4 V ,V I L | - 0 .4 V)
'CC(off)
35
50
mA
Supply Current from VEE (with driver inhibited)

(V||_ l - 0 .4 V. V |L| - 0 .4 V)
'EE(off)
25
40
mA
#AII typical values are at Vcc +S-0 V, V e e -5.0 V, T a +28C.

##Por conditions shown as Minor Max. use the appropriate value specified under recommended operating
conditions for the applicable device type.
Ground unused inputs and outputs.
MC3453
SWITCHING CHARACTERISTICS (Vqc +5-0 V. Vee -S.O V ,T a +25C.)

Characteristic
Symbol
Propagation Delay Tims from Logic Input to

Output Y or Z (R|_ SOohms, C|_ 40 pF)
Min
Typ
9.0
9.0
Max
15
15
Unit
16
20
25
25
ns
Propagation Delay Time from Inhibit Input

to Output Y or Z (R l 60 ohms. Cl 40 pFI
PLH|_
PHLL
*PLH|
PHL|
FIGURE 2 - LOGIC INPUT TO OUTPUTS PROPAGATION

DELAY TIME WAVEFORMS
FIGURE 3 - INHIBIT INPUT TO OUTPUTS PROPAGATION

D ELAY TIME WAVEFORMS
OUTPUT 2
0V
TEST CIRCUITS
FIGURE 4 - LOGIC INPUT TO OUTPUT PROPAGATION
DELAY TIME TEST CIRCUIT
FIGURE 5 - INHIBIT INPUT TO OUTPUT PROPAGATION

DELAY TIME TEST CIRCUIT
V CC - S.O V
Channel A shown under test, the other

channel* ar tested sim ilarly.
MC3453

(1/4 Circuit Shown)
To Remainder
o f Quad
O utput*
To Remainder
o f Quad
MC3481
MC3485
MOTOROLA
Product Preview
IBM 360/370
QUAD
LINE DRIVER
QUAD SINGLE-ENDED LINE DRIVER
The MC3481 and M C3485 are quad single-ended line drivers
specifically designed to meet the IBM 360/370 I/O specification.
The tw o options o f enable, fa u lt flag and o u tp u t configuration
provide the designer fle x ib ility in system configuration and sim plifies
fault flagging.
O u tp u t levels are guaranteed over the fu ll range o f o u tp u t load
and fault conditions. Compliance w ith the IBM requirements fo r
fault protection, flagging, and power u p /p o w e rd o w n protection fo r
the bus make this an ideal line driver fo r party line operation.
Separate Enable and Fault Flags MC3481
Common Enable and Fault Flag MC3485
Power U p/D ow n Does N o t D isturb Bus
S ch o ttky C irc u itry fo r High-Speed
Internal Bootstraps fo r Faster Rise Times
10% Supply Tolerance
L S U F F IX
CASE 6 20
I
P S U F F IX
CASE 648
MC3485 has LS Totem Pole D river O u tp u t
S P E C IF IC A T IO N G U A R A N T E E C O M P L IA N C E W IT H
IB M 3 6 0 /3 7 0 IN P U T /O U T P U T P E R IP H E R A L S P E C IF IC A T IO N G A 2 2 -6 9 7 4 -3
M C 34 85
COMMON ENABLE
COMM ON F A U L T FLA G
M C 3481
D U A L ENABLE
IN D IV ID U A L F A U L T F L A G
D rive r O u tp u t A
F a u lt Flag A
In p u t A
E nable A B
In p u t B
F a u lt Flag B
D river O u tp u t B
G nd
E
E
E
E
E
E
Ej
E
T ] v cc
D rivor O u tp u t A
T "| D rivor O u tp u t D
D river O u tp u t A
T ] F a u lt Flag D
In p u t A
7 ] In p u t D
Enable A BC D
In p u t B | j ^
"g~| Enable CD
- 3-1 F a u lt Flag
(O pen C o lle c to r)
~r~| In p u t C
Drivor O u tp u t B
T ] In p u t C
~j~| F a u lt Flag C
D river O u tp u t B
~j~] D rive r O u tp u t C
D rivor O u tp u t C
G nd
[_
See M C 7 5 125/7 and M C 7 5 1 2 8 /9 L ine Receivers.
This is advance in fo rm a tio n and s p e cifica tio n s are subject to change w ith o u t n otice.
5-79
JD rive r O u tp u t C
MC3486
MOTOROLA
QUAD RS-422/423 LINE RECEIVER

M otorola's Quad RS-422/3 Receiver features fo u r independent
receiver chains w hich co m ply w ith El A Standards fo r the Electrical
Characteristics o f Balanced/Unbalanced Voltage D igital Interface
Circuits. Receiver o utputs are 74LS com patible, three-state struc
tures w hich are forced to a high impedance state when the appropri
ate o u tp u t co ntro l pin reaches a logic zero co nd itio n. A PNP device
buffers each o u tp u t co ntro l pin to assure m inim um loading fo r either
logic one o r logic zero inputs. In addition, each receiver chain has
internal hysteresis c irc u itry to improve noise margin and discourage
o u tp u t in sta b ility fo r slow ly changing inp u t waveforms. A summary
o f MC3486 features include:
Four Independent Receiver Chains
High Impedance O u tp u t C ontrol Inputs

(P IA Com patible)
111
Internal Hysteresis 30 m V (Typ) @ Zero V o lts Common Mode
T T L C om patible
Single 5 V Supply Voltage
DS 3486 Second Source
QUAD RS-422/3 LINE RECEIVER

WITH TH R EE-STATE
OUTPUTS
L S U F F IX
CASE 6 20
J
^
P S U F F IX
P LA S T IC P A C K A G E
CASE 648
R E C E IV E R C H A IN B LO C K D IA G R A M
D iffe re n tia l
In p u ts
Threo-Stete
C o n tro l
In p u t
MC3486
ABSOLUTE MAXIMUM RATINGS (Now 1)

Rating
Symbol
Value
VCc
8.0
tnput Common Mode Voltage

Three-State Control Input Voltage
V|CM
V|D
V|
US
25
8.0
50
-65 to +150
Output Sink Current

Storage Temperature
Ceramic Package
Plastic Package
<0
Tstg
Tj
Unit
Vdc
Vdc
Vdc
Vdc
mA
C
C
+175
+150
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device
cannot be guaranteed. They are not meant to imply that the devices should be oper
ated at these limits. The 'Table of Electrical Characteristics" provides conditions for
actual device operation.

Symbol
Value
Unit
Vcc
4.75 to 5.25
Vdc
ta
0 to +70
V|CR
-7.0 to +7.0
C
Vdc
V IDR
6.0
Vdc
Rating
ELECTRICAL CHARACTERISTICS (Unless otherwise noted minimum and maximum limits apply over recommended temperature and
power supply voltage ranges. Typical values are for T/^ 25C, Vcc 5.0 V and V | k 0 V. See
___________________________________ Note 1 . ) ______________________________________________________________________
Max
Unit
Characteristic
Symbol
Min
Typ
V
2.0
V|H
(Three-State Control)
V
0.8
V|L
Differential Input Threshold Voltage (Note 4)
(-7.0 V < V|C < 7.0 V. V |H - 2.0 V)
(lO 0.4 mA. V o h > 2.7 V)
d o - 8 .0 m A ,V o L > 0 5 V)
VTH(D)
Input Bias Current

(Vcc 0 V or 5.25) (Other Inputs at 0 V)
(V) - - 1 0 V)
(V| - -3 .0 V)
(V| +3.0 V)
(V |-+ 1 0 V )
l8(D>
0.2
-0.2
mA
-3.25
-1.50
+150
+3.25
V
< <
o o
r I
Input Balance and Output Level

(-7.0 V < V |C < 7.0 V, V |H - 2.0 V,
See Note 3)
(lO 0.4 mA, V|D 0.4 V)
0 o - 8 .0 m A . V iD - 0 . 4 V )
Output Third State Leakage Current
(V|(D) +3.0 V, V |L - 0.8 V. V 0 L 0.5 V)
<V|(D) - -3 .0 V. V ,L = 0.8 V, V q l 2.7 V)
2.7
0.5
-15
-40
40
-100
mA
-100
MA
oz
MA
>OS
,V I(0) 3.0 V, V |H - 2.0 V. Vo 0 V)

See Note 2)
(V|H - 0.5 V)
(V|H - 2.7 V)
(V|H - 5.25 V)
11IK -10 mA)
(V |L - 0 V )
IlL
pA
|H
-
V|K
ice
5-81
20
100
-1 5
85
mA
MC3486
ELECTRICAL CHARACTERISTICS (continued)

SWITCHING CHARACTERISTICS (Unlen otherwise notad, Vc c 5.0 V and t A - 2SC.)
Characteristic
Propagation Delay Time Differential
Inputs to Output
Propagation Delay time Three-State
Control to Output
(Output Low to Third State)
(Output High to Third State)
(Output Third State to High)
(Output Third State to Low)
Symbol
Min
tPHL(D)
PLH(D)
Max
Typ
Unit
ns
35
30
R*
*PLZ
*PHZ
PZH
tPZL
35
35
30
30
NOTES:
3. Rofer to EIA RS422/3 fo r exact conditions. In p u t balance and
guarantood output lovels are dono simultaneously fo r w orst case.
4. Differential input threshold voltago and guaranteed output
levels are done simultaneously for worst case.
1. A ll currants Into device p in t are shown as positivo, out o f dovico

p in t are nogativo. A ll vo Itogas referenced to ground unless
otherwise notad.
2. Only one output at a tim o should be shorted.
FIGURE 1 - SWITCHING TEST CIRCUIT AND WAVEFORMS

Propagation Delay Differential Input to O utput
To Scope
(Input)
3.0 V ------Input
0 V ----- >
PLH(D)
/ s
16 pF
_ (Includes Probe
and Stray
Capacitance)
3-State Control
+1.5 V
*PLH(O I
V q h ----O utput y ^ 1 .3 V
\ l.3
VOL
0V
Input Pulta Characteristics
tT L H *TH L 6 - n* <10* to SOM)
PRR - 1.0 MHz, 50% D u ty Cycle
+2.0 V
FIGURE 2 - PROPAGATION DELAY THREE-STATE CONTROL INPUT TO OUTPUT

Input Putt* Characteristics
To Scope
tT LH *T H L "
n* I ' * to SOKI
PRR - 1.0 MHz, 50% D uty Cycle
(Input)
Control i
To Scope
(Output)
Pulse
Generator
+1.5 V fo r tp H Z *n d tp 2 H
1.5 V fo r t p l 2 end t p ^ L
A ll Diodes 1N916 o r
Equivalent
CL " 18 PF
(Include*
Probe and Stray
Capacitance)
3.0 V
Input
0V
*PHZ
*PLZ
r l. 6 V j r 1.6 V
' --------- *
- tp L Z
1.6 V SW1 Closed

SW2 Closed
SW1 Closed
SW2 Closed
*PHZ
L
0V
1BV
1.6 V
SW1 Open
SW2 Closed
*PZH
5-82
SW1 Closed
SW2 Open
MOTOROLA
QUAD RS-422 LINE DRIVER

WITH THREE-STATE
OUTPUTS
QUAD LINE DRIVER WITH

THREE-STATE OUTPUTS
M otorola's Quad RS-422 D river features fo u r independent driver

chains w hich com ply w ith El A Standards fo r the Electrical Char
acteristics o f Balanced Voltage D igital Interface C ircuits. The outputs
are three-state structures w hich are forced to a high impedance state
when the appropriate o u tp u t co n tro l pin reaches a logic zero co nd i
tio n . A ll in p u t pins are PNP buffered to m inim ize input loading fo r
either logic one or logic zero inputs. In add itio n, internal circ u itry
assures a high impedance o u tp u t state during the transition between
power up and power dow n. A summary o f MC3487 features include:
hM
iU
Four Independent D river Chains
PNP High Impedance Inputs (PIA C om patible)
Fast Propagation Times (Typ 15 ns)
T T L C om patible
Single 5 V Supply Voltage
O u tp u t Rise and Fall Times Less Than 20 ns
DS 3487 Second Source
'Y if ii "
w
L S U F F IX
CASE 6 20
J w
p n
P S U F F IX
CASE 648
PIN CON NEC TIO N S
} O u tp u ts D
D R IV E R BLOCK D IA G R A M
312
C /D C o n tro l
>111
>O u tp u ts C
J10>
39
In p u t C
TRUTH TABLE
C o n tro l
In p u t
N o n -In v e rtin g
O u tp u t
In p u t
Inve rtin g
O u tp u t
H = High Log ic State
X = Irre le va n t
Z = T h ird -S ta te (H igh Impedance)
5-83
MC3487
ABSOLUTE MAXIMUM RATINGS

Rating
Input Voltage
Operating Junction Temperature Range
Ceramic Package
Plastic Package
Symbol
Value
Unit
VCC
V|
8.0
Vdc
5.5
Vdc
ta
0 to +70
C
C
Tj
175
150
-65 to +150
Tstg
"Absolute Maximum Ratings" are those values beyond which the safety of the device cannot
be guaranteed. They are not meant to imply that the devices should be operated at these limits.
The "Table of Electrical Characteristics" provides conditions for actual device operation.
ELECTRICAL CHARACTERISTICS (Unless otherwise noted specifications apply 4.75 V < V cc ^ 5.25 V and 0C < T A < 70C.
Typjcal values measured at V cc 5.0 V, and TA 25C.)
Characteristic
Symbol
V|L
V ,h
Min
2.0

(V||_ - 0.5 V)
'IL

(V|H " 2.7 V)
(V |H - 5.5 V)
>IH
Input Clamp Voltage

**IK
(lOL 48 mA)
Unit
Vdc
Vdc
-400
liA
+50
+ 100
V|K
-1 .5
v OL
0.5
v0h
2.5
'os
-4 0
-140
mA
i 100
noo
+100
-100
2.0
10.4
105
85
mA

<V|H 2.0 V) 2
Output Leakage Current - Ki-Z State
(V |L - 0.5 V ,V | L(Z ) - 0.8 V)
(V|H - 2.7 V. V |L(Z )<* 0.8 V)
Output Leakage Current Power OFF
(VO h 6 0 V . V c c - 0 V )
(V o l * -o .26 v . v c c * o v i
Output Offset Voltage Difference1
Output Differential Voltage 1
v o s -v o s
Vt
Output Differential Voltage Difference 1
<
H
I
<l
-1

<'O H " -2 0 mA)
Max
0.8

(Control Pins Gnd)3
(Control Pins ** 2.0 V)
Typ
jiA
'OL(Z)
fiA
'OL(off)
0.4
'CCX
Ice
1. See EIA Specification RS-422 for exact test conditions.

2. Only one output may be shorted at a time.
3. Circuit in three-state condition.
SWITCHING CHARACTERISTICS (Vcc 5.0 V, TA 25C unless otherwise noted.)
Characteristic
Symbol
High to Low Output
l PHL
Low to High Output
*PLH
Output Transition Times Differential
High to Low Output
*THL
Low to High Output
TLH
Propagation Delay Control to Output
(R|_ 200 n , C|, 50 pF)
*PHZ(E)
(RL - 2 0 0 n , CL -5 0 p F )
*PLZ(E)
(R l = .C l S0 p F)
tPZH(E)
(R l - 200 n , c u - so pF)
PZL(E)
5-84
V
V
V
mA
Typ
Max
20
20
Min
Unit
ns
ns
20
20
ns
25
25
30
30
MC3487
FIGURE 1 - THREE-STATE ENABLE TEST CIRCUIT

AND WAVEFORMS
To Scope (Inp ut)
3.0 V or Ond
Input
O
Pu Im generator characterlttlct
Open fo r tp 2 H (E ) Tet Only
Z Q - BO n
PRR - 1.0 MHz
SOX D u ty Cycle
*TLH. *T H L < 5 n*
C|_ Includes Probe and

Jig Capacitanco
Open fo r
P ZLfE ) T*1 Only
Control
Input
*PZL(E)-
VOL
0 V
vqh
FIGURE 2 - PROPAGATION DELAY TIMES INPUT TO

OUTPUT WAVEFORMS AND TEST CIRCUIT
SOX D uty Cyclo
C|. Include! probe
5-85
MC3487
FIGURE 3 - OUTPUT TRANSITION TIMES TEST CIRCUIT AND WAVEFORMS

Scop*
In p u t
-<TLH
Pu Im generator characteristics
Z0 - SO n
PRR - 1.0 MHz
50% Duty Cycle

*TLH . t T H L < 5 n *
5
FIGURE 5 - OUTPUT SINK CURRENT versus OUTPUT VOLTAGE
Vqh, OUTPUT VOLTAGE (VOLTS)
V0L. OUTPUT VOLTAGE-LOW (mV)
5-86
MC3488A
MC3488B
MOTOROLA
Product Preview
DUAL
RS-423/RS-232C
DRIVERS
DUAL RS423/RS-232C LINE DRIVERS
The M C 3488A and MC3488B dual single ended line drivers have
been designed to satisfy the requirements o f E IA standards RS-423
and RS-232C, as well as C C ITT X.26, X.28 and Federal Standard
FIDS1030. They are suitable fo r use where signal wave shaping is
P1 SUFFIX
C A S E626
desired and the o u tp u t load resistance is greater than 450 ohms.

O utput slew rates are adjustable fro m 1.0
to 100 /is by a single
U SU FFIX
CASE 693
external resistor. O u tp u t level and slew rate are independent o f

power supply variations o r matching. Inp u t undershoot diodes lim it
transients below ground; o u tp u t current lim itin g is provided in both
o u tp u t states. They can be operated w ith supply voltages from 9.0
to 15 V .
The M C 3488A has a standard 1.5 V in p u t logic threshold fo r T T L
or NMOS co m p a tib ility . The MC3488B in p u t logic threshold is set
at V c c /2 fo r use w ith CMOS logic systems.
PIN CONNECTIONS
PNP Buffered Inputs to M inim ize In p u t Loading
Wide Power Supply Operating Range
Adjustable Slew Rate L im itin g
O ption o f E ither 1.5 V o r V q c / 2 In p u t Threshold
M C 3488A Equivalent to 9636A
Logic Levels and Slew Rate Independent o f Power Supply
Wuve I
Shape l 1
s '] V CC
j>
In p u t A | 2
In p u t B | 3
Voltages o r Matching
!>
G nd
Wave Shape
MC3486
5-87
7 | O u tp u t A
6 | O u tp u t B
T |
TYPICAL APPLICATION
This is advance in fo rm a tio n and s p e cifica tio n s are subject to chanoe w ith o u t notico.
v ee
MC3488A, MC3488B
ABSOLUTE MAXIMUM RATINGS (Note 1)

Rating
Value
Unit
VCC
v EE
+15
-15
o+
<0-
+150
-150
Ta
Tj
0 to +70
mA
Output Current
Source
Sink
Ceramic Package
Plastic Package
C
C
175
150

Note 1:
Symbol
-65 to +150
Tstgl
"Absolute Maximum Ratings'* are those values beyond which the safety of the
device cannot be guaranteed. They are not meant to imply th8t the devices should
be operated at these limits. The 'Table of Electrical Characteristics" provides
conditions for actual device operation.
RECOMMENDED OPERATING CONDITION

Characteristic
Symbol
Min
VCC
V EE
10.8
10.8
Typ
12
-12
Max
Unit
13.2
-13.2
ta
25
70
Wove Shaping Resistor
Rw
10
500
kn
TARGET ELECTRICAL CHARACTERISTICS (Unless otherwise noted specifications apply over

0C < TA < 70C, 9.0 V < IV CC, V EE l< 15 V and 2.0 k < Rw < 400 k)
Characteristic
MC3488A
MC3488B
MC3488A
MC3488B
Symbol

(V| h 2.4 V) MC3488A
(V|H 5.5 V)
MC3488A
(V|H VCC)
MC3488B
(l|K -1 5 mA)
IH

(Rw - 2.0 ktl)
<Rw 2.0 kn)
Output Resistance
(RU> 4 5 0 n )
Max
Unit
0.8
Vcc/2 -2.0
V
V|H
IL

(v c c - v e e o v . -6.o v < v 0 < 6 jo v )
Typ
V
-

(V | l = 0,4V>

(R|_ )
RS-423
(R|_ 3.0 kR) RS-232C
(R|_ 450 n ) RS-423
(RL - )
RS-423
(R l 3.0 k ll) RS-232C
(RL 4 5 0 n ) RS-423
Min
VlL
2.0
Vcc/2 + 2.0
-80
10
100
100
-1 3
-5.0
-5 j0
-4.0
-6.0
-6.0
-6.0
M
M
V|K
Vo l
v OH
>SC+
sc-
5.0
5.0
4.0
+15
-15
6.0
6.0
6.0
150
-150
ox
-100
ice
ee
+18
-18
25
50
100
mA
#iA
mA
Ro
Note: A diode it connected in series with V EE for all test conditions.
5*88
MC3488A, MC3488B
TRANSITION TIMES (Unless otherwise noted, CL - 30 pF, f = 1JO kHz, Vcc 12 V, V Ee - -12 V, TA - 25C,
Rj_ 450 n . Transition times measure 10% to 90% end 90% to 10%)
Characteristic
Symbol
Min
Transition Time, Low to High State Output

(Rw 10 kn)
<Rw 100kn)
(Rw S00kn)
(R w 1000 kn)
*TLH
0.8
8.0
40
80
1.4
14
70
140
Transition Time, High to Low State Output

(Rw 10 kn)
(Rw = 100 kn)
(Rw 500 kn)
(Rw = 1000 k)
*THL
0.8
8.0
40
80
1.4
14
70
140
Typ
Max
Unit
MS
_
-
PS
FIGURE 1 - TEST CIRCUIT & WAVEFORMS

FOR TRANSITION TIMES
To
VCC
To
V ee
FIGURE 2 - OUTPUT TRANSISTION TIMES

veisus WAVE SHAPE RESISTOR VALUE
TRANSITION TIMES, iTLH^THL M
5-89
MC3490 MC3494
MOTOROLA
ANODE (DIG IT) DRIVERS FOR

GAS-DISCHARGE DISPLAYS
SILICON MONOLITHIC
INTEGRATED CIRCUIT
SEVEN-DIGIT GAS-DISCHARGE DISPLAY DRIVERS

Seven channel digit (anode) drivers, the MC3490 and MC3494
are specifically conceived to be used with high-voltage, gas-discharge
numeric displays such as the Burroughs' Panaplex, Beckman (Sperry)
Cherry, or Diacon displays .
The MC3490 version is configured such that a high logic level
input causes the driver to turn on while the MC3494 requires a low
logic level to turn the drivers on. Both devices are designed to mate
with the MC3491 cathode (segment) driver.
With a low input current requirement of only 300 (iA typically,
these devices are compatible with popular MOS ctyps.
Minimum breakdown voltage is specified at 48 V and output
drive current capability is typically 30 mA per channel.
PIN CONNECTIONS
MC3480
High Breakdown Voltage 55 V Typical
Low Input Current for MOS Compatibility
Available with Either Active High or Active Low Inputs
Operable from Either Positive or Negative Supply Voltages
Input Clamp Oiodes on MC3494 Version for DC Restoration
Internal Pull-down Resistors
O utput
C
O utput
D
O utput
E
O utput
F
O utput
G
MC3494
vss
1
MOS
Calculator
or Clock C ircuit
17
[7
IT
V6E E
TYPICAL APPLICATION
WITH CAPACITIVE LEVEL SHIFT TO CATHODE DRIVER
Vqd
|7
(7
-W r
Anode
O utput*
* 0 . 1 F
MC3490
^ > -
-1 8 0 V
or
MC3494
VCC
OGe*-Di(Chorge
Vttual Display
Segment
O utput*
* VCC Digit*
(Anode*)
* V c g I* tied to the m a tt potitive

voltage of the MOS c ircuit
^Regittered Trademark o f Burroughs Corporation
5-90
S' 5 s
1
1
MC3490, MC3494
MAXIM UM RATINGS (T a 2 5C unless otherwise noted)

Rating
(Current Limited to -S mA)
Negative Supply Current
Symbol
Value
Unit
vee
-60
Vdc
-6.0
Vcc-20.Vcc
-50
mAdc
Vdc
mAdc
830
6.7
mW
mW/C
<EE
V|
Input Voltage
Output Current
{V0 = -5 V)
Package Power Dissipation
Derate above 25C
o
Pd
Tj
150
Ta
0 to +70
Tstg
-65 to +150
ELECTRICAL CHARACTERISTICS (TA 25C, Vcc Gnd VEE -6 0 V thru 5.0 kn. unless otherwise noted.)
MC3494
Symbol
Min
MC3490
Typ
Max
Min
Unit
VS(BR)
-48
-55
-48
Typ
-55
Max
Substrate Breakdown Voltage
Vdc
Input Current On State

V| = 0.0 V (See Figure 4)
V| = -7 .0 V (See Figure 3)
'lion)
-
250
-
700
-
-200
-350
Input Current Off State

V| = -15 V
V | 0.0 V
l(off)
<-1.0
-45
50
Input Voltsge - Off State

V oss V e e (See Figures 3 and 4)
Input Voltsge - On State
V o " Vcc-S-0 V (See Figures 3 and 4)
v l(off)
V|(on)
Characteristic
pA
-
Output Voltage Off State

V| = 0.0 V
V| - -7.0 V
v O(off)
Output Voltage On State

lO " -20 mA, V| - 0.0 V
I q -20 mA, V| -7.0 V
VQtonl
fiA
<1.0
-5.0
-2.0
Vdc
-2.0
-5 .0
Vdc
-4 8
-4 8
-
-3 .5
>5.0
Vdc
Vdc
NOTE: Minimum* and maximums are relative to absolute values.
SYSTEM DISCUSSION
The MC3491 and MC3490/MC3434 high voltage driver
system is designed such that it can be floated and any
point in the system may be tied to circuit ground. In a
MOS system, normally either the ground pin on the
MC3491 is tied to the most negative MOS voltage; or
the V q c P'n on tha MC3490/MC3494 is connected to
the most positive MOS voltage. In the electrical character
istics table, this V c c vo,ta9 is assumed to be 0.0 volts.
The MC3490/MC3494 provides its own internal voltage

reference when a current (-100 /iA to -5 mA) is drawn
at the V e e P'n (Pin 8). This can be provided by connecting
a resistor from Pin 8 to the high voltage reference on the
cathode driver or any other voltage more negative than
V c c 60 V. This voltage (Pin 8) is approximately -55 V
and provides a reference for the pull*down function for
each channel.
5-91
MC3490, MC3494
TYPICAL PERFORMANCE CHARACTERISTICS

FIGURE 1 SUBSTRATE CURRENT versus
SUBSTRATE VOLTAGE
'EE. SUBSTRATE CURRENT (mA)
FIGURE 2 - PERMISSIBLE OPERATING RANGE
vee . substrate voltage ivoltsi
FIGURE 3 - OUTPUT VOLTAGE and INPUT CURRENT

versus INPUT VOLTAGE
Vo. OUTPUT VOLTAGE IVOLTSI
FIGURE 4 - INPUT CURRENT and OUTPUT VOLTAGE

versus INPUT VOLTAGE
MC3494

(1/7 Shown)
vcc
MC3490
Input
Output
V EE
vee
5*92
MC3490, MC3494
12-DIGIT CMOS GAS DISCHARGE DISPLAY
When the number of digits for a gas discharge display
system is greater than the number of segment drivers, it is
generally more economical to level translate down to the
cathode segments than to translate up to the digit anodes.
An example of this technique is shown in the 12 digit
display system where the display anodes and cathodes are
referenced to ground and -180 V respectively.
The positive logic CMOS address circuits are powered
by -10 V (V DD 0, Vss -10 V) with the MC14558
decoder outputs capacitor-coupled to the MC3491 Segment
Drivers and the scan circuit directly-coupled to the
MC3490 Anode Drivers. Thus, only eight capacitors
(seven segments, one decimal point) are required as com
pared to 12 capacitors, if the strobed digit drivers were
ac coupled.
The MC3491 has input clamp diodes allowing for dc
restoration of the segment address pulse. This high voltage
driver (80 V) also features programmable segment current
by the selection of a single external resistor.
The MC3490 Anode Driven are selected by the positive
going output of the digit scan circuit. (If the scan circuit
outputs were negative going, the low logic level input
MC3494 Anode Driver should be used.) The internal
zener diode string of the MC3480 references the off
drivers (and display anodes) to -50 V without the need of

pull-down resistors.
Digit scanning for this example is derived from two
cascaded MC14022 Octal Counter/Drivers. The 12 se
quenced output pulses are achieved by resetting the
counters with the second counter Q7 output. In addition
to driving the two MC3490s, the counter output should
also control the system multiplexer (not shown) to
properly synchronize the entire display system.
The M CI4558 BCD-to Seven Segment Decoder has an
Enable input which readily provides for display cathode
blanking. For the illustrated display, the cathode drivers
should be turned off prior to anode switching and main
tained off for some period after the next anode is strobed.
This cathode blanking overlap is derived by trailing
edge time delaying the Gate 1 output of the non-symmetric
4 kHz scan oscillator with the integrated network and
inverter Gate 3.
The high voltage power supply rise and fall times should
be greater than the charge time of the coupling capacitors
to prevent large transients from possible degrading the
interface electronics.
For this example, power supply rise and fall time of
50 ms minimum will suffice.
FIGURE 5 - 12-DIGIT CMOS GAS DISCHARGE DISPLAY SYSTEM
5-93
MC3490, MC3494
3-1/2 DIGIT VOLTMETER

This specific application provides a 3*1/2 digit DVM
utilizing the MC1505 dual ramp subsystem and CMOS
MC1443S digital subsystem. Interfacing' between low
voltage logic ICs and the higher voltage gas discharge
displays requires level translation or shifting. The method
described for the 3-1/2 Oigit OVM uses directly coupled
high voltage (200 V) transistors to translate upward to the
MC3494 * Anode Drivers. Three of the transistors com
prising the MPQ7042 high voltage quad transistor are used
for this function. These transistors, connected in a com
mon-base, constant-current configuration, are turned on
by the negative going digit select output pulses of the
MCI 4435. The current of approximately 330 fiA is com
patible with 200 #iA typical input current of the MC3494
and the sink current capability of the MC14435.
The CMOS MC14558 BCD-to-Seven Segment Decoder
has the capability of directly driving the MC3491 Segment
Driver. Cathode blanking is accomplished by taking the
clock signal from Pin 4 of the MC14435 (approximately
50% duty cycle) and tying it to the Enable input of the
MC14458. The display segment current is increased accord
ingly to 1.1 mA (manufacturers maximum specified current
equals 1.25 mA) for this relatively large cathode blanking

period.
The positive and negative polarity signs are direct
driven by the fourth transistor of the MPQ7043 and
MPS-A42 transistor, Q2, respectively. Their dc segment
currents are scaled to produce the same brightness as the
multiplexed digits.
The 1/2 digit segments are driven by transistor Q1.
Its emitter is normally referenced to ground through
MC14572 Inverter G2, the output inverter of the Overrange Oscillator.
When an overrange situation occurs, the oscillator is
enabled, thus causing the display to flash at the oscillator
rate (approximately 8 Hz). This is accomplished by blank
ing the 1/2 digit through Q1 and the multiplexed digits
through diode D1 to the decoder enable input.
See the MC1405 'and MC14435 data sheets for more
details of DVM system.
FIGURE 6 - 3-54 DIGIT DIGITAL VOLTMETER
MC3490, MC3494
12-HOUR CLOCK WITH GAS DISCHARGE DISPLAYS

The MC3491 cathode driver and MC3494 anode
driver, greatly simplify the interfacing of a clock chip
(MOSTEK MK50250) to a gas discharge clock display
(Burroughs CD60733-CM).
TheMK50250hasa6digitclockdisplay with multiplex
ed 7 segment outputs. The MC3491 cathode drivers switch
each display cathode between ground (on condition) and
+76 Volts (off condition) with current limiting for the
display provided via the current programming pin on the
MC3491. The +75 Volt reference is obtained from a
75-Volt zener diode. Z1. R1. and a 50-Volt zener diode
Internal to the MC3494 anode driver.
The programming current is reduced during the time
when the "two seconds" indicator digits are ON, to reduce
the current through these smaller digits of the display.
Four diodes attached to each of the "hours and "min
utes" digits, provide a voltage of +180 Volts across the
680 ktt resistor. During the "seconds" digits display time,
the vol.tage is reduced to +130 Volts, thus reducing the
programming current.
The anodes for each of the six digits are switched
between the +180 Volt positive supply and +130 Volts
via the MC3494 anode drivers. Inter-digit blanking is
provided in the anode circuits. Level translation from

the clock chip output to the input to the MC3494 uses
two MPQ7042 quad high voltage transistor packages oper
ating in an emitter follower current source mode. Each
current source turns on one of the MC3494 drivers by
sinking 300 *iA to ground for the proper "on digit.
The AM/PM clock output is in the high state when
PM is indicated and has a 85% duty cycle corresponding
to each anode on time. A MC14001 Quad NOR Gate
decodes this output to turn on the appropriate AM or PM
indicator during the D6 digit. These Gates control the
AM/PM display indicators with the remaining MPQ7042
high voltage transistors which were not used in anode
selection.
The colon separating hours and minutes is switched on
during the units of hours digit on time. The colon cathodes
are switched from +75 Volts to ground via T1 during the
D5 digit time while the anodes are switched between
+180 and+130 Volts.
Further information concerning operation or technical
specifications on the MOSTEK clock chip, MK50250, and
the Burroughs clock display, CD60733-CM is obtainable
from the manufacturers.
FIGURE 7 - 1 2 HOUR CLOCK WITH GAS DISCHARGE DISPLAY SYSTEM
5-95
<g>
MC3491
MC3492
MOTOROLA
EIGHT-SEGMENT VISUAL DISPLAY DRIVERS

The MC3491 and MC3492 are eight-segment cathode drivers for
use with gas-discharge displays, such as the Burroughs' Panaplex
Beckman, Cherry or Diacon types. Both devices are directly compat
ible with MOS logic outputs due to their low 300 fiA input current
requirement.
All eight driver output currents are simultaneously programmable
by selection of a single external resistor. As programmed, all eight
currents match to within typically 1% of each other.
Both devices provide dc restoration. The units are specified for a
minimum breakdown voltage of 80 V.
The MC3492 device is made for larger and higher intensity dis
plays requiring higher segment current.
High Breakdown Voltage 80 V Min*
Drives Seven Cathode Segments plus Decimal Point
All Currents Simultaneously Programmable with One Resistor
MC3491 is Pin-for-Pin and Functionally Equivalent to DM8889

Output Current/Programming Current Ratio
Typically 4.5:1 forMC3491
9:1 for MC3492
SEGMENT DRIVERS FOR

GAS-DISCHARGE DISPLAYS
SILICON MONOLITHIC
INTEGRATED CIRCUIT
P SU FFIX
PLASTIC PACKAGE
CASE 701
PIN CONNECTIONS
Programming .
C urrent LL
Input 1
] O utpu t 3
In p u t 3 E
i ]|O u tp u t 4
In p u t 4 [T
3 O u tp u t S
o) O u tp u t 6
Companion with MC3490 and MC3494 Anode Drivers
MC3492 Provides Increased Output Current for High

Intensity Displays
In p u t 7 [T
In p u t 8 [T
5-96
J|Output 2
In p u t 2 ^
In p u t 6 E
In p u t 6 ^
'Higher Voltage Selection Available
3 O u tp u t 1
T] O u tp u t 7
3 O u tp u ts
<].Substrata (Gnd)1
MC3491, MC3492
MAXIMUM RATINGS
(Unless otherwise noted, TA = 25C)
Rating
Symbol
Value
U nit
O utput OFF Voltage

(Current Lim ited to 0.5 mA)
v 0 (o ff)
95
O utput ON Voltage
(Current Lim tied to 2.0 mA)
v O(on)
50
V|
20
Input Voltage
Programming Current
V
uA
'prog
40 0
2500
M C 3491
M C 3492
Tj
150
Ta
O to 70
Tstg
C
C
C
-6 5 to +150
ELECTRICAL CHARACTERISTICS (Unleu otherwise noted, Vcc < 80 V, T A 25C, Pin 10 Gnd. All voltages with respect to Gnd.I
MC3492
MC3491
Characteristic
Input Current
(V|H 7.0 VI
Input Clamp Voltage
IJ|K -1.0 mA)
Input OFF Voltage
Input ON Voltage
Output OFF Current
(V |L 0 V ,V O = V CC>
Output ON Current (at V |n = 7.0 V)*
prog 100 jiA)
(Iprog 350 mAI
(Iprog 200 #iA)
('prog
Output Current Matching
(All eight outputs)
Output OFF Voltage
(Iprog = 00 mA, RL = 1.0 M n ,V |L = 0 V )
"prog " 200 jiA .R L - 1.0 M , V ,L = 0 V)
Output Saturation Voltage
(Iprog = 100#jA, R l - I.OM O, V |H = 7.0 V)
('prog 200 jjA, R l * 1.0 MU. V |H 7.0 V)
Output Voltsge Compliance Range
(Iprog 100 fiA , l 0 (on) = 450 uA, V ,H = 7.0 V)
(See Figure 3)
Max
Unit
400
ItA
-1.0
1.5
2.4
-
3.5
5.0
V
V
Max
Min
200
Typ
300
400
200
Typ
300
VlK
-1.0
VlL
VlH
'O(off)
1.0
1.5
2.4
-
1.0
3.5
5.0
400
1450
450
1650
500
1850
-
< 1
Vcc-50
Vcc
Symbol
Min
>IH
t>A
dA
'O(on)
AIq
< 10
1.3
3.75
-
1.6
4.5
< 1
1.9
5.25
< 10
mA
%
V
Vo(off)
VO(sat)
_
-
3.0
-
5.0
-
Vcc-5-0
V cc
3.0
5.0
V
VoR(on)
50
5.0
Hprog 200 uA, l0 (on) 5 1.6 m A . V |H = 7.0 V)
(See Figure 3)
'Measured one channel at a time.
5-97
- 5.0
50
10. OUTPUT CURRENT 1/iA)
l|. INPUT CURRENT l/iA>
3D
1 ..
r
a
3
>
1
MC3491, MC3492
TYPICAL PERFORMANCE CHARACTERISTICS

FIGURE S - TYPICAL PROGRAMMING CURRENT vtrcut VOLTAGE ON PROGRAMMING PIN
ITA - 25C)
MC3492
. PROGRAMMING CURRENT biA)
MC3491
5-99
MC3491, MC3492
3-1/2DIG IT VOLTMETER
This specific application provides a 3-1/2-digit OVM
utilizing the-MC1505 dual ramp subsystem and CMOS
MC1443S digital subsystem. Interfacing between low
voltage logic ICs and the higher voltage gas discharge
displays requires level translation or shifting. The method
described for the 3-1 /2-digit DVM uses directly coupled
high voltage (200 V) transistors to translate upward to
the MC3494 Anode Drivers. Three of the transistors
comprising the MPQ7042 high voltage quad transistor are
used for this function. These transistors connected in a
common-base, constant-current configuration are turned
on by the negative-going digit select output pulses of the
MC14435. The current of approximately 330 fJA is
compatible with 200 jiA typical input current of the
MC3494 and the sink current capability of the MCI 4435.
The CMOS MC14558 BCD-to-Seven Segment Decoder
has the capability of directly driving the MC3491 or
MC3492 Segment Drivers. Cathode blanking is accom
plished by taking the clock signal from Pin 4 of the
MC14435 (approximately 50% duty cycle) and tying it to
the Enable input of tho MC14458. The display segment
current is increased accordingly to 1.1 mA (manufacturers

maximum specified current equals 1.25 mA) for this
relatively large cathode blanking period.
The positive and negative polarity signs are direct
driven by the fourth transistor of the MPQ7043 and
MPS-A42 transistor, Q2, respectively. Their dc segment
currents are scaled to produce the same brightness as the
multiplexed digits.
The 1/2-digit segments are driven by transistor Q1.
Its emitter is normally referenced to ground through
MC14572 Inverter G2, the output inverter of the Overrange Oscillator.
When an overrange situation occurs, the oscillator is
enabled, thus causing the display to flash at the oscillator
rate (approximately 8 Hz). This is accomplished by blank
ing the 1/2 digit through Q1 and the multiplexed digits
through diode D1 to the decoder enable input.
See the MC1405 and MC14435 data sheets for more
details of DVM system.
FIGURE 6 - 3-K DIGIT DIGITAL VOLTMETER
ISO V
5-100
MC3491, MC3492
12-DIGIT CMOS GAS DISCHARGE DISPLAY
When the number of digits for a gas discharge display
system is grester than the number of segment drivers, it is
generally more economical to level translate down to the
cathode segments than to translate up to the digit anodes.
An example of this technique is shown in the 12 digit
display system where the display anodes and cathodes are
referenced to ground and -180 V respectively.
The positive logic CMOS address circuits are powered
by -10 V (V q d = 0, Vss -10 V) with the MC14558
decoder outputs capacitor-coupled to the MC3491 Segment
Drivers and the scan circuit directly-coupled to the
MC3490 Anode Drivers. Thus, only eight capacitors
(seven segments, one decimal point) are required as com
pared to 12 capacitors, if the strobed digit drivers were
ac coupled.
The MC3491 and MC3492 have input clamp diodes
atlowing for dc restoration of the segment address pulse.
These high voltage drivers (80 V) also feature programma
ble segment current by the selection of a single external
resistor.
The MC3490 Anode Drivers are selected by the positive
going output of the digit scan circuit. (If the scan circuit
outputs were negative going, the low logic level input
MC3494 Anode Driver should be used.) The internal
zener diode string of the MC3490 references the off

drivers (and display anodes) to -50 V without the need of
putl-down resistors.
Digit scanning for this example is derived from two
cascaded MC14022 Octal Counter/Drivers. The 12 se
quenced output pulses are achieved by resetting the
counters with the second counter Q7 output. In addition
to driving the two MC3490's, the counter output should
also control the system multiplexer (not shown) to
properly synchronize the entire display system.
The MC14558 BCO-to-Seven Segment Decoder has an
Enable input which readily provides for display cathode
blanking. For the illustrated display, the cathode drivers
should be turned off prior to anode switching and main
tained off for some period after the next anode is strobed.
This cathode blanking overlap is derived by trailing
edge time delaying the Gate 1 output of the non-symmetric
4 kHz scan oscillator with the integrated network and
inverter Gate 3.
The high voltage power supply rise and fall times should
be greater than the charge time of the coupling capacitors
to prevent large transients from possible degrading the
interface electronics.
For this example, power supply rise and fall time of
50 ms minimum will suffice.
FIGURE 7 - 12-DIGIT CMOS GAS DISCHARGE DISPLAY SYSTEM
5-101
MC3491, MC3492
12-HOUR CLOCK WITH GAS DISCHARGE DISPLAYS

The MC3491 or MC3492 cathode drivers and MC3494
anode driver, greatly simplify the interfacing of a clock
chip (MOSTEK MK50250) to a gas discharge clock dis
play (Burroughs CD60733-CM).
The MK50250 has a 6-digit clock display with multi
plexed 7-segment outputs. The MC3491 cathode drivers
switch each display cathode between ground (on condi
tion) and +75 Volts toff condition) with current limiting
for the display provided via the current programming pin
on the MC3491 or MC3492. The -1-75 Volt reference is
obtained from a 75-Volt zener diode, Z1, R1, and a
50-Volt zener diode internal to the MC3494 anode driver.
The programming current is reduced during the time
when the "two seconds" indicator digits are ON, to
reduce the current through these smaller digits of the dis
play. . Four diodes attached to each of the "hours" and
"minutes" digits, provide a voltage of -*-180 Volts across
the 680 k n resistor. During the "seconds" digits display
time, the voltage is reduced to +130 Volts, thus reducing
the programming current.
The anodes for each of the six digits are switched
between the +180 Volt positive supply and +130 Volts
via the MC3494 anode drivers. Inter-digit blanking is
provided in the anode circuits. Level translation from

the clock chip output to the input to the MC3494 uses
two MP07042 quad high voltage transistor packages oper
ating in an emitter-follower current source mode. Each
current source turns on one of the MC34S4 drivers by
sinking 300 /iA to ground for the proper "on" digit.
The AM/PM clock output is in the high state when
PM is indicated and has an 85% duty cycle corresponding
to each anode on time. A MC14001 Quad NOR Gate
decodes this output to turn on the appropriate AM or PM
indicator during the D6 digit. These Gates control the
AM/PM display indicators with the remaining MPQ7042
high voltage transistors which were not used in anode
selection.
The colon separating hours and minutes is switched
on during the units of hours digit on time. The colon
cathodes are switched from +75 Volts to ground via T1
during the D5 digit time while the anodes are switched
between +180 and +130 Volts.
Further information concerning operation or technical
specifications on the MOSTEK clock chip, MK50250. and
the Burroughs clock display, CD60733-CM is obtainable
from the manufacturers.
FIGURE 8 - 12-HOUR CLOCK WITH GAS DISCHARGE DISPLAY SYSTEM
5-102
MC75107
MC75108
MOTOROLA
DUAL LINE RECEIVERS

The M C75107 and MC75108 are M T T L com patible dual line
receivers featuring independent channels w ith common voltage supply
and ground terminals. The MC75107 circu it features an active pull-up
(totem -pole) o u tp u t. The MC 75108 circu it features an open-collector
o u tp u t config u ra tion th a t perm its the Wired-OR logic connection w ith
similar outputs (such as the M C5401/MC7401 M T T L gate or additional
MC75108 receivers). Thus a level o f logic is implemented w ith o u t
extra delay.
The MC75107 and M C 75108 circuits are designed to detect inp u t
signals o f greater than 25 m illivo lts am plitude and convert the p ola rity
of the signal into appropriate M T T L com patible o u tp u t logic levels.
High Common-Mode Rejection Ratio
High In p u t Impedance
High Inp u t Sensitivity

D ifferential In p u t C ommon-M ode Voltage Range o f 3.0 V
D ifferential In p u t C ommon-M ode Voltage o f More Than 15 V

Using External A tte n u a to r
Strobe Inputs fo r Receiver Selection

Gate Inputs fo r Logic V e rsatility
M T T L or M D TL Drive C apability
High DC Noise Margins
MC55107 Available as JM 38510/10401
DUAL LINE RECEIVERS

P S U F F IX
CASE 646
L S U F F IX
CASE 6 32
T O -1 16
TRU TH TABLE
D IF F E R E N T IA L
IN P U T S
A B
O UTPUT
Y
V l o > 25 mV
L Of H
L or H
2 5 m V V | D *; 25 mV
V , 0 < -2 5 mV
5-103
STR O BES
L Of H
L or H
NOE TERMINATE
L Of H
L or H
MC75107, MC75108
MAXIMUM RATINGS (T a - 0C to +70C unleu otherwise noted)

Rating
Symbol
Value
Unit
+7.0
-7.0
Vdc
Oifferentisl-Mode Input Signal Voltage Range
VCC
VEE
V |D
6.0
Vdc
V ICR
+ 5.0
Vdc
Strobe Input Voltage ,
V I(S)
5.5
Vdc
625
3.85
mW
,mW/C
PD
Plastic and Ceramic Dual-ln-Line Packages

Derate above T a +2SC
ta
0 to +70
Tstg
-6 5 to +150

Characteristic
Symbol
Min
Typ
Max
Unit
VCc
VEE
+4.75
-4.75
+5.0
-5.0
+5.25
-5.25
Vdc

Output Sink Current
'OS
-1 6
mA
V IDR
-5.0
+5.0

Input Voltage Range, any differential input to ground
V ICR
V|R
-3.0
-5.0
*3.0
+3.0
Vdc
Vdc
ta
+70
Vdc
DEFINITIONS OF INPUT LOGIC LEVELS

Characteristic
Symbol
Test Fig.
Min
Max
U nit
High-Level Input Voltage (between differential inputs!
v IOH
5.0
Vdc
Low-Level Input Voltage (between differential inputs)
v IOL
0.025
-5 .0 t
-0.025
Vdc
High-Level Input Voltage (at strobe inputs)
V IH(S)
2.0
5.5
Vdc
Low-Level Input Voltage (at strobe inputs)
V IL(S)
0.8
Vdc
tT h e algebraic convention, where the most positive limit it designated maximum, it used with Low -Level Inp u t Voltage Level ( V|
ELECTRICAL CHARACTERISTICS {T a 0C to +70C unless otherwise noted)

Symbol
Tett Fig.
High-Level Input Current to 1A or 2A Input

(V c c Ma*. VEE * Max. v IO * 0-5 V. V|C = -3 .0 V
to +3.0 V) t
IH
Low-Level Input Current to 1A or 2A Input

(V c c Max. VgE Max, V|Q -2 .0 V. V ic -3 .0 V
to +3.0 V) |
'IL
High-Level Input Current to 1G or ?G Input

(V c c Max, V e e Max, V|H(S) * 2.4 V)$
(V c c Max, V e e * Max. V|H(S) * VCC MaxJJ
Low-Level Input Current to 1G or 2G Input
(V c c M**> VEE * Max. V | l (SI * 0.4 V)$
High-Level Input Current to S Input
(V c c Max, Vgg Max. V|H(S) * 2.4 V)J
(V c c Max, VEE Max. V|H(S) V CC MaxU
>IH
Low-Level Input Current to S Input

(V c c Max, V e e Max, V|i_{s) * 0.4 V)J
'IL
High-Level Output Voltage

( V c c Min, V e e Min, l|0Mj - - 4 0 0 *jA,
V |C -3 .0 V t o +3.0 V )*
VOH
Low-Level Output Voltage

(V c c Min, VgE Min, l | j n|( 16 mA
V|C " *3 .0 V to +3.0 V) J
High-Level Leakage Current
( V c c * Min, V e e " Min. V q h V c c Max I t
Short-Circuit O utpuj Current i i
(V c c Max, Vee Max
High Logic Level Supply Current from V c c
(VCc Max, VgE Max, V|Q 25 mV, TA +25C) %
v OL
Characteristic
High Logic Level Supply Current from V ee

(V c c Max, V e e Max, V |D - 25 mV, TA +25C)*
Min
Typ#
30
Max
U nit
75
pA
-1 0
*A
'
4
-
'IL
IH
40
1.0
-1 .6
80
2.0
PA
mA
-3.2
mA
0.4
250
'C E X
'OSC
CCH+
CCH-
<iA
mA
mA
ItA
mA
_
18
30
&4
-15
mA
mA
( F o r conditions thow n at M in or M ax, ute the appropriate value specif iad under recommended operating conditions for the applicable device type.
# A (I typical valuet are et V j j * 0 .0 V. V g - 5 . 0 V, T a * *2 5 C .
# # N o t m ore than one output should be shorted at a time.
5-104
MC75107, MC75108
SWITCHING CHARACTERISTICS (VCC - +5.0 V. VEE - -5 .0 V. TA - +25CI

Symbol
Test Fig.
Propagation Delay Time, low-to-high level from

differential Inputs A and B to o utput
(R L 3 3 0 f t . C|_ 50p F )
(R L - 3 9 0 t l , CL 15 pF)
Characteristic
tPLH(D)
Propagation Delay Time, high-to-low level from

differential inputs A and B to outp u t
(R L - 3 9 0 n , C(_ = 50 pF)
(R U 3 9 0 n . C f 15pF>
PHUD)
Propagation Delay Time, low-to-high level, from strobe

in put G or S to output
(RL - 3 9 0 n , CL - 5 0 p F |
(Rl_ 390 SI. CL 15 pF)
tPLH(S)
Propagation Delay Time, high-to-low level, from strobe

input G or S to output
(R L * 3 9 0 n , CL = 50 pF)
(R L = 3 9 0 n . CL = 15pF>
PHL(S)
M in
Typ
Max
19
25
25
U n it
ns
ns
19
ns
-
13
20
13
20
ns
TEST CIRCUITS
FIGURE 1 - V|DH nd V |DL
Vcc
FIGURE 2 - l|H and l|L

OPEN
2G S 1G V EE
Vcc
'z a t T S
VEg
N O T E : Each pair o f differential in p u ts is tested

separately. T h e in p u ts o f the o th e r pair
are gro un d od
N O T E : W h en testing o n e channel, the in p u ts o<

the o th er c hannel are grounded.
FIGURE 3 - V|H(S)> V|L(S). v OH. V q L' 8nd 'OH

See
Test
V|H(S>-
V|US)- Tabio
V Cc
_L
1AI I S .
MC75107
sink- Ic E X
!E O
load
Se e
Test
Table
sink. IC E X
i-o|
>
2B|
V |C
TEST TABLE
V EE
p o d
'lo a d
v0
i
5-105
MC751C8
V|0
ST R O B E 1G or 2G ST R O BE S
APPLY
TEST
v ON
'C E X
25 mV
VOH
cex
-as mV
v OH
VO L
>CEX
VOL
-26 mV
-25 mV
V|HIS>
ViLIS)
VlHIS)
V|HIS)
NOTES: 1. V,C -3 .0 V to 0 .0 V.
2. Whift tMtlng on channil, th inputs of 1
should b grounded.
V|H(S)
V|M(S)
VIL(S)
VIH(S>
MC75107, MC75108

FIGURE 4 - l|H{G)> l|L(G).
hUS)
'IH (S )
V IH ( S ) *
V |L (S )* _
11LIS)
V lO
TEST
INPUT 1A
INPUT 2A
STROBE 1G
STROBE S
l|H at Strobe 1G
25 mV
Gnd
Gnd
Gnd
1ih atS trob a 2G
Ond
+25 mV
V IH(S)
Gnd
Gnd
V IH(S)
Gnd
l|H etS tro b o S
+26 mV
+26 mV
Gnd
111_ nt Strobe 1G
-28 mV
Gnd
III. otS trob o 2G
Gnd
-2 5 mV
V IL(S)
Gnd
-25 mV
-25 mV
4.6 V
III, ot StrobeS
FIGURE 5 - I qs
V IH(S>
4.5 V
4.S V
V IL(S)
Gnd
V IU S )
4.8 V
FIGURE 6 - Icc and IgE

VCC+
NOTES: 1. Each channol it tested separately.

2. N o t more than one o u tp u t should be tastad at ona tim e.
STROBE 2G
V EE
MC75107, MC75108

FIGURE 7 - PROPAGATION DELAY TIME TEST CIRCUIT
AND WAVEFORMS
INPUT
A
+ 1 0 0 mV
1 00 m V
____ /
*p1
* --------V 1
STROBE
INPUT
G o rS
HL(D)
*PHL(D)
*PLH (D )
V v
I
I
1 / ----------
/ 1,6V
--------------*PHC(S)
*PLH(S>H
------ V O H
OUTPUT
Y
+ I.B V
T T l.B V
4Vl.e v
v+ 1.6V
VOL
1. Tho pulte generator! have the follow ing characteristic*: z0 6 0 f l , t r t f 10 + 8 nt, t p i 500 ns, PRR - 1 MHz
tp 2 - 1 m i, PRR - SOO kHz.
2. Strobe in put pulse It applied to Strobe 1G when Inputs 1A-1B are being tested, to Strobe S when Inputs 1A-1B or 2A-2B
are being tested, and to Strobe 2G when Inputs 2A-2B are being tested.
3. C|_ includes probe and |ig capacitance.
4. A ll dlodet are 1N016 or equivalent.
5-107
<g>
MC75125
MC75127
MOTOROLA
SEVEN CHANNEL
LINE RECEIVERS
SEVEN CHANNEL LINE RECEIVERS
16
The MC75125 and M C75127 are seven-channel line receivers

designed to satisfy the requirements o f the in p u t/o u tp u t interface
specification fo r IBM 360/370.
Special low-power design and Schottky-diode-clam ped tra n
1*
1
lt0PVi6W
>
sistors allow low supply-current requirements w hile m aintaining fast

sw itching speeds and high-current T T L outputs. The MC75125 and
MC75127 are characterized fo r operation from 0 to 70C .
B B S jl
J p rrr
161 *S M i 1
Meets IBM 360 /37 0 I/O Specification
In p u t Resistance 7 k H to 20 k2
O u tp u t C om patible w ith D T L or T T L
Schottky-C lam ped Transistors
Operates from a Single 5 V o lt Supply
High-Speed Low Propagation Delay
R atio Specification tp L H ^ P H L
Seven Channels in One 16-Pin Package
Standard V c c and Ground Positioning on MC75127
ill
11I
P S U F F IX
CASE 6 48
T Y P IC A L A P P L IC A T IO N S
IBM 3 6 0 /3 7 0 IN T E R F A C E
5-108
L S U F F IX
CASE 6 2 0
MC75125, MC75127
MAXIMUM RATINGS (TA 25C unless otherwise noted)

Rating
Symbol
Value
VCC
V|
+7.0

Input Voltage
Ceramic Package
Plastic Package
Derate Above TA - 25C
Ceramic Package
Plastic Package

Characteristic
High Level Output Current
Low Level Output Current
-2 .0 to +7.0
1/RflJA
1150
960
7.7
ta
0 to +70
PD
Unit
V
V
mW
mW/C
C
C
Tj
+ 175
+ 150
-6 5 to +150
Tstg
/
Symbol
Min
Typ
Max
Vcc
5.0
-
5.5
-0.4
OL
4.5
-
ta
'OH
16
+ 70
Unit
Vdc
mA
mA
(Unless otherwise noted, these specifications apply over recommended power supply and temperature ratings. Typical values measured at
Ta - 25C and VCC - *5 .0 V)__________________________________________________________________________________________
Max
Unit
Min
Characteristic
Symbol
Typ
V
1.7
High-Level Input Voltage
V |H
Low-Level Input Voltage
Low-Level Output Voltage (Vcc 4.5 V, Vm 1.7 V, Io l 16 mA)
Short Circuit Output Current* (Vcc

v - Vo
Input Resistance (Vcc 4.5 V, 0 V, or Open, AV| 0.15 V to 4.15 V)
Outputs High-Logic State (V cc " 5.5 v - 'OH
mA>a" input* at 0.7 V)
Outputs Low-Logic State (Vcc 5.5 V, Iq l 16 mA, all inputs at 4.0 V)
Characteristic
Low-to-High-Level Output
High-to-Low-Level Output
Ratio of Propagation Delay Times
Transition Tima, Low-to-High-Level Output
Transition Time, High-to-Low Level Output
Symbol
0.7
3.1
0.4
0.5
0.3
-
0.42
-0.24
mA
'IL
0.2
-
'os
-1 8
-6 0
mA
mA
v OL
IlH
High-Level Input Current (Vcc 5.5 V, V| >3.11 V)

Low-Level Input Current (V cc 5.5 V, V| 0.15 V)
SWITCHING CHARACTERISTICS (VCc " 5.0 V, TA 25C,
2.4
V|L
v OH
High-Level Output Voltage (Vcc 4.5 V, V il " 0.7 V, loH -0 -4 mA)
kn
7.4
'CCH
15
20
25
mA
'CCL
28
47
mA
= 400 n , Cl - SO pF. unless otherwise noted. See Figure 1)

MC75127
MC75125
Max
Min
Max
Typ
Min
Typ
Unit
ns
14
18
.2 5
30
0.5
0.8
1.0
1.0
7.0
3.0
1.3
12
12
PLH
tPHL
7.0
10
tPLH/tPHL
'TLH
*THL
No more than one output should be shorted at a time.
5-109
7.0
10
0.5
1.0
1.0
14
18
0.8
7.0
25
30
1.3
12
3.0
12
ns
ns
MC75125, MC75127
FIGURE 1 - PARAMETER MEASUREMENT INFORMATION

TEST C IRC UIT
VCc
NOTES:
A . Th pulM santrator hat th follow ing characteristic*:
z out "* 90 n - PRR 9 MHz.
8. C|_ includM probB and Jig capacitsnc*.
C. A ll diodei arc M MD7000 o r aquivslsnt.
FIGURE 2 - SCHEMATIC (EACH RECEIVER)
5-110
l|. INPUT CURRENT (mA)
ICC. SUPPLY CURRENT (mA)
Vcc. SUPPLY VOLTAGE (VI
V0L, LOW LEVEL OUTPUT VOLTAGE (V)

o
o
I)
o
in
in
MC75125, MC75127
V q , OUTPUT VOLTAGE (V)
no
>
M o
*5 O
O'
FIGURE B- INPUT CURRENT versus INPUT VOLTAGE
S
oBn<
Vq. OUTPUT VOLTAGE IV)
S o
i 5
" >
c
5*0 Hm
r a
< >
p 3
< z
o Q
FIGURE 6 - LOW-LEVEL OUTPUT VOLTAGE

versus OUTPUT CURRENT
MC75128
MC75129
MOTOROLA
EIGHT-CHANNEL
LINE RECEIVERS
EIGHT-CHANNEL LINE RECEIVERS
The MC75128 and M C75129 are eight-channel line receivers

designed to satisfy the requirements o f the in p u t/o u tp u t interface
specification fo r IBM 3 60 /37 0 . Both devices feature com m on
strobes fo r each group o f fo u r receivers. The MC75128 has an activehigh strobe; the MC75129 has an active-low strobe.
L S U F F IX
CASE 732
Special low-power design and Schottky-diode-clamped transistors

allow
low
supply-current
requirements
w hile
maintaining
fast
sw itching speeds and high-current T T L outputs. Both devices are

characterized fo r operation fro m 0 to 70C .
P S U F F IX
CASE 738
Meets IBM 360 /37 0 I/O Specification

In p u t Resistance 7 kJ2 to 20 kf2O u tp u t C om patible w ith D T L or T T L
Schottky-C lam ped Transistors

Operates fro m a Single 5 V o lt Supply
High-Speed Low Propagation Delay
Ratio Specification - tp L H ^ P H L
Common Strobe fo r Each Group o f Four Receivers
MC75128 Strobe - Active-High
MC75129 Strobe - A ctive -Lo w
IB M 3 6 0 /3 7 0 IN T E R F A C E
D R IV E R
M C 8 T 13/2 3
R E C E IV E R
M C 75 12 8 /1 2 9
20
V CC
19
1Y
IB
2Y
17
3Y
^16
4Y
is
5Y
,4
6Y
13
7Y
12
8Y
2S
5-112
MC75128, MC75129
MAXIMUM RATINGS (TA 25C unless otherwise noted)

Rating
Power Supply Volt8ge
A Input Voltage
Ceramic Package
Plastic Package
Derate Above TA 25C
Ceramic Package
Plastic Package
Symbol
Vcc
ViA
V|S
Value
+7.0
-0.15 to +7.0
+7.0
Unit
V
V
V
pd
11S0
960
-7.7
0 to +70
mW
1/RflJA
ta
mW/C
C
C
Tj
+175
+150
-65 to +150
Tstg

Characteristic
High Level Output Current
Low Level Output Current
Symbol
VCC
'OH
'OL
ta
Min
4.5
0
Typ
5.0
-
Max
5.5
-0.4
16
+70
Unit
Vdc
mA
mA
C
(Unless otherwise noted, these specifications apply over recommended power supply and temperature ratings. Typical values measured at
TA 25C and Vcc +5.0 V)
Characteristic
Symbol
Min
Max
Typ
Unit
V
V|H
_
_
A Inputs
1.7
S Inputs
2.0
Low-Level Input Voltage
V
V|L
_
.A Inputs
0.7
_
S Inputs
0.7
High-Level Output Voltage (Vcc 4.5 V, V|[_ 0.7 V, Ioh -0.4 mA)
2.4
3.1
V
VOH
Low-Level Output Voltage (Vcc 4.5 V, V|h 1.7 V, Iq l 16 mA)
0.4
0.5
V
Vo l
Input Clamp Voltage (Vcc 4.5 V, l| *-18 mA, S Inputs)
-1.5
V
V|K
High-Level Input Current
Wee 8.5 V, V| 3.11 V, A Inputs)
0.42
mA
0.3
>IH
-W
(Vcc 5.5 V, V| 2.7 V, S Inputs)
20
MA
'Low-Level Input Current

(Vcc 5.5 V, V| = 0.15 V, A Inputs)
-0.24
mA
IlL
(Vcc 5-5 V, V| = 0.4 V, S Inputt)
-0.4
Short Circuit Output Current (Vcc 5.5 v v O 0)
-18
-60
mA
os
Input Resistance (Vcc 4 $ V, 0 V, or Open, AV| - 0.15 V to 4.15 V)
7.0
20
kn
n
Power Supply Current Outputs High-Logic State, all inputs at 0.7 V
mA
CCH
- .
(VCc 5.5 V, Strobe at 2.4 V - MC75128)
19
31
(Vcc 5.5 V, Strobe at 0.4 V - MC75129)
31
19
Power Supply Current Outputs Low-Logic State, all inputs at 4.0 V
mA
CCL
(VCC 5-5 V, Strobe at 2.4 V - MC75128)
S3
32
53
(VCC 5.5 V. Strobe at 0.4 V - MC76129)
32
(V cc" 6-0 V ,TA 28C, Rj. 400 n , Cj_a 50pF, unless otherwise noted. See Figures 1 and2)
MC75128
MC76129
Unit
Min
Min
Typ
Max
Typ
Max
Propagation Delay Time From A Inputs
ns
7.0
14
14
25
tpLH<A)
25
7.0
10
30
10
18
30
18
tpHL<A>
Propagation Delay Time From S Inputs
ns
_
_
26
40
20
35
tpLH<S)
35
16
30
22
tpHL<S)
Ratio of Propagation Delay Times A Inputs
tPLH<A>/tpHL*A)
0.8
1.3
0.5
1.3
0.5
0.8
Transition Time, Low-to-High-Level Output
1.0
7.0
1.0
7.0
12
ns
12
*TLH
Transition Tima, High-to-Low-Level Output
1.0
1.0
3.0
12
3.0
12
ns
*THL
Characteristic
No more than one output should be shorted at a time.
5-113
MC75128, MC75129
FIGURE 1 - PARAMETER MEASUREMENT INFORMATION
VOLTAGE WAVEFORMS
LOAD CIRCUIT
INPUT
(See Note*
A, D, and E)
VCc
OUTPUT
----FROM OUTPUT
UNDER TEST ~ f ~
* M
- - V
(See Note C) r
- i60 pF
" (See Noto B)
VOH
OUTPUT
A . In p u t pulte* ere supplied by a generator having tho

follow ing charsctsrlftlct: Z 0 - SO SI. PRR S MHz.
B. Includes probe and Jig capacitance.
C. A ll dlodet are M MD7000 or equivalent.
D. Tho ttro b e Inputs o f MC7S129 aro ln-phate w ith the
output.
E. V ro f j - 0.7 V and V raf2 1.7 V fo r totting data (A)
Inputs, yf rof~1 " v ref2 * 1-3 V fo r ttrobe Inputt.
t-* T H L *TLH
FIGURE 2 - SCHEMATIC (EACH RECEIVER)
Other Channels
5-114
-!-V0L
5-115
en
MC75140P1
MOTOROLA
DU AL LINE RECEIVER
The MC75140P1 is a dual line receiver w ith com m on Strobe and
Reference inputs. The Reference voltage is externally applied. This
voltage may range fro m 1.5 to 3.5 volts, thus allowing fo r adjust
m ent o f m axim um noise im m u n ity in a given system design. The
MC75140P1 is intended fo r use as a single-ended receiver in M T T L
systems. Use in a party-line (bus-organized) system is aided by the
low in p u t current o f the receiver.
Single +5.0 -V olts Power Supply
100-m V Sensitivity
Low In p u t C urrent
M T T L C om patible O utputs
Adjustable Reference Voltage
Comm on O u tp u t Strobe
DUAL
LINE RECEIVER
(to p view)
C IR C U IT S C H E M A T IC
(1 /2 C irc u it S how n)
Vcc
CASE 626
Vcc
OUTPUT
REF.
LINE
2 INPUT INPUT 2
T Y P IC A L A P P L IC A T IO N
H IG H F A N -O U T F R O M A S T A N D A R D M T T L G A T E
n H = O j= T O = i Z r
OUTPUT
1
STROBE
INPUT
LIN E
INPUT 1
GNO
F U N C T IO N T A B L E
L IN E IN P U T
STR O BE
O UTPUT
V re f - 100 m V
V ro< < 100 m V
P ositive Logic
H High Level, L L o w Level,
X * N o n sig n ific a n t
Most MCS400/MC7400 devices are capable of maintaining

a 2.4-volt level under loads up to 7.5 mA.
5-116
MC75140P1
MAXIMUM RATINGS (T a - 0 to +70C unlew otherwitanoted.)

Rating
Supply Voltage
Reference Voltage
Line Input Voltage (with respect to Ground!
Line Input Voltage (with respect to Vref)
Operating Temperature Range (Ambient)
Symbol
^ref
V|(L)
VI(L)-Vref
V|(S)
PD
Unit
Volts
Volts
Volts
Volts
Volts
Value
7.0
v Cc
5.5
-2.0 to +5.5
5.0
S.S
mW
mW/C
C
C
830
6.6
0 to +70
-65 to +150
ta
Tstn

Rating
Reference Voltage Range
Input Voltage Range (Line or Strobe)
Symbol
vcc
Vref R
V|R
Ta
Min
4.5
1.5
0
0
Nom
5.0
-
Max
5.5
3.5
5.5
+70
Unit
Volts
Volts
Volts
C
Short-Circuit O utput Current* *

VCC - 5.5 V
o s
'CCH
Supply Current (output low)

Vs> - 0 V .V U - V ref + 100 mV
'CCL
SWITCHING CHARACTERISTICS(Vcc S.O V. Vref 2.5 V. CL

See Figure 1.
-55
18
30
20
35
-18
Supply Current (output high)

V|fs) * 0 V, V |(u - Vref 100 mV
1
o
<
ELECTRICAL CHARACTERISTICS (Vcc S.O V +10%. Vref 1.5 to 3.5 V, TA = 0 to +70C unless otherwise noted.)
Max
Min
Symbol
Characteristic
Typ*
High-Level Line Input Voltage
Vref + 100
V|H(L)
Low-Level Line Input Voltage
V|L(L)
2.0
High-Level Strobe Input Voltage
V|H(S)
0.8
Low-Level Strobe Input Voltage
V|L(S)
vOH
2.4
V|L(L) v ref " 100 mV. V|L(S) 0.8 V, Ioh -400 (iA
VOL
0.4
V|H(L) * Vref + 100 mV. V| l (S) -8 V. >OL " 16 mA
0.4
V|L(L) Vref * 100 "V. V,H(S) " 2.0 V. I0 L 16 mA
Strobe Input Clamp Voltage
V|(S)
-1.5
l|<SI -12 mA
Strobe Input Current (at max Input Voltage)
'l(S)
2.0
V|(S) 5.5 V
High-Level Input Currents
80
Strobe (V|(S) 2.4 V)
'lH(S)
35
100
Line (V|( l ) Vcc. v ref 1-5 V)
'IH(L)
70
200
Reference (Vref 3.5 V, V|( l ) " 1.5 V)
'lH(ref)
Low-Level Input Currents
-3.2
Strobe (V|js) " 0.4 V)
'lL(S)
-10
Line (V i j u -O V , Vref = 1 5 V )
'IL(L)
-20
Reference (Vref 0 V, V |(y - 1.5 V)
'lL (re f)
Unit
mV
mV
Volts
Volt
Volts
Volt
Volts
mA
*iA
mA
nA
*A
mA
mA
mA
15 pF, R|_ 4 00 Cl, Ta +25C unless otherwise noted.)
Characteristic
Propagation Delay Tim e (low-to-high level o u tp u t fro m Line input)
Propagation Delay Tim e (high-to-low level outp u t fro m Line input)
Propagation Delay Tim e (low-to-high level outp u t fro m Strobe input)
Propagation Delay Tim e (high-to-low.level output fro m Strobe input)
All typical value* ere st Vcc 5.0 V, T a * 25C.

"Only one output ihould be thorted at a time.
5-117
Symbol
Min
Typ
Max
U nit
PLH(L)
tPHL(L)
<PLH(S>
PHL(S)
22
ns
22
12
8.0
35
30
22
16
ns
ns
ns
MC75140P1
Vcc
I / 10% w V I
Vnl
- J r
2.SV
STROBE*
INPUT
_ b
O -t|
ITKl <tOw
flL-on
[/
J/uv
m m
___
MC75140P1
VX
4 i'------ -------- u v
I
9KUU
IN3QS4
m*
I'
K-4-vutta
OUTPUT
dndudtttrty
tnd jig apacittnn)
5
FIGURE 2 - OUTPUT VOLTAGE veruii
LINE INPUT VOLTAGE
Vc i 5.0
Vrtl 2.5 V
_ Vi(S)-0V
T/^25* C
1.0
2.0
3.0
VinlLI. LINE INPUT VOLTAGE (VOLTS)
FIGURE 3 - SCHMITT TRIGGER
4-0
5.0
FIGURE 4 - TRANSFER CHARACTERISTICS FOR

SCHMITT TRIGGER
-----Ta * 25cC
5-118
0.5
1.0
t .8
2.0
2.5
Vjn. INPUT VOLTAGE (VOLTS)
10
15
MC75140P1
FIGURE 6 - GATED OSCILLATOR
I. FREQUENCY (MHi)
FIGURE 6 - GATE OSCILLATOR FREQUENCY

versus RC TIME CONSTANT
RCT1ME CONSTANT bis)
FIGURE 7 - DUAL BUS TRANSCEIVER
MC55325
MC75325
MOTOROLA

Inform ation
DU AL MEMORY DRIVER
DUAL MEMORY DRIVER
The M C 55325/75325 is a m o n o lith ic integrated c irc u it m em ory

driver w ith logic inputs, and is designed fo r use w ith magnetic
memories.
The device contains tw o 600-m A source-switch pairs and tw o
600-m A sink-switch pairs. Source selection is determined by one o f
tw o logic inputs, and source turn-on is determined by the source
strobe. Likewise, sink selection is determined by one o f tw o logic
inputs, and sink turn-on is determined by the sink strobe. W ith th it
arrangement selection o f one o f the fo u r switches provides turn-on
w ith m inim um tim e skew o f the o u tp u t current rise.
600-m A O u tp u t C apability
Fast Sw itching Times
In p u t Clamp Diodes
Dual Sink and Dual Source Outputs
M D T L and M T T L C o m p a tib ility
2 4 -V o lt O u tp u t C apability
L S U F F IX
CASE 620
P S U F F IX
P LA S TIC P AC KA G E
CASE 648
(M C 75 3 25 o n ly )
5-120
MC55325, MC75325
MAXIMUM RATINGS ITa 25 unless otherwise noted)

Rating
Supply Voltage (Note 1)
Symbol
Vcci
Value
7.0
26
5.6
VCC2
Input Voltage
V|
Pd
Ceramic and Plastic Packages
1.0
6.6
ta
MCS532S
-55 to +125
MC76325
0 to +70
Storege Temperature Range
-65 to +150
Tstg
Note 1 Voltage values are with respect to the network ground terminal.
TRUTH TABLE
Unit
Vdc
Vdc
Vdc
ADDRESS INPUTS
STROBE INPUTS
OH
O ff
O ff
O ff
W
mW/C
C
O ft
O ff
O ff
OH
OH
OH
On
O ff
OH
O ff
OH
OH
O ft
On
O ff
O ff
H * h ig h lo v e l, L lo w le v e l, X Ir r e le v a n t
NOTE: N o t moro t h e n O ne o u tp u t Is to b e o n
a t a n y o n o tim e .
ELECTRICAL CHARACTERISTICS (Ta * T|ow to Thigh unless otherwise noted*1*)

Symbol
Characteristic
Input Voltege High Logic State
Input Voltege Low Logic Stete
Input Clamp Voltage
(Vcci 4.5 V, VCC2 -2 4 V, l | -10 mA. T a 25C)
Output Current Off State
(Vcci 4.5 V. Vcc 2 24 V)
TA T|ow Thigh
TA - 25C
(Vcci - 4.5 V. VCC2 24 V, l0 - 0)
Saturation Voltage*3*
Source Outputs
(Vcci 4.6 V. VcC2 16 V. Isource m"600 mA, R l 24 ohms.
Note 4)
TA - T |ow to Thigh
TA - 25C
Sink Outputs
(Vcci
v * VCC2 15 V,
>600 mA, R l 24 ohms.
Note 4)
T a - T io * to Thigh
TA 25C
Input Current at Maximum Input Voltage
(VCC1 6.5 V, VCC2 - 24 V, V| 5.5 V)
Address Inputs
Strobe Inputs
(Vcci - 6.6 V, VCC2 24 V. V| = 2AV)
Address Inputs
Strobe Inputs
(VCC1 - 6.6 V. VCC2 24 V, V, 0.4 V)
Address Inputs
Strobe Inputs
Supply Current Output Condition Off
(Vcci - 6.5 V. Vcc2 24 V, TA - 25C)
From Vcci
From Vcc2
Supply Current from Vcci >Either Sink "On"
(VCC1 6.5 V, VCC2 24 V, ltink - 50 mA, TA - 26C)
Supply Current from Vcc2< Either Source "On"
(VCC1 - 6.5 V.N/CC2 - 24 V. lMurea - -60 mA. TA - 25C)
V|H
VlL
V|
MCS6326
MC76326
Min Typ <2 Max Min Typ*2 1Max
2.0
2.0
0.8
0.8
-1.3 -1.7
-1.3 -1.7
mA
off
VOH
19
3.0
23
500
150
19
3.0
23
200
200
0.43
0.9
0.7
03
0.43
0.9
0.43 0.75
0.9
0.43 0.75
0.7
mA
1.0
2.0
3.0
6.0
40
80
-1.0 -1.6
-2.0 -3.2
1.0
2.0
3.0
6.0
40
80
-1.0
-2.0
-1.6
-3.2
fiA
>IH
mA
IL
mA
'CC(off)
-
<CC2
14
7.6
55
22
20
70
32
50
(1) Ttow - -5BC for MCSS326. 0C for MC7S325

Thigh " +126C for MC55325, +70C for MC75325
(2) All typical values are at T a 25C
(3) Not more than one output It to be "on" at any one time.
(41 Saturation voltage must be measured using pulse techniques: Pulte Width 200 (is, Duty Cycle < 2%
5-121
V
V
V*at
cci
Unit
V
V
V
14
7.5
55
22
20
70
mA
32
50
mA
MC55325, MC75325
SWITCHING CHARACTERISTICS (Vcci
- 5.0 V ,C L - 2 5 pF , T A - 25C)
Chsractaritlics
PropagationDelayTimetoSourceCollectors
(Vcc2* 15V, Rl" 24ohms) Low-to-HighLevel
High-to-LowLevel
TransitionTime
;
(Vcc2 20VrR(_ 1kohms) Low-to-HighLevel. i :
High-to-LowLevel' '
PropagationDelayTTmetoSinkOutputs
IVCC215V, Rl24ohms) Low-to-HighLevel
High-to-LowLevel
TransitionTime
(Vcc2 " 15V. Rl 24 ohms) Low-to-HighLevel Output
High-to-LowLevel Output
StorageTimetoSinkOutputs
(VCC2 " 15V. RL- 24ohirn)
Symbol
Min
tPLH
PHL
*TLH
*THL
MC66325/MC7632S
Typ
Max
25
25
tPLH
tPHL
*TLH
tTHL
ts
__
50
50
ns
ns
ns
ns
20
20
45
46
ns
ns
7.0
9.0
.16
15
20
30
ns
ns
ns
55
7.0
Unit
FIGURE1- SWITCHINGTIMESTOSOURCECOLLECTORSANDSINKOUTPUTS
* P L H m
In p u t P u lM C h a ra c te ris tic s :
z0 - S O D , P u lM W id th - 2 0 0 n t,
* T L H * T H L < 1 0 "* D u t y C y c le < 1 %
90%
*TLH
FIGURE3- PROPAGATIONTIME,
TRANSITIONTIMEANDSTORAGETIME
TOSINKOUTPUTS
.FIGURE2- PROPAGATIONTIMETO
SOURCECOLLECTORS
25pF
_L Vgci +B.0V
C l In clu d e s Pro b e
and J ig C a p a cita n ce
V CC1
S o u rc e W S h o w n U n d e r T e s t
**int
C l In clu d e * P ro b e
and J ig C a p a cita n ce
S in k Y S h o w n U n d e r T e t t
FIGURE4- SWITCHINGTIMESONSOURCEOUTPUTS (SeeFigureS)

3 .0 V
In p u t
0 V
vo h
O u tp u t
VO L'
90%; L
'
In p u t P u lM C h a ra c te ris tic s :
39 0 %
10%
10%1
-J
5-122
* T H L * T L H < 1 0 n , D u tV C y c l* < 1 %
P u lM W i d t h - 2 0 0 rtt
MC55325, MC75325
FIGURE 6 - TRANSITION TIME ON SOURCE OUTPUTS

To Scopa
I q f f . COLLECTOR OFF CURRENT (fiA)
FIGURE 6 - SOURCE COLLECTOR CURRENT

(Off-Stata) varsus AMBIENT TEMPERATURE
FIGURE 7 - SINK OUTPUT VOLTAGE-HIGH STATE V0 H

versut AMBIENT TEMPERATURE
21
is
15
>
V CC1*4.5
VC C 2 'M
6.0
75
-50
-----------<
<
1 >2
-25
25
50
75
tOO
125
s e
FIGURE 9 - SOURCE OR SINK SATURATION VOLTAGE

wreus SOURCE OR SINK CURRENT
T
< <
Vuu SATURATION VOLTAGE (VOLTS)
FIGURE 8 - SOURCE OR SINK SATURATION VOLTAGE

vsnu* AMBIENT TEMPERATURE
----4.5 V
ta
* 70C
ta
- 25C
TA *12 5C
T a -0 C
-SKOC
R*t 17;to
250
Rl 1 48
1
300
1
50
425
3(55
41
38
31
28
26
24
1
1
1
1 ---------1----------- 1
350
400
450
500
550
600
IS. SOURCE OR SINK CURRENT (mA)
s;E0
i
540
4 ro
-----
650
MC55325, MC75325
BASE DRIVE RESISTOR
An internal 575 SI resistor connected between the

VcC2 and the Rjnt terminals is provided in the MC55325/
75325 to supply sufficient base drive for source currents
to 375 mA at VcC2 of 15 Volts or 600 mA at VcC2 of
24 Volts. Connecting the R node to the R;nt node
selects this internal resistor. If source currents greater
than 375 mA are required, the R;nt node should be left
open and an appropriate resistor connected between
VCC2 and the R node. This method allows source base
drive currents regulated to typically within 5%. This
has an added advantage of removing the power dissipated
in the resistor from the IC package, allowing the device to
source greater currents at a given junction temperature.
The value of the required external resistor in a parti
cular memory application may be computed using the
following equation:
16 (VCC2 min-VS-2.2)
Rext
lL-1-6 (VCC2 min-Vs-2.9)
An internal pull-up resistor in parallel with a clamping

diode to V q C2 <s provided at each sind-output collector to
protect against voltage surges generated by switching re
duction loads.
FIGURE 10 - TYPICAL CIRCUIT USED

FOR Roxt CALCULATION
V CC2
(1 )
Where:
Rext - kJ2.
Vg the source output voltage referred to
ground.
Il
mA.
During the load current pulse the power dissipated in
the resistor, Rext is
Pn
Ro
VS
- lL<VCC2min-Vs-2)
x
t
^6
Where: PRext = mW.

The source collector current Ics is approximately 94%
of total load current, l(_. The remaining current flows in
the base of the source transistor through the external
resistor Rext or the source gate. See Figure 10 for added
details.
SELECTION M ATRIX
The combination of current source and sink pairs
within the MC75325 is often utilized to implement a
selection matrix for core memory systems. A typical,
simplified system is shown in Figure 11.
The selection of any particular line (line 7, for ex
ample) is made by activating a particular, unique combin
ation of two source/sink pairs. For an example, with
the Mode Select input high and B1 low, current source X
of #1 MC75325 will be activated. This selects lines 4-7.
When input C4 goes low, on #4 MC75325, current will
flow through line 7 from source X (of device #1) to sink

Y of device #4.
Changing the logic state of device #1 to input 01
low, device #4 to input A4 low, and applying a low to
the Mode Select input, reverses the direction of the current
in line 7 with the #1 MC75325 sinking the current and
the #4 device sourcing it.
Drive line inductance and capacitance only limits the
number of drive lines a source/sink pair can drive and thus
the size of a matrix possible.
MC55325, MC75325
FIGURE 11-TYPICAL
APPLICATION - CORE MEMORY
SELECTION MATRIX
Modo
Soleet
5-125
MC75450
MOTOROLA
DU AL PERIPHERAL
POSITIVE "A N D " DRIVER
D UAL PERIPHERAL
POSITIVE "A N D " DRIVER
The M C 75450 is a versatile device designed fo r use as a generalpurpose dual interface c irc u it in M D T L and M T T L type systems.
This device features tw o standard M T T L gates and tw o noncom m itted,
high-current, high-voltage NPN transistors. Typical applications in
clude relay and lamp drivers, pow er drivers, MOS and memory
drivers.
L S U F F IX
CASE 6 32
(TO -1 1 6)
M D T L and M T T L C o m p a tib ility
300 m A O u tp u t C urrent Drive C apability

(each transistor)
Separate Gate and O u tp u t Transistor fo r M axim um Design

F le x ib ility
High O u tp u t Breakdown Voltage:

VCER = 30 V o lts m inim um
V cc
2A
2Y
P S U F F IX
CA S E 6 4 6
2B
2C
SUB2E S T R A T E
M A X IM U M R A T IN G S ( T / \ = 0 t o + 7 0 C unless othe rw ise noted)

R eting
S ym b ol
V alue
U n it
P ow er S u p p ly V olta g e (See N o te 1)
V cc
+ 7.0
V dc
In p u t V oltage (See N o te 1)
Vjn
5.5
V dc
V c C ', 0 " S u b s tra te V oltage
35
V dc
C o lle ctor-to-S u b strate V olta g e
35
V dc
35
V dc
C ollector-Base V oltage
V CB
C o lle c to r-E m itte r V olta g e (See N o te 2)
V CE
30
V dc
E m itter-B ase Voltage
VEB
5 .0
V dc
300
mA
C o lle c to r C u rre n t (co n tin u o u s) (See N o te 3)

P ow er D issipa tion (Package L im ita tio n )
Pd
Plastic and Ceram ic Du8l In -L in e Packages

Derate above
= + 2 5 C
830
mW
6.6
m W /C
O pe ra tin g Tem p eratu re Range
Ta
0 to +70
Storage T e m p eratu re Range
T stg
-6 5 to +150
N O TE S:
1.
V olta g e values are w ith respect to n e tw o rk ground te rm in a l.
2. This value applies w hen the base-em ltter resistance (R q e > I s equel to or less
then 5 0 0 ohm s.
3. B o th h a lv e s o f th o s e d u a l c ir c u its m a y c o n d u c t th e ra te d c u r r e n t s im u lta n e
ously.
5-126
P ositive Log ic: Y AG (gate o n ly )

C AG (gate and tra nsisto r)
C IR C U IT S C H E M A T IC
o Vcc
MC75450
RECOMMENDED OPERATING CONDITIONS (See Note 4)

Characteristic
Supply Voltage
Note 4.
Symbol
Min
Nom
Max
Unit
Vcc
4.75
5.0
5.25
Vdc
The substrate, pin 8, mutt always be at the most negative device voltage for proper operation.
ELECTRICAL CHARACTERISTICS (Ta 0 to +70?C unless otherwise noted.)

|
Characteristic
Symbol
Test Fig.
Min
Unit
Typ*
MTTL GATES
V|H
2.0
Vdc
LowrLeyel Input Voltage
VlL
0.8
Vdc

(VCC 4.5 V, V|L - 0.8 V. I0 H -4> ^
(VccT4.75 V, V|H - 2.0 V, Iq l' ** 16 mA)
v OH
2
2.4
3.3
0.22
0.4
High-Level Input Current

(VCC " 5.25 V ,V in- 2.4 V)
(VCC " 5.25 V,Vj - 5.5 V)
Low-Level Input Current
(VCc - 5.26 V .V | - 0.4 V)
Vdc
V0 L
>IH
Input A
Input 6
Input A
Input G.
Vdc
>
IL
os
40
80
1.0
2.0
-1.6
-3.2
-18
-5 5
2.0
6.0
4.0
11
-1.5
mA
>CCH
'CCL
Input Clamp Voltage (Vcc 4.75 V, l|n -12 mA)
Vin
mA
mA
Supply Current
High-Level Output (Vcc 5.25 V, V|n 0)
Low-Level Output (Vcc " 5.25 V, V|n 5.0 V)
MA
mA
Input A
Input G
Short-Circuit Output Current*

(VCc 5.25 V)
OUTPUT TRANSISTORS
Symbol
Characteristic
Collector-Base Breakdown Voltage
(!c B 100 (A, lg 0)
VCBO
Collector-Emltter Breakdown Voltage

dc 100 wA, RgE 500 ohms)
VCER
Emitter-Base Breakdown Voltage

(IE -1 0 0 jiA, lC -0 )
Veb O
Static Forward Transfer Ratio (See Note 5)

(VCE 3.0 V. IC - 100 mA. TA - +25C)
(VCE - 3.0 V. Ic - 300 mA. TA - +25C)
(VcE _ 3.0 V, lC 100 mA, TA 0C)
(VcE - 3.0 V, Ic - 300 mA, TA - 0C)
hpE
Bese-Emltter Voltage (See Note 5)

(lB - 10 mA, lC 100 mA)
(lg - 30 mA, Ic 300 mA)
VflE
35
30
Unit
5.0
25
30
20
25
- -
Vdc
Vdc
Vdc
0.85
1.06
1.0
1.2
0.25
0.5
0.4
0.7
Vdc
VCE(set)
-
Note 5. These parameters must be measured using pulse techniques; tyy 300 jis, duty cyclo 2%.
All typical values at Vcc 5.0 V, TA +25C.
Not more than one output should be shorted at a time.
5-127
Max
Vdc
Collector-Emitter Saturation Voltage (See Note 5)

(lB 10 mA, lC - 100 mA)
(lg 30 mA, Ic 300 mA)
Typ
Min
MC75450
SWITCHING CHARACTERISTICS (Vcc _ 5.0 V. TA +25C unless othorwiw noted.)

Chsractargtic
Symbol | Tett Ftg. | Min
| Typ |
M b
14
6.0
| Unit |
MTTL GATES
Propagation Delay Time (C_ >15 pF, R|_ 400 ohms)
ns
-
tPLH
tPHL
OUTPUT TRANSISTORS *
Switching Times (ic " 200 mA. I g ( i > 20 mA, Iq(2 ) -40 mA.
v BE(off) -1.0 V . C|_ 15 pF, R(. " 50 ohms)
Delay Tima
Rise Time
Storage Time
Fail Time
ns
td
V
s
tf
9.0
11
14
8.0
GATES AND TRANSISTORS COMBINED #

Propagation Delay Time (Ic " 200 mA, C|_ - 15 pF, R[_ - 50 ohms)
High-to-Low Level Output
tPLH
tPHL
Transition Time* (Ic 200 mA, C|_ 15 pF, Rl 50 ohms)

Low-to-Hlgh-Level Output
*TLH
*THL
ns
9
-
21
16
7.0
8.0
ns
-V oltage and current values are nom inal; exact values vary slightly w ith transistors parameters.
DC TEST CIRCUITS FOR MTTL GATES

FIGURE 1 - V | H. Vo l
FIGURE 2 - V | L,V 0 H
V CC
V CC
(Arrows indicate actual direction of current flow. Current into a terminal is a positive value.)
FIGURE 3 - l | H
FIGURE 4 - l|L, Vin
V CC
4.5 V
5-128
V CC
MC75450
DC TEST CIRCUITS FOR MTTL GATES (continued)

FIGURE 5 - l o s
FIGURE 6 - IccM' lCCL

VCc
VCc
Both g a tn ara tsttad tlm ultanaoutly.
(A rro w t .Indicata actual dtractlon o f currant flo w . Currant Into a tarmtnal It a potltlva valua.)
FIGURE 7 - PROPAGATION DELAY TIMES, EACH GATE

+2.4 V
Vc c
^
_
+b o v
OUTPUT
v
>PIL - 400
1N3064
PULSE
GENERATOR
(Saa No to A )
H
1__ {__L____I
SUBSTRATEO OQND
* H H Mi
OR EQUIV
CL - 15 pF
(SaaN otaB)
NOTES: A. Tha pulta ganarator hat tha follow ing charactarittlcs: t * , 0.S It*, PRR - 1.0 M H *. zQ 33 80 n .
B. C l includat proba and jig copacltvnca.
VOLTAGE WAVEFORMS
5-129
MC75450

FIGURE 8 - SWITCHING TIMES, EACH TRANSISTOR
10V
NOTES: A. The pulte generator ho* the follow ing charactarittict: t * , - 0.3 p *,'d u ty cycle < I K , zo *50 f t.
8. C|_ Include* probe and Jig capacitance.
VOLTAGE WAVEFORMS
FIGURE 9 - SWITCHING TIMES. GATE AND TRANSISTOR

10 V
NOTE8: A. The puite generator ha* the.foilow lng characterlttlc*: t * , - O.B fi*. PRR - 1.0 MHz, zD & 50 f t .
B. C l include* probe and Jig capacitance.
VOLTAGE WAVEFORMS
5-130
MC75451
MC75452
MC75453
MC75454
MOTOROLA
DUAL
PERIPHERAL DRIVERS
DUAL PERIPHERAL DRIVERS

These versatile devices are useful fo r interfacing digital logic to
industrial electronic systems. They are useful as lamp drivers, relay
drivers, logic buffers, line drivers, or MOS drivers.
Each o f these devices consists o f a pair o f M T T L gates w ith the
o u tp u t of each gate internally connected to the base o f a transistor.
MC75451 provides the A N D fu n ctio n
MC75452 provides the N AN D fu n ctio n
MC75453 provides the OR fu n ctio n
MC75454 provides the NOR fu n ctio n
300 m A O u tp u t C urrent C apability
O utput Breakdown Voltage 30 V Min
M TT L com patible Inputs
P S U F F IX
U S U F F IX
CASE 6 93
CASE 626
M C 75 45 2 - P ositive N A N D
M C 75451 - P ositive A N D
TRU TH TABLE
A
L ( " o n state)
L ( " o n " state)
L ( " o n " state)
H ( " o f f " state)
high level. L
lo w level
1 |------1 2 |------ 1 3
1A
1B
1V
GND
Positive Log ic: Y = AB
M C 75 45 4 - P ositive N O R
M C 7 5 4 5 3 - P o s itiv e OR
V CC
2B
TR U TH TABLE
TRU TH TABLE
A
L ( " o n " state)
L ( " o n " state)
L ( " o n " state)
H ( " o f f state)
L ( " o n " state)
h ig h le v e l. L
H = high level, L = lo w level.
to w level
P ositive Log ic: Y ** A B
Positive L og ic: Y - A B
5-131
MC75451, MC75452, MC75453, MC75454
TVIAXIMUM RATINGS ITa * 0C to 70C unless otherwise noted.)

Rating
Value
Symbol
7.0
Power Supply Voltage! 1)
Vcc
5.5
Input Voltage
V|
5.5
' Interemitter Voltage(2)
Output Voltage! 3)
30
Vo
300
Output Current(4)
o
830
Power Dissipation @Ta 25C
Pd
6.6
Derate above Ta +25C
0 to +70
ta
-65 to +150
Tstg
Unit
Vdc
Vdc
Vdc
Vdc
mA
mW
r mW/C
C
c
(1) Voltage values are with respect to network ground terminal.

(2) Tljis is the voltage between two emitters of a multiple-emitter transistor.
(3) THE* is the maximum voltage which should be applied to any output when it
Is in the "off" state.
(4) Both halves of these dual circuits may conduct rated current simultaneously;
however, power dissipation averaged over a short time interval must fall within the
continuous dissipation rating.
ELECTRICAL CHARACTERISTICS (Unlessotherwise noted, specifications apply for 4.75 > Vcc
Figure Symbol
Characteristic
1.2
V|H
1.2
VlL
Input Clamp Voltage
4
v,
(VCC = 4.75 V, l| = -12 mA)
2
OH
MC75451, MC75453
(VCc 4 75 v <vOH 30 V, V|H - 2.0 VI
MC75452, MC75454
(VCC = 4.75 V, Vq h = 30 V. V|L " 0.8 V)
1
Vol
MC75451, MC75453
(VCC 4.75 V. V |L = 0.8 V)
MC75452, MC75454
(VCC = 4.75 V ,V |H -2 .0 V)
(lOL " 100 mA)
(lOL 300 mA)
3
*IH
(VCC= 5.25 V, V| Z4 V)
(VCC = 5.25 V, V| - 5.5 V)
Input Current Low Logic Stats
4
*IL
(Vcc = 5.25 V, V| 0.4 V)Power Supply Current Output High Logic State
5
<CCH
(VCC = 5.25 V, Vt 5.0 V)
MC75451
(Vcc 5.25 V, V| 0)
MC75452
(VCc = 5.25 V, V| - 5.0 V)
MC75453
MC75454
(VCC 5.25 V, V| 0)
Power Supply Current Output Low Logic State
5
CCL'
MC75451
(VCC = 5.25 V, V| 0)
MC75452
(VCC =* 5.25 V, V| - 5.0 V)
MC75453
(VCC = 5.25 V,V| = 0)
(VCC 5.25 V, V( - 5.0 V)
MC75454
>5.25 V and 0C < Ta < 70C)

Min
2.0
-
Typ (1)
100
jiA
0.8
-1.5
Unit
Vdc
Vdc
Vdc
Max
-1.2
-
Vdc
0.25
0.5
0.4
0.7
-1.0
40
1.0
-1.6
7.0
11
8.0
13
11
14
11
17
52
56
54
61
65
71
68
79
mA
mA
(1) Typical Values Measured with Vcc 5.0 V, Ta = 25C.

TEST CIRCUITS
FIGURE 1 - Vo l .
V|H - MC75452 and MC7S454
V| l MC7S4S1 and MC75453
(Current into terminal is shown as a positive value.

Arrows indicate actual direction of current flow.)
FIGURE 2 Iq h #
V|H - MC75451 and MC754S3
V |L - MC7S452 and MC75454
VCC
VCC
5-132
HA
mA
mA
MC75451, MC75452, MC75453, MC75454
SWITCHING CHARACTERISTICS (Vcc " 6.0 V, TA - +25C union otherwito noted.)

Characteristic
(lO 200 mA. Cj. - 16 pF, RL - 50 ohm*)
MC75451
Low-to-High-Leve) Output
High-to-Low-Lovel Output
MC75462
Hiflh-to-Low-Level Output
Symbol Tact Fig.
Min
Typ
Max
Unit
PLH
tPHL
17
18
nt
tPLH
tPHL
18
16
nt
PLH
IPHL
15
17
tPLH
tPHL
25
19
nt
TLH
*THL
6.0
11
ns
*TLH
*THL
ao
9.0
nt
MC75453
*TLH
*THL
5.0
8.0
nt
MC75454
TLH
*THL
5.0
8.0
nt
MC75453
High-to-Low-Leval Output
MC75454
Transition Time
(l0 200 mA. CL - 15 pF. RL - 50ohmt)
MC76451
MC75452
FIGURE 3 - l|H
(ALL DEVICE TYPES)
V CC
ns
TEST CIRCUITS (Continued)

(Current into terminal it shown at a potitive value.
FIGURE 4 l|L>V|
(ALL DEVICE TYPES)
4.5 v
MC75451
MC75452
Open
MC764B3 ----- T
MC76484
V CC
Open
I $
$
6 r ~ -T ------ - 4 - 1
Each in put it tatted separately.
FIGURE 5 - lcCH> (CCL

(ALL DEVICE TYPES)
VCc
See page 1 fo r specific gate type.
Open
Both gates are tatted simultaneously.
5-133
MC75451, MC75452, MC75453, MC75454

< 5 .0
< 1 0 n*
1 90%
1.SV
10%
NOTES:
A. Pulta ganarator characteristic*: t w 0.5 (it,

P R R - 1 .0 M H I. lo ^ S O f J
B. Cj_ includat proba and,tast fixture,capacltenca.
REPRESENTATIVE SCHEMATIC DIAGRAMS

(112Circuit* Shown)
5-134
9OX
1.5V
10% a
MC75461
MC75462
MC75463
MC75464
MOTOROLA
DU AL HIGH-VOLTAGE PERIPHERAL DRIVERS
DUAL HIGH-VOLTAGE
PERIPHERAL DRIVERS
The MC75461 thru MC75464 series is sim ilar to the MC75451

th ru MC75454 series peripheral drivers; however, the MC75461
series features greater voltage ca pa b ility allowing operation w ith
higher o u tp u t voltages or w ith inductive loads. These devices are
useful as lamp drivers, relay drivers, logic buffers, line drivers, or
MOS drivers.
Each o f these devices consists o f a pair o f M T T L gates w ith the
outp ut o f each gate in te rn a lly connected to the base o f a transistor.
MC75461
MC75462
M C 75463
MC75464
provides
provides
provides
provides
the
the
the
the
A N D fu n ctio n
N A N D fu n ctio n
OR fu n ctio n
NOR fu n ctio n
300 mA O u tp u t C urrent C apability
No O u tp u t Latch-up at 30 V
M T T L com patible Inputs
U S U F F IX
P S U F F IX
CASE 626
CASE 693
M C 75 46 2 - Positive N A N D
M C 75461 - P ositive A N D
V CC
TR U TH TA BLE
TRU TH TABLE
A
L ( " o n " state)
H ( " o ( l " state)
L ( " o n statel
H r o l l " state)
L ( " o n " statel
H ( o ff" s ta te )
L ( o n state)
H " high level. L lo w level
H = high level, L = lo w level.

2 ------ 3
3
1A
1B
VY
1A
GND
1B
1Y
G ND
Positive Log ic: Y - AB
Positive Log ic: Y *= AB
M C 7 5 4 6 4 - Positive NO R
M C 7 5 4 6 3 - P ositive OR
TRU TH TABLE
TRU TH TABLE
A
L C o n " stato)
L ( " o n " state)
L ( " o n " state)
L ( " o n " state)
H - high level. L lo w level.
high level, L = lo w level

I2 |
|3
1Y
[3
1Y
GND
GND
P ositive Log ic: Y - A + B
Positive Log ic: Y = A B
5-135
MC75461, MC75462, MC75463, MC75464
MAXIMUM RATINGS (T a * 0C to 70C unless otherwise noted.)

Value
Symbol
Rating
7.0
Power Supply Voltage(1) . _ .
Vcc
5.5
Input Voltage
V|
5.5
Interemitter Voltage(2)
Output Voltage<3)
35
Vo
. 300
, Output Current(4)
lo
830
Power Dissipation@Ta * 25C
pd
6.6
0 to +70
Operating Ambient Temperature Range ta
-65 to +150
Tstg
Unit
Vdc
Vdc
Vdc
Vdc
mA
mW
mW/C
C
C

(2) TM* Gp'tftsvoltage between two emitters of a multiple-emitter transistor.
(3) This ts the maximum voltage which should be applied to any output when it
it in the "oh" state.
however, povwr dissipation averaged over a short time interval must fail within the
ELECTRICAL CHARACTERISTICS (Unless otherwise noted, specifications apply for 4.75 > Vcc ^ *>.25 V and 0C < T a <70C)
Unit
Figure Symbol
Min
T v ^ ir Max
Characteristic
Vdc
2.0*
1.2
V|H
Vdc
0.8
1.2
V|L
-1.2
-1.5
Vdc
4
Input Clamp Voltage
V|
(Vcc 4.75 V, l| -12 mA)
*iA
*. 100
2
>OH
MC75461, MC75463
(v Cc 4 7 5 v, Voh 35 v, V|H - 2.0 v)
MC75462, MC75464
(Vcc 4 75 V, Vo h 35 V, V|L - 0.8 V)
1
Vdc
VOL
(VCC 4.75 V ,V |L -0 .8 V)
MC75461, MC75463
MC75462,
MC75464
(Vcc 4.75 V, V |H 2.0 V)
0.15
0.4
lOL 100 mA
0.7
>OL 300 mA
0.35
Input Current r- High Logic State
3
IH
. . J V c c - 5.25 V, V| 2.4 V) '
HA
40
(VCC S.25 V, V) - 5.5 V)
i 1.0
mA
4
mA
-1.0
-1.6
>IL
(VCC 5 25 V, V| - 0.4 V)
Power Supply Current Output High Logic State
mA
5
'CCH
_
MC75461
(Vcc 5 25 V, V|H 5.0 V)
8.0
11
_
MC7S462
(Vcc 5.25 V, V|L 0)
13
17
_
MC75463
(VCC " 5.25 V, V|H 5.0 V)
8.0
11
MC75464
14
(VCC 5-25 V, V il 0)
19
Power Supply Current Output Low Logic State
5
mA
gcl
(VCC 5.25 V. V|L - 0)
MC75461
61
76
(Vcc = 5 25 V. V|H - 5.0 V)
MC75462
65
76
MC75463
(Vcc 5.25 V, V il 0)
63
76
MC75464
(VCC 5 25 V, V|H 5.0 V)
72
85
(1) Typical Values Measured with Vcc 5.0 V, Ta 25C
TEST CIRCUITS
FIGURE 1 - V o l
V|H ~ MC7S482 and MC75464
V |L - MC76461 and MC76463
(Current into terminal is shown as a positive value.

FIGURE 2 - I q h .
V |H - MC76461 and MC7S483
Vi I - MC76482 and MC7S464
V CC
*Sm Pag* 1 fo r (pacific gata type.
5-136
MC75461, MC75462, MC75463, MC75464
SWITCHING CHARACTERISTICS (Vcc 5.0 V, TA +2SC unlew otherwise noted.)

Characteristic
Symbol Test Fig.
(lO ~ 200 mA, Cl - 15 pF, RL - 50 ohms)
MC7S461
Low-to-High-Levd Output
6
tPLH
Higtvto-Low-Level Output
*PHL
MC75462
6
tPLH
tPHL
MC75463
6
*PLH
tPHL
MC7S464
6
*PLH
PHL
Trantition Time
(lO 88200 mA. Cl - 15 pF. Rl 50 ohmt)
MC75461
6
*TLH
*THL
MC75462
6
*TLH
*THL
MC75463
6
*TLH
*THL
MC75464
6
*TLH
*THL
7
Output Voltage - High Logic Level after Switching (Latch-up Tett)
VOH
(VS=30V l0 300 mA)
FIGURE 3 - I| h
(ALL DEVICE TYPES)
Vcc

(Current into terminal it thown at a positive vatue.
Arrovw* indicate actual direction of current flow.)
Typ
Max
Unit
45
30
55
40
nt
50
40
65
50
ns
45
30
55
40
nt
50
40
65
ns
8.0
10
20
20
ns
12
15
25
20
ns
8.0
10
25
25
nt
12
15
20
20
nt
mV
Min
VS-10
FIGURE 4 - l|L.V|
(ALL DEVICE TYPES)
Open
Each Input it tattod toparataly.
FIGURE 6 - IcCH. 'CCL

(ALL DEVICE TYPES)
Vcc
See paga 1 fo r tpacific gata typa.
Open
Both gates ara tasted tlm ultanaoutly.
5-137
50
MC75461, MC75462, MC75463, MC75464
FIGUne 6 - SWITCHING TIMES TEST CIRCUIT AND WAVEFORMS
< 5 .0 r
MC75462
and
MC75464. H
Input
< 1 0 ns
t 90%
1.5V
10%
3 V
90% *
1.6V
10 % ^
NOTES; A. Pulse generator characteristics: tw - 0.5 in .

PRR - 1.0 MHz, z0 s 6 0 n
B. Cu includes probe and test fix tu re capacitance.
0 V
3.0 V
0 V
Voh
VOL
FIGURE 7 OUTPUT VOLTAGE AFTER SWITCHING TEST CIRCUIT AND WAVEFORMS

(LATCHUPTEST)
V8 - 30 V
To Scop* M
(Inp ut)
MC78403
MC76464
5.0 V
Ir i
T1N3064
[orEquh
4MC7546
IMC75461
MC75462
Pulse
Generator
(See Note A)
To Scope
1 (Output)
J L CL - 15 pF
'< S ~ Note B)
GNO'
,|
Input
i I
MC7S4S1 30% \
J
and
1.5 V * ,
MC75463
, Input
MC75402
and
,
MC75464
See Page 1 fo r specific gate type.
O utput A ll Types
!- < 10 1
< 5 I
90%
,5 V
'
<10 I
jy-90%
**1.5 V
0 V
<10 i
90%
y *sp r
1.5 v \ i
3 V
3V
0 V
vo h
Vo l
NOTES: A. The pulse generator has the follow ing characteristics: PRR - 12.5 kHz, Z out 50 n
B. C l Includes probe and |lg capacitance.
5-1 38
MC75461, MC75462, MC75463, MC75464

(1/2 Circuit* Shown)
5-1 39
<8>
MC75491
MC75492
MOTOROLA

Inform ation
MULTIPLE
LIGHT-EMITTING DIODE (LED)
DRIVERS
QUAD LED SEGMENT DRIVER - MC75491
HEX LED DIG IT DRIVER - MC75492
The MC75491 and M C 75492 are designed to interface MOS logic

to com m on cathode lig h t-e m ittin g diode readouts in serially ad
dressed m u lti-d ig it displays. Using a segment address and dig it scan
LED drive m ethod in a tim e m u ltip lexin g system results in a
m inim izing o f the num ber o f required drivers.
Low Inp u t C urrent Requirem ent fo r MOS C o m p a tib ility
Low Standby Power Drain
Source or Sink C urrent C apability o f 50 m A fo r MC75491
Sink C urrent C apability o f 250 m A fo r MC75492
Four High-Gain D arlington Drivers in a Single Package MC75491
Six High-Gain D arlington Drivers in a Single Package MC75492
P S U F F IX
CASE 6 46
M C 75491 C IR C U IT S C H E M A T IC
(1 /4 C irc u it S how n)
C O N N E C T IO N D IA G R A M S
4 k
^VW-
c
14 j In p u t 4
E m itte r 1 | 2
C o lle cto r 1 | 3
v ss o
TO O TH E R
D R IV E R S
TRU TH TABLE
IN P U T
O UTPUT E
OUTPUT C
E mi tt er .
?2| C o lle c to r 4
H I v ss
10| C o lle c to r 3
9 | E m itte r 3
8 ) In p u t 3
O u tp u t 1 [ 1
14| In p u t 1
O u tp u t 2 | 2
131 O u tp u t 6
In p u t 2 [ T
- > 3
C < }
G ND [IT
In p u t 3 | 5
O u tp u t 3 [ 6
O u tp u t 4 | 7
5-140
~ P i
r< F
1 2 1 In p u t 6
111 Vss
1o| In p u t 5
9 | O u tp u t 5
8 | In p u t 4
MC75491, MC75492
M A X IM U M RATINGS (Ta - 0 to +70C unless otherwin noted.)

Value
Rating
Symbol
MC7S491
MC7S492
Unit
Bias Supply Voltegs (See Note 1)
VSS
10
10
Input Voltage (See Note 2)
V ln
-5.0 to Vss
-5.0 to Vss
Vdc
Collector Voltage (See Note 3)
vc
10
10
Vdc
Collector-to-Emitter Voltage
Vdc
VCE
10
Vdc
Colfector-to-lnput Voltage
Vd
10
10
Vdc
Emitter Voltage (Vjn > 5 .0 Vdc)
VE
10
Vdc
Emitter-to-lnput Voltage
VE|
5.0
Vdc
Continuous Collector Current (Each Collector)

(All Collectors)
'c
50
200
250
600
mA
mA

Ceramic and Plastic Dual In-Line Packages
Pd
ta
0 to +70
Tstg
-65 to +150
830
6.6
mW
mW/C
Note 1. V$s terminal voltage is with respect to any other device terminal.
Note 2. With the exception of the inputs, the GND terminal must always be the most negative device voltage for proper operation.
Note 3. Voltage values are with respect to GND terminal unless otherwise noted.
ELECTRICAL CHARACTERISTICS (Vss = 10 Vt,c* TA 0 to +70C unless otherwise noted.)

MC75492
MC75491
Symbol
Characteristic
Low-Level Collector-to-Emitter Voltage
(Vin 8.5 V thru 1.0 kn, l<)L 50 mA,
VE - 5.0 V)
TA +25C
TA 0 to +70C
Typ
Min
Min
Max
Typ
Max
Unit
Vdc
VCEL
-
High-Level Collector Current

VCH 10 V, V E - 0 ,lin 40tA
VCH 10 V. VE 0, Vjn 0.7 V .
>CH

(Vin - 6.5 V thru 1.0 kn. I q l 250 mA)
TA " +25C
Ta 0 to +70C
Vq l
High-Level Output Current

V0H 10 V, ljn 40 fiA
v 0 H - 1 0 V. v in 0.5 V
<OH
0.9
1.2
1.5
100
0.9
-
1.2
1.5
HA
100
Vdc
200
200
2.2
3.3
2.2
3.3
mA
100
nA
1.0
1.0
mA
HA
Input Current at Maximum Input Voltage

Vin - 10 V, Iq l -2 0 mA
'in
Emitter Current Reverse Bi8S

lC 0. Vin - 0. V E 5.0 V
er
Bias Supply Current (Vss 10 V)
'SS
'
SWITCHING CHARACTERISTICS (Vss 7.5 V ,T A " +2SC unless otherwise noted.)

Propagation Delay Time, High-to-Low Level
RL = 200n, V |H 4.5 V ,C L 15pF,V E = 0
RL = 39 , V |H 7.5 V, Cl 15 pF
PHL
Propagation Delay Time, Low-to-High Level

Cl = ISpF, V e = 0, R l = 200 n, V )H = 4.5 Vdc
CL = 15pF,R L = 3 9 n ,V |H 7.5 Vdc
*PLH
rw
20*
40
nt
T o collector o u tp u t.
5-141
40*
'
80
I& COLLECTOR CURRENT (mA)
FIGURE 3 - COLLECTOR CURRENT versus INPUT CURRENT
tC. COLLECTOR CURRENT (mA)

VcE(on). COLLECTOR-TOEMITTER VOLTAGE (Vdc)
Ifl. OUTPUT CURRENT (mA)
FIGURE 4 - OUTPUT CURRENT verntt INPUT CURRENT
IQ. OUTPUT CURRENT (mA)
MC75491, MC75492
TYPIC A L CHARACTERISTICS and

SWITCHING TIM E CIRCUITS
FIGURE 7 - MC75491/MC75492 INPUT CURRENT
FIGURE 8 - MC76491 SWITCHING CIRCUIT
. G N O (C|_ in clude * probe'snd

iig capacitance.)
FIGURE 9 - SWITCHING WAVEFORM DEFINITIONS
<TLH < 1 0 n
!
|
i
f"
i !
*] { t T K U < 1 0 n *
---------------------------- V ,H
In p u t
0 V
.
O utpu t
\s 0 %
'
V0
'O HH
-----
TpBOX
j>---------- h
i - 4 i ----------------------VOL
!
i
tP H L 1 H
'
T 1 *PLH r .
The pulto generator hM th e fo llo w in g charactertstict:

- 60 O . PRR - 1 0 0 k H z . PW - 1.0/1*.
TYP IC A L APPLICATIONS
FIGURE 12 - OUAD-OR-HEX LAMP DRIVER
5 -1 43
MC7S491, MC75492
TYPICAL APPLICATIONS (continued)

-t d . uo . *,
FIGURE 13 MOS-TO-MTTL LEVEL TRANSLATOR
FIGURE 1 4 - QUAD HIGH-CURRENT NPN

TRANSISTOR DRIVER
FIGURE 15 - QUAO-OR-HEX HIGH-CURRENT

PNP TRANSISTOR DRIVER
In p u t l
V ee
(Suitable fo r u a w ith com m on-enode V L E D displays)
FIGURE 17 - MOS CALCULATOR CHIP-TO-LED INTERFACE CIRCUIT

f v SS
8 (1 /4 MC7S491 C ircuit)
2 Packages
Rl
H
-0-224
MOS
Calculator
Chip
M u ttl-O Igit LEO
Display
(N Digits)
- I
I
r v
N (1 /6 MC7S492 C irc u it)

2 Packages if N - 12
ON
-O -
rb-Voo
T h i* axam ple uses tim e m ultip le xin g o f th a Individual dig its In a visibla display to m in im iz e display
c irc u itry . U p to twelve digits, each o f w hich use a seven segment display w ith decim al p o in t, m ay
be displayed using o n ly tw o MC75491 and tw o MC78492 drivers.
5-1 44
MC75491, MC75492
TYPIC A L APPLICATIONS (continued)

FIGURE 18 - STROBED "NOR" DRIVER
2-MC7S491
Circuits
" Lamp or Relay
In p u t 1
S trobe
In p u t
M nput 2
M C75492
^
_
(MC75491
o nly)
FIGURE 19 - DC MOTOR SPEED/DIRECTION CONTROL CIRCUIT

S pecd/D irection
C o ntrol
o r Equiv
Each a m p lifie r sym bol represents 1 /4 MC7S491 c irc u it (tw o packages to ta l).
<g>
SN75431
SN75432
MOTOROLA
Product Preview
DU AL
PERIPHERAL
DRIVERS
DUAL POSITIVE AND/NAND
PERIPHERAL DRIVERS
The SN75431 and SN 75432 are dual peripheral drivers designed

fo r systems em ploying either T T L o r D T L logic. The SN75431
provides a positive A N D fu n ctio n and the SN75432 provides the
positive N A N D .
These devices provide a high-speed interface to medium-voltage
peripherals requiring drive currents up to 300 m A. A pplications
include high-speed buffers, line drivers, MOS drivers, memory
drivers, and power drivers.
Both parts are m echanically and fu n ctio na lly the same as the
75450B, 460 and 470 equivilents.
JG S U F F IX
CASE 6 93
Characterized fo r Currents U p to 300 m A
Very Fast Sw itching Speed
T T L o r D T L C om patible
Standard 5.0 V Supply
Available in Both Plastic and Ceramic Package
P S U F F IX
CASE 6 26
SN 75431
P ositive A N D
S N 7 54 32
P ositive N A N D
V CC
P ositive Logic Y A B
Positivo Logic Y = A B
F u n ctio n Table (Each O rivor)
F u n ctio n Table (Each O rivor)
L
L
L
H
L (o n)
L
H
H
L
H
L
H
L
L
H
L
H
L
H ( o ff)
H
H
H High Level
L * L ow Level
This is advance in fo rm a tio n and sp ecifica tio ns are subject to change w ith o u t notice.
5-146
SN75451BP
SN75452BP
SN75453BP
SN75454BP
MOTOROLA
DUAL PERIPHERAL DRIVERS
DUAL
PERIPHERAL DRIVERS
These versatile devices are useful fo r interfacing digital logic to

industrial electronic systems. They are useful as lamp drivers, relay
drivers, logic buffers, line drivers, or MOS drivers.
Each of these devices consists o f a pair o f M T T L gates w ith the
o u tp u t of each gate intern a lly connected to the base o f a transistor.
SN75451BP
SN75452BP
SN75453BP
SN75454BP
provides
provides
provides
provides
the
the
the
the
A N D fu n ctio n
N A N D fu n ctio n
OR fu n ctio n
NOR fu n ctio n
300 m A O u tp u t Current C apability
O u tp u t Breakdown Voltage 30 V Min
M TT L com patible Inputs
Guaranteed AC L im its
P S U F F IX
U S U F F IX
CE R A M IC P A C K A G E
CASE 693
CASE 6 26
S N 7 54 52 B P - P ositive N A N D
S N 75451B P - P ositive A N D
V CC
TRUTH TABLE
TR U TH TABLE
A
L ( " o n state)
L ( " o n state)
H ( " o f f * state)
L ( " o n " state)
H ( " o f f state)
L ( " o n " state)
H - high level. L
1B
1Y
lo w level
GND
Positive L og ic: Y = A B
S N 7 54 54 B P - P ositive N O R
S N 7 5 4 5 3 8 P - P ositive OR
TRU TH TABLE
IB
1Y
high level. L = lo w level
L ( o n " state)
H (" o ff
state)
H ("o ff
state)
H ( " o ff-
state)
h ig h le v e l. L
lo w le ve l
GND
Positive Log ic: Y * A B
Positive L o g ic: Y - A B
5-147
SN75451BP, SN75452BP, SN75453BP, SN75454BP
MAXIMUM RATINGS (Ta = 0c to 70C unless otherwise noted.)

Value
Symbol
Rating
7.0
Power Supply Voltage! 1)
vcc
5.5
Input Voltage
V|
5.5
Interemitter Vottage(2)
Output Voltage(3)
30
Vo
300
Output Current(4)
'O
830
Power Dissipation @Ta " 25C
pd
6.6
Derate above Ta +25C
0 to +70
ta
-65 to +150
Tstg
Unit
Vdc
Vdc
Vdc
Vdc
mA
mW
mW/C
C
C

(2) This is the voltage between two emitters of a multiple-emitter transistor.
(3) This is the maximum voltage which should be applied to any output when it
is in the "off" state.
however, power dissipation averaged over a short time interval must fall within the
ELECTRICAL CHARACTERISTICS (Unless otherwise noted, specifications apply for 4.75 >Vcc > 5.25 V and 0C < T/^ < 70C)
Characteristic
Figure Symbol
Min
Typ (1)
Max
Unit
2.0
Vdc
1.2
V |H
0.8
1,2
Vdc
V|L
Input Clamp Voltage
4
-1.2
Vdc
-1.5
V|
(VCC 4.75V ,l|-12m A )
2
100
HA
'OH
(VCC = 4.75 V ,V 0 H 30 V ,V m = 2.0 V)
SN75451BP, SN75453BP
(VCC 4.75 V, Vqh - 30 V. V |L - 0.8 V)
1
Vdc
Vo l
(VCC = 4.75 V .V |L 0.8 V)
SN75451 BP, SN75453BP
(Vcc 4.75 V ,V |H 2.0 V)
0.4
(IOL= 100 mA)
0.25
0.7
O L 300 mA)
0.5
3
>IH
(Vcc 5-25 V, V| - 2.4 V)
40
;*A
(Vcc - 5.25 V, V| 5.5 V)
1.0
mA
4
mA
-1.0
-1.6
'IL
(Vcc 5.25 V ,V | 0.4 V)
Power Supply Current - Output High Logic State
5
mA
'CCH
SN75451BP
(VCc * 5-25 V, V| - 5.0 V)
7.0
11
SN75452BP
(V CC = 5.25 V , V| * >
11
14
(VCC - 5.25 V. V| m5.0 V)
SN75453BP
8.0
11
SN75454BP
(VCC 5.25 V, V| -0 )
13
17
Power Supply Current - Output Low Logic State
5
mA
*CCL
SN75451BP
* _
(Vcc 5.25 V, V| 0)
52
65
SN75452BP
(V CC 5.25 V , V | = 5.0 V)
71
56
SN75453BP
(V CC 5.25 V, V | =0)
54
68
SN75454BP
(V CC 5.25 V , V | - 5.0 V)
79
61
(1) Typical Values Measured with Vcc 5-0 V, T/\ =* 25C.
TEST CIRCUITS
*
w-
(Current into terminal is shown as apositive value.

______ _
Arrow* indicate actual direction of current flow.)
___________
FIGURE 1 - V q l .
FIGURE 2 - Iqh,
V | h SN75452BP and SN75454BP
V|H -SN75451BP and SN75453BP
V|L - SN75451BP and SN754538P
V|[_ - SN75452BP and SN75454BP
VCc
VCc
SN75451 BP
SN754S4BP
Vqh
V|H Or V|i_
*Sm Page 1 fo r specific gate typ*.
5-148
Each in put Is tested separately.
SN75451 BP, SN75452BP, SN75453BP, SN75454BP
SWITCHING CHARACTERISTICS ( V c c - 5.0 V. T a +2SC unlew otherwise noted.)

Characteristic
Symbol Test Fig.
(lO 53200 mA. Cl 15 pF, Rl " 50 ohms)
SN75451BP
6
*PLH
PHL
SN75452BP
6
*PLH
tPHL
SN75453BP
6
PLH
PHL
SN754S4BP
6
tPLH
PHL
Transition Time
(l0 * 200 mA, Cl " 15 pF, RL " 50 ohms)
SN75451BP
6
*TLH
*THl
SN75452BP
6
*TLH
*THL
SN75453BP
6
*TLH
*THL
Min
Typ
Max
Unit
17
18
25
25
ns
18
16
35
35
ns
15
17
25
25
ns
25
19
35
35
ns
6.0
8.0
8.0
12
ns
6.0
9.0
8.0
12
ns
5.0
8.0
8.0
12
ns
5.0
8.0
8.0
12
ns
SN75454BP
TLH
*THL
High-to-Low-Level O utpu t
TEST CIRCUITS (Continued!

(Current in to terminal it shown at a positive value.
Arrow s indicate actual direction o f current flow .)
FIGURE 3 I | h
(A L L OEVICE TYPES)
IH
V CC
Open
_Q
FIGURE 4 I | l V j
(A L L DEVICE TYPES)
Each in put it tested separately.
FIGURE S - IcCH* *CCL

(A L L DEVICE TYPES)
Vcc
SN75451BP
SN7S4S2BP
SN7S453BP
SN7S454BP
So* page 1 fo r specific gate type.
Both gates are testod simultaneously.
5-149
SN75451BP, SN75452BP, SN75453BP, SN75454BP
FIGURE6 - SWITCHINGTIMESTESTCIRCUITANDWAVEFORMS
^10nt
y 90%
1.5 V
10%
SN75451 BP
SN754S2BP
90% ""
1.5V
10% 3
90%
1.5
SN76451 BP
and
SN7S4S3BP
A. Putio generator charocteriitics: tw * 0.5 lit,
PRR 1.0 MHz, 2q
SO l l
8. C l include* probe and t o il fixtu re capacitance.
O utput
All
Tvpe*
50%
10%

11/2 Circuits Shown)
5-150
THL
50% J
10% /
*T L H J
1 90%
VOH
Vo l
COMMUNICATION INTERFACE (Telephony)

Temperature Range
Commercial
Military
Page
MC3416
MC3417/
3418
MC3517/
3518
4 x 4 x 2 Crosspoint Switch..................................................... 6-3

Continuously-Variable-Slope Delta
Modulator/Demodulator ...................................................... 6-12
MC3419
MC3519*
Subscriber Loop Interface Circuit.............. .......................
industrial
0*3
6-30
MC3416
MOTOROLA

Inform ation
4 x 4 x 2 CROSSPOINT
SWITCH
4 x 4 x 2 C R O S S P O IN T S W ITC H
D IE L E C T R IC A L L Y IS O LA T E D
M O N O L IT H IC
The MC3416 consists o f a pair o f 4 x 4 matrices o f d ielectrically

isolated SCR's, triggered by a com m on selection m a trix. The device is
intended fo r switching analog signals in co m m unication systems. The
use o f d ielectric isolation processing provides excellent crosstalk
isolation w hile m aintaining m inim al insertion loss.
The selection array consists o f PNP transistors w ith the inp u t
L S U F F IX
CASE 6 23
thresholds com patible w ith either CMOS or T T L logic families.

The MC3416 is a m o n o lith ic pin-fo r-p in replacement fo r the
discontinued MCBH7601 h yb rid device.
Low Series Resistance ron = 6.0 Ohms (T yp) @ I a K = 20 m A
High Series Resistance r0 f f = 100 MJ2 (M in)
Pin C om patible w ith MCBH7601 or RC4444
High Breakdown Voltage 30 V (Typ)
Selection M a trix C om patible w ith T T L o r CMOS Logic Levels
D ielectric Isolation Insures Low Crosstalk and Low Insertion Loss
P S U F F IX
CASE 6 49
F IG U R E 1 - R E P R E S E N T A T IV E C E L L S C H E M A T IC
(Repeated 16 Times)
A n o d o A1
A no d e A 2
(B 1.C 1.D 1
are E q u iva le n t)
(B 2 .C 2.D 2
era E qu iva le nt)
R o w Select
W
(X .Y .Z are E qu iva le nt) o
Cathode
c roi
W1
SCR1
(X 1 ,Y 1 ,Z 1 are E qu iva le nt)
SCR2
D1 6
D2
C o lu m n Select A
(B .C .D are E qu iva le nt)
C athode W2
(X 2 .Y 2 .Z 2 are E quivalent)
F IG U R E 2 - M A T R IX C O N F IG U R A T IO N A N D N O M E N C L A T U R E
(X Indicates a Possible Connection)
A
B 'C o lu m n . c
12
12
12
Anodo
A1
Cathode
Y2
Row S alact
12
A ssociotod Pairs
Triggered
S im u lta n e o u ily
Cathode
22
C olum n
Sl#ct A
Colum n
SictO
Colum n
S # l*ct C
Z1
I
I ~
|______
r-T I
I ~
I
j "
I 7
/
/
o /
/
>
6-3
I Cathod*
1
X2
_ _ I How Select
ilJ
X
22 1 Cathod*
_____ 1
W2
2j ]
Anod#
------1
A2
_2"ol
An<Xl#
B1
AT
z i
Ar
z i Ar
------1 Anodo
D1
Z
l _
| ^
I
1 Calhodo
VI
I------
Anode
02
j
1___ __
W1
| R o w Salact
I Cathoda
13 1
V
15 I
C Athodo
I I
L_
I Z~
Colum n |
S il* c t D I
Cathodo I
R o w S l* c t
----------------- >
X1
MC3416
MAXIMUM RATINGS (Unless otherwise noted. T a " 25C)

Rating
Anodo-Cathode Current - Continuous
(only one SCR at a time) .
Enable Current
Symbol
'AK
'En
Ta
Tsta
Tj
Value
160
Unit
' mA.
10
0to+70
.mA
oc
-65 to +150
150C
C
C
ELECTRICAL CHARACTERISTICS (Unless otherwise noted, T a 0 to 70CI

Characteristic
Min
Max
Unit
b v Ak
25
Vdc
bvk a
25
Baia-Cothode Breakdown Voltage1

(lBK25fiA)
b v bk
25
Vdc
Cathode-Base Breakdown Voltage

(IKB "25fiA)
'' '
Basa-Emitter Breakdown Voltage
Ob e 25iA)
Emftter^Cathoda Breakdown Voltage
t*EK 2S#*Al
BVkb
25
Vdc
b vbe
25
Vdc
BVek
25
Vdc
OFF State Resistance

(V a k -1 0 V )
foff
100
MR
Dynamic ON Resistance
(Center Current * 10 mA) (See Figure 8)
(Center Current ** 20 mA)
ron
4.0
2.0
12
10
Holding Current
(See Figure 10)
'H
0.7
3.0
Enable Current
(VB 15 V) (See Figure 7)
'En
4.0
mA/mA
Symbol
Anode Cathode Breakdown Voltage

<IAK-25A)
Cathode-Anode-Breakdown Voltage *<KA 25mA)
Vdc
mA
mA
Anode-Cathode ON Voltage
(lAK 10 mA)
Oa k 20 mA)
VAK
Gate Sharing Current Ratio @Cathodes

(Under Select Conditions with Anodes Open) (See Figure 3)
Gsh
0.8
1.0
1-1
1.25
Inhibit Voltage
(VB 3.0 V) (See Figure 9)
Vjh
0.3
Inhibit Current
(VB - 3.0 V) (See Figure 9)
inh
0.1
mA
OFF State Capacitance

IVAK OVl 1See Figure6)
Coff
2.0
PF
Turn-ON Time
(See Figure 4)
on
1.0
MS
dv/dt
800
V/<IS
Minimum Voltage Ramp (Which Could Fire the SCR Under

Transient Conditions)
FIGURE 3 - TEST CIRCUIT

4.S m A
6-4
MC3416
FIGURE 4 - TEST CIRCUIT FOR dv/dt AND ton
O + io V
O V g Scope
O V g Scope
Tw o W ire
}> C ro u p o in t
Element
Under Test
0+6 V
O V j Scope
O +IO V
O V K Scope
FIGURE 6 - TEST WAVEFORMS FOR dv/dt AND Vtn
FIGURE 7 - ENABLE CURRENT

(Both SCR's Must Turn On)
FIGURE 8 - THE CROSSPOINT SCR

l-V CHARACTERISTIC ( Iq - 0)
FIGURE 9 - INHIBIT VOLTAGE AND INHIBIT

CURRENT (Both SCR'* Must Remain OFF)
FIGURE B- TEST CIRCUIT FOR OFF-STATE CAPACITANCE
Bln
0-0
High
L/C
Meter
Low
v lnh
10 V 3.3 V
Device
Under
Test
A ll Device Pin* Other Than Pint

Under T e n Are Connected to Tett
Equipment Qround Terminal
Three-Term inal, Guarded. Differential Capacitance Meter
6-5
l|n h
10'V
MC3416
FIGURE 11 - ANODE-CATHODE ON VOLTAGE versus
CURRENT AND TEMPERATURE
IH.HOLOING CURRENT (mA)
FIGURE 1 0 - HOLDING CURRENT versus

AMBIENT TEMPERATURE
FIGURE 12 - DIFFERENCE IN ANODE-CATHODE ON

VOLTAGE (Between Associate Pairs of SCR's)
versus ANODE-CATHODE CURRENT
FIGURE 13 - OFF-STATE CAPACITANCE versus ANODECATHODE VOLTAGE
VOLTAGE (mV)
i80
140
120
4.0
6:0
8.0
10
12
14
16
18
20
IAK. AN00E CATH00E CURRENT (mA)
FIGURE 14 - DYNAMIC ON RESISTANCE versus ANODECATHODE CURRENT
FIGURE 15 - DYNAMIC ON RESISTANCE versus

AMBIENT TEMPERATURE
ron.OYNAMIC RESISTANCE (OHMS)
1\K 10 mA
I;\ K * W
S 4.0
2.0
-10
10
20
30
40
50
60
6-6
70
SO
SO
MC3416
FIGURE 17 - CROSSTALK vwsus SIGNAL FREQUENCY
FEEDTHROUGH (dB)
FIGURE 16 - FEEDTHROUGH vmw* SIGNAL FREQUENCY
SIGNAL FREQUENCY IkHi)
FIGURE 18 - TEST CIRCUIT FOR FEEDTHROUGH versus FREQUENCY
FIGURE 19 - TEST CIRCUIT FOR CROSSTALK versus FREQUENCY
6-7
2
O
to
O)
Anode
A1
0
Row Select W ,
Anode Anode
A2
B1
21
13 ------------Cathode
XI
-------------
Row Select Z
jj7
16
12
s .
1 1 Cathode
Y1
18
11
Cathode
W2
X2
Y2
9 -------------Z1
Column
Select
A
Column
Seloct
B
Column
Select
C
Column
Select
D
Z2
4
FIGURE 20 - REPRESENTATIVE SCHEMATIC OIAGRAM
23 -------------
19
Anode
02
Row Select X ,
20
Anode Anode
C2
D1
r Ifif
r !UXJf
"*1
r >
* alr Ip
1- VaU
* A.r
s.?1:- i f 1- r T*aU
:
D
15 ------------- i
W1
Anode Anode
B2
Cl
MC3416
TELEPHONE APPLICATION OF THE CROSSPOINT SWITCH

The MC3416 crosspoint switch Is designed to provide
a low-loss analog switching element for telephony signals.
It can be addressed and controlled from standard binary
decoders and is CMOS compatible. With proper system
organization the MC3416 can significantly reduce the size
and cost of existing crosspoint matrices.
tained through the SCR to retain an ac signal path. This

requires that each subscriber-input to the array be capable
of sourcing dc current as well as its ac signal. With each
subscriber acting as a dc source, each trunk output then
acts as a current sink. The instrument-to-trunk connection
in Figure 21 shows this configuration. However, with each
subscriber acting as a dc source, some method of inter
connecting them without a trunk must be provided. Such
a local or intercom termination is shown in Figure 22.
Here both subscribers source dc current and exchange ac
signals. The central current sink accepts current from both
subscriberswhile the high output impedance of the current
sink does not disturb the system.
These configurations are system compatible. The dc
SIGNAL PATH CONSIDERATIONS

The MC3416 is a balanced 4 x 4 2-wire crosspoint array.
It is ideal for balanced transmission systems, but may be
applied effectively in a number of single ended applications.
Multiple chips may be interconnected to form larger crosspoint arrays. The major design constraint in using SCR
crosspoints is that a forward dc current must be main
FIGURE 21 - INSTRUMENT-TO-TRUNK CONNECTION
FIGURE 22 -TYPICAL INSTRUMENT TO INSTRUMENT CONNECTION
6-9
MC3416
current restriction is not a restriction in the design of

an efficient crosspoint array. Because of the current sink
terminations, a signal path may use differing numbers of
crosspoints in any connection or in two sides of the same
connection further relaxing restrictions in array design.
Figure 23 demonstrates circuit operation. S1, S2, and
S3 are open. The Crosspoint SCR's are off as they have no
gate drive or dc current path through S I. By closing S2 and
S3, gate drive is provided, but the SCR's still remain off as
there is no dc current path to hold them on. Close St and
the circuit is enabled, but with S2 and S3 off there is still
no signal path. Closing S2 and S3 with SI closed - current
is injected into both gates and they switch on. DC current
through Rj_ splits around the center-tapped winding and
flows through each SCR, back through the lower winding
and through SI to ground. If S2 and S3 are opened, that
current path still remains and the SCRs remain on. If an ac
signal is injected at either G1 or G2, it will be transmitted
to the other signal port with negligible loss in the SCR's. To
disconnect the ac signal path the SCR's must be com
mutated off. By opening S1 the dc current path is inter
rupted and the SCR's switch off. The ac signal path is dis
connected. With S1 closed the circuit is enabled and may
be addressed again from S2. and S3. This circuit demon
strates a balanced transmission configuration. The trans
mission characteristics of the SCR's simulate a relay con
tact in that the ac signal does not incur a contact voltage
drop across the crosspoint. The memory characteristics of
the crosspoint are demonstrated by the selective application
of S I, S2, and S3.
The selection of R|_ is governed by the power supply
voltage and the desired dc current. If 10 mA is to flow
through each SCR then R|_ must pass 20 mA. Thus,
(V c c - V a k )/R L 20 mA. The selection of Rp is governed
by the characteristics for crosspoint turn on. Adequate
enable current must be injected into the column select
and Rp should drop at least 1.5 Volts. The PNP transistor
has a typical gain of one. Thus, Rp should pass at least
2 mA to provide 4 mA column select current.
FIGURE 23CROSSPOINT OPERATION

DEMONSTRATION CIRCUIT
02
SI
ON
ON
ON
ON
OFF
S2
X
OFF
ON
X
X
S3
OFF
X
ON
X
X
LINE CONDITION
Enabled, Not Connected
Enabled, Not Connected
Addressed end Connected
G1 Connected to G2
' Disconnected.
X = irrelevant
ADDRESSING CONSIDERATIONS
The gate current required for SCR turn on is 1 mA typically.

The CMOS one-of-n decoders listed in Table I provide
both active high and active low outputs and are well suited
for standard addressing organizations. The major design
constraint in organizing the addressing structure is that
any signal path which is to be addressed must create a dc
path from a source to a sink. If that path requires two
crosspoints they must be addressed simultaneously. Of
course, once the path is selected, the addressing hardware
is free to initiate other signal paths. To meet the dc path
The MC3416 crosspoint switch is addressed by selecting

and turning on the PNP transistor that controls the SCR
pair desired. The drive requirements of the MC3416 can be
met with standard CMOS outputs. A particular crosspoint
is addressed by putting a logical "1 " on the emitter and a
logical "0" on the base of the appropriate transistor. A
resistor in the base circuit of the transistor is required to
limit the current and must also drop 1.6 Volts to assure
forward bias of the two diodes in the collector circuits.
6-10
MC3416

requirement, crosspoint arrays should be designed in blocks
such that any given dc path requires only one crosspoint
per block. A signal path, however, may still use two crosspoints in the same block by sequentially addressing two
dc paths to the same terminator. For example, the left or
right pairs of crosspoints in Figure 22 must be addressed
simultaneously but the left pair may be addressed in
sequence after addressing the right pair. This is not a
difficult constraint to meet and it does not require unneces
sary addressing hardware.
TABLE I
Active High Output*
MCI4655
Dual Binary to 1 of 4
MC14514
4-bit latch/4 to 16
MC14028
BCD to Decimal Decode
Active Low Outputs

MC14556
MC14S15
DISCONNECT TECHNIQUES
Since the crosspoint switch maintains signal paths by
keeping dc currents through active SCR's, disconnects are
easily accomplished by interrupting the dc current path.
This can be done anywhere in the circuit, but if the dis
connect is done at the terminator then all signal paths
established to that terminator are broken simultaneously.
In both Figures 21 and 22 this is done by turning off the
current sink circuit with a CMOS buffer gate. MC14049
or MC14050 buffers will drive the transistor switch. Once
a disconnect is completed, the terminator may be re-enabled
and used for another call. Usage of the terminators may be
easily monitored with optoelectronic couplers in the
collectors o f the current sinks without disturbing trans
mission characteristics.
See Application Note AN-760 for additional applications suggestions.
MC3417, MC3517
MC341S, MC3518
MOTOROLA
S p e c ific a tio n s a n d A p p lic a tio n s

In fo r m a tio ii
CONTINUOUSLY VARIABLE
SLOPE DELTA
MODULATOR/DEMODULATOR
LASER-TRIMMED
INTEGRATED CIRCUIT
CONTINUOUSLY VARIABLE SLOPE

DELTA MODULATOR/DEMODULATOR
Providing a .simplified approach to digital speech encoding/
decoding, the MC3517/18 series of CVSDs is designed for military
secure communication and commercial telephone applications.
A single IC provides both encoding and decoding functions.
Encode and Decode Functions on the Same Chip with

a Digital Input for Selection
Utilization of Compatible |2|_ Linear Bipolar Technology
CMOS Compatible Digital Output
Digital Input Threshold Selectable (V cc /2 reference

provided on chip)
L SUFFIX
CERAMIC PACKAGE
CASE 620
MC3417/MC3517 has a 3-Bit Algorithm (General

Communications)
MC3418/MC3518 has a 4-Bit Algorithm (Commercial Telephone)
PIN CONNECTIONS
Analog j ^
Input I-----Analog I
Foodback I
Syllabic I
Filter I
C a in r
C o n tro l I
Ref I------Input () I 8
Filter i-----Input l - l l 8
I Digital Data
_ I J Input I-)
Digital
_1_JThreshold
1Coincidence
I On In in
1 7 1 Vcc/2
I O utput
~| Digital
J O utput
6-12
MC3417, MC3418, MC3517, MC3518
MAXIMUM RATINGS
(All voltages referenced to Vgg, T /\ 25C unless otherwise noted.)
Rating
Power Supply Voltsge
Differential Analog Input Voltage
Digital Threshold Voltage
Logic Input Voltage
(Clock, Digital Data, Encode/Decode)
Coincidence Output Voltage
Symbol
Value
Unit
VCC
V |D
-0 .4 t o +18
t5.0
Vdc
Vdc
VTH
-0 .4 to Vcc
-0 .4 to +18
Vdc
Vdc
-0 .4 to +18
-0 .4 to Vcc
Vdc
Vdc
V Logic
Vo<Con)
Syllabic Filter Input Voltage
V|(Syl)
Gain Control Input Voltage
-0 .4 to Vcc
V I(GC)
V|(Ref) V c c /2 - 1.0 to Vcc
-2 5
'Rof
Reference Input Voltage

V q q /7 Output Current
Vdc
Vdc
mA
(VCC 12 V, V EE - Gnd, TA - 0C to +70C for MC3417/18, T a -55C to +125C for MC3517/18 unless otherwise noted.)
MC3417/MC3517
Characteristic
Power Supply Voltage Range (Figure 1)
Power Supply Current (Figure 1)
(Idle Channel)
(VCc - 5j0 V)
(VCC 15 V)
MC3418/MC3518
Symbol
Min
Typ
Max
Min
VCCR
4.75
12
165
4.75
Typ
12
Max
Unit
165
Vdc
mA
ice
-
3.7
6.0
16k
5.0
10
3.7
6.0
5.0
10
SR
32 k
>GCR
V|
0.001
3.0
3.0
1.3
VCC ~ 1-3
0.001
1.3
VCC " 1 5
mA
Vdc
Analog Output Range (Pin 7)

(4.75 V < V c c < .185 V. I0 5.0 mA)
input Bias Currents (Figure 3)
(Comparator in Active Region)
Analog Input (11)
Analog Feedback (12)
Syllabic Fitter Input (13)
Reference Input (15)
v0
1.3
VCC - 1-3
1.3
V CC -1 -3
Vdc
Input Offset Current

(Comparator in Active Region)
Analog Input/Analog Feedback
111 -121 - Figure 3
Integrator Amplifier
115-161 - Figure 4
>10
Input Offset Voltage

V /l Converter (Pins 3 and 4) Figure 5
V |0
Transconductance
V /l Converter, 0 to 3.0 mA
Integrator Amplifier, 0 to t SjO mA Load
gm
Clock Rate
Gain Control Current Range (Figure 2)
Analog Comparator Input Range
(Pins 1 and 2)
(4.75 V < V c c < 165 V)
Propagation Delay Times (Note 1)

Clock Trigger to Digital Output
(Cl 25 pF to Gnd)
Clock Trigger to Coincidence Output
(Cl " 25 pF to Gnd)
(R l 4 kfl to Vcc)
Coincidence Output Voltage
Low Logic State
('OL(Con) " 3 0 mA)
Coincidence Output Leakage Current
High Logic State
(v 0 h - i5X> v , o c < t a < 7oc)
Samples/s
#*A
Mb
0.5
05
0.06
-0.06
15
15
05
-0 5
0.25
0.25
0.06
-0.06
1.0
1.0
05
-0 .3
#*A
0.15
0.6
0.05
0.4
0.02
02
0.01
0.1
2.0
6.0
2.0
6.0
0.1
0.3
10
0.1
05
10
1.0
05
1.0
05
25
25
3.0
2.0
1.0
05
1.0
05
2.5
2.5
3.0
2.0
VoL(Con)
0.12
0.25
0.12
0.25
Vdc
'OH(Con)
0.01
0.5
0.01
05
mA
mA/mV
1J0
*PLH
tPHL
tPLH
1PHL
mV
1.0
nt
NOTE 1. All propagation delay times measured 50% to 50% from the negative going (from V cc ,0 +0-4 V)
6-13
of the clock.
MC3417, MC3418, MC3517, MC3518
ELECTRICAL CHARACTERISTICS (continued)

MC3417/MC3517
Symbol
Min
Applied Digital Threshold Voltage Range

(Pin 12)
VT H
+ 1.2
Digital Threshold Input Current

(1 .2 V C Vth < V c c - 2 .0 V)
(V||_ applied to Pins 13,14 and 15)
(V| h applied to Pins 13,14 and 15)
Maximum Integrator AmplifierOutputCurrent
'l(th)
*GC 12.0 mA. Vcc 5.0 V

TA 25C
0C < Ta < +70C
MC3417/18
-55C < TA < +125C MC3517/18

(V|L - 0 V )
Digital Data Input Clock Input
Encode/Decode Input
Clock Input, V | l 0 4 V
Min
+ 15
Typ
-
Max
Unit
VCC - 2 -0
Vdc
-1 0
5.0
5.0
-5 0
_
+ 10
-1 0
-
3.0
6.0
3.0
6.0
3.5
3.5
Gnd
V ,h + 0.4
V th -0 .4
18.0
Gnd
V1h+0.4
V t h - 0 .4
18.0
5.0
5.0
-5 0
--
+ 10
mA
mA
Vdc
-
mV
0.5
0.75
1.5
IS
2.3
i 4.0
i 2.5
3.0
i4.5
5.0
7.5
10
_
_
_
_
_
_
_
1.0
1.3
2.5
i 4.0
i 4.5
55
6.0
8.0
10
_
_
_
_
-
(GC 33-0
v c c " 5-0 V
TA - 25C
0C < TA < + 70C
MC3417/18
-55C < TA < +125C MC3517/18
MC3418/MC3518
Max ,
fiA
>0
Vcc/2 Generator Maximum Output Current
>Ref
(Source only)
Vcc/2 Generator Output Impedance
zRef
(0 to +10 mA)
Vcc/2 Generator Tolerance
r
(4.75 V < V c c < 16 5 V)
Logic Input Voltage (Pins 13,14 and 15)
Low Logic State
VlL
High Logic State
V|H
Dynamic Total Loop Offset Voltage
EVoffset
(Note 2) Figures 3 ,4 and 5
iG C 12 .o>ia, v c c - i 2 v
TA 25C
0C < TA < + 70C
MC3417/18
-55C < TA < +125C MC3517/18
IqC " 33.0 uA, Vcc 12 V
TA - 25C
0C < TA < +70C
MC3417/18
-55C < TA < +125C MC3517/18
_
_
2.0
2.8
5.0
t
Vdc
vol
v OH
v HSyl)
0.1
V c c - 1 0 Vcc - 0.2
+3.2
0.1
0.4
-
Vcc
V cc 1-0
+3.2
<
o
o
1
o
ro
Digital Output Voltage

(lOL 3.6 mA)
(lOH -0.35 mA)
Syllabic Filter Applied Voltage (Pin 3)
(Figure 2)
Integrating Current (Figure 2)
(lGC " 12.0/iA)
(lQ C 1-SmA)
(I q c 3-0 mA)
Dynamic Integrating Current Match
(IQC 1-6 mA) Figure 6
<V|H - 18 V)
Digital Data Input
Clock Input
Encode/Decode Input
Typ
-
<
o
o
1
ro
b
Characteristic
Vcc
Vdc
8.0
1.45
2.75
_
10
ISO
3.0
100
12
1S5
3.25
#iA
mA
mA
mV
0.4
-
Hint*
v O(Ave)
8.0
1.45
2.75
-
10
1.50
3.0
i 100
12
1.55
3.25
250
_
-
+5.0
+5.0
+5.0
-1 0
-360
-3 6
-7 2
250
tiA
iH
_
+5.0
+5.0
+5.0
mA
iL
-1 0
-360
-3 6
-7 2
NOTE 2. Dynamic total loop offset (EVoffje,) equals V jq (comparator) (Figure 3) minus V | q x (Figure 5). The input offset voltages of the
analog comparator and of the integrator amplifier include the effects of input offset current through the input resistors. The slope
polarity switch current mismatch appears as an average voltage across the 10 k integrator resistor. For the MC3417/MC3517. the
dock frequency is 16.0 kHz. For the MC3418/MC3518, the clock frequency is 32.0 kHz. Idle channel performance is guaranteed if
this dynamic total loop offset is less than one-half of the change in integrator output voltage during one clock cycle (ramp step size).
Laser trimming is used to insure good idle channel performance.
6-14
MC3417, MC3418, MC3517, MC3518
DEFINITIO NS AND FUNCTION OF PINS

Pin 1 Analog Input
This is the analog comparator inverting input where
the voice signal is applied. It may be ac or dc coupled
depending on the application. If the voice signal is to be
level shifted to the internal reference voltage, then a bias
( l| nt) flows into pin 6 when the analog input (pin 1) is

high with respect to the analog feedback (pin 2) in the
encode mode or when the digital data input (pin 13) is
high in the decode mode. For the opposite states, l | nt
flows out o f Pin 6. Single integration systems require a
resistor between pins 1 and 10 is used. The resistor
capacitor and resistor between pins 6 and 7. Multipole
is used to establish the reference as the new dc average of

the ac coupled signal. The analog comparator was designed
configurations will have different circuitry. The resistance

between pins 6 and 7 should always be between 8 k2 and
for low hysteresis (typically less than 0.1 m V ) and high
13 k2 to maintain good idle channel characteristics.
gain (typically 70 dB).

Pin 7 Analog Output
Pin 2 Analog Feedback
This is the non-inverting input to the analog signal
comparator within the IC. In an encoder application it
should be connected to the analog output o f the encoder
circuit. This may be pin 7 or a low pass filter output
This is the integrator op amp output. It is capable of

driving a 600-ohm load referenced to V c c /2 to + 6 dBm
and can otherwise be treated as an op amp output. Pins 5,
6, and 7 provide full access to the integrator op amp
for designing integration filter networks. The slew rate
connected to pin 7. In a decode circuit pin 2 is not used
of
and may be tied to V q c / 2 on pin 10, ground or left open.
typically 0.5 V/fis. Pin 7 output is current limited for

both polarities of current flow at typically 30 m A.
The analog input comparator has bias currents of

1.5 |iA max, thus the driving impedances of pins 1 and 2
should be equal to avoid disturbing the idle channel
characteristics o f the encoder.
Pin 3 Syllabic Filter
This is the point at which the syllabic filter voltage is
returned to the IC in order to control the integrator step
size. It is an NPN input to an op amp. The syllabic filter
consists o f an RC network between pins 11 and 3. Typical
time constant values of 6 ms to 50 ms are used in voice
codecs.
Pin 4 Gain Control Input

The syllabic filter voltage appears across Cs of the
syllabic filter and is the voltage between V c c ancl P'n 3.
The active voltage to current ( V - l ) converter drives
pin 4 to the same voltage at a slew rate of typically
0.5 V/ps. Thus the current injected into pin 4 O g c)
is the syllabic filter voltage divided by the Rx resistance.
Figure 6 shows the relationship between Ig c (x-axis) and
the integrating current, l | nt (V-axis). The discrepancy,
which is most significant at very low currents, is due to
circuitry within the slope polarity switch which enables
trimming to a low total loop offset. The Rx resistor is
then varied to adjust the loop gain of the codec, but
should be no larger than 5.0 k f l to maintain stability.
the internally compensated integrator, op amp is
Pin 8 V g
The circuit is designed to work in either single or dual
power supply applications. Pin 8 is always connected to
the most negative supply.
Pin 9 Digital Output
The digital output provides the results o f the delta
modulator's conversion.
It swings between V c c
anc*
V e e ant* <s CMOS or T T L compatible. Pin 9 is inverting

with respect to pin 1 and non-inverting with respect
to pin 2. It is clocked on the falling edge of pin 14.
The typical 10% to 90% rise and fall times are 2 50 ns and
50 ns respectively for V c c = 12 V and C l = 25 pF
to ground.
Pin 10 V c c /2 Output
An internal low impedance mid-supply reference is
provided for use of the M C 3417/18 in single supply
applications. The internal regulator is a current source
and must be loaded with a resistor to insure its sinking
capability. If a + 6 dBmo signal is expected across a
6 00 ohm input bias resistor, then pin 10 must sink
2.2 V /6 0 0 SI - 3.66 m A. This is only possible if pin 10
sources 3.66 m A into a resistor normally and will source
only the difference under peak load. The reference load
resistor is chosen accordingly. A 0.1 /jF bypass capacitor
Pin 5 Reference Input

This pin is the non-inverting input o f the integrator
amplifier. It is used to reference the dc level o f the output
signal. In an encoder circuit it must reference the same
voltage as pin 1 and is tied to pin 10.
from pin 10 to V E *s a'so recommended. The V c c /2

reference is capable o f sourcing 10 m A and can be used
as a reference elsewhere in the system circuitry.
Pin 11 Coincidence Output
The duty cycle o f this pin is proportional to the
Pin 6 Filter Input

This inverting op amp input is used to connect the
voltage across Cs- The coincidence output will be low

whenever the content o f the internal shift register is all
integrator external components. The integrating current
1s or all 0s. In the M C3417 the register is 3 bits long
MC3417, MC3418, MC3517, MC3518
DEFINITIONS AND FUNCTIONS OF PINS (continued)

while the M C3418 contains a 4 bit register. Pin 11 is an
open collector of an NPN device and requires a pull-up
can be transmitted. The digital data input level should be
resistor. If the syllabic filter is to have equal charge and
for proper clocking.
maintained for 0.5 jus before and after the clock trigger
discharge tim e constants, the value o f Rp should be

Pin 14 Clock Input
much less than Rs> In systems requiring different charge

and discharge constants, the charging constant is RsCs
The clock input determines the data rate <$ the codec
circuit. A 32K bit rate requires a 3 2 kH z clock. The
while the decaying constant is (R s + RplCs- Thus longer

decays are easily achievable. The NPN device should not
switching threshold of the clock input is set by pin 12.
100 ns respectively for R|_ = 4 k2 to + 1 2 V and C l

25 pF to ground.
The shift register circuit toggles on the falling edge o f the

clock input. The minimum width for a positive-going
pulse on the clock input is 3 00 ns, whereas for a negativegoing pulse, it is 9 00 ns.
Pin 12 Digital Threshold
Pin 15 Encode/Decode
be required to sink more than 3 m A in any configuration.

The typical 10% to 90% rise and fall times are 200 ns and
This pin controls the connection o f the analog input
This input sets the switching threshold for pins 1 3 ,1 4 ,

and 15. It is intended to aid in interfacing different logic
families without external parts. Often it is connected to
comparator and the digital
input comparator to the
the V c c /2 reference for CMOS interface or can be biased

tw o diode drops above V g g for T T L interface:
comparison will be clocked into the register on the

falling edge at pin 14. If low, the digital input state will be
internal shift register. If high, the result o f the analog
entered. This allows use of the 1C as an encoder/decoder

Pin 13 Digital Data Input
or simplex codec without external parts. Fur&erm ore, it

allows non-voice patterns to be forced onto the trans
mission line through pin 13 in an encoder.
In a decode application, the digital data stream is

applied to pin 13. In an encoder it may be unused or may
be used to transmit signaling message under the con
trol of pin 15. It is an inverting input with respect to
pin 9. When pins 9 and 13 are connected, a toggle
flip-flop is formed and a forced idle channel pattern
Pin 16 V c c
The power supply range is from 4 .7 5 to 16.5 volts
between pin V c c ad VEE-
FIGURE 2 - Iq c R- GAIN CONTROL RANGE and

int ~ INTEGRATING CURRENT
FIGURE 1 - POWER SUPPLY CURRENT
,QC
v cc
R, < 5 k
JL JL
1
2
IS
14
3
g
J
0.0S
I oi ^
16
CVSD
M C 3 S 17
M C 3 5 18
13
( D ig ita l
D a ta In p u t
12
11
10
: 0 . 1 * iF
^
D ig ita l
O u tp u t
N o te : D ig ita l O u t p u t - D ig ita l D a ta In p u t
Fo r sta tic to ttin g , tho d o c k it o n ly nee o ttary fo r
p re c o n d itio n in g to o b ta in p ro p a r tta ta f o r a given in p u t.
6-16
MC3417, MC3418, MC3517, MC3518
FIGURE 3 - INPUT BIAS CURRENTS, ANALOG

COMPARATOR OFFSET VOLTAGE AND CURRENT
FIGURE 4 - INTEGRATOR AMPLIFIER OFFSET

VOLTAGE AND CURRENT
Vc c
u- JL JL 4:
5 1 I s
v IO (co m p arato r)
+ .0-
12, k
SO R 1V
16
113
1W
1=fc
0.01^
15
3
14
4
l E 10 k l
CVSO
M C 3 5 17
M C 3 5 18
13
12
11
0.0S flF JT
10
0 .1
mF
N o te : T h o analo g co m p a ra to r o ffse t vo ltag a l i tested

u n d e r d y n a m ic c o n d itio n s and thoroforo m ust
be m easured w ith a p p ro p ria te filte rin g .
FIGURE 5 - V /l CONVERTER OFFSET VOLTAGE,

FIGURE 6 - DYNAMIC INTEGRATING CURRENT MATCH
V |o a n d V |o x
V CC
* 3 2 k H z M C 3 4 18 /M C 3 S 18
16 kH z M C 3 4 17 /M C 3 5 17
JL JL'i
o l I r
VCC
16
16
16
15
14
5
4
0.1
6
V lO X
+
(In te g ra to r _
A m p lif ie r
O ffse t
V o lta g e
p lu s S lo p e
P o la r it y
S w itc h
oM lsm atch ) -
0 .0 5
ftF
CVSO
M C 3 S 17
M C 3 5 18
14
3
4
CVSO
M C 3 5 17
M C 3 5 18
13
12
13
12
11
10
11
10
* 3 2 k H l M C 3 4 18 /M C 3 S 18
16 kH z M C 3 4 17 /M C 3 5 17
N o te s: 1 . V 0( a v ) > D y n a m ic In te g ratin g C u r re n t M atch .
is tho averago vo ltage o f tho tria n g u la r w ave
fo rm observod at tho m easu re m e nt p o in ts ,
ecros* 1 0 k f l re sisto r w ith I q c 1 . 5 m A .
2 . S e e N o to 2 o f tho E le c t r ic a l C h a ra c te ris tic s ,
page 3 .
N o te : V i o x th * everage vo ltag e o f th e tria n g u la r

w a ve fo rm o bse rved at th e m e asu re m e n t p o in ts .
6-17
vo(AV). NORMALIZED DYNAMIC

INTEGRATING CURRENT MATCH (mV)
6-18
SV0| f t. DYNAMIC TOTAL LOOPOFFSET (fl)V|
MC3417, MC3418, MC3517, MC3518
FIGURE 12 - CVSD WAVEFORMS
FIGURE 13 - BLOCK DIAGRAM OF THE CVSD DECODER
Clock
MC3417, MC3418, MC3517, MC3518
FIGURE 1 4 - 1 6 k H i SIMPLEX VOICE CODEC

(Uting MC3417, Single Polo Companding and Singla Integration)
CIRCUIT DESCRIPTION
The continuously variable slope delta modulator
(CVSD) is a simple alternative to more complex conven
sign of the difference between the input voltage and

the integrator output. That sign bit is the digital output
and also controls the direction of ramp in the integrator.
The comparator is normally clocked so as to produce
tional conversion techniques in systems requiring digital

communication of analog signals. The human voice is
analog, but digital transmission o f any signal over great
distance is attractive^ Signal/noise ratios do not vary with
distance in digital transmission and multiplexing,
a synchronous and band limited digital bit stream.

If the clocked serial bit stream is transmitted,
received, and delivered to a similar integrator at a remote
switching and repeating hardware is more economical and

easier to design. However, instrumentation A to D con
point, the remote integrator output is a copy o f the

transmitting control
verters do not meet the communications requirements.

The CVSD A to D is well suited to the requirements of
digital communications and is an economically efficient
loop
integrator output. To the
extent that the integrator at the transmitting locations

tracks the input signal, the remote receiver reproduces
the input signal. Low pass filtering at the receiver output
will eliminate most o f the quantizing noise, if the clock
rate o f the bit stream is an octave or more above the
bandwidth o f the input signal. Voice bandwidth is 4 kHz
and clock rates from 8 k and up are possible. Thus the
delta modulator digitizes and transmits the analog input
to a remote receiver. The serial, unframed nature o f the
data is ideal for communications networks. With no
means o f digitizing analog inputs for transmission.

The Delta Modulator
The innermost control loop o f a CVSD converter is
a simple delta modulator. A block diagram CVSD Encoder
is shown in Figure 11. A delta modulator consists o f a
comparator in the forward path and an integrator in
the feedback path o f a simple control loop. The inputs
input at the transmitter, a continuous one zero alternation

is transmitted. If the tw o integrators are made leaky, then
during any loss of contact the receiver output decays to
to the comparator are the input analog signal and the

integrator output. The comparator output reflects the
6 -2 0
MC3417, MC3418, MC3517, MC3518
CIRCUIT DESCRIPTION (continued)

zero and receive restart begins without framing when the
if it contains all Is or Os. This condition is called coinci

dence. When it occurs, it indicates that the gain of the
integrator is too small. The coincidence output charges
receiver reacquires. Similarly a delta modulator is tolerant

of sporadic bit errors. Figure 12 shows the delta modu
lator waveforms while Figure 13 shows the corresponding
CVSD decoder block diagram.
a single pole low pass filter. The voltage output of this

syllabic filter controls the integrator gain through a pulse
amplitude modulator whose other input is the sign bit
or up/down control.
The Companding Algorithm

The fundamental advantages o f the delta modulator
are its simplicity and the serial format of its output.
The simplicity o f the all ones, all zeros algorithm
Its limitations are its ability to accurately convert the
should not be taken lightly. Many other control algo

rithms using the shift register have been tried. The key to
input within a limited digital bit rate. The analog input

must be band limited and amplitude limited. The fre
the accepted algorithm is that it provides a measure of

the average power or level o f the input signal. Other
quency limitations are governed by the nyquist rate while

the amplitude capabilities are set by the gain o f the
integrator.
techniques provide more instantaneous information

about the shape of the input curve. The purpose of
the algorithm is to control the gain o f the integrator
The frequency limits are bounded on the upper end;
and to increase the dynamic range. Thus a measure of

the average input level is what is needed.
that is, for any input bandwidth there exists a clock

frequency larger than that bandwidth which will trans
The algorithm is repeated in the receiver and thus
mit the signal with a specific noise level. However, the
the level data is recovered in the receiver. Because the

algorithm only operates on the past serial data, it changes
the nature o f the bit stream w ithout changing the channel
amplitude limits are bounded on both upper and lower

ends. For a signal level, one specific gain will achieve an
optimum noise level. Unfortunately, the basic delta
bit rate.
The effect o f the algorithm is to compand the input
signal. If a CVSD encoder is played into a basic delta
modulator has a small dynamic range over which the

noise level is constant.
The continuously variable slope circuitry provides
modulator, the output o f the delta modulator will reflect

the shape o f the input signal but all o f the output will
be at an equal level. Thus the algorithm at the output is
needed to restore the level variations. The bit stream
in the channel is as if it were from a standard delta modu
increased dynamic range by adjusting the gain of the

integrator. For a given clock frequency and input
bandwidth the additional circuitry increases the delta
modulator's dynamic range. External to the basic
delta modulator is an algorithm which monitors the
lator with a constant level input.

The delta modulator encoder with the CVSD algorithm
past few outputs o f the delta modulator in a simple

shift register. The register is 3 or 4 bits long depending on
the application. The accepted CVSD algorithm simply
monitors the contents of the shift register and indicates
provides an efficient method for digitizing a voice input

in a manner which is especially convenient for digital
communciations requirements.
CVSD DESIGN C O N SID ERA TIO N S
o
A simple CVSD encoder using the M C 3417 or MC3418
is shown in Figure 14. These ICs are general purpose
2. Required number of shift register bits

3. Selection of loop gain
CVSD building blocks which allow the system designer

to tailor the encoder's transmission characteristics to the
application. Thus, the achievable transmission capabilities
are constrained by the fundamental limitations o f delta
modulation and the design of encoder parameters. The
performance is not dictated by the internal configuration
of the M C3417 and M C3418. There are seven design
considerations involved in designing these basic CVSD
4. Selection of minimum step size

5. Design of integration filter transfer function
6. Design o f syllabic filter transfer function
7. Design of low pass filter at the receiver
The circuit in Figure 14 is the most basic CVSD circuit
possible. For many applications in secure radio or other
intelligible voice channel requirements, it is entirely
sufficient. In this circuit, items 5 and 6 are reduced to
their simplest form. The syllabic and integration filters
building blocks into a specific codec application.

These are listed below:
1. Selection of clock rate
are both single pole networks. The selection o f items

1 through 4 govern the codec performance.
6 -2 1
MC3417, MC3418, MC3517, MC3518
CVSD CIRCUIT SCHEMATIC
6-22
MC3417, MC3418, MC3517, MC3518
CVSD DESIGN CONSIDERATIONS (continued)

Layout Considerations
Selection o f Loop Gain

The gain of the circuit in Figure 14 is set by resistor
Care should be exercised to isolate all digital signal

paths (pins 9, 11, 13, and 14) from analog signal paths
Rx. Rx must be selected to provide the proper integrator

step size for high level signals such that the companding
(pins 1 - 7 and 10) in order to achieve proper idle channel

performance.
ratio does not exceed about 25%. The companding ratio

is* the active low duty cycle of the coincidence output on
Clock Rate
pin 11 of the codec circuit. Thus the system gain is

dependent on:
With minor modifications the circuit in Figure 14

may be operated anywhere from 9.6 kHz to 64 kHz
1. The maximum level and frequency o f the input
clock rates. Obviously the higher the clock rate the higher
signal.
2. The transfer function of the integration filter.
the S/N performance. The circuit in Figure 14 typically

produces the S/N performance shown in Figure 15.
For voice codecs the typical input signal is taken to be

a sine wave at 1 kHz o f 0 dBmo level. In practice, the
The selection of clock rate is usually dictated by the

bandwidth of the transmission medium. Voice band
useful dynamic range extends about 6 dB above the design
width systems'will require no higher than 9600 Hz.
level. In any system the companding ratio should not
Some radio systems will allow 12 kHz. Private 4-wire

telephone systems are often operated at 1 6 'kHz and
exceed 30%.
To calculate the required step size current, we must
describe the transfer characteristics of the integration
filter. In the basic circuit o f Figure 14, a single pole of
160 Hz is used.
commercial telephone performance can be achieved

at 32K bits and above. Other codecs may use bit rates
up to 200K bits/sec.
R = l O k f i, C = 0 .1 /j F
FIGURE IS - SIGNAL-TONOISE PERFORMANCE

OF MC3417 WITH SINGLE INTEGRATION, SINGLE-POLE
AND COMPANDING AT 16K BITS - TYPICAL
Vq _
I; C ( S + 1 / R C )
c jq
S +
cj0
= 2nf
1 0 3 = w 0 = 2 jrf
f
1 5 9 .2
Hz
Note that the integration filter produces a single-pole

response from 300 to 3 kHz. The current required to
move the integrator output a specific voltage from zero
is simply:
V
CdV 0
l i R+
dt
Now a 0 dBmo sine wave has a peak value of 1.0954

volts. In 1/8 o f a cycle o f a sine wave centered around
the zero crossing, the sine wave changes by approximately
its peak value. The CVSD step should trace that change. The required current for a 0 dBm 1 kH z sine wave is:
INPUT LEVEL (dB) RELATIVE TO SLOPE OVERLOAD
Shift Register Length (Algorithm)

The MC3417 has a three-bit algorithm and the MC3418
lj = . 1 1 V
+ 0 1 f'f L L U = 0.9 3 5
1 *2 (1 0 k2)
0.125 ms
has a four-bit algorithm. For clock rates of 16 kHz and

below, the 3-bit algorithm is well suited. For 32 kHz
mA
*The maximum voltage across Rl when maximum
and higher dock rates, the 4-bit system is preferred.

Since the algorithm records a fixed past history of the
input signal,, a longer shift register is required to obtain
slew is required is:

1.1 V
the same internal hsitory. A t 16 bits and below, the

4-bit algorithm will produce a slightly wider dynamic
Now the voltage range of the syllabic filter is the

power supply voltage, thus:
range at the expense o f level change response. Basically

the M C 3417 is designed for low bit rate systems and the
M C3418 is intended for high performance, high bit rate
system. A t bit rates above 6 4 k bits either part will
work well.
Rx = 0 .2 5 (V c c )
1
0 .935 mA
A similar procedure can be followed to establish the

proper gain for any input level and integration filter type.
6-23
MC3417, MC3418, MC3517, MC3518
CVSD DESIGN CONSIDERATIONS (continued)

Minimum Step Size
The final parameter to be selected for the simple codec
For values of V Q near V c c /2 the V /R term is negli

gible; thus
in Figure 14 is idle channel step size. With no input signal,

the digital output becomes a one-zero alternating pattern
i-c k ^ a
1
S AT
and the analog output becomes a small triangle wave.
where A T is the clock period and A V 0 is the desired
Mismatches of internal currents and offsets limit the
peak-to-peak value of the idle output. For a 16K-bit
minimum step size which will produce a perfect idle
system using the circuit in Figure 14
channel pattern. The M C 3417 is tested to ensure that

a 20 m Vp-p minimum step size at 16 kH z will attain a
'
proper idle channel. The idle channel step size must be
0 .1 g F 2 0 m V
62.5 MS
twice the specified total loop offset if a one-zero idle
The voltage on Cs which produces a 33
pattern is desired. In some applications a much smaller

minimum step size (e.g., 0.1 m V) can produce quiet
determined by the value o f Rx .
jiA
current is
Ij Rx a V s m in ; for 33 fiA , Vsm in = 4 1.6 m V
performance without providing a 1 - 0 pattern.

T o set the idle channel step size, the value o f Rmin
must be selected. With no input signal, the slope control
algorithm is inactive. A long series o f ones or zeros never
occurs. Thus, the voltage across the syllabic filter capaci
In Figure 14 Rs is 18 k2. Th at selection is discussed

with the syllabic filter considerations. The voltage divider
of Rs and Rmin must produce an output o f 4 1 .6 m V.
Vcc
tor (Cs) would decay to zero. However, the voltage

divider o f R s and Rmin (see Figure 14) sets the minimum
allowed voltage across the syllabic filter capacitor. That
voltage must produce the desired ramps at the analog
output. Again we write the filter input current equation:
RS
RS + Rmin
VSmin
Rmin 2.4 MJ2
Having established these four parameters clock rate,

number of shift register bits, loop gain and minimum
step size the encoder circuit in Figure 14 will function
at near optimum performance for input levels around
Vo
_dV0
- + C
R
dt
OdBm.
IN C REA SIN G CVSD PERFORM ANCE

Integration Filter Design
The circuit in Figure 14 uses a single-pole integration
network formed with a 0.1 p F capacitor and a 10 k2
resistor. It is possible to improve the performance of the
circuit in Figure 14 by 1 or 2 dB by using a two-pole
integration network. The improved circuit is shown.
The first pole is still placed below 300 Hz to provide
the 1/S voice content curve and a second pole is placed
somewhere above the 1 kHz frequency. For telephony
circuits, the second pole can be placed above 1.8 kHz
to exceed the 1633 touchtone frequency. In other com
munication systems, values as low as 1 kHz may be
selected. In general, the lower in frequency the second
pole is placed, the greater the noise improvement. Then,
to ensure the encoder loop stability, a zero is added to
keep the phase shift less than 1 8 0 . This zero should
be placed slightly above the low-pass output filter break
frequency so as not to reduce the effectiveness o f the
second pole. A network o f 2 35 Hz, 2 kH z and 5.2 kHz
is typical for telephone applications while 160 Hz,
1.2 kH z and 2.8 kH z might be used in voice only channels.
(Voice only channels can use an output low-pass filter
which breaks at about 2.5 k H z.) The two-pole network
in Figure 16 has a transfer function of:
T h e se co m p o n e n t valu e s are fo r th e telep h o n e ch an n e l c irc u it

pole* describe d In th e t e x t .T h e R 2 , C 2 p ro d u c t can be p ro vid e d
w ith d iffe re n t valu e s o f R a n d C . R 2 s h o u ld b e cho sen to be eq ual
to the te rm in a tio n re sisto r o n p in 1 .
6-24
MC3417, MC3418, MC3517, MC3518
INCREASING CVSD PERFORMANCE (continued)

Thus the tw o poles and the zero can be selected arbitrarily
is optimum. Then record the syllabic filter voltage and
as long as the zero is at a higher frequency than the first
the current. Repeat this for all desired signal levels.
pole. The values in Figure 16 represent one implementa

tion o f the tejephony filter requirement.
Then derive the resistor diode network which produces

that curve on a curve tracer.
The selection o f , the two-pole filter network effects

the selection of the loop gain yalue and the minimum step
it is then inserted in place of Rx in the circuit and the
size resistor. The required integrator current for a given

change in voltage now becomes:
forced optimum noise performance will

from the active syllabic algorithm.
.V o /R ^ R iC ,
R
o \R
o
(R2 P 2 C 1 +
R
o
Once the network is designed with the curve tracer,
Diode breakpoint networks may be very simple or
A AVq
be achieved
moderately complex and can improve the usable dynamic

range of any codec. In the past they have been used in
AT
high performance telephone codecs.
R 1 C 1 R 2 C2 '
R
o
Typical resistor-diode networks are shown in Figure 17.
The calculation of desired gain resistor Rx then proceeds
FIGURE 17 - RESISTOR-DIODE NETWORKS
exactly as previously described.

Syllabic Filter Design
The syllabic filter in Figure 14 is a simple single-pole
network of 18 k2 and 0.33 juF. This produces a 6.0 ms
time constant for the averaging o f the coincidence output
signal. The voltage across the capacitor determines the
integrator current which in turn establishes the step size.
The integrator current and the. resulting step size deter
mine the companding ratio and the S/N performance.
The companding ratio is defined as the voltage across
C s /V c c The S/N performance may be,improved by modifying
the voltage to current transformation produced by Rx.
If the performance of more complex diode networks

is desired, the circuit in Figure 18 should be used. It
simulates the companding characteristics o f nonlinear
If different portions of the total Rx are shunted by diodes,
Rx elements in a different manner.
the integrator current can be other than ( V q c - V s )/R x These breakpoint curves must be designed experimentally
Output Low Pass Filter
for the particular system application. In general, one
A low pass filter is required at the receiving circuit

output.to eliminate quantizing noise. In general, the lower
would wish that, the current would double with input
the bit rate, the better the filter must be. The filter in
Figure 20 provides gxcellent performance for 12 kHz
level. To design the desired curve, supply current to pin 4

of the codec from an external source. Input a signal
level and adjust the current until the S/N performance
to 40 kHz systems.
TE L EPH O N E C A R R IE R Q U A L IT Y CODEC USING M C3418

Tw o specifications o f the integrated circuit are speci
The circuit in Figure 18 provides a 3 0 dB S/Nc ratio
fically intended to meet the performance requirements

o f commercial telephone systems. First, slope polarity
switch current matching is laser trimmed to guarantee
over 50 dB o f dynamic range for a 1 kH z test tone at

a 37.7K bit rate. A t 37.7K bits, 4 0 voice channels may
be multiplexed on a standard 1.544 megabit T1 facility.
This codec has also been tested for 10~? error rates with
asynchronous and synchronous data up to 2400 baud
and for reliable performance with D T M F signaling. Thus,
the design is applicable in telephone quality subscriber
loop carrier systems, subscriber loop concentrators and
small PABX installations.
proper idle channel performance with 5 m V minimum

step size and a typical 1% current match from 15 /iA
to 3 m A. Thus a 3 00 to 1 range o f step size variation is
possible. Second, the M C 3418 provides the four-bit
algorithm currently used in subscriber loop telephone
systems. With these specifications and the circuit of Fig
ure 18, a telephone quality codec can be mass produced.
6-25
MC3417, MC3418, MC3517, MC3518
TELEPHONE CARRIER QUALITY CODEC USING MC3418 (contlnuedl

The Active Companding Network
related to the voltage across Rx, which established the
The unique feature of the codec in Figure 18 is the
integrator current. In Figure 18, the voltage across Rx is
step size control circuit which uses a companding ratio
amplified by the differential amplifier A 2 whose output
reference, the present step size, and the present syllabic

filter output to establish the optimum companding
is single ended with respect to pin 10 o f the IC.
ratios and step sizes for any given input level. The com
output o f A2 is lower than 0.7 volts. Thus D1 is fully on.
For large signal inputs, the step size is large and the
panding ratio of a CVSD codec is defined as the duty
The present step size is not a factor in the step size
cycle of the coincidence output. It is the parameter
control. However, the difference between 12% comp-
measured by the syllabic filter and is the voltage across
panding ratio and the instantaneous companding ratio at
Cs divided by the voltage swing o f the coincidence output.

In Figure 18, the voltage swing o f pin 11 is 6 volts. The
operating companding ratio is analoged by the voltage
voltage across Rx in a direction which reduces the d if

ference between the companding reference and the
between pins 10 and 4 by means of the virtual short
operating ratio by changing the step size. The ratio of
across pins 3 and 4 of the V to I op amp within the inte

grated circuit. Thus, the instantaneous companding
R4 and R3 determines how closely the voltage at pin 4

will be forced to 12%. The selection o f R3 and R4 is
pin 4 is amplified by A 1. The output o f A1 changes the
initially experimental. However, the resulting companding
ratio of the codec is always available at the negative

input o f A1.
The diode D1 and the gain of A1 and A 2 provide
control is dependent on Rx , R3, R4, and the full diode

drop D1. These values are easy to reproduce from codec
to codec.
a companding ratio reference for any input level. If

the output o f A 2 is more than 0.7 volts below V c c /2 ,
then the positive input of A1 is (V c c /2 - 0.7). The on
diode drop at the input of A1 represents a 12% com
panding ratio (12% = 0.7 V /6 V ).
The present step size o f the operating codec is directly
For small input levels, the companding ratio reference

becomes the output of A2 rather than the diode drop.
The operating companding ratio on pin 4 is then compared
to a companding ratio smaller than 12% which is deter
mined by the voltage drop across Rx and the gain o f A 2
FIGURE 18 - TELEPHONE QUALITY DELTAMOD CODER

(Both double integration and active companding control are used to obtain improved CVSD performance.
Laser trimming of the integrated circuit provides reliable idle channel and step size range characteristics.)
V o ic e /N o n -V o ic e
SELECT
C lo c k
In p u t
D ig ita l
O u tp u t
MC3417, MC3418, MC3517, MC3518
TELEPHONE CARRIER QUALITY CODEC USING MC3418 (continued)

FIGURE 19 - SIGNAL-TO-NOISE PERFORMANCE
AND FREQUENCY RESPONSE
(Showing tha improvement raalized with
the circuit in Figure 18.1
and A 1. The gain o f A 2 is also experimentally determined,

but once determined, the circuitry is easily repeated.
With no input signal, the companding ratio at pin 4
goes to zero and the voltage across Rx goes to zero. The
8. SIGNAL-TO-NOISE PERFORMANCE OF TELEPHONY

QUALITY OELTAMOOULATOR
voltage at the output o f A 2 becomes zero since there is

no drop across Rx . With no signal input, the actively
controlled step size vanished.
The minimum step size is established by the 500 k
resistor between V (jC and V c c /2 and is therefore inde
pendently selectable.
The signal to noise results o f the active companding
network are shown in Figure 19. A smooth 2 dB drop is
realized from + 1 2 dBm to - 2 4 under the control o f A 1.
A t - 2 4 dBm, A 2 begins to degenerate the companding
reference and the resulting step size is reduced so as to
extend the dynamic range o f the codec by 20 dBm.
The slope overload characteristic is 8lso shown. The
active companding network produces improved perfor
mance with frequency. The 0 dBm slope overload point is
raised to 4 .8 kH z because o f the gain available in control
ling the voltage across Rx . The curves demonstrate that
the level linearity has been maintained or improved.*
The codec in Figure 18 is designed specifically for
37.7 K bit systems. However, the benefits o f the active
companding network are not limited to high bit rate
systems. By modifying the crossover region (changing
INPUT LEVEL IN dBmO

b. FREQUENCY RESPONSE wersu* INPUT LEVEL
(SLOPE OVERLOAD CHARACTERISTIC)
F
Oft
T>
Z
-1
Ul
>
ut
_l
H
D
H
3
O
0 d B m IN P U T
O-
the gain of A 2 ), the active technique may be used to

improve the performance o f lower bit rate systems.
-10-20-30-
The performance and repeatability o f the codec in

Figure 18 represents a significant step forward in the art
-40-
and cost o f CVSD codec designs.
-50*A larger value for C2 is required in the decoder circuit

-60*
than in the encoder to adjust the level linearity with

frequency. In Figure 1 8 ,0 .0 5 0 fiF would work well.
O
2 kH z
4 kH z
6 kHz
8 kH z
10 kHz
IN P U T F R E Q U E N C Y IN H z
FIGURE 20 - HIGH PERFORMANCE ELLIPTIC FILTER FOR CVSD OUTPUT

Cl
u , a 6 kHz
A d B a t w t a n d a b o v t 2 9 .3 d B
6-27
MC3417, MC3418, MC3517, MC3518
FIGU RE 21 - F U L L DU PLE X/32K B IT CVSO VOICE CODEC USING MC3S17/18 A N D MC3B03/6 OP AMP
D ig it a l O u t p u t
Codec Components
" X 1 .R X 2 -3 .3 Kn
R p l , R p 2 3 .3 k n
R S 1> ^ S 2 - 1 K n
R|1* R I2 - 2 0 kn
R l2 - 1 kn
r M 1 . R |U 2 "5 M n ( M C 3 4 1 7 )
M in im u m (ta p (izo 2 0 m V
r M 1. r M 2 ~ 16 M n (M C 3 4 18 )
M in im u m step *izo - 6 m V ' '
Input Filter Specifications------
F ilt e r C o m p o n e n ts
1 2 d B /O cto vo R o lio f f ab ova 3 .3 k H z

6 d B /O cto vo R o llo f f b elo w 5 0 H z
R l - 9 65 n
R 2 - 72 kn
R3 - 72 kn
R 4 - 6 3 .4 6 kn
RS - 127 kn
R 6 - 3 6 5 .5 ,k n
R 7 - 1.6 4 5 Mn
R 8 72 kn
R 9 - 72 kn
R I O - 2 9 .5 kn
R 1 1 - - 72 kn
Cl
C2
C3
C4
C5
C6
C7
C8
C9
N o to : A lt R o t. 0 . 1 % to
A ll C a p . 1 . 0 %
1% .
Output Filter Specifications

Brook F re q u e n c y 3 .3 k H z
S to p B and 9 k H z
S to p B an d A tte n . SO d B
R o llo f f > 4 0 d B /O cte vo
C s i . C s 2 - 0 .0 5 ( i f
C m.C ,2 -0 .0 5 ^ F
2 M C 3 4 1 7 (o r M C 3 4 1 8 )
1 M C 3 4 0 3 (o r M C 3 4 0 6 )
N o te : A ll R at. 5 %
A ll C a p . 5 %
6-28
3 .3 # iF
- 837 p F
- 5 36 p F
- 1000 p F
- 222 p F
- 77 pF
38 pF
- 837 pF
- 5 36 p F
MC3417, MC3418, MC3517, MC3518
C O M PA RA TIVE CODEC PER FO R M A NC E
FIGURE 22 - COMPARATIVE CODEC PERFORMANCE -
The salient feature o f CVSD codecs using the MC3517

and MC3518 family is versatility. The range o f codec
complexity tradeoffs and bit rate is so wide that one
cannot grasp the interdependency of parameters for
voice applications in a few pages.
Design of a specific codec must be tailored to the
digital channel bandwidth, the analog bandwidth, the
quality of signal transmission required and the cost
objectives. To illustrate the choices available, the data in
Figure 22 compares the signal-to-noise ratios and dynamic
range o f various codec design options at 32K bits.
Generally, the relative merits o f each design feature will
remain intact in any application. Lowering the bit rate
will reduce the dynamic range and noise performance
of all techniques. As the bit rate is increased, the overall
performance o f each technique will improve and the need
for more complex designs diminishes.
Non-voice applications o f the MC3517 and MC3S18
are also possible. In those cases, the signal bandwidth
and amplitude characteristics must be defined before
the specification o f codec parameters can begin. How
ever, in general, the design can proceed along the lines of
the voice applications shown here, taking into account the
different signal bandwidth requirements.
-45
-40
-35
-30
-25
-2 0
-15
-10
-5.0
AKPLITUDEIdB)_____________________
These curvet demonstrate the improved performance obtained

with severs) codec designs of varying complexity.
Curve a Complex companding and double integration
(Figure 18 - MC3418)
Curve b Double integration (Figure 21 using Figure 6
MC3418)
Curve c Single integration (Figure 21 MC3418) with
6 mV step size
Curve d Single integration (Figure 21 MC3417) with
25 mV step size
MC3419
MC3519
MOTOROLA
Advance Information
TELEPHONE LINE FEED AND 2- TO 4-WIRE
CONVERSION CIRCUIT
SUBSCRIBER LOOP
INTERFACE CIR CU IT
(SLIC)
BIPOLAR LASER-TRIMMED
IN TEGRATED CIRCU IT
. . . designed to replace the h ybrid transform er c irc u it in Class 5,

PABX and Subscriber carrier equipm ent, providing signal separation
fo r tw o-w ire d iffe re n tia l to four-w ire single-ended conversions and
suppression o f longitudinal signals at the tw o-w ire input. It provides
dc line current fo r powering the telset, operating from up to a 60 V
supply.
L SU FFIX
CASE 7 26
Transm it and Receive Gain is E xternally Selected
On-Hook Power Below 5.0 mW
Current Sensing O utputs Provided fo r O ff-H o o k Status from Both

T ip and Ring Leads
Size and W eight Reduction Over Present Approaches
P SU FFIX
CASE 701
C om patible w ith IEEE and REA Specifications
The sale o f this p rod u ct is licensed under patent No. 4,004,109.

A ll royalties related to this patent are included in the u n it price.
This is advance in fo rm a tio n and sp ecifica tio ns are subject to change w ith o u t notice.
6-30
MC3419, MC3519
M A X IM U M R A TIN G S
Rating
Maximum Rated Voltage
Maximum Power Dissipation Ta = 25C
Derate above +25C
MC3419
MC3519

Symbol
Value
VEE1.V EE2
60
Vdc
PD
1.5
Watts
ta
0 to +70
-40 to +85
-65 to + 150
C
C
150
Tstg
Tj
Unit
E LEC TR IC A L C H A R A C TER ISTIC S (V e ei VEE2 * -48 V. Vcc 0. V a g -6 v - TA 2St>cl

Characteristic
Loop Current Range
(RL o o o " - 190001
Transhybrid Reception Ratio Figure 2
<Rl -9 0 0 n .V RX, 0.775 V RMS, VQ - 0)
Transhybrid Transmission Ratio - Figure 2
<RL 900 n , V RX 0. V G 0.775 V RMS)
Transhybrid Rejection Ratio Figure 2
(Rl - 900 Ii, V RX - 0.775 V RMS. V Q - 0)
Input Resistance (R and T)Figure 2
In-Band Longitudinal Suppression Ratio Figure 3
<Lon = 0.775 V RMS, f - 1 kHz, RL - 900
60 Cycle Longitudinal Suppression Ratio Figure 3
<8Lon 30 V RMS, f 60 Hz. RL - 1900 )
Longitudinal Capacity Figure 3
(60 Hz)
Level Linearity
(f 300 Hz to 3400 Hz,
Reception V r x 0.775 V r m s ,
Transmission V r l " 0.775 V r m )
Idle Noise
Off-Hook Power Dissipation (IC)
('Loop a 120 mA)
On-Hook Power Dissipation
Tip Status Current
('Loop s 0 to 120 mA)
Ring Status Current
('Loop = Oto 120 mA)
Voltage Range of Analog Ground
Analog Ground Input Current
Fault Currents
(Tip to V c c Figure 2)
(Ring to Vcc Figure 2)
(Ring and Tip to Vcc P'Sure 2)
(Tip to Ring Short Figure 2)
Logic Low
Min
Typ
Max
Unit
Lp
20
120
mA
VRL/VRX
-0.1
+0.1
dB
VTX/V RL
-0.1
+0.1
dB
VTX/V RX
-46
dB
n
900
Rin
VTX/Lon
-66
dB
VTX/Lon
-66
dB
'Lon
35
">Ar m s
VRX/VRL
V RL/V TX
-0.1
-0.1
-
+0.1
+0.1
-
dB
dB
dBrnCn
0.6
5.0
Watts
mW
0.0104
mA/mA
rs / ' r
0.0104
Vr
pD(Off)
pD(On)
t s / ' t
Gnd
'T
r
Ii t M ' r I
t + ir
mA/mA
-12
Volts
1.0
liA
0
5.0
5.0
120
mA
mA
mA
mA
Vdc
X -1
> >
Power Down Input Levels

Logic High
Symbol
Vcc-1.0
V cc-2.0
MC3419, MC3519
FIGURE 2 - AC TRANSMISSION TESTS OF MC3419 A T BA LAN C E
FIGURE 3 - LONGITUDINAL TEST
6-32
MC3419, MC3519
FIGURE 4 - DESIGN EQUATIONS
Internal to the MC3419 sre three precise gain constants

K1 - 4
K2 = 23.75
K5 - 0.4 ,K5' - 0.6
1. The dc feed resistance is Rf

..............f
K5 and K5' are selected by connecting TX1 or TX2 to RX respectively.

The remaining TX pin is connected to R6 and R7.
R l + R2
Rf 1+K1K2 + R 3 + R 4
Z Tho termination resistance is R0
R1 + R2
, ro ^ o-.
R 1 + K1K2KB + R 3+ R 4
FIGURE S - HYBRID LOOP CURRENT versus LOOP RESISTANCE

(FOR 24 AND 48 V SUPPLY)
R L . L O O P R E S I S T A N C E (k O )
6-33
MC3419, MC3519
FIGURE 6 - RING TRIP USING MC3419
e-34
MC3419, MC3519
FIGURE 7 - M O TO RO LA 3-CHIP SUBSCRIBER C H A N N E L U N IT
MC
14 0 3
EP
VCC
BP
V AG
CP
R1
R2
RX
TX1
EN
6-35
V EE1
,3
18 k
V A -
V AG
HeIMF
RXO
+A
TX2
27 k
1 |lF
CN
BN
V AG
-W V -
TS
PD
V EE2
800 k
A A A r-
TXO
-B
AO
RXI
TXI
M SI
VSS
2000 pF
+B
-A
BO
ADI
VDD
CCI
1 2000 pF
H
2 .7 k
V / -
VLS
t> ]
4000 pF
VDD
CCI
24
23
C I1
22
RDD
C I2
RCE
C21
ROC
CZ2
TOC
R1
T D D 18
R2
TOE
21
20
17
16
M SI
ADO
PDi I B
12 C 0 2
IR E F
VSS
1 2 .0 4 8 M B it s
>& 0 k H z
i 2 .0 4 8 M H z
M u -A
COI
1 2 8 kH z
2 .0 4 8 M B it s
> 8 .0 k H z
1 8 .0
kH z
14
13
30 k
-W V 0.1 I l f
OH
-R T
I-1 2 V
IPD
1 -4 8 V
R B
RE
M C 3 4 19
6-36
N O T E : T h o ta le o f th is p ro d u c t
it licen to d u n d e r p aten t
N o . 4 ,0 0 4 ,1 0 9 . A ll ro y a lt le t
re lated to t h is p ate n t are
in c lu d e d in th e u n it p rice .
MC3419, MC3519
FIGURE 8 - SUBSCRIBER LOOP INTERFACE CIRCUIT, MC3419
MC3419, MC3519
DESCRIPTION OF MC3419 SUBSCRIBER LOOP INTERFACE CIRCUIT

Figure 8 depicts a complete subscriber loop interface
c ir c u it
fo r
s ta n d a rd
e n d -o ffic e
telephone
When a load resistance (R |_) is connected to Tip and
loop
Ring, the dc current flows in R 1, R2, and circuits A and
connections. The circuit consists of an 18 pin dual in-line
A ', The control outputs, op amps B, B', and the voltage

reference are now on. The current gain o f circuit A and A '
M C 3 4 1 9 , M JE 271 PNP and M JE270 NPN power

darlington transistors, an M D A 2 2 0 bridge rectifier and six
resistors. This composite circuit provided the following
line interface functions:
1. 2-wire balanced to 4-wire single-ended signal
to the T X outputs is K2 4 . The current gain of circuits B

and B' is K1 = 23.75. For a current in R1 and R2 of Ijg,
the current in the collector of circuits B and B' is
K1 K2lfsj. The total current in the load is (1+K1 K2)lfy|.
The dc feed resistance at the Tip and Ring terminals is
conversion.
2. Independent Receive Gain selection (R 5).
Rf
3. Independent Transmit Gain selection (R 8).

4. Independent Transhybrid null selection (R 6 + R 7)*
5. 600 to 9 00 n resistance ac loop termination (R1, R2,
The current which flows in the load w ill be:
R3. R 4 ) \
Loop
6. Resistive dc power-feed from 4 0 0 to 8 00 f i (R1,

R2, R3, R 4).
7. Ring to ground. Tip to ground. Ring and Tip to
ference from 50 to 3400 Hz (30 m A RMS).

9. 1500 volt secondary lightning protection.
10. Temporary power line fault protection.
11. Proportional ring current sense indication in RS.
12. Proportional tip current sense indication in TS.
13. Suppression of longitudinal component in RS and
TS normal connections.
14. Independent 4-wire common input for noise iso
lation.
15. Independent quiet battery supply input for battery
noise rejection.
16. Near zero power dissipation in normal on-hook
condition.
17. Level linearity of better than 0.1 dB over the entire
level and frequency range.
V CC " V EE2
R L + Rf
The dc feed current is thus determined by the loop

resistance.
ground fault current limiting (10 m A ).

8. Rejection o f longitudinal or common mode inter
(R1 + R2)
+ R3 + R4
1+K1K2
The dc component o f ix is a measure of the mismatch

between the source and the sink current of the various
differential stages. Circuit C and C ' source or sink current
through CN and CP until the dc component of ix = 0. C
and C' also keep the m id-point voltage of the load at
V q q /2 . Thus, with a metallic current in the load, the
SLIC supplies current to the load w ith impedance Rf.
Various fault dc conditions must be accounted for in
practice. The T ip and Ring leads can be shorted to ground
in the field in any combination. The SLIC limits these
fault currents by the arrangement o f the control outputs
of circuit A and A . If the Ring lead 1s tied to ground, a
current through R2 w ill turn on the control output o f
circuit A . This enables op amp B' and provides a sinking
path for the voltage reference. If the T ip lead is open or
connected to ground, the current in R 1 is zero. The ix
control lead is sinking current but cannot turn on circuit
Reflected complex impedances may also be provided
C ' because the voltage reference is V g g . C ircuit B is also
with an additional capacitor.
o ff since the control output o f circuit A ' is off. The

current in the Ring lead is now ( ( V q c *V e e )/(R 4 + R 2 ) ] .
DC C H A R A C TER ISTIC S
The Ring fault current in the SLIC is less than 10 mA.
The first function the S LIC must perform is to enable

and disable itself on the basis of the switch-hook
condition in the attached instrument. With the station
on-hook, the Ring and T ip terminals are open. No metallic
SM A LL S IG N A L AC C H A R A C TE R IS T IC S
With a load R|_ applied across T ip and Ring, the flow
o f metallic current in R|_ enables and biases the SLIC
current can flow in resistors R1 and R2, thus the input

and various outputs of circuit A and A ' are zero. The
control outputs o f <A and A ' are o ff, causing the op amps
B and B' and the voltage reference to have no bias. The
reference pull down resistor pulls the reference voltage to
circuit. Now consider an ac generator in series with R[_

causing differential signal across Ring and Tip at a
frequency between 3 00 and 3400 Hz. The impedance
presented to the generator is Rj_ + R0 where R0 is the ac
V g g . No current flows in any part of the circuit if the Tip

and Ring terminals are open. The power dissipation in this
derived by a method similar to Rf.
state is back bias leakage only.
23.75 as before. However, the T X 2 path to i j x is an
input impedance o f the SLIC at the two-wire part. R0 is

The gain of circuits A , A ', B, and B' is K1 = 4 and K2 =
6-37
MC3419, MC3519
added load for ac signals and the current returned to R x
The
current
amplifiers within
the
S LIC
are all
is divided by the current divider of 2 .5 k2 and 1.66 k2.
wide-band amplifiers such that essentially no group delay
As connected, the ratio of these resistors creates another
occurs for 4 kHz band limited signals and resistive loads.
constant K5 = 0.4. (TX1 and T X 2 connection can be
Thus, the SLIC functions as a near ideal transimpedance
reversed to produce K 5' - 0 .6 ).
converter for ports V r x *V r l * ant* ^ T X * Complex loads

Z l may be balanced by replacing (R 6 + R 7) with a
The ac termination is thus:

R f
complex balance network z.
Rl +R 2
1+K 1K 2K 5
+ R3 + R4
The ac current in SLIC is then
L O N G IT U D IN A L S IG N A L SUPPRESSION
B o th low frequency and voice-band longitudinal
rejection are produced by the same mechanisms within
v9
n = o ^ T " where v is the generator voltage.
R L + Ro
The current in R1 and R2 is given by
this SLIC.
A longitudinal interference from 0 to 3 40 0 Hz in the
1+K1K 2K5
loop produces a common mode voltage a t Ring and T ip .

Circuit A and A ' sense these in phase currents in R1 and
and the output signal current is

K K 1 -K 5)
ig (1+K 1K 2K 5)
TX =
VTX
v9
C'
R2 and cause an ac signal ix . Circuit C and

are driven
by the Class B transistor pair to produce currents which
will reduce the common mode component at nodes CN
thus
and CP by the open loop ac gain o f the circuit C and C'.

The high compliance of the ix output and a large current
K 1(1-K 5)
1+K 1K 2K 5
( rL+8ro)
gain in circuit C and C' allow the open loop gain to be

quite large.
The differential signal in the load is input, as tw o out

o f phase signals, into circuits A ' and A . The A ' signal is
Constants K1, K2 are held in close tolerance within the
inverted and summed in phase with the output of A in
integrated circuit. If R l + R3 = R 2 + R 4, then the
A ". The transmit gain voltage o f the SLIC can be set at

any arbitrary value by selecting R8.
longitudinal balance at Tip and Ring will be good. Thus,
Now assume a two-wire load R ^ and a generator vg at
and CN w ill be equal. The phase inversion in A " w ill cause
V r x - The generator sees a low impedance at R )(,

assuming V ^ q is connected to a dc potential.The current
the common mode remainder to sum out o f phase at T X 2
the remaining component of common mode signal at CP
and thus w ill contribute little output a t V j x - The overall

performance o f this common mode rejection loop is
into R x *s simply ip x = vg/R 5 .

This current is multiplied by K1 in circuits B and B'.
The output transistors drive a load Rj_ + R3 + R4 in
determined by the matching o f R1 + R 3 and R4 + R2, as

well as the matching of constants w ithin the chip. 60 dB
appears readily achievable.
parallel w ith (R 1+ R 2 )/(1 + K 1 K 2 K 5 ) so that the voltage

gain from V r x to Tip and Ring is
V RL
r L
= -K 2
The circuit C and C' outputs are limited to 3 0 m A to

insure longitudinal capacity for both the IEEE and R EA
standards.
where
V RX
LOOP C O N D IT IO N SENSING
R1 + R 2
Cl =
(R 1 + R 2 )+ (R L+R 3+ R 4)(1+K 1 K 2K 5) I
Three analog sensing outputs are provided for detecting

the condition o f the subscriber loop. Each output consists
of the open collector of a current sourcing device. The RS
The signal current across the load is in phase with V r x

and out o f phase w ith the termination RQ. The current in
and TS outputs are derived from the sense currents in

circuits A and A . Thus, in a normal metallic connection
R0 causes a signal at iy x This current may be cancelled for any load R l by
the TS and RS currents are related to Ring and Tip

currents by constants.
selecting the sum o f (R 6 + R 7).

Balance is achieved for a load R l by designing
DC Metallic
R 5(1+K 1K 2K 5)
.
K 1K
^ " h e re
1 K2(1-K
2 0 -K 55)~
)
RS
(R 6 + R 7 ) =
1+K1K 2
V C (T V EE
(R l + Rf )(1+K 1K 2)
1+K1K 2
V C C V EE
(R L+R f )(1+ K 1K 2)
(R 1+R 2) + (R L +R 3+ R 4 )(1 +K 1 K 2K 5 )
C2 =
it s
R1 + R 2
6-38
MC3419, MC3519
AC Metallic
'RS
'TS
support the sensing resistors and control all other current

in the SLIC. If the voltage across V q q and V g g j *s
tered, noise at V q q will not effect the performance of the
= (R|_+R0 )n + K 1 K 2 K 5 )
loop. In a short circuit condition, the
current will be
about 130 m A while the V g g 2 curfent is 3 m A. It is,
_____ ^RL_____
therefore, possible to supply V g g 2 from a far <lu'eter

supply.
{R|_+R0 )(1 +K 1 K 2 K 5 )
current and the TS current w ill be proportional to the Tip
Furthermore, an analog ground input ( V ^ q ) is Pro

vided to allow for proper noise grounding for the V p x
and V j x terminals. The true input signal is the ac voltage
between V ^ q and V p x - The true output voltage should
c u rre n t.
be taken between V ^ q and V j
Note that if the current has a metallic path from Tip to

Ring, but also an unbalanced load to ground in Ring or
Tip, that the RS current will be proportional to the Ring
Second party
detection
and
ground
start
detection can be handled using this feature. Providing a

PROTEC TIO N
metallic path does exist, the longitudinal component in

RS and TS w ill be suppressed in RS and TS by circuit C
and C'. With no metallic connection, circuit B and B* are
Tw o types o f electrical hazards can be expected at the
off such that the longitudinal impedance is R l + R3 and

the induced current from a given source will be decreased
Ring and Tip terminals of the SLIC. Transient currents

caused by electrical storms and power line cross connects
during installation and maintenance. The diode bridge,
by 1 + K1K 2. In this case, the longitudinal current will
coupled with R3 and R4, provide this protection. Ring
produce peak outputs a t RS and TS which are less than

the average output of a long-loop metallic current.
and Tip are normally protected by a gas tube or carbon
The longitudinal sense output provides a full-wave
strike. The SLIC itself must provide secondary protection
blocks against the primary effects o f a near lightning
rectified current proportional to the longitudinal loop
for 1500-volt transients. A transient voltage at Ring or Tip
current once metallic connection has been established.

Simple filtering of this lead can produce a dc measure of
will turn on one o f the four diodes. The resistors lim it the
maximum current to 50 amps, which is the rated surge
the longitudinal status of an operating loop. Excessive
current o f the diodes. A typical turn on time of 2 0 0 ns is
longitudinal current can produce a fault indication.
readily achievable w ith silicon rectifiers.
NOISE A N D POWER SUPPLY REJEC TION
rectified by the upper and lower pair resulting in a current
Power line faults from 120-volt lines will be half-wave

of 2 amp RMS in each with 30 ohm source resistors.
The main 48-volt battery in a large office can supply

considerable power but is often quite noisy and difficult
to filter. W ithout a means of rejecting supply noise, the
channel to channel crosstalk canâlso become excessive. In
Extended short circuit conditions w ill cause R 3 and R4

to bum open, eliminating the fault and causing no further
damage. The extemalization o f the R3 and R4 resistors
this SLIC, tw o V g g pins are provided to allow for quiet
from the SLIC's feedback loop is a critical step in provid
battery and power battery connection. Circuits A and A '
ing sufficient electrical hazard protection.
6-39
VOLTAGE COMPARATORS
Temperature Range
Commercial
Military
L M 311/ 2 1 1*
LM339, A /
239, A *
LM 2901*
MCI 414
MC1710C
MC1711C
MC3302P*
M C 3430-3433
Page
7-3
LM 111
High-Performance Voltage Comparators.........................................
LM139, A
M CI 514
MC1710
MC1711
MC3302L
Quad Single-Supply Comparators ................................................... 7-7

Quad C om parator........................................... .................................. 7-11
Dual Differential Voltage Comparator.............................................. 7-15
Differential Voltage Comparators..................................................... 7-19
Dual Differential Voltage Comparators........................................... 7-23
Quad Single-Supply Com parator..................................................... 7-27
Quad High-Speed Voltage Com parators........................................ 7-31
*lndu8trial
7-2
LM111
LM211
LM311
MOTOROLA
HIGHLY FLE X IB LE VOLTAGE COMPARATORS

The a b ility to operate fro m a single power supply o f 5.0 to 30
volts or 15-volt sp lit supplies, as co m m on ly used w ith operational
am plifiers, makes the LM111 / LM211 / LM311 a tru ly versatile
comparator. Moreover, the inputs o f the device can be isolated from
system ground w h ile the o u tp u t can drive loads referenced either to
ground, the V c c o r the V g g supply. This fle x ib ility makes it
possible to drive M D T L , M R T L , M T T L , o r MOS logic. The o u tp u t
can also switch voltages to 50 volts at currents to 50 m A. Thus the
L M 111 / LM211 / LM311 can be used to drive relays, lamps or
solenoids.
HIGH PERFORMANCE
VO LTAGE COMPARATORS
J f l S U F F IX
CASE 6 93
SUGGESTED C O M PAR ATO R DESIGN C O N FIG U R ATIO N S

SPLIT POWER-SUPPLY w ith
OFFSET BALANCE
SINGLE SUPPLY
3 vcc
3
1 OUTPUT
6 BALANCE (STROBE
3 5 BALANCE
H SU FFIX
M E T A L PAC KAG E
CASE 601
GROUND-REFERRED LOAD
LOAD REFERRED to
NEGATIVE SUPPLY
O I BALANCE /STROBE
BALANCE
In p u t p o la rity Is reversed w h en
G N D p in is used as an o u tp u t.
In p u t p o la rity is revorsod when

G ND p in is used as an o u tp u t.
LOAD REFERRED to
POSITIVE SUPPLY
STROBE CA PA BILITY
N SU FFIX
CASE 626
( LM 31 1 O n ly)
0 vcc
7 OUTPUT
6 8ALANCE/STHOBE
5 BALANCE
7-3
LM111, LM211, LM311
MAXIMUM RATINGS (TA = +25C unless otherwise noted.)

Value
Symbol
Rating
Total Supply Voltage
r'
Output to Negative Supply Vo)t8ge :
V cc + |V e e I
- LM111
LM211
'
Vo - V EE
Ground to Negative Supply Voltage

Unit
LM311
36
36
Vdc
SO
40
Vdc
v EE
30
30
Vdc
V,D
V{n
30
30
Vdc
15
15
Vdc
Input Voltage (See Note 1)

Power Dissipation (Pkg. Limitation)
Metal Package
Derate above T A " +25C
Plastic* and Ceramic Dual In-Line Packages
Derate above T a = +25C
Operating Ambient Temperatures Range
Pd
mW
mW/C
mW
mW/C
dC
680
4.6
625
5.0
Ta
-55 to +125
-2 5 to +85
LM111
LM211
LM311
Tstg
0 to +70
-65 to +150
-65 to +150
LM31 IN only is availsble in the plastic dual in-line package.
ELECTRICAL CHARACTERISTICS (Vcc " +15 V, V EE - ' 5 V, TA = +25C unless otherwise noted.)
LM111
Characteristic
Symbol
Input Offset Voltage (See Note 2.)

Rs < 5 0 kfi, TA " +25C
Rs ^ 5 0 kn.Tiow * < T A <Thjgh*
Input Offset Current (See Note 2.)
TA = +25C
T (o w < T A < T hiflh
Input Bias Current
T A - +25C
""low ^ ^ A ^^hiqh
Voltage Gain
Response Time (See Note 3.)
Min
Typ
Max
Min
Typ
Max
0.7
-
3.0
4.0
2.0
-
7.5
10
4.0
6.0
-
50
70
'60
200
100
150
100
200
250
300
Av
10
20
*TLH
nA
I' io I
'IB
Tlow < T A < T high. VCC > 4 .5 V. V EE 0

V io < - 6 .0 mV, lsink < 8 .0 mA
V io < - 1 0 mV, lsink < 8 .0 mA
Strobe "On" Current
TA = +25C, V io > 5 .0 mV, V0 * 35 V
V |D > 1 0 m V ,V o = 3 5 V
T lo w < T A < T hiqh, V |D > 5 .0 mV, V0 - 35 V
Input Voltage Range
Tlow < T A < Thigh
Positive Supply Current
Negative Supply Current
Unit
mV
lv iol
Saturetion Voltage
TA = +25C, V|D < - 5 .0 mV, I q = 50 mA
V |o < - 1 0 m V , l0 -5 0 m A
T tow= -5 5 C fo r LM111
* -2SC for LM211
= 0 for LM311
LM311
LM211
nA
200
0.75
-
1.5
-
0.75
1.5
0.23
3.0
0.4
-
0.23
3.0
0.4
-
mA
0.2
50
nA
nA
V0 L
's
V/mV
200
'0 L
-
0.2
0.1
10
0.5
'
,ns
V
UA
V|R
-
ice
'EE
14
+5.1
-4.1
+6.0
-5.0
14
+5.1
4.1
+7.5
-5.0
mA
mA
Thigh -+125C for LM111

= +85C for LM211
+70C for LM311
Note 1.
This rating applies for 15-volt supplies. The positive input voltage limit is 30 volts above the negative supply. The negative input
voltage limit is equal to the negative supply voltage or 30 volts below the positive supply, whichever is less.
Note 2.
The offset voltages end offset currents given wo the maximum values required to drive the output within a volt of either supply
with a 1.0-mA toad. Thus, these parameters define an error band and take into account the "worst case effects of voltage gain and
input impedance.
Note 3.
The response time specified is for a 100-mV input step with 6.0-mV overdrive.
7-4
LM111, LM211, LM311
T Y P IC A L C HA R AC TER ISTIC S
FIGURE 2 - INPUT BIAS CURRENT and INPUT OFFSET
CURRENT versus TEMPERATURE
FIGURE 3 - COMMON-MODE LIMITS versus TEMPERATURE
FIGURE S - EQUIVALENT OFFSET ERROR versus

INPUT RESISTANCE
FIGURE 4 - OUTPUT SATURATION VOLTAGE versus

OUTPUT CURRENT
Rin, INPUT RESISTANCE (0)
7-5
LM111, LM211, LM311
A PPLICATIO NS IN F O R M A T IO N
FIGURE 6 - ZERO-CROSSING DETECTOR DRIVING
>VC C - 5 . 0 V
3k
BALA N CE
A D JU S T
BALAN CE I
3k
Q
IN P U T
O(
,V c O U TPU T
I N P U T S L M 3 1 1 ^ >o
t
O U TPU T
L
T O M O S L O G IC
- /
E E 5 10 k
o g n d I
e e
-1 0 V
7-6
LM139 LM139A
LM239 LM239A
LM339 LM339A
MOTOROLA
QUAD SINGLE-SUPPLY COMPARATORS
QUAD COMPARATORS
These com parators are designed fo r use in level detection and lowlevel sensing applications in Consumer, A u to m o tive and Industrial
electronic applications.
Power Supply Options

Single Supply = 2.0 to 36 Vdc
Split Supplies = 1.0 - 1 8 Vdc
N S U F F IX
Wide Operating Tem perature Range 55 to +125C
Low Supply C urrent Drain 2.0 m A (Max)
CASE 6 46
L M 2 3 9 /2 3 9 A ,
L M 3 3 9 /3 3 9 A o n ly
Low In p u t Biasing C urrent 25 nA (Typ)
Low In p u t Offset Voltage - 5.0 mV (Max) LM 139, 239, 339
J S U F F IX
CASE 6 32
T O -116
2.0 mV (Max) L M 139A , 239A, 339A
T T L and CMOS C om patible
M A X IM U M R A TIN G S
Symbol
Value
Unit
V CC
+36 or i1 8
Vdc
V IDR
36
Vdc
Rating
V ICR
-0.3 to +36
Vdc
O utput Sink Current
Uink
20
mA
Power Dissipation @ T a = 25*C

Ceramic Package
Derate above 25C
Plastic Package
Derate above 25C
Pd
1.25
10
1.25
10
Watts
mW/C
Watts
mW/C

LM139, 139A
LM239. 239A
LM 339.339A
LL
O u t p u t |
T5] 0 U ; P U ,
l l
v c c
(T
12]
G nd
in p u t
r j
77|
-I
In p u t
4+
1-
In p u t r j
1+
iD 'T
I n p u t i
ta
T stg
1 O u tp u t
O u tp u t r
-55 to +125
-40 to +85
0 to +70
-65 to +150
7-7
2-
[ I
I]
,n 3p +u t
,n 3P -u t
I n p u t i
2*
I
( T o p V ie w )
LM139, LM139A, LM239, LM239A, LM339, LM339A
E L E C T R IC A L C H A R A C TE R IS T IC S IV qc * +6.0 Vdc, T a 2SC unless otherwise noted.)

LM139.A
Characteristic
Symbol

(Vref - 1.4 Vdc, V0 = 1.4 Vdc, Rs 0) LM139,239,339
LM139A, 239A.339A
V |0
ho
'IB
V|CR
ice
'EE
-
Input Bias Current

Input Common Mode Voltage Range (Note 1)
Supply Current
(R|_ )
Response Time (Note 2)
(V r L - 5.0 Vdc, R l 5.1 kn)
Output Sink Current
(Vi|_) > +1.0 Vdc, V |(+) 0, V o < +1 5 Vdc)
(V|(_) > +1.0 Vdc, V|(+) - 0, V o < 600 mVdc)
Saturation Voltage
(V| (.) > +1.0 Vdc, V| (+) = 0, Ijink < 4.0 mAdcl
<Vt(_) > +1.0 Vdc, V|(+j 0, I * , * < 6.0 mAdcl
Voltage Gain (VCC " 15 V)
(RL > 1 5 k n )
LM139, 239, 339
LM139A, 239A, 339A
(V|(+) > +1.0 Vdc, V |(.) = 0, V q 5.0 Vdc)
Min
Typ
Max
LM239, \
Min
LM339, A
Max
Typ
Typ
Max
t2.0
1.0
5.0
12.0
3.0
25
-
2.0
1.0
50
5.0
50
nA
250
25
250
nA
Vcc
-1.5
0.8
VCC
-1.5
2.0
0.8
2.0
mA
1.3
1.3
M*
2.0
1.0
25
5.0
100
I-
25
-
5.0
2.0
5.0
2.0
V cc
-1.5
ri
0.8
2.0
1.3
6.0
6.0
16
-
6.0
6.0
16
-
6.0
6.0
16
-
400
500
400
500
400
500
50
200
200
50
200
200
0.1
0.1
mA
'sink
mV
V*at
Aw
PER FO R M A NC E C H A R A C TER ISTIC S Guaranteed Over Temperature Range (Vpc +5.0 Vdc)
-40C to +85C
-55 to +125C
Characteristic
Symbol Min Typ Max Min Typ Max
<v ref +1 -4 Vdc<Vo 1-4 Vdc, Rs 0) LM139,239,339
LM139A, 239A, 339A
v IO
<10
'IB
V|CR
Saturation Voltage
<V|(_) > 1.0 Vdc, V|(+j = 0, liink < 4.0 mAdc)
v sat

(V|(+) > 1.0 Vdc, V |(.) = 0, Vo 30 Vdc)
(All V| > 0 Vdc)
OL
Unit
mVdc
OL
Input Bias Current

Min
0.1
0 to 70C
Typ Max
Min
jjA
Unit
mV
19.0
4.0
VCC
-2.0
700
V|D
50
200
200
9.0
4.0
9.0
4.0
150
150
400
400
nA
VCC
-2.0
VCC
-2.0
Vdc
700
700
mV
1.0
1.0
1.0
MA
36
36
36
Vdc
100
300
nA
"
Note* 1. The input common-mode voltage or either input signal voltage should not be allowed to go negative by more than 300 m V. The
upper end of the common-mode voltage range is Vcc 1-5 V, but either or both inputs can go to +30 Vdc without damage.
2. The response time specified is for a 100 mV input step with S mV overdrive. For larger signals, 300 ns is typical.
FIGURE 2 - INVERTING COMPARATOR WITH HYSTERESIS
FIGURE 3 - NON-INVERTING COMPARATOR WITH HYSTERESIS
+Vcc
+ VCC
R 2 R 1 //R r e F
R 3 =* R l / / R
VH -
r e f
R 1 //R R E F
R 1 //R R E F
* R2
// Rl
A m o u n t o f H y s ts re s ls
"Vomlnl
VH '
7-8
R2
TY P IC A L C H A R AC TER ISTIC S
(V c c
Vdc, T a +2 5 C (each comparator) unless otherwise noted.)

INPUT OFFSET VOLTAGE NORMALIZED TO 25*C
FIGURE 4 - NORMALIZED INPUT OFFSET VOLTAGE
T I * !5C
T
2
i5C
12
12
16
Vcc (Vdc)
FIGURE 7 - OUTPUT SINK CURRENT versus
OUTPUT VOLTAGE
INPUT OFFSET CURRENT NORMALIZED TO 25*C
FIGURE 6 -.NORMALIZED INPUT OFFSETlCURRENT
VSAT. OUTPUT SATURATION VOLTAGE (mV)
FIGURE S - SQUAREWAVE OSCILLATOR
FIGURE 8 - DRIVING LOGIC

VCc
+V CC > 4 V
100 k
-W A r -
-O V o
VCC
+VCc<
1/4 L M 13 9 , 13 9 A
Rs
T1 |
- S o u rc o R e sistan ce
LOGIC
CMOS
TTL
DEVICE
1/4 MC14001
1/4MC7400
Vcc
Volts
+ 15
+6
T 2 I - ------
R l RS
Rl
kn
T 1 - T 2 - 0 .6 9 R C
f
100
10
7 .2
C O iF )
Af -
R 2 - R 3 - R4
R l * R 2 //R 3 //R 4
7-9
These quad comparators feature high gain, wide band
width characteristics. This gives the device oscillation ten
dencies if the outputs are capacitively coupled to the
inputs via stray capacitance. This oscillation manifests it
self during output transitions (V o l . to V o h )- T o alleviate
this situation input resistors < 1 0 k2 should be used. The
a d d itio n o f po sitiv e fe e d b a c k ( < 1 0 m V ) is-also

re c o m m e n d e d .
It is good design practive to ground all unused pins.
Differential input voltages may be larger than supply
voltage without damaging the comparator's input voltages.
More negative than - 3 0 0 m V should not be used.
FIGURE 10 - ZERO CROSSING DETECTOR

(Single Supply)

(Split Supplies)
V | N m in * 0 . 4 V p e a k f o r I K p hase d is t o r t io n (@ ).
D 1 prevent* in p u t fro m g o in g negetivo b y m oro then 0 .6 V .

R1 + R2 R3
R3 <
fo r im a ll e rro r In z e ro cro ssing
7-10
MOTOROLA
<8 >
QUAD COMPARATOR
QUAD SINGLE SUPPLY COMPARATOR
This com parator is designed fo r use in level detection and lowlevel sensing applications in Consumer, A u to m o tive and Industrial
electronic applications.
Power Supply O ptions Single Supply = 2.0 to 36 Vdc

Split Supplies = 1.0 to 18 Vdc
Wide Operating Tem perature R an g e -----40 to +85C
Low Supply C urrent Drain 2.0 m A (Max)
Low Inp u t Biasing Current - 25 nA (Typ)
Low Input O ffset Voltage 2.0 mV (Max)
T T L and CMOS C om patible
N S U F F IX
CASE 646
\y
M A X IM U M R ATIN G S
Rating
Power S up p ly
Voltage
S ym b ol
Value
U n it
v Cc
* 3 6 o r -1 8
Vdc
O u tp u t (
2
LL
I O u tp u t
E
3
O u tp u t [ I
^ O u tp u t
In p u t D iffe re n tia l V olta g e Range
V ID R
36
V dc
In p u t C o m m o n Mode V oltage Range
V ICR
-0 3 to +36
V dc
O u tp u t S ink C u rre n t
'sin k
20
mA
P ow er D issipa tion @ T / \ - 2 5 C
Pd
1.25
W atts
m W /C
In p u t r
1 E
10
Ta
-4 0 to +85
-6 5 to +150
- In p u t t
2
H .
| + ln p u t
_1J
3
T stg
Plastic Package
Derate above 2 5 C
O perating A m b ie n t T e m p eratu re Range
Storage Tem perature Range
12] G n ii
v c c [T
- in p u t
+ ln p u t
+ In p u t I
2
UL
3
T o p V ie w
FIG U R E 1 - C IR C U IT S C H E M A T IC
7-11
- in p u t
- 'T '
LM2901N
(V Cc *5 .0 Vdc. TA - 25C unless otherwise noted.)
Min
Typ
Max
Unit
2.0
7.0
mVdc
5.0
50
25
250
nA
nA
V ICR
V cc -1-5
Supply Current
(RL - - I
Response Time (Note 2)
(V r l 5.0 Vdc. RL S.1 M l)
cc
'EE
0.8
2.0
mA
1.3
(i*
Output Sink Current

(V|(_) > +1.0 Vdc. V|(+) - 0, V o < + 1 5 Vdc)
'sink
6.0
16
Saturation Voltage
(V_, > +1.0 Vdc, V|(+) " 0, lt iit - 4j0 mAdc)
Vsat
400

(V|(+) > +1.0 Vdc. V|(_) - 0, V q - 5.0 Vdc)
'OL
Symbol
Characteristic
(Vref 1.4 Vdc. V o 1.4 Vdc. RS 0)
Input Bias Current
Input Common Mode Voltage Range (Note 1)
V |0
<10
'IB
"
mA
mV
0.1
Notes 1. The input common-mode voltage or either input signal voltage should not be allowed to go negative by more than 300 mV. The
upper end of the comtnon-<node voltage range is Vcc 1-5 V. but either or both inputs can go to -1-30 Vdc without damage.
2. The response time specified is for a 100 mV input step with 5 mV overdrive. For large signals, 300 ns is typical.
FIGURE 2 - INVERTING COMPARATOR WITH

HYSTERESIS
FIGURE 3 - NON-INVERTING COMPARATOR WITH

HYSTERESIS
V CC
*V CC
R 2 R 1 //R R E f.
A m o u n t o f H y ste re sis V
vH.
R 1 //R
R 1 //R
EP
vH.
F + R2
7-12
R2
* Vomin)
LM2901N
(VCC +15 Vdc, T /\ = +25C unless otherwise noted.)
FIGURE S - INPUT BIAS CURRENT
FIGURE 7 - OUTPUT SINK CURRENT versus

OUTPUT VOLTAGE
FIGURE 6 - NORMALIZED OFFSET CURRENT
VsAT. OUTPUT SATURATION VOLTAGE (mVI
FIGURE 9 - SQUAREWAVE OSCILLATOR
FIGURE 8 - DRIVING LOGIC
t v CC > 4 V
Vcc
1/4 LM2901N
>vc c O
R g - S o u rc o R s t it t s n c o
R1 => Rs
LOGIC
CMOS
TTL
DEVICE
1/4 MC14001
1/4 MC7400
Vcc
Voltf
+ 15
5
Rl
kft
c im f )
100
10
R2 - R3 - R4
R 1 R2//R3//R4
7-13
LM2901N
The LM 2901N is a quad comparator having high gain,
wide bandwidth characteristics. This gives the device oscil
lator tendencies if the outputs capacitively couple to the
inputs via stray capacitance. This oscillation manifests
itself during output transitions (V o l t0 VOH )- T o
alleviate this situation input resistors < 1 0 kJ2 should
not be used. The addition of positive feedback 1 0 m V)

is also recommended
It is good design practice to ground all unused pins.
voltage without damaging the comparators input voltages.
More negative than -3 0 0 m V should not be used.

(Split Supplies)

(Singta Supply)
v IN m in
V |N
D 1 p ro vo ntt in p u t fro m g o in g negatlvo b y m oro than 0 .6 V .

R l R2 - R3
R3 <
71
fo r sm a ll erro r in zero crossing
v P 00*1 *o r 1 * p hase d is t o r t io n (AO).
MOTOROLA
DUAL DIFFEREN TIAL VOLTAGE COMPARATOR

. . . designed fo r use in
memory applications.
level detection,
DUAL
D IFFER EN TIA L
COMPARATOR
low-level sensing, and
Two Separate O utputs
Strobe Capability
High O utp u t Sink C urrent

2.8 m A M inim um (Each Comparator) fo r MC1514
1.6 mA m inim um (Each Comparator) fo r MC1414
D ifferential In p u t Characteristics
Input Offset Voltage = 1.0 m V fo r MC1514
= 1.5 m V fo r MC1414
Offset Voltage D rift = 3 .0 m V / C fo r MC1514
= 5 .0 m V /C fo r MC1414
Short Propagation Delay Time 40 ns typical
O utput C om patible w ith A ll Saturating Logic Forms

V q = +3.2 V to -0 .5 V typical
(D U A L MC1710)
M A X I M U M R ATIN G S (T/^ = 2 5 C unless otherwise noted.)

Symbol
Value
Unit
Vdc
m o
m o
Rating
+14
-7 .0
D ifferential Mode Input Voltage Range
V|DR
5.0
Vdc
Common Mode Input Voltage Range
V|CR
7.0
Vdc
Peak Load Current
'L
10
mA
Power Dissipation (Package Lim itation)

Pd
< <
Derate above T A = 2 5 C
1000
mW
6 .0
m W /C
625
mW
Derate above T A = 25C
5.0
m W /C
-5 5 to +125
M C 1514
ta
0 to +75
M C 1414
T stg
-6 5 to +150
7-15
L S U F F IX
CASE 632
T O -116
P S U F F IX
CASE 646
(M C 14 1 4 o n ly )
MCI 414, MC1514
ELECTRICAL CHARACTERISTICS ( V c c
" +12 Vdc. V e e
-6
VdcT A 2SC u n le g o th e rw is e noted.) (Each C om parator)
MC1414
MC1514
Characteristic
(V o = 1.4 Vdc, T A 2SC)
(V0 1.8 Vdc,TA T|0w*)
(V0 = 1.0 Vdc, TA Thioh*
Temperature Coefficient of Input Offset Voltage
(V q = 1.4 Vdc, T a 2SC)
(V0 = 1 .8 VdC, T A Tjoyy)
(V0 = 1.0 Vdc, T A T hioh)
Input Bias Current
(V o 1.4 Vdc, T A 25C)
(V0 1.8 Vdc, TA T (ow)
<Vo = 1 .0 V d c .T A Thiah)
Open Loop Voltage Gain
(TA 25C)
t A T|oW to Thioh)
Output Resistance
Symbol
Min
Typ
Max
Min
Typ
Max
Unit
mVdc
V |0
13
5.0
6.5
6.5
5.0
3.0
7.0
3.0
1.0
-
5.0
7.5
7.5
12
-
20
45
20
15
18
-
25
40
40
1250
1000
1700
-
1000
800
-
1500
-
200
-
ohms
5.0
Vdc
Vdc
1.0
-
2.0
3.0
3.0
3.0
1.0
-
AV(q /AT
MV/C
MAdc
*10
fiAdc
'IB
V /V
Avol
Ro
200
Differential Voltage Range
V|DR
5.0

(V |D > 5 .0 mV, 0 < I q < 5 .0 mA)
Vo h
2.5
3.2
4.0
2.5
3.2
4.0
-1.0
-
-0.5
-
-1.0
-0.5
'o s
2.8
3.4
0
-
1.6
2.5
0
-
mAdc
V|CR
5.0
5.0
Vdc
CMRR
80
100
70
100
dB
Strobe Low Level Current

(V| t_ = 0)
'IL
2.5
25
mA
Strobe High Level Current

(V jh <= 5.0 Vdc)
lH
1.0
1.0
MA
Strobe Oisable Voltage

(V0 L < 0 .4 V d c )
V |L
0.4
0.4
Vdc
Strobe Enable Voltage

(V0 H > 2 .4 Vdc)
Propagation Delay Time (Figure 1)
V|H
3.5
6.0
3.5
6.0
Vdc
*PLH
*PHL
20
40
ns
20
40
so
sr
15
6.0
cc
'EE
12.8
11
18
14
PD
230
300

(V ,o > - 5 .0 mV, I q s 2.8 mA)
(V|Q > - 5 .0 mV, I q s 1-6 mA)
Output Sink Current
(V|D > - 5 .0 mV, V0 L < 0.4 V, TA - T,ow to T hteh)
(Vgg 7.0 Vdc)
Common-Mode Rejection Ratio
(Vgg - 7 0 vdc. Rs < 20 0 n )
Strobe Response Time (Figure 2)

Total Power Supply Current, Both Comparators
(V0 < 0 )
Total Power Consumption, Both Comparators
Vdc
vol
15
6.0
12.8
11
18
14
mAdc
230
300
mW
T|ow -5SC for MCi514, 0C for MC1414

Thigh" +125C for MC1514, +75C for MC1414
FIGURE 2 - STROBE RESPONSE TIME
7-16
RS
MC1414, MC1514
T YPIC A L CHARACTERISTICS
(Each Comparator)
FIGURE 3 - VOLTAGE TRANSFER
CHARACTERISTICS
FIG U R E 4 - IN P U T OFFSE T V O L T A G E
v a rtu * TE M P E R A TU R E
Ta. AMBIENT TEMPERATURE PC)
FIGURE 5 - INPUT OFFSET CURRENT

versus TEMPERATURE

versus TEMPERATURE
Ta . ambient temperature pci
FIGURE 8 - VOLTAGE GAIN

versus TEMPERATURE
FIGURE 7 - GAIN VARIATION

WITH POWER SUPPLY VOLTAGE
Ta. ambient temperature m
7-17
MC1414, MC1514
F IG U R E 10 - POWER D IS S IP A T IO N
versus T E M P ER A TU R E
FIG U R E 9 - RESPONSE T IM E
-25
25
50
75
100
12S
TA. AMBIENT TEMPERATURE (OC)
FIGURE 11 - RECOMMENDED SERIES RESISTANCE

versus MRTL LOADS
FIGURE 12 - SINK CURRENT versus TEMPERATURE
ZS
50
Ta . TEMPERATUREPC)
FIGURE 13 CROSSTALK*
*Womcat comfitimA o n - no lo*&
7-18
75
too
125
<>
MOTOROLA
D IFFER EN TIA L
COMPARATORS
D IFFER EN TIA L VO LTA GE COMPARATORS

...d e s ig n e d fo r use in
memory applications.
level detection,
low-level sensing, and
D ifferential In p u t Characteristics
Inp u t Offset Voltage = 1.0 m V MC1710
= 1.5 m V MC1710C
Offset Voltage D r ift = 3 .0 /iV / C - M C1710
= 5 .0 /iV / C MC1710C
Fast Response Tim e 40 ns
O u tp u t C om patible w ith all Saturating Logic Forms

V q = +3.2 V to -0 .5 V (Typ)
Low O u tp u t Impedance 200 Ohms
CASE 601
M A X IM U M R ATIN G S (T a = +25C unless otherwise noted.)

Rating
Symbol
Value
Unit
V cc(m ax)
ÊE(m ax)
+14
-7.0
Vdc
Vdc
V ID
5.0
Volts
V ICR
7.0
Volts
L SU FFIX
'L
10
mA
CASE 632 02
T O -1 16
Metal Package
Derate above T a - +25C
680
4.6
mW
mW/C

Derate above T a = +25C
625
5.0
mW
mW/C
ta
-55 to +125
0 to +75
Tstg
-65 to +150
Differential Input Signal Voltage

Common Mode Input Swing Voltage
Peak Load Current
Power Dissipation
(Package Limitations)

PD
MC1710
MC1710C
E Q U IV A L E N T C IR C U IT
P SU FFIX
CASE 646
(M C 17 1 0C O n ly )
7-19
MC1710, MC1710C
ELECTRICAL CHARACTERISTICS IVcc "
+*2 Vdc. V e e *

(Vo - 1.4 Vdc, T a - +25C)>
(V q
V0
(Vq
(V0
-6.0 Vdc. T A
...
Characteristic
MC1710
MC1710C
MC1710
MC1710
1 8 Vdc, TA - -55C)
1.0 Vdc.T&d +125C; ;
1.5 Vdc, T X 0C)
;'
1.2Vdc,TA =+7SC)
1.0
1.0
v~ "
Unit
(Vo 1 .5 V d c .T A -0 C )
(Vo - 1 2 Vdc. TA - +75C)
MC1710C
MC1710C
Input 6iasCurrent
(Vo 1.4 Vdc. T a - +25C)
8.5
6.5
3.0
1.0
12
12
20
25
45
20
mV/C
, 3.0
5.0
1.0
7.0
3.0
7.5
7.5
'
pAdc
1IB
MC1710
MC1710C
MC1710
MC1710
MC1710C
MC1710C
1 8 Vdc. TA -55C)
1.0 Vdc. T A +125C)
1.5Vdc,TA = 0C)1.2 Vdc, TA - +75C)
' :
3.0
3.0
ft Adc
MC1710
MC1710C
MC1710
MC1710
5.0
AV|q /AT
(V0 1.8 Vdc, T A - -55?C)

(V0 * 1.0 Vdc,TA - +125C)
2.0
<10
Voltage Gain
(TA = +25C)
Max
Typ
mVdc
MC1710C
MC1710C

(Vo - 1.4 Vdc, T A - +25C)
40
- -
4 0 M. :
v/v
lV Ayol
~
I
(TA " T | o w *0 Thigh) 111
Min
VlO
(Vq
(Vo
(V o
(Vq
= +25C unlew otherwise noted.)
Symbol
'
Output Resistance
MCI 710 ~
MC1710C
1250
1000
---- MCI 710

^MC1710C
1000
800
1700
1700
---------------
-_
_
200
r0
V|D
5.0
Positive Output Voltage

(V10 > 5.0 mV. 0 < lo < 5.0 mA)
v OH
2.5
3.2
4.0
Vo l
1
-1.0
-0.5
Negative Output Voltage

(V|0 > -5 :0 mV)
---
Output Sink Current

(V|0 > -5 .0 m V , VO < 0 )
(V ,D > - 5 .0 mV, V0 > 0, TA = T(ow)
Vdc
Vdc
MC1710
M CI7IOC
2.0
1,6
1.0
0.5
80
70

(V0 < 0 )
d + - >
'
Volts
dB
...
MC1710
MC1710C
100
100
40
35
ns
mAdc
-
|Q-
Pd
- ------------
. - _ .
2.5
2.5
2.0
5.0
VlCR
CMRR
Vdc
'
mAdc
tPLH
tPHL^
(1) T|ow -55C forM C 1710.0(,CforMC1710C

Thigh +125C for MCI 710, +75Cfor MC1710C
Ohms
Propagation Delay Time for Positive and Negative Going Input Pulse
(VtD 5.0m V + V ,0 )
Power Consumption
...1
'Os
MCI 710
MC1710C

|V E E . . -7.0 Vdc)
Common-Mode 'Rejection Ratio
(V e e " -7-0 Vdc, R$ < 200 Ohms)
6.4
5.5
115.
9.0
7.0
..
ISO
mW
MC1710, MC1710C
FIGURE 1 - VOLTAGE TRANSFER
CHARACTERISTICS
FIGURE 2 - INPUT O FFSET VO LTA G E

versus TEMPERATURE
_____
MCmO'N CWIOC
ly
m c u io o i
s '*
*25
S0
t a . a m b ie n t t e m p er at u r e i ci
FIGURE 3 - INPUT OFFSET CURRENT

versus TEMPERATURE

versus TEMPERATURE
FIGURE S - GAIN VARIATION

WITH POWER SUPPLY VOLTAGE
FIGURE 6 - VOLTAGE GAIN

versus TEMPERATURE
7-21
*100*125
MC1710, MC1710C
TYPICAL CHARACTERISTICS (Continued)

FIGURE 7 - RESPONSE TIME
FIGURE 8 - POWER DISSIPATION versus TEMPERATURE

______
25
*S0
MC17I 0. KC17I 0C
MC17I 0 I nly
75

versus MRTL LOADS
FIGURE 10 - FAN-OUT CAPABILITY

WITH MOTL OR MTTL OUTPUT SWING
FAN OUT CAPABILITY
MOTOROLA
K ill I
MC1711C
DUAL D IFF ER EN TIA L

COMPARATOR
DUAL D IFFER EN TIA L VO LTA GE COMPARATOR

. . . designed fo r use in level detection, low-level sensing, and memory
applications.
Typical Characteristics:
D iffe ren tia l In p u t

Inp u t O ffset Voltage = 1.0 mV
O ffset Voltage D rift = 5 .0 p V / C
Fast Response Tim e - 40 ns

O u tp u t C om patible w ith A ll Saturating Logic Forms
V o u t = + 4-E3 V to -0 .5 V typ ical
Low O u tp u t Impedance 200 ohms
G SU FFIX
M E T A L PAC KAG E
CASE 603
T Q -1 00
M A X IM U M R A TIN G S (T a = + 25C unless otherwise noted.)

Symbol
Value
Unit
Vcc
VEE
+ 14
-7.0
Vdc
Differential Input Signal Voltage
V IDR
5.0
Volts
Common-Mode Input Swing Voltage
V ICR
7.0
Volts
Peak Load Current
50
mA
Power Dissipation (package lim itation)

Metal Package
Derate above 1 ^ = +25C
Pd
680
4.6
625
5.0
mW
mW/C
ta
-55 to +125
0 to +75
T stg
-6 5 to +150
Rating
Ceramic and Plastic Dual In-Line Packages

Derate above T /\ = +25C
MC1711
MC1711C
L SU FFIX
CA S E 632
T 0 -1 1 6
mW
mW/C
P SU FFIX
CASE 6 46
(M C 1 7 1 1C o n ly )
C IR C U IT SCHEMATJC
C o nn e cte d to p in 4 via tho substrate on

soma p lastic u nits.
7-23
MC1711, MC1711C
E L E C T R IC A L C H A R A C T E R IS T IC S (each comparator) (V^c +12 Vdc, Vgg - -6.0 Vdc, T a +25C unless otherwise noted.)
MC1711
Characteristic
(V ,CR 0 Vdc. T A = +25C)
(V |CR * 0 Vdc. T A - +25C)
(V |CR 0 Vdc, T A - T low to Thigh*)
( V ic r * 0 Vdc, T A = T|0W to Thigh)
Symbol
Min
MC1711C
Typ
Max
Min
Max
Typ
Unit
mVdc
V io
-
1.0
1.0
-
3.5
5.0
4.5
6.0
1.0
1.0
-
5.0
7.5
6.0
10
5.0
S.O
0.5
-
10
20
20
-
0.5
-
15
25
25
75
150
150
-
25
-
25
-
700
500
1500
-
700
500
1500
-
Ro
200
200
V IDR
5.0
5.0
Vdc

(V |D > 10 mVdc, 0 < lo < 5 .0 mA)
v OH
2.5
3.2
5.0
2.5
3.2
5.0
Vdc

(V|D > - 1 0 mVdc)
v OL
-1.0
-0.5
-1.0
Vdc
v OL(st)
-1.0
-1.0
Vdc
Output Sink Current

(V in > - 1 0 m V . V o > 0 )
'Os
0.5
0.8
0.5
0.8
mAdc
Strobe Current
<v strobe= 100 m Vdc)
st
1.2
2.5
1.2
2.5
mAdc
V ICR
5.0
5.0
Volts
Response Time
(V b = 5.0 mV + V ,0 )
*R
40
40
ns
Strobe Release Time
l SR
12
12
ns

(V0 <O V d c)
ice
<EE
mAdc
8.6
3.9
130

(V0 - 1.4 Vdc, T A
(V0 1.8 Vdc,TA
<V0 = 1.5 Vdc. T a
(V o = 1 0 Vdc, T A
<V0 1 .2V dc,TA
Input Bias Current
(Vo = 1.4 Vdc, TA
(V q = 1.8 Vdc, T A
(Vo = 1-5 Vdc, T A
(V0 = 1.0 Vdc, T A
(V0 = 1-2 Vdc, T A
A V| q /AT
+25C)
-55C)
- 0C)
= +125C)
-+ 7 5 C )
lB
+25C)
- -55C)
0C)
+125C)
= +75C)
Voltage Gain
(TA = +25C)
(TA = T|0VV to Thigh^
Output Resistance
Strobed Output Level

<Vrtrobe<0.3Vdc)
Input Common-Mode Range

(V EE = -7.0 Vdc)
Power Consumption
*T|ow -55C for MC1711, 0C for MC1711C
Thigh= +125C for MC1711, +75C for MC1711C
<iV/C
/lAdc
'10
jiAdc
-
100
150
150
V /V
AVol
-0.5 .
8.6
3.9
200
130
ohms
200
mW
MC1711, MC1711C
TYPICAL CH ARACTERISTICS
FIG U RE 1 - V O LT A G E
T R A N S FE R C H AR AC T ER IST IC S
F IG U R E 2 - IN PUT B IA S C U R R E N T
versus T E M P E R A T U R E
FIG U RE 3 - V O LT A G E G AIN
versus TE M P ER A TU R E
FIG U R E 4 - RESPONSE T IM E
FOR V A R IO U S INPU T O V E R D R IV E S
150
( V /V )
> >
T a = *2 5 C
50
GAIN
H- E
LOOP VOLTAGE
3
i
0
-5 0
A vol. OPEN
FIG U R E 6 - STROBE RELEASE T IM E

FOR V A R IO U S INPU T O V E R D R IV E S
P0 . dc POWER
DISSIPATION
ImW)
FIG U R E 5 - V O L T A G E G A IN V A R IA T IO N
W ITH POWER SUPPLY V O LT A G E
MC1711
M C 1 71 I
O nly
60
-4 0
-2 0
O nly
0
<20
*4 0
60
80
+100
+120
*1 40
I. T IM E (ns)
T A . A M B IE N T T E M P E R A T U R E . ( Cl
7-25
C C * 12V
V EE * -6 0 V
+100
MC1711,MC1711C
FIGURE 7 - COMMON-MODE PULSE RESPONSE
F IG U R E 8 - O U TP U T PULSE S T R E T C H IN G
W IT H C A P A C IT IV E L O A D IN G

versus MRTL LOADS -
FIGURE 10 - FAN-OUT CAPABILITY

WITH MDTL OR M TTL OUTPUT SWING
V ////A
MINIMUM HIGH STATE

"T T L .
8
6
MOTL, MTTl - /
INPUT VOlTACe\
h9
V
MAXIMUM LOW STATE-^
1
g
m tu . mot 1
.
Rj. SERIES RESISTANCE (k OKilS)
/ 7
____________________ J
MOTL
4
ACTUAL OUTPUT
SWING
t v
' /. MCIJ1I
IICI71IC |
t-w v
i
k (A
tori
FAN OUT CAPABILITY
MOTOROLA
QUAD SINGLE-SUPPLY COMPARATOR
QUAD COMPARATOR
These com parators are designed specifically fo r single positivepower-supply Consumer A u to m o tive and Industrial electronic ap
plications. Each MC3302 contains fo u r independent comparators
suiting it ideally fo r usages requiring high density and low-cost.
Wide Operating Temperature Range - -40 to +85C
Single-Supply O peration - +2.0 to +28 Vdc
D ifferential Inp u t Voltage = V c c
Compare Voltages at Ground Potential
M TT L C om patible
P S U F F IX
CASE 646
Low C urrent Drain 700 /jA typical @ V c c +5.0 to +28
O utputs can be Connected to Give the Im plied AN D Function
Vdc
M A X IM U M R ATIN G S (T a = + 2 5 C unless oth e rw ise noted.)

R ating
Power S up p ly Range
O u tp u t S in k C u rre n t (See N o te
1)
S ym b ol
Value
vCc
<0
+ 2 .0 to +28
U n it
V dc
20
mA
D iffe re n tia l In p u t V oltage
V ID R
i V CC
V dc
C om m on-M ode In p u t V oltage Range (See N o te 2)
V ICR
-0 .3 to + V c c
V dc
1.2
10
W atts
m W /C
W atts
Power D issipation @
T^
- 2 5 C
Derate above 2 5 C
Ceram ic Package L S u ffix
1.2
10
Derate above 2 5 C
E Q U IV A L E N T C IR C U IT
m W /C
C
ta
- 4 0 to +85
-5 5 to +125
Plastic Package
Ceramic Package
Storage Tem perature Range
F IG U R E 1 -
PD
Plastic Package P S u ffix
O perating A m b ie n t T e m p eratu re Range
L S U F F IX
CASE 6 32
T O -1 16
T stg
- 6 5 to +150
N o te 1.
Requires an e xte rn a l resistor, R
,0 ,im it cu rre n t b e lo w m a xim u m rating.
N o te 2.
If e ith e r (+) or (-) in p u ts o f any co m p a ra to r go m o re than several tenths o f a v o lt

b e lo w g ro un d, a p arasitic tra n sisto r turns " o n " causing high in p u t cu rre n t and
possible fa u lty o u tp u ts .
7-27
Vcc - PIN 3
GROUND - PIN 12
MC3302
ELECTRICAL CHARACTERISTICS (Vcc

Characteristic Ooftaitiorts
(1/4 Circuit Shown),
. .
o 'p
v 0
^ o *
ill
/
All
JL
^ 7
l|0-Ulll-lllll
, Hl| ~
>it
vio BM-vi
vcej
-
Il*
\
1I
Y ,?
4*
Characteristic Input Offset Voltsge (Vr#f >1.2 Vdc)

(TA - 2SC)
(TA - -40 to +85C)
vee
+15 Vdc, T a +2SC (each comparator) unless otherwise rvoted.)
VccT 1 *"
\
'
"
ij
VO
?
T '*
Qi
vet*
>IO
Input Bias Current

(TA - +25C)
(TA -40 to +85C)
>IB
|A
300 *V
v .e
_______
e$
20
40
3.0
30
500
1000
2.000
.30,000
2.0
V|DR.
v cc

(I, 2.0 mA. Vcc + 5 0 t o +28 Vdc:
V0 L
Output Sink Current

(Vcc +5-0 Vdc)
(TA - +26C, V0 L 400 mV)
(Ta - -4 0 to +85C. V0 L 800 mV)
sink
Transition Time
(R|_ * 15 kH)
7-28
mhos
Vdc
jiAdc
-
-ii. -
1.0
ISO
400
mVdc
mAdc
6.0
2.0
Volts
V|CR
0-26
CMRR
' -
60
2.0
0.15
0.8
dB
*PHL/LH
*THL
TLH
Power Supply Current (Total of four

comparators)
(RL V c c " +5 j0 to +28 Vdc)
nAdc
V/V
>OL
Unit
nAdc
gm

For Positive and Negative-Going
Input Pulse
(R|_ 15 M l)
3.0
Transconductance
CommOn-Mode Rejection Ratio
vce
Avol

(OutputVoltage,High)
Max
Typ
mVdc
Voltage Gain
<TA - +25C, RL 15 kHJ

(Vcc +28 Vdc)
?)v ,
.M in
V |0
input Differential Voltage Range
Symbol
V*
PS
mAdc
ic e
<EE
-
0.7
13
MC3302
( V q c +' 5 Vdc.
+25C (each comparator) unless otherwise noted.)
FIGURE 4 - NORMALIZED OFFSET CURRENT
TYPICAL APPLICATIONS
The M C 3302 is a quad comparator having high gain,
be used. The addition of positive feedback {1 to 10 m V)
wide bandwidth characteristics. This gives the device

oscillator tendencies if the outputs capacitively couple
to the inputs via stray capacitance. This oscillation mani
is also recommended.
It is good design practice to ground all unused pins.
voltage without damaging the comparator's input voltages.
fests itself during output transitions (V o L t0 v OH)To alleviate this situation input resistors < 10 k f l should
More negative than - 3 0 0 m V should not be used.
7-29
MC3302
TYPICAL APPLICATIONS (continued)
FIGURE 6 - FREE-RUNNING SQUARE-WAVE OSCILLATOR
FIGURE 7 - TIME DELAY GENERATOR
FIGURE 8 - COMPARATOR WITH HYSTERESIS
vcc
Rl
, 1VCC-V.tl)t
Rl R2Ri
(V )-V 0 Low) R1
Vih2*V,riRl R2 Rl
Vthl Vfct
7-30
MC3430
thru
MOTOROLA
MC3433
QUAD D IFFER EN TIA L VOLTAGE
COMPARATOR/SENSE AMPLIFIERS
The M C 3430 th ru M C3433 high speed comparators are ideal fo r
application as sense am plifiers in MOS memory systems. They are
specified in a unique way w hich combines the effects of in p u t offset
voltage, in p u t offset cu rren t, voltage gain, temperature variations
and inp u t comm on-m ode range in to a single fun ctio na l parameter.
This parameter, called In p u t S ensitivity, specifies a m inim um d iffe r
ential inp u t voltage w hich w ill guarantee a given logic state. Four
variations are offered in the com parator series.
The MC3430 and MC3431 versions feature a three-state strobe
input com m on to all fo u r channels w hich can be used to place the
fo u r o utputs in a high-impedance state. These tw o devices use
a ctive-p u ll-u p M T T L com patible outputs. The M C3432 and MC3433
are open-collector types w hich perm it the im plied AN D connection.
The MC3430 and MC3432 versionsare specified fo r a 7 .0 m V input
sensitivity over the 0 to 7 0C temperature range, w hile the MC3431
and M C3433 are specified fo r 1 2 m V.
Propagation Delay Time 40 ns
O utputs Specified fo r a Fanout o f 10 (M C7400 type loads)
Specified fo r all co nd itio ns o f 5% Power Supply Variations,

Operating Tem perature Range, In p u t Common-Mode Voltage
Swing fro m -3.0 V to 3.0 V, and Rs ^ 200 ohms.
7-31
QUAD HIGH-SPEED
VO LTAGE COMPARATORS
SILICON MONOLITHIC
INTEGRATED CIRCUITS
L S U F F IX
CASE 6 20
P S U F F IX
CASE 648
MC3430, MC3431, MC3432, MC3433
MAXIMUM RATINGS (Ta 0 to +7QPC unless othervvita notad.)

Rating
Differential Mode Input Signal Voltage Range
Symbol
Value
Unit
VCC- V EE
7.0
6.0
Vdc
Vdc
5.0
Vdc
5.5
Vdc
+7.0
Vdc
V|DR
V ICR '
V I(S)

Output Voltage (MC3432 33 vcrcions)
v0
Ceramic Package
Plastic Package
Tj
Operating Temperature Ranga

Storage Temperature Ranga
175
150
Ta
0 to +70
Tstg
-65 to +150
Typ
+5.0
-5.0
Max
+5.25
-6.25
Unit
16
+5.0
+3.0
mA
+3.0
RECOMMENDED OPERATING CONDITIONS (Ta 0 to +70C unless otherwise noted.)

Characteristic
Symbol
Min
Vcc
V ee
+4.75
-4.75

Output Load Current
Common-Mode Input Voltage Ranga
Input Voltage Range (any input to Ground)
<OL
V|DR
V|CR
V|R
-5.0
-3.0
-5.0
Vdc
Vdc
Vdc
Vdc
ELECTRICAL CHARACTERISTICS (Vcc 5.0 Vdc, V ee * -5.0 Vdc. T a 0C to +70C unlen otherwise noted.)
___________________________________ Typical Values are Measured at T a 25C_____________________________
MC3430. MC3431
MC3432, MC3433
Characteristic
Symbol
Min
Max
Min
Typ
Max
Typ
Input Sensitivity (See Oiscussion on Page 3)
VlS
(RS < 2 0 0 Ohms)
(Common Mode Voltage Ranga = -3.0 V < V;n < 3.0 V)
4.75 < VCC < 5.25 V
0
( MC3430, MC3432
6.0
6.0
- 4 .7 5 > V EE > - 5 .2 5 V A
MC3431.MC3433
10
10
(Common Mode Voltage Range = -3.0 V < V ;n < 3 .0 V)
4.75 < VCC <5-25 V
7Q0 i MC3430. MC3432
7.0
7.0
- 4 .7 5 > V ee > -5 .2 5 V A
MC3431, MC3433
12
12
2.0
2.0
~
VlO
(RS < 2 0 0 Ohms)
Input Bias Current
lB
_
_
20
(Vcc " 5.25 V, V EE *5.25 V)
MC3430, MC3432
40
20
40
MC3431. MC3433
20
40
40
20
1.0
1.0
to
Voltage Gain
1200
1200
Ayol
Strobe Input Voltage (Low State)
0.8
0.8
V IL(S)
Strobe Input Voltage (High State)
V|H(S)
2.0
2.0
Strobe Current (LowState)
(VCC 5-25 V. V EE -5 25 V, Vin = 0.4 V)
Strobe Current (High State)
(VCC 5.25 V. V ee = -5 25 V. V in - 2.4 V)
(VCC 5.25 V. V e e " -5-25 V. V in 5.25 V)
Output Voltage (High State)
(lO -4 00 mA, VCC 4.75 V. V E - -4.75 V)
Output Voltage (Low State)
(lO 16mA. VCC " 4 .7 5 V . V EE -4 .7 5 V)
Output Leekage Current
(VCC 4.75 V. V EE -4-75 V, Vq - 5.25 V)
Output Current Short Circuit
(VCC 5.25 V. V ee = -5.25 V)
Output Disable Leakage Current
(VCC 5.25 V. V ee *5-25 V)
High Logic Level Supply Currents
(V cc - 5.25 V. V e e " -5-25 V)
'IL(S)
Unit
mV
mV
iA
ftA
V/V
V
-1.6
-1.6
mA
40
1.0
40
1.0
*iA
mA
V
11HIS)
voh
2.4
vol
>CEX
os
-18
off
ice
ee
7-32
45
-17
0.4
0.4
250
mA
-70
mA
40
MA
60
-30
45
-17
60
-30
mA
mA
MC3430, MC3431, MC3432, MC3433
A UNIQUE FUNCTIONAL PARAMETER FOR COMPARATORS

A unique approach.is"uted in specifying the MC3430-33quad
comparators. Previously, comparators have been specified aslinear
devices with common operational amplifier type parameters such
' as voltage gain (Ayoi), input offset voltage (V |n), input offset
current (I| q ) and common-mode rejection rotio(CMRR). This is
true despite the fact that most comparators are seldom operated in
their linear region because it is diff icult to hold a high gain com
parator in this narrow region. Comparators are normally used to
"detect" when an unknown voltage level exceeds a given reference
voltage.
'
The most desirable comparator parameter is what minimum dif
ferential input voltage is required at the comparators input ter
minals to guarantee a given putput logic state. This new and im
portant parameter has been called input sensitivity (Vjg) and is
analagous tb the input threshold- voltage specification on i core
- memory sense amplifier. The input sensitivity specification in
cludes the effects of voltage gain, input offset voltage and input
offset current and eliminates the need for specifying these three
parameters.
In order to make this parameter as inclusive as possible on the
; MC3430-33 series quad comparators, the input sensitivity is speci
fied within the following conditions:
Commercial Temperature Range 0 to 7(fiC
Power Supply-Variations 5% (all conditions)
-------Input Source Resistance <200 Ohms
Common-Mode Voltage Range - -3.0 V to +3.0 V
Note: Typical values have been included on the omitted parameters ,,

for applications where*'the- offset vditbges are externally nulled.'
Voltage gain is defined as the ratio of the resulting a V q to a
change in the V | q r using conditions at which the V |() and l|Q
are nulled. Thus, for worst case MTTL logic levels, the required
output voltage change is 2.0 V (VoHmin V oi/na* * 2.4 V
-
Type
Number
W o Ayol*
mV V /V
Max T yp
0.4 V). If 2.0 mV ere required at the input terminals to induce

. this change in logic state, the voltage gain would be 1000 V/V.
Gain however it not the only factor affecting the logic tran
sition. Normally input offset voltages, that are not externally
nulled, can add an appreciable error that drastically overshadows
'the comparator gain. Therefore, the 2.0 mV for example, required
to cause the logic transition is often masked. An input offset
voltage of.up to 7.5 mV might be required to reach the linear
region. A further consideration is the input offset current o f up to
10 fiA flowing through the matched 200-0hm source resistors at
the input terminals which can create an additional error of 2.0
mV. In order to determine a worst case input sensitivity, it must
be assumed that minimum specified gain and maximum specified
offset voltage and current conditions exist. Also it must be as
sumed that these three factors are cumulative, requiring a worst
' case input of: '
Logic Transition 2.0 mV
V|0 - 7.6 mV
I io of HO'fiA thru 200-0hm resistor = 2.0 mV
Therefore, 2 + 7.5 + 2 11.5 mV.
The effects of power supply voltage variations, temperature
changes and common-mode input voltage conditions'have not
been considered, as they are not present in the gain and offset
specifications on most comparators.
Thus, the input sensitivity specification greatly reduces the
'1 1effort required in determining the worst case differential voltage
required by a given comparator type.
Teble I compares the' worst case input sensitivity of three
popular comparator types at both room temperature and over the
specified commercial temperature range (0 to 70C). This sensi
tivity was computed from the specified voltage gain, offset voltage
and offset current limits.
TABLE I - WORST CASE COMPARISONS
- i
T a - 2 C
OrifertfltU llnput
Error Voltage
to
Volta g j Required R $ > 2 0 0 (1 Generated Into
for 3 .0 V Output
yA
200 ft Source
Resistors
C hange. Mx , .
Total
Sensitivity
mV
MC3430.
MC3432
MC343I.
MC3433
M C 17 11C
5.0
1500
2.0 m V
15
3.0 m V
10
10
M LM 311
7.5
200 k
0 .0 15 m V
6.0"
0.0012 m V
7.516
6.0
T a 0 to 7 0 C
VlO
mV
^vol*
V /V
Typ
Differential Input
Voltage Required
for 3.0 V Output
1000
10 100 k
5.0
Rs
io
200 n
liA
Max
Error Voltage
Generated Into
200 n Source
Resistors
Total
Sensitivity
mV
7.0
12
3.0 m V
25
5.0 m V
13
0.030 mV
70* *
0.014 m V
10.04
Typical values given. at minimum gein not always specified.

* * I io measured in nA
FIGURE 3 - GUARANTEED OUTPUT STATE versus

INPUTVOLTAGE
FIGURE 2 - GUARANTEED OUTPUT STATE versus

DIFFERENTIAL INPUT VOLTAGE
3.0
1 1 1 1
Cl
Uncti Uinti
H*Ston
----- MC.1430
MC1432
0.5
types ~
Gu*rntMd
VOH
MC3430
MC3432
'n
Guartntutd
Voi All device types
-I
Undtttimintd
Region
(Expended
MC1431
mc:1433
1
4 Voh
' All diviu
.
Umti
R|ion
VOL ;
4C3430
AC3432 2
-3 0V < V ira < 3 ov

4.75 V < VCC < 5.25 V
-4 75 V> VE > -5-25V
GIC<Ta<70C-----1
1
1
3S -30 -25 -20 -IS -10 -5
0
S 10 IS 20
DIFFERENTIAL INPUT VOLTAGE (mV)
1
l
25 30
Vin(B)
J5tt
1
35
VinW
Guv* iteed
L
Su e
1
RS<200n
-3.0 V V|CR<3.0V
0C<T a <70C
4.75 V < Vcc 5-25 V
-4.75 V > Vee -5.25 V
<
>
Vin(A). INPUT VOLTAGE (VOLTS)
7-33
----0 V&ut
MC3430, MC3431, MC3432, MC3433
S W ITC H IN G C H A R A C TE R IS T IC S IVgc1 +5.0 Vdc, Vgg * -5.0 Vdc,
* +25C uhless otherwise noted.)

MC3430, MC3431
MC3432, MC3433
Characteristic
Symbol
Fig.
Min
Typ
Max .
High to Low Logic Level Propagation Delay

Time (Differential Input*) 6.0 mV + V|s
Low to High Logic Level Propagation Delay
Time (Differential Inputs) 5.0 mV + Vis
Open State to High Logic Level Propagation '
Delay Time (Strobe)
High Logic Level to Open State Propagation
Delay Time (Strobe)
tPHUD)
63-11
20
45
tPLH(D)
6,8-11
33
55
tPZH(S)
tPHZ(S)
Open State to Low Logic Level Propagation

Delay Time (Strobe)
tPZL(S)
Low Logic Level to Open State Propagation

Delay Time (Strobe)
tPLZtSI
High Logic to Low Logic Level Propagation

Delay Time (Strobe)
*PHL(S>
Low Logic to High Logic Level Propagation

Delay Time (Strobe)
*PLH(S)
Min
Typ
Max
27
50
Unit
ns
40
65
ns
35
ns
35
ns
40
ns
35
ns
40
ns
35
ns
cL
I S pF
SO p F
TEST CIR C U ITS

FIGURE 4 - STROBE PROPAGATION DELAY TIMES tpLZ(S), tpZL(S), tpHZ(S)snd *PZH(S)
S.O V
*PLZ(S>
*PZL( 8)
*PHZ< 8)
VI
V2
SI
S2
10 0 m V
10 0 m V
GND
GND
C tO M d
Ctoaad
Open
GND
GND
100 m V
tpZK(S)
10 0 m V
Clo iad
Clo tad
lO p a n
Cloaad
C lo n d
C L ln clu d M |lg < n d proba capadtanca.

E j,, waveform charactarlttici:
t r L H a n d t T H L < 10 n * n>aaturod 1 0 % to 9 0 % .
E|n
1 7
>v------ -
* P H Z (S )<
tP L Z (S )
Eo
Vq
* P H Z (S ) .
0 .6 V
Bin
ov*P Z L<S )
-t P Z H t S )
'P Z H t S )
Eo
VOL
7-34
VOH-------------y ^ ) .5 V
I S pF
50 pF
MC3430, MC3431, MC3432, MC3433
FIGURE6 - STROBEPROPAGATIONDELAYtp|.H(S) AN0 <PHL(S)

9.0 V
3.0 V --------
Eln
0V
PLH(S)
6o
vqh
Vq l -
Etn wtvtform chtrtcttrfitics:
t-pLH ttnd *T H L ^ 10 n t m onured 10% to 90%.

P R R - 1.0 M H z
O uty C vcto - S O *
FIGURE6 - DIFFERENTIALINPUTPROPAGATIONDELAYt p L H (D> ANDtpHL(D)

5.0 V
v re f +
v is
+6.0 m V --------y
i
V REF
0 V ------ *
*PHUOI
P L H (0 (
VO H
Eo
VOL-
_A
E|n waveform chtractarlttict:

Output of Chtnrwt 0 shown undr t#*t, other chtnnols
S I ot " A " fo r MC3430, MC3431

S1 at " B " fo r MC3432, MC3433
CL - SO pF to ta l fo r MC3430, MC3431
CL - 15 pF to ta l fo r MC3432, MC3433
tmted imil*riy.
Davlco V REF mV
MC3430
11
MC3431
IS
MC3432
11
MC3433
IS
t ji_ n and t ^ H L < 10 n measured 1 0 * to BOK,

P R R > 1 . 0 M Hz
D uty C yc l* - BOM
FIGURE7- CIRCUITSCHEMATIC
(1/4Circuit Shown)
7-35
MC3430, MC3431, MC3432, MC3433
RESPONSETIMEwrsutOVERDRIVE-MC3430.MC3431
FIGURE8 - OUTPUTLOWTOHIGH
FIGURE9- OUTPUTHIGHTOLOW
TIME (m)
TIME (m)
RESPONSETIMEversusOVERDRIVE- MC3432. MC3433

FIGURE11 - OUTPUTHIGHTOLOW
FIGURE.10- OUTPUTLOWTOHIGH
TtKE(ro)
TIME (in)
FIGURE12- AVERAGEINPUTOFFSETVOLTAGE
versusTEMPERATURE
FIGURE13- RESPONSETIMEversusTEMPERATURE
AMBIENT TEMPERATURE (BC)
7r36
MC3430, MC3431, MC3432, MC3433
FIGURE14- 4-BITPARALLELA/DCONVERTER
7-37
MC3430, MC3431, MC3432, MC3433
FIGURE15- LEVELDETECTORWITHHYSTERESIS
FIGURE16- TRANSFERCHARACTERISTICSAND
EQUATIONSFORFIGURE15
Vr ef
V|ow
Vh igh
vH
V in (VOLTS)
V h io h
. R2 lV0 (ma*) VHEFi
V" f +
'r o f +
R1 + R2-----------
R2 fV0 (mln) V r e f )
Hysteresis Loop (V^)

v h Vhigh v low "
FIGURE17- DOUBLEENDEDLIMITDETECTOR
FIGUREIS - VOLTAGETRANSFERFUNCTION
+5.0 V
7-38
DATA CONVERSION
Temperature Range
Commercial
Military
MC1405
MC1406
MC1408
MC3408
MC3410, C
MC3412
MC6890
MC10317L
MC10318L/L9
MC1505
MC1506
MC1508
MC3510
MC6890A
Page
Dual Ramp A/D Converter Subsystem ......................................
6-Bit Multiplying D/A Converter ..............................................
10-Bit Multiplying D/A Converter ................................ ..........
High-Speed 12-Bit D/A Converter............................................
8-Bit Bus-Compatible MPU D/A Converter................................
7-Bit High-Speed A/D Flash Converter ....................................
High-Speed 8-Bit D/A Converter...............................................
8 -2
8-3
8-17
8-29
8-43
8-49
8-60
8-61
8-65
8-66
MC1405
MC1505
MOTOROLA
DUAL RAMP A /D CONVERTER SUBSYSTEM

The M C 1505/M C 1405 is intended to perform the dual ramp fu n ctio n fo r
either a 3-1/2 or 4-1/2 d ig it D VM o r use as a general-purpose analog-to-digital
(A /D ) converter. It can be com bined w ith the CMOS MC14435 logic system
to produce the complete 3-1/2 d ig it D VM fu n ctio n .
The M C1505 uses the proven dual ramp A /D conversion technique. The
subsystem consists o f an on-chip voltage reference, a pair o f voltage/current
converters, an integrator, a com parator, a cu rren t switch and associated con
tro l and calibration c irc u itry . O nly one capacitor and tw o calibration
potentiom eters are required fo r norm al operation.
Accuracies to 13 Bits
Low Power C onsum ption: 42 mW @ +5.0 V
Single Power Supply O peration +5.0 V to +15 V
Low Power Supply and Temperature S ensitivity
D igital Inputs and O u tp u ts C om patible w ith Both M T T L and
CMOS
Accepts Either Positive o r Negative In p u t Voltages
Combines w ith M C 14435 to Produce 3-1/2 D igit A /D Converter
F IG U R E 2 - P IN C O N N E C T IO N S A N D F U N C T IO N A L D IA G R A M
ANALO G -TO -D IG ITAL

CONVERTER SUBSYSTEM
SILICON MONOLITHIC
INTEGRATED CIRCUIT
(as used in Figure 1)
O th e r Uses:
B CD A /D C o n ve rte r: 2 -1 /2 to 4 -1 /2 D ig its (L S I o r MSI Logic)
Data A c q u is itio n S ystem s w ith R em ote M C 15 05

V oltage to Fre q ue ncy Conversion
D elta M o d u la tio n and Signal G en e ra tion
Panel Meters
D ig ita l V o ltm e te rs
P ortable In stru m e n ts
In d u s tria l M easurem ent and C o n tro l
B in a ry A /D C o n ve rte r: 8 -to -1 3 B it* (L S I o r MSI Logic)
In d u s tria l M easurem ent and C o n tro l

H igh Noise E n viro n m e n ts (In te g ra tin g C o nve rte r w ith M T T L , M H T L , and CM OS C o m p a tib ility )
8-3
MCI405, MC1505
M AXIM UM RATINGS
ZeroCalibrationControl PinVolt8ga
Power Dissipation(Package Limitation) CeramicDual In-LinePackage
DerateaboveTA+25C
OperatingAmbient TemperatureRange
' MC1S05L
MC1405L
StorageTemperatureRange
Unit
Vdc
Volts
Volts
Volts
Value .
+16.5
+16.5
Symbol
VCC
V10
VR
VI
V2
V4
CharacterMe
PowerSupplyVoltage
Digital Input Voltage
ReferenceInput Voltage
UnknownInput VoltageRange
2.0
5.0
5.0
5.0
pd
1000
6.0
ta
-55to+125
0to+70
-65to+150
Tstg
Volts
mW
mW/C
c
ELECTRICAL CHARACTERISTICS (Vcc -
+15Vdc. V r 1.000 Vdc. VI =2.000 Vdc, V2 *0.000Vdc. V103*2.0Vdc.

______Ta 2SCunlesso lh e rw ia no tad.)
MC1405
MC1505
Symbol Figure Min | Typ | Max Min | Typ | Max Unit
Characteristic
A/DCONVERSIONSYSTEM(1)
0.01 0.05
0.01 0.05 %F.S.
Linearity: DeviationfromStraight
9.
Er
11
LinethroughZeroandFull Scale (2)
PSSF
0.002
0.02
0.002
0.02 %l%
Mid-ScalePowerSupplySensitivity
3
(PSSof I r - 0 x + '0>- V1- 1.0V)
9
%F.S./%
ZeroCalibrationPowerSupplySensitivity
PSSZ
0.001
0.001
(VI * V2-0V)
0.0006 0.0012
0.0006 0.0018 %/mV
InputCommonModeSensitivity
|CMSIX| 3
(Vx 2.0 V, VCmV2isvaried)
0.004
|TCF|
Full ScaleTemperatureDrift (3)
0.004
%lC
9
0.001
ZeroCalibrationTemperatureDrift (3)
|TCZ|
9
0.001
- %F.S./C
VOLTAGEREFERENCE
1.4
1.1
ReferenceVoltage, Pin11
3
1.25
Vdc
1.15 1.25 1.35
Vref
0.003 0.01
0.003 0.02 %l%
ReferenceVoltagePowerSupplySensitivity PSSVREF
3
%/C
|TCVrEf| 3
ReferenceVoltageTemperatureDrift
0.015
0.015
REFERENCECURRENTCONVERTER
ReferenceCurrent
250
250
It A
3
|R
40
Input BiasCurrent
114
10
10
40
nA
3
Input Rangeof Vr
1.2
1.2
Vdc
V14
3
0.8
0.8
2.0
mV
Input Offset Voltage(V14-V15)
1.0
2.5
3
5.5
|Vrr|
INPUTCURRENTCONVERTER
UnknownCurrent
500
500
UA
3
'X
4.0
4.0
Input Resistance
3
kn
R|
Input Differential Range
vx
0
2.0
0
2.0
Volts
3.10
CMR 3.10,12 -1.5
+1.5 -1.5
Input CommonModeRange
+1.5 Volts
11
200
Input BiasCurrents
3,9
200
-300 . 12
-300
mV
1.0
2.5
2.0
5.5
Input Offset Voltage(V13-V3)
3
ivxxl
RAMPOFFSETSOURCE
| RampOffset Current
25
25
m
A|
o
4
(1) Systemparametersmeasuredusingexternal voltagereference, independentof VII - VrefIntegratorCapacitor2.0pF
ClockFrequency30kHz
-
V CC - 1 6 V
12) Doesnot includequantizingerror. SeeFigure10 forcalibration.
8-4
MC1405, MCI 505
ELECTRICAL CHARACTERISTICS (Vcc "

Vdc. V R -1 .0 0 0 Vdc, V I - 2.000 Vdc. V2 - 0.000 Vdc. V 1 0 > 2.0 Vdc.
___________________________________ T a " 2SC units otherwise n
o
t a
d
. ) _____________________
Ch*ractar!stic
CURRENTSWITCH
Digital Input LogicLevels, Pin10
HighLawl. Logte"1"
LowLeytl, Logic"O'*
Digital InputCurrent
HighLovtl. Logic"1"
LowLaval. Logic"0"
INTEGRATOR
InputBiasCurrent
OutputVoltageSwing
High
Low
COMPARATOR
Output Logic Levels, Pin9
HighLevel, Logic"1" _ _
_
LowLeve, Logic"0"
low
(SinkCurrent-1.6 mA)
InputThreshold
POWERSUPPLY
PowerSupplyCurrent
(Vcc-+5.0Vdc)
(Vcc-+15.0Vdc)
PowerSupplyVoltageRange
PowerConsumption
(VCC+5.0Vdc)
(Vcc-+15.0Vdc)
Symbol
Figure
V|H
V|L
3.18
3.18
>IH
III
3
3
16
V7
MC1B06
Min | Typ 1 Max
2.0
- -5.0
10
12.8
13.0
0.2
0.8
Vdc
Vdc
2.0
-60
-5.0
-50
1.0
tiA
30
10
50
12.8
13.0
nA
Volti
1.0
0.35
__
0.2
-Volts
14.0
0.35
.0.5
1.1
0.9
1.0
1.1
12.0
12.0
4.75
8.4
9.0
-
13.0
16.5
42
135
60
195
13.5
14.0
0.35
0.5
VTH(7)
0.9
1.0
cc
3
3
-
4.75
8.4
9.0
-
13.0
16.5
42
135
60
195
- -55CforMC1505L, 0Cfor MC1405L

+126Cfor MC1505L. +70Cfor MC1405L
T tow
T h ig h "
FIGURE3- STANDARDTESTCONFIGURATION
VCC 1.000V VREF VCC
>R- vOL
>2 V
169 159 14p13<
Vcc~vo t
10
1.6mA
< 0.8 VJ 2.000
V
1
V0 H
ro
VOL
>X- vOH 0.1
N ote: A test fo r functional

parts may bo performed
using a pulso generator on
Pin 10.
3A 4 A 5 A
6 A
t *3
x >R
7A 8 A
Noto: A ll dc supplies
bypassed w ith 0.1 (xF.
HH
FIGURE4 - IqMEASUREMENT
VCC 1.000V1.8V
100pF
FIGURES- 16MEASUREMENT
Vcc 1.000V 2.0V
16115y14l F 4 'T
8-5
mA
0.35
13.5
3
3
PC
Unit
0.8
V0H
VOL
Vcc
MC1406
Min I Typ I Max
Volts
mA
Vdc
mW
MC1405, MCI 505
GENERAL INFORMATION
Dual Rajnp Analog-to-Digital Conversion _
A /D Subsystem Circuit Description
The dual ramp method of A/O conversion is a proven

system which is capable of very high accuracy. The con
version is an Integrating process which offers high noise
rejection and immunity to changes in the clock rate and
integrator capacitor value. The particular method used in
the MC1505 is a noniterating dual slope technique which
produces an accurate result after one conversion period.
Dual ramp conversion.is accomplished with the system
of Figure 2. The conversion begins at time t l , when current
Ix causes the integrator output, or ramp, to cross the
comparator threshold, as shown in Figure 6. The clock is
activated and the counters begin counting from zero. The
system counts for a fixed period T, with a ramp slope
which depends on the input voltage, i.e., a steep slope is
caused by a high input voltage. When the counters have
reached full scale, the overflow count triggers a -f 2 flipflop which changes the ramp control polarity current. I r
The MC1505 incorporates special circuit features which

allow all the analog functions of the dual ramp system to
be performed on a single monolithic chip using standard
bipolar processing.
Voltage-to-current conversion for both the input and
reference voltages allows the use of la high-speed current
switch and single supply operation. The unbuffered dif
ferential inputs have sufficiently high input impedance for
power supply monitoring applications, and provide flexi
bility for other input formats since they will accept either
positive or negative voltages.
The voltage reference, shown in Figure 7, is one of the
six basic circuits in the subsystem. It provides a low im
pedance output which has excellent temperature stability,
and high power supply rejection. Biasing for the other
circuits in the M C I505 is derived from the voltage
reference circuitry.
FIGURE6 - DUALRAMPA/OCONVERSIONWAVEFORMS
AVoncapacitor isequal inTl andT2
1 r
1 r
" '- 'L
WhereIx it oppositeIr polarity.'

IXT1-Ir T2
SinceIxandI r areproprotional to.VXandV r ,

VXT1-Vr T2
Comparator
LT
Ramp
Control
now controls the integrator and the down ramp begins at

t2. This ramp continues at a fixed slope for a time period
which depends on the amplitude achieved by the up ramp.
Thus T2 is determined by the input voltage. When the
ramp crosses the comparator threshold at t3, the clock
stops and the counter holds a digital value which is pro
portional to the unknown input voltage.
After the down ramp crosses the comparator threshold,
a timing sequence in the digital section strobes the latches
to store the data, resets the counters, and reverses the
ramp at t4 to begin a new conversion.
Since the voltage change across the capacitor is equal
on the up and down ramps, an equal amount of charge is
exchanged. The equations of Figure 6 show that the
system output Is the ratio of the unknown and reference
currents, and long term changes in the clock rate and
integrator capacitor do not effect the reading.
T2-T1 VX
VR
T2correspondstothenumberof countsinthe
output digital word.
Tl andT2arederivedfromthedock, sotheir
ratioisindependentof clockfrequency.
The same basic amplifier circuit is used in both the
reference and input voltage-to-current converters. It is an
extremely well balanced amplifier with low input offset
voltage temperature drift. The reference converter uses a
pair of PNP transistors to derive current I r , in conjunction
with a reference resistor which has the same temperature
coefficient as those used in the input converter. The value
of the reference current is V p/R 5. The collectors of
transistors 0 1 , 0 2 and 0 3 in Figure 7 all track with a two
diode temperature coefficient, which assures constant
current ratios.
The reference resistor value can vary by 30% of 4.0
kn due to process variations. Moreover, these variations
will also affect the input bridge resistors. Thus, the ratio
of reference to unknown current has a close tolerance for
a wide range of resistor values.
MC1405, MC1505
The input voltage-to-current converter is a bridge or

bilateral current source whose output current is V x/R 1. If
the bridge is perfectly balanced, its output impedance and
common mode rejection are infinite. However, the design
has the ability to tolerate bridge mismatches of approxi
mately 0.5%. In order to tolerate this mismatch, the
output of the bridge current source is connected to the
current switch which is a low temperature coefficient, low
impedance source of 1.25 volts. This technique effectively
eliminates output current changes due to finite output
impedance which is caused by resistor mismatch. This
input current converter makes possible the use of a single
supply voltage and differential inputs which can be used at
or below ground potential.
An important feature of the MC1505 is the ramp offset
current source which is added to the unknown current and
does not allow the ramp to reach zero slope when the
input voltage is zero. The ramp range is shown in Figure 8.
The ramp offset current has a value of I r / 10, so that the
minimum ramp slope is 5% of the full scale slope. This
allows reliable conversion at low input voltages by assuring
a nearly constant comparator propagation delay and a
good ramp signal-to-noise ratio. It also prevents turn-off
of the diode in the current switch at low levels, re

stricting the voltage change at the output of the resistor
bridge. Still another feature is that it provides a con
venient temperature compensated zero adjust which can
correct errors in the resistor bridge and input buffer
amplifiers when they are used. The ramp offset current is
compensated by 100 extra counts in the digital logic
during ramp down, so it does not appear in the digital
output (see Figure 8).
The current switch uses current steering for very high
speed operation. A smooth transition occurs as one current
is turned on while the other is turned off. This minimizes
error during the ramp reversal at its peak, especially since
the reference current source has a very high output im
pedance and does not change value when switched. The
settling time of the input current converter is not a factor
in system accuracy. At the ramp peak, lx is turned off, so
the amplifier settles after the unknown current is de
coupled from the integrator. When the ramp is below the
comparator threshold, the unknown current is switched on
and thus the current can settle before the ramp enters the
active conversion range. The switch operates into a voltage
of 1.95 volts and is translated by a follower so its input
FIGURE7- A/DCONVERTERANALOGSUBSYSTEM
Input
Ton
lx
Zaro
A d jutt
I q Input
O utput
N '
Integrator
MC1405, MC1505
FIGURE8 - MCISOSSYSTEMTIMINGDIAGRAM
(2.0 Volt Full Scale Input)
'x (m e x )
'O
Slop*)
_ 'X(m ax)
'X + 'o
I q corrstpondt to ramp
(tops w h in l x - 0 .
Remp
Control
I'X + 'O * T1 'R (T2 + TO)
threshold is 1.25 volts.

The integrator is a single stage, wide bandwidth ampli
fier. Its low propagation delay and low output impedance
minimize ramp spikes due to output current reversal during
ramp turn-around. The input bias current is typically one
part in 50,000 of the full scale current, so that its temper
ature change contributes negligible error. Gain and input
offset voltage are not critical since the integrator is driven
from current sources.
The comparator is designed for low hysteresis by
maintaining a constant power dissipation regardless of
output state. This hysteresis is typically 0.1 mV and
remains constant with temperature variations, so that no
measurable system error is contributed. Temperature vari
ations in the value of the comparator threshold are not an

error factor, since the only requirement is that the
threshold remain constant during a given conversion cycle.
Voltage gain of the comparator is 2,000,000 when driving
CMOS, and 40,000 with one TTL load. The comparator
output is slew rate controlled to provide output rise and
fall times of approximately 80 ns. This minimizes noise
generation which could affect system stability.
The system is zeroed and full scale calibrated by
potentiometers which provide temperature compensation.
All the other resistors are diffused in close proximity,
yielding reference and unknown currents which have a
closely tracking resistive temperature coefficient.
8 -8
MC1405, MC1505
The input configurations for the M C I505 are shown
in Figure 11. Note that the differential input voltage must
always remain the same polarity with Pin 1 positive with
respect to Pin 2. Figures 11 and 13 will aid in the under
standing of the input circuitry.
The input common mode rejection of the MC1505 is
high enough to maintain rated accuracy with small changes
in common mode voltage, such as would be seen with
ground errors and noise. The system must be recalibrated,
however, for larger changes in common mode input
voltage.
The MC1505 is arranged so that lx = I r when
V x = V r , or so that the ramp slopes are equal for input
and reference voltages of 1 volt. As shown in Figure 8, a
system with a 2 volt full-scale input requires twice as
many digital counts during T2 as for T1. A system with a
1 volt full scale would require an equal number of counts
in T1 and T2. Figure 9 illustrates a 3-1/2 digit system,
but typical accuracies of the MC1505 allow its use in 4
digit applications. It can also be used in systems which
require 4-1/2 digit resolution.
The ramp offset current and 100 count delay are shown
in Figure 8. In certain applications, a different number of
counts may be used. The system will not always operate
properly, however, with a 10 count delay since the ramp
offset current is used to zero the system and compensate
for error in the input resistor bridge. This error, known as

IXO* 's current which flows to or from the input con
verter with zero volts applied to the input. It is typically
between 15.0 jiA, which is 1% of full scale in a 2 volt
system. A 10 count delay would need a 0.5% ramp offset
current, which would not always be able to cancel this
error. Also, a 10 count delay does not provide enough
signal-to-noise margin for consistently accurate low-level
conversion.
The integrating capacitor is chosen with the equations
shown in Figure 9. The maximum ramp voltage should
be used for best signal-to-noise ratio, but temperature
changes in lx , I r and the capacitor should be anticipated
to prevent integrator saturation. Variations in clock fre
quency should also be considered. A polar capacitor with
Pin 7 at the + terminal may be used. However, settling
time will be increased when electrolytics are used. Tantalum
electrolytics are preferred.
The lower half of the diode current switch is split with
separate diodes for lx and lo - In most applications Pins
12 and 13 will be connected so that the two device
emitters are effectively one, since the main purpose of
these pins is for testing. Connecting these pins allows
proper system zero adjustment and prevents turn-off of
the switch diode with low unknown current levels. This
yields better conversion accuracy.
FIGURE9a- ACCURACYTEST
3-1/2Digit Panel Metar
a jie j 3}
3
D ig ita l
S u b tv s tc m
M C I 4435
or E q u lv .
100
Analog
Input
J0 to * 2 V
1
C o m m o n C a th o d e
L E D D isp la y *
V DD
v DD
10 k j
Full Scale '
Calibration'
v Do
0311
2 ,2 n 2
^ iin f T
* S o i^
>
D ecodo r/
D rive r
M C14511
O
0.01 /iF 2
TXT
Integrator Capacitor
Zero Calibration
V SS
Overrange
a)c)
C|- V2|(m
.7 k
"
( U p R a m p C o u n ts) l/f clo ck
See Electrical Characteristics Table

V 7 (max) it typically V q q -2 .0 V
V TM (7) * typically 1.0 V
*Optional Clamp diode on Pin 13,

may bo noeded for rocovery from
negativo differential inputt.
8-9
00
FIGURE8b- CMOSDIGITALSUBSYSTEM
3-1/2 Digit BCDA/DConverter
MC1405, MCI 505
Ramp Control
MClSOSPin 10
8-10
MC1405, MCI 505
FIGUREBe-FUNCTIONALDIAGRAMOF
MC14436CMOSDfdlTALSUBSYSTEM
> 0 0 ds5
t
DS3
Cl O-
4
C2 O -
1
BCD
2
4
Oisplay- e
Update O -
<OU)
Comparator 5
(Comp)
O-
Latchat
Transm inion
G ates
ST
Logic
One
Shot-
J t
ST
1
BCO
R
2
4
8
Latches
4
TransGates
ST
-h > ------ O Q O
rC
13
-D>T---- 0 02
-> -A > Q 3
Count
Dalay
C
Delay
B C P ,*
R
ST
4
Latches
S T
4
Trans
mission
dates '
-
f~-
- Qverranflo
(Ofi)
. ,
Logic
.
"V ^
I Ramp C ontrol
(RC)
_J> _ J 1 / 2 0 ig lt
(1/2 O)
FIGURE10- CALIBRATIONSET-UP
Zero Calibration:
Set standard a t 0.0005 V .
' '
: Adjust xero potsn tio m e te r'fo r panel mater display transition
between 0.000 and 0.00,1 V. Noto: An analog Input of
-1 m V yields a roadlng o f 6i099.'1 1 -'
Repeat zero and fu ll scale calibration u n til meter Is calibrated
at both ends o f tho scale.
Full Scala Calibration:
Set standard at 1.9995 V.
Adjust fu ll scale potentiom eter fo r penal meter display tran
sition between 1.999 end 1.000 V. (overrange)
Linearity Test:
Adjust standard fo r the desired panel meter transition and
record the value o f the standard.
A t in itial turn-on, set Pin 14 to * 1 .0 V o lt w ith fu ll scala potentiometer.
8 -1 1
MC1405, MC1505
FIGURE 11 -ANALO G 1NPUTRANGE

Tha Input circuit fo r tha M C I 505 has a unipolar dlffarential
Input ranga o f +2 volt* and a bipolar common m od* Input range
o f 1.6 volt*.
Positive Input:
V x V I - V2
VCM -V 2
V x Ranga 0 to * 2 .0 V
V CM Range 1.8 V
V X - 2 .0 V
3.5 V
0.5 V
1-BV
-1.3 V
Vc m -O V
Negative Input:
V X - V 1 - V2
V CM V I
1
~
2
n
V CM * 1 5 V
V x Ranga 0 to +2.0 V
V c m Range 1 .5 V
rr
-1 .6 V
V x 2.0 V
O2
-0.5 V
-3.5 V
v CM - 1.5 v
v CM - 0 V
Allowable Pin Voltagot:
Pin 1: -1.5 V to *3 .5 V
Pin 2: -3.6 V t o +1.5 V
FIGURE12- CIRCUITTOPREVENTPOSSIBLELATCKUP
WITHAPPLICATIONOFNEGATIVEINPUTVOLTAGES
The MC1405/1505 A /D analog subsystem is intended

for positive input voltages only (i.e., pin 1 positive with re
spect to pin 2). However, should pin 2 become more than
100 mV positive with respect to pin 1, the internal input
amplifier may go into a latchup mode which will require
that the system power be turned off and then reapplied to
reset the system. To prevent this problem a PNP transistor
can be used as shown in the accompanying figure. The
base-emitter junction o fth e transistor clamps pin 13 at
one diode drop above the reference voltage (pin 11) to
prevent the latchup. The gain of the transistor insures that
the reference need not sink more than 500 jiA of current.
The 47 k2 resistor is required only if the A/D system
is to continue to convert under reverse polarity conditions
such as for autopolarity schemes.
47 k t l resistor required If conversions are to continue during

Input polarity reversal, otherwise tie pins 12 and 13 together.
8 -1 2
MC1405, MC1505
FIGURE13- MAXIMUMCOMMON-MODEINPUT
VOLTAGEvnut TEMPERATURE
FIGURE14- INPUTCURRENTvarftti INPUTVOLTAGE

1.4
V2, COMMON-MOOE INPUT VOLTAGE (VOLTS)
7.0
V [ 2.0
6.0 5
&
5.0 3
2
4.0
5
3.0 |
C9
Nati: VI ti nits tht commo imodi
aptblily of th input convtrttr.
2 .0 1
1.0 ;
5 as
11*
g 0.6
3 0.4
5 0.2
a,
5 0
o-a2
< -0 .4
3 -0 .6
Z -0 8
Nett: Oban* ccmmon nodttn dttmpeHurt

Kmtotion shown in Figures 11 and 13
= -1.0
-u
0
0
1.2 TA'25C
1.0
;5
-1.4
-5.0 -4.0
25
75
T. TEMPERATURE (OC)
-3.0
-2.0
-1.0
i
0
i
1.0
i
2.0
i
3.0
FIGURE16- REFERENCECURRENTvwrsusREFERENCE
INPUTVOLTAGE
VX. ANALOG INPUT VOLTAGE (VOLTS)
V r. REFERENCE INPUT VOLTAGE.PIN 14 (Vdc)
lx< UNKNOWN CURRENT (mA)
FIGUREIS- UNKNOWNCURRENTversusANALOG
INPUTVOLTAGE
FIGURE17-TYPICALPOWERSUPPLYCURRENT
vortusPOWERSUPPLYVOLTAGE
Icc. POWER SUPPLY CURRENT (mA)
VI or V2. ANALOG INPUT VOLTAGE (VOLTS)
FIGURE18- TYPICALPOWERSUPPLYCURRENT
versusTEMPERATURE
| 8.0
kz
I
6.0
1
V)
cc
5
4,
____Rar np Contra High or Low

t a * 25C
V CC-15 V
5.0
10
2.0
15
+25
+75
T. TEMPERATURE (OC)
Vcc. POWER SUPPLY (Vdc)
8-13
MC1405, MC1505
FIGURE20- INTEGRATOROUTPUTSWING
versusTEMPERATURE
FIGURE 19 - CURRENT SWITCH TRANSFER

CHARACTERISTIC
600
500
400
100
NDTP: Ci mntS<witch
Hvtshcld Remjini Ccnttint
CC*
100
V.
-----
400
0
1.0
2.0
3.0
-55
4.0
FIGURE21 - COMPARATORTHRESHOLD
vairsusTEMPERATURE
If a voltage drop o f 2.0 V fu ll scale can bo tolerated tho

retlttora may be Increased by a factor of ten and a unity gain
buffer may be employed.
+125
+175
FIGURE22- RAMPCURRENTRATIO
versusPOWERSUPPLY
1
IX 10
IR
FIGURE23- CURRENTMEASUREMENTCIRCUITRY
V7 Min)
-------+75
T. TEMPERATURE (C)
VIO. RAMP CONTROL INPUT (VOLTS)
T.TEMPERATURE PC)
*25
1
____
'CC
5.0
10
15
Vcc. POWER SUPPLY (Vdc)
FIGURE24- DVMVOLTAGERANGING
20
MC1405, MC1505
FIGURE25- MTTLDIGITALSUBSYSTEM
12 Bit BinaryA/DConvertor
(1.0Volt Full Scale, 512Count Oelay)
VCc
R
D" Q
' s
c ga
LD
c -o g
Overran ge
(JO
- a.
CJ1
Comparator Input
o f M CI BOS (Pin 9)
N o tn :
1. NANO Gate* M C7400 or equlv.
NOR Gate* MC7402 o r equiv.
Inverter* - MC7404 o r equiv.
2. Tha clock period th o u ld ba p-eater
than tw lc a th * w o rn cete rippla dalay
through the counter* to achieve fu ll
accuracy.
3. The counter delay th o u ld ba
approxim ately 10% o f T I ,
hence 512 count*.
00
MC1405, MC1505
FIGURE28- 12-BITBINARYA/DLOGICSUBSYSTEM
USINGCMOS
MOTOROLA
MC1406L
MC1506L
Inform ation
SIX BIT, M ULTIPLYING

DIGITAL-TO-ANALOG
CONVERTER
SIX BIT, MULTIPLYING

DIGITAL-TO-ANALOG CONVERTER
. . . designed fo r use where the o u tp u t current is a linear product

o f a six-bit digital w ord and an analog inp u t voltage.
C ZD
( to p view)
Digital Inputs are M D TL and M TT L C om patible
Relative Accuracy 0.78% E rror m aximum
Low Power Dissipation 85 mW typical @ 5 .0 V
Adjustable O u tp u t C urrent Scaling
00
Fast Settling Tim e
Standard Supply Voltage: +5.0 V a n d -5 .0 V t o -1 5 V
150 ns typical
C ER AM IC P A C KAG E
CASE 632
T O - 116
FIG U R E 2 - D to A T R A N S F E R C H A R A C T E R IS T IC S
F IG U R E 1 - O U T P U T C U R R E N T S E T T L IN G T IM E
(A L L B IT S S W IT C H E D , R L = 5 0 H )
2.0 V
2.0 mA
OV
SB!
0 niA
.0 mA
M
n H
a g i i H
H
H
B SSS
2.0 mA
(000000)
100 ns/OIV.
INPUT W ORD
TY P IC A L APPLIC ATIO N S
T ra ckin g A -to -D C onverters

Successive A p p ro x im a tio n A -to -D Converters
D ig ita t-to -A n a lo g M eter Readout
Sam ple and H o ld
Peak D e tecto r
P rogram m able Gain and A tte n u a tio n
D ig ita l V aricap T u n in g
V id e o Systems
8-17
S tepping M o to r D rive
C R T Character G eneration
D ig ita l A d d itio n and S u b tra ctio n
A n a lo g -D ig ita l M u ltip lic a tio n
D ig ita l-D ig ita l M u ltip lic a tio n

A n a lo g -D ig ita l D ivisio n
P rogram m able Pow er S upplies
Speech E ncoding
( 111111)
MC1406L, MC1506L
M A X IM U M R A TINGS
(TA+25Cunionotherwisenoted.)
Rating
Digital Input V6ftage

AppliedOutput Voltage
ReferenceCurrent*
ReferenceAmplifier Inputs
PowerDissipation(PackageLimitation)
CeramicPackage
DerateaboveTA=+25C
OperatingTemperatureRange
Unit
Vdc
Value
+5.5
-16.B .
+8.0, Vee " "
5.0
5.0
vCc. Vee
Symbol
Vcc
VEE
VgthruVô
v0
PowerSupplyVoltage
'12
Vi2,Vi3
PD
Vdc
Vdc
mA
Vdc
1000
mW
mW/C
-55 to+125
0 to+70
-65 to+150
6.7
ta
MC1506L
MC1406L
StorageTemperatiireRange
Ttg
6C
I -J
ELECTRICAL CHARACTERISTICS (Vcc* +5.0 Vdc, Vgg

15 Vdc, ^ 2.0 mA, all logic inputs in low logic state,
tA ThlghtoTiovy, unlessotherwisenoted.)
Unit
Characteristic
Figure Symbol
Min Typ Max
%
0.78
RelativeAccuracy(Errorrelativetofull scaleIq)'
10
Er
ns
150
300
SettlingTime(within1/2 LSB (includestrf] TA+25C)
9
*S
PropagationDelayTime
9
PHL.
ns
10
50
TA=+25C
*PLH
PPM/C
|TCI0 |
80
Output Full ScaleCurrent Drift
Vdc
3,14
Digital Input LogicLevels
2.4
HighLevel, Logic"1
LowLevel, Logic"0"
;
0.8
-r
Digital Input Current

V'
HighLevel, ViH'.-SiOV
LowLevel, V| 0.8V
ReferenceIhputBiasCurrent (Pin13)
r
Output Current Range
Vee-^-OV
Vee -6.0to-15 V
OutputCurrent
Vref *2.000V, R 1.000k f l .
Output Current
(all bitshigh)
Output VoltageCompliance
(Er<0.78%at TA+25C)
ReferenceCurrentSlewRate
(TA- +25C)
Output Current PowerSupplySensitivity
PowerSupplyCurrent
A1 thruA6; V|L=0.8V
A1 thruA6 ;V|h= 2.4V
PowerDissipation(all bitshigh)
Vg -5.0 Vdc
.i
Vee 15Vdc
3,13 !
.
3-.
r '
3
3
MV-
;
>13
or
iil
lo
iQ(min)
3,4,5
+ i
o o
> >
8,15
SR Iref
10
PSRR(-)
3,11,12
ic e
>EE
PD
*Thigh +70Cfor MC1406L Ttow0Cfor MCI406L

H25Cfor MC1508L
- -55CforMC1506L
8-18
' -
0
0
+0.01
-1.5
; # 7
-0;0fe : -0.01
0
2.0'-:
2.1
2.0
4.2
1.97
2.1
10
+0.25
-0.45
+0.1
-0.3
19.
mA
mA
mA
mA
ma
2.0
0.002
0.010
+7.2
-9.0
+11
-11
85
175
120
Vdc
mA/|is
mA/V
mA
mW
240
MC1406L, MC1506L
The M C 15 0 6 L consists o f a reference c u rre n t a m p lifie r,

and R-2R ladder, and six high-speed cu rre n t sw itches. F o r
m any a pplications, o n ly a reference resistor and a reference
supply voltage need be added.
The switches are in ve rtin g in o p e ra tio n , th e re fo re a lo w
state at the in p u t tu rn s on the specified o u tp u t cu rre n t
co m ponent. The sw itches use a c u rre n t steering technique
fo r high speed and a te rm in a tio n a m p lifie r th a t consists o f
an active load gain stage w ith u n ity gain feedback. The
te rm in a tio n a m p lifie r holds the parasitic capacitance o f the
ladder at a constant voltage d u rin g sw itch in g and provides
a lo w im pedance te rm in a tio n o f equal voltage fo r all legs
o f the ladder.
The R-2R ladder divides the reference a m p lifie r cu rren t
in to
b in a rily-re la te d
switches.
co m po n e nts w h ich are fed to the
N ote th a t there is alw ays a re m ain d er cu rre n t
th a t is equal to the least s ig n ific a n t b it.
T h is cu rre n t is
shunted to ground, and the m a xim u m cu rre n t is 6 3 /6 4 o f

the reference a m p lifie r c u rre n t, o r 1.969 m A fo r a 2.0 m A
reference
cu rre n t
if
the
NPN
cu rre n t
source
pair is
p e rfe c tly m atched.
C O M P L E T E C IR C U IT S C H E M A T IC
(D ig ita l In p u ts ; p in s 5 ,6 ,7 ,8 ,9 ,1 0 )
B L O C K D IA G R A M
USB
AI
A?
A3
A4
AJ
LSB
A6
00
versus TEMPERATURE
MC1406L, MC1506L
lo. OUTPUT CURRENT (mA)
bo
MC1406L, MC1506L
TEST CIR C U ITS and TYPICAL CHARACTERISTICS (continued)
. .... FIGURE9 - TRANSIENTRESPONSE
^1.5 V
-1m
-
FIGURE 10- RELATIVEACCURACYTESTCIRCUIT

12-M D-tO-A Comwtt*
OtotOV
Ootpel
jtO
A?|> A l|
tov#
15
q:
iu All
29 pf
FIGURE12- TYPICALPOWERSUPPLYCURRENTvertusVEE
FIGURE11 - TYPICALPOWERSUPPLYCURRENT
versusTEMPERATURE
10
POWER SUPPLY CURRENT (mA)
V c c +5.0 V
1
3
E
UJ
fie
u
s
tt
90
8.0
ee - ALL Bll SHIGH

1----------- 1----------lE E -A L L BITS LOW _
i
r
Ic c - A L L BITS HIGH
--------- -----ice--A L L B I
frr
-4.0
V e e . NEGATIVE POWER SUPPLY (Vdc)
T, TEMPERATURE (C)
8-21
re
MC1406L, MC1506L
GENERAL IN FO R M A TIO N
TYPIC A L CHARACTERISTICS (continued)
Output Current Range
FIG U R E 13 - LO G IC IN P U T C U R R E N T versus IN PU T V O LTA G E
The output current maximum rating of 4.2 mA may be

used only for negative supply voltages below -6 .0 volts,
due to the increased voltage drop across the 400-ohm
resistors in the reference current amplifier.
Output Voltage Compliance
The MC1506L current switches have been designed for
high-speed operation and as a result have a restricted out
put voltage range, as shown in Figures 4 and 5. When a
current switch is turned off", the follower emitter is
near ground and a positive voltage on the output terminal
can turn "on" the output diqde and increase the output
current level. When a current switch is turned "on", the
negative output voltage range is restricted. The base of
the termination circuit Darlington amplifier is one diode
voltage below ground; thus a negative voltage below the
specified safe level will drive the low current device of the
Darlington into saturation, decreasing the output current
level.
FIG U R E 14 - MSB TR A N S FE R C H A R AC TER ISTIC S

versus T E M P ER A TU R E (MSB IS "W O R ST CA SE ")
For example, at +25C the allowable voltage compliance

on Pin 4 to maintain six-bit accuracy is +0.1 to -0 .3
Volts. With a full scale output current of 2.0 mA, the
maximum resistor value that can be connected from Pin 4
to ground is 150 ohms.
Accuracy
Absolute accuracy is the measure of each output current
level with respect to its intended value, and is dependent
upon relative accuracy and full scale current drift. Relative
accuracy is the measure of each output current level as a
fraction of the full scale current. The relative accuracy of
the MC1506L is essentially constant with temperature due
to the excellent temperature tracking of the monolithic
resistor ladder. The reference current may drift with
temperature, causing a change in the* absolute accuracy
of output current.
FIG U RE 15 - REFERENCE IN P U T'FR E Q U E N C Y RESPONSE

2.0
The best temperature performance is achieved with a

-6 .0 V supply and a reference voltage of -3 .0 volts. These
conditions match the voltage across the NPN current source
pair in the reference amplifier at the lowest possible volt
age, matching and optimizing the output impedance of
the pair.
0
Unless otherwise specified:
R12 R13 * 1.0 k fi
R|. * 50 n (pin 4 to GNO)
Curve A: Large Signal Bandwidth
-4.0
(Method of Figure 6)
Vft f - 2.0 V(p-p) offxat 1.0 Vabove GNO-6.0 CiurveB: Small Signal Bandwidth
(Method of Figurs 6) '
Vref = 50 mV(pp) oflsal 20QmVabovsGNOj
Curve C Large and Small Signal Bandwidth
(Method of Figure 22 with no op-ampl RL * 501i|^
RS=Rl*S0J1
-to
V f = 2.0V
Vs
= 120 mV(pp) centered at 0 V
-12
- 2.0
0.01
0.02
0.1
. 0.2
1.0
f, FREQUENCY (MHi)
The MC1506L/MC1406L is guaranteed accurate to with

in 1 /2 LSB at +25C at a full scaleoutput current o f
1.969 mA. -This corresponds to a reference,amplifier out
put current drive to the ladder o f 2.0 mA, with the loss of
one LSB = 31 iiA that js the ladder remainder shunted to
ground. The input current to Pin 12 has a guaranteed
current range value of between 1.9 to 2.1 mA, allowing
2.0
8 -2 2
MC1406L, MC1506L
GENERAL INFORMATION (continued)

some mismatch in the NPN current source pair. The
accuracy test circuit is shown in Figure 10. The 12-bit
converter is calibrated for a full scale output current of
1.969 mA. This is an optional step since the MC1506L
accuracy is essentially the same between 1.5 to 2.5 mA.
Then the MC1506L full scale current is trimmed to the
same value with R12 so .that a zero value appears at the
error amplifier output The counter is activated and the
error band may be displayed on an oscilloscope, detected
by comparators, or stored in a peak detector.
Two 6-bit D-to-A converters may not be used to con
struct a 12-bit accurate D-to-A converter. 12-bit accuracy
implies a total error of 1 /2 of one part in 4096, or
0.012%, which is more accurate than the 0.78% specifi
cation provided by the MC1506L.'
Multiplying Accuracy
The MC1506L may be used in the multiplying mode
with six-bit accuracy when the reference current is varied
over a range of 64:1. The major source of error is the
bias current of the termination amplifier. Under "worst
case" conditions these six amplifiers can contribute a total
of 6.0 n A extra current at the output terminal. If the
reference current in the multiplying mode ranges from
60 u A to 4.0 mA, the 6.0 fiA contributes an error of
0.1 LSB. This is well within six-bit accuracy.
A monotonic converter is one which supplies an increase
in current for each increment in the binary word. Typi
cally, the MC1506L is monotonic for all values of reference
current above 0.5 mA.
The recommended range for
operation with a dc reference current is 0.5 to 4.0 mA.
Settling Time
The "worst case" switching condition occurs when all
bits are switched "on", which corresponds to a high-to low
transition for all bits. This time is typically 150 ns to
within 1/2 LSB, while the turn " o ff" is typically under
50 ns.
The slowest single switch is the least significant bit,
which turns "on" and settles in 50 ns and turns "o ff" in
30 ns. In applications where the D-to-A converter func
tions in a positive-going rarrtp mode, the "worst case"
switching condition does not occur, and a settling time
of less than 150 ns may be realized.
Reference Amplifier Drive and Compensation
around circuit or current mirror for feeding the ladder.

The reference amplifier input current, 112, must always
flow into Pin 12 regardless of the setup method or reference
voltage polarity.
Connections for a positive, reference voltage are shown
in Figure 6. The reference voltage source supplies the full
current 112. Compensation is accomplished by Miller feed
back from Pin 14 to Pin 13. This compensation method
yields the best slew rate, typically better than 2.0 mA/fis,
and is independent of the value of R 12. R 13 must be used
to establish the proper impedance for compensation at
Pin 13. For bipolar reference signals, as in the multiplying
mode, R 13 can be tied to a negative voltage corresponding
to the minimum input level. Another method is shown
in Figure 22.
It is possible to eliminate R13 with only a small sacri
fice in accuracy and temperature drift. For instance when
high-speed operation is not needed, a capacitor is connected
from pin 14 to V e : The capacitor value must be increased
when R12 is made larger to maintain a proper phase
margin. For R12 values of 1.0, 2.5, and 5.0 kilohms,
minimum capacitor values are 5 0 ,1 2 5 , and 250 pF.
Connections for a negative reference voltage are shown
in Figure 7. A high input impedance is the advantage of
this method, but Miller feedback cannot be used because
it feeds the input signal around the PNP directly into the
high impedance node, causing slewiHg problems and high
frequency peaking.
Compensation involves a capacitor
to V e e n P'n 14> using the values of the previous para

graph. The negative reference voltage must be at least
3.0 V above V e e . Bipolar input signals may be handled
by connecting R 1 2 to a positive reference voltage equal to
the peak positive input level at Pin 13.
When a dc reference voltage is used, capacitive bypass
to ground is recommended. The 5.0 V logic supply is not
recommended as a reference voltage. If a well regulated
5.0 V supply which drives logic is to be used as the refer
ence, R 12 should be decoupled by connecting it to +5.0 V
through another resistor and bypassing the junction of
the two resistors with 0.1 UF to ground. For reference
voltages greater than 5.0 V , a clamp diode is recommended
between Pin 12 and ground.
If Pin 12 is driven by a high impedance such as a
transistor current source, none of the above compensation
methods apply and the amplifier must be heavily compen
sated, thus decreasing the overall bandwidth.
The reference amplifier provides a voltage at Pin 12 for

converting the reference voltage to a current, and a turn
8-23
MC1406L, MC1506L
APPLICATIONS IN FO RM A TIO N
FIGURE 16- OUTPUTCURRENTVOLTAGECONVERSION
Theoretical Vq
Vo S w ,,T +T t T t f s +f +H > *KRo{s}

Adjust Reel that V q with all digital inputs at
low level is equal to 9.844 vctts.
Vo n ,5K,,f +?t ff+f t +s r+w , " ,0V # - 9M4V
An alternative method is to use the MC1539G and input

compensation. Response of this circuit is also on the
order of 2.0 /us.
FIGURE 18
Voltage outputs of a larger magnitude are obtainable

with this circuit which uses an external operational ampli
fier as a current to voltage converter. This configuration
automatically keeps the output of the MC1506L at ground
potential and the operational amplifier can generate, a
positive voltage limited only :by its positive supply voltage.
Frequency response and settling time are primarily deter
mined by the characteristics of the operational amplifier.
In addition, the operational amplifier must be compensated
for unity gain, and in some cases overcompensation may be desirable.
Note that this configuration results in a positive output
voltage only, the magnitude of which is dependent on
the digital input.
The following circuit shows how the LM301AG jean
be used in a feedforward mode resulting in a full scale
settling time on the order of 2.0 #is.
The positive voltage range may be extended by cascoding the output with a high beta common base tran
sistor, Q1, as shown.
FIGURE17
The output voltage range for this circuit is 0 volts to

BV q b O f the transistor. Variations in beta must be
considered for wide temperature range applications. An
inverted output waveform may be obtained by using a
load resistor from a positive reference voltage to the
collector of the transistor. Also, high-speed operation is
possible with a large output voltage swing.
Vo
8-24
MC1406L, MC1506L

Combined Output Amplifier and Voltage Reference
Bipolar or Negative Output Voltage
For many of its applications the MC1506L requires a

reference voltage and an operational amplifier. Normally
the operational .amplifier is used as a current, to voltage
converter and its output need only go positive. With the
popular MC1723G voltage regulator both of these functions
are provided in a single package with the added bonus of
up to 150 mA of output current, see Figure 19. Instead
of powering the MC1723G from a single positive voltage
supply, it uses a negative bias as well. Although the refer
ence voltage of the MC1723G is then developed with
respect to that negative voltage it appears as a common
mode signal to the reference amplifier in the D-to-A con
verter. This allows use of its output amplifier as a
classic current-to-voltage converter with the non-inverting
The circuit of Figure 20 is a variation from the standard

voltage output circuit and will produce bipolar output
signals^ A positive current may be sourced into the sum
ming node to offset the. output voltage in the negative
direction. For example, if approximately 1.0 mA is used
a bipolar output signal results which may be described
as a 6-bit "1's" complement offset binary. V ref may be
used as this auxiliary reference. Note that R o has been
doubled to 10 kilohms because of the anticipated 20 V
(p-p) output range.
FIGURE20 - BIPOLARORNEGATIVEOUTPUT
VOLTAGECIRCUIT
input grounded.
Since 15 V and +5.0 V are normally available in a
combination digital-to-analog system, o n ly . the -5 .0 V
need be developed. A resistor divider is sufficiently accu
rate since the allowable range on pin 5 is from -2 .0 to
-8 .0 volts. The 5.0 kilohm pulldown resistor on the ampli
fier output is necessary for fast negative transitions.
Full scale output may be increased to as much as 32 volts
by increasing Ro and raising the +15 V supply voltage to
35 V maximum. The resistor divider should be altered to
comply with the maximum limit of 40. volts across the
MC1723G. Co may be decreased to maintain the same
R0 C0 product if maximum speed is desired.
Programmable Power Supply
The circuit of Figure 19 can be used as a digitally
programmed power supply by the addition of thumbwheel
switches and a BCD-to-binary converter. The output volt
age can be scaled in several ways, including 0 to +6.3 volts
in 0.1-volt increments, 0.05 volt; or 0 to 31.5 volts in
0.5-volt increments, 0.25 volt.
FIGURE19 - COMBINEDOUTPUTAMPLIFIERand
VOLTAGEREFERENCECIRCUIT
Polarity Switching Circuit, 6-Bit Magnitude Plus

Sign D-to-A Converter
Bipolar outputs may also be obtained by using a polarity

switching circuit. The circuit of Figure 21, gives 6-bits
magnitude plus a sign bit. In this configuration the oper
ational amplifier is switched between a gain of +1.0 and
-1.0. Although another operational amplifier is required,
no more space is taken when a dual operational amplifier
such as the MC1558G is used. The transistor should be
selected for a very low saturation voltage and resistance.
FIGURE21 - POLARITYSWITCHINGCIRCUIT
(6-Bit MagnitudePlusSignD-to-AConverter)
8-25
MC1406L, MC1506L

Programmable Gain Amplifier or Digital Attenuator
tv ..
' -1.1 I
' I
-When used in the multiplying mode the MC1506L can

be applied as a digital attenuator.: See Figure 22. One ad
vantage of this technique is that if Rs - 50 ohms, no
compensation capacitor is needed and a wide large signal
bandwidth ,is achieved. The small and large signal band*
widths are now identical and are shown in Figure 15.
The best frequency response is obtained by not allowing

1-12 to reach zero. -Rs can be set for a 1 .0 m A variation
in relation to 112- 12 630 never be negative.
The output current is always unipolar. The quiescent
dc output current level changes with the digital word that
makes ac coupling necessary.
FIGURE22 - PROGRAMMABLEGAINAMPLIFIEROR
DIGITALATTENUATORCIRCUIT
FIGURE24- OCCOUPLEDDIGITALATTENUATOR
andDIGITALSUBTRACTION
Of* is
'IS* >0*101
wv
I L
j
f
IIT L
rH i
l
*0
- 10
yip
mil i)
Panel Meter Readout
The MC1506L can be used to read out the status of
BCD or binary registers or counters in a digital control
system. The current output can be used to drive directly
an analog panel meter. External meter shunts may be
necessary if a meter of less than 2 0 mA full scale is used.
Full scale calibration can be done by adjusting R 12 or V ref.
l0*l0l-0?
O&talUbtraction:
vo* RU| Rg
|w-w|
PrepaMMMi AmpMitr
Conwui dyttl inputsiq A *8
v0*
FIGURE23- PANELMETER READOUTCIRCUIT
sw-sw
Vjjy .
Mil BIJj
w te-sa
This digital subtraction application is useful for indi*

eating when one digital word is approaching another in
value. More information is available than with a digital
comparator.
Bipolar inputs can be accepted by using any of the
previously described methods, or applied differentially to
R 12i and R122 or R 1 3 j and R132- V o will be a bipolar
signal defined by the above equation. Note that the circuit
shown accepts bipolar differential signals but does not have
a negative common-mode range. A very useful method is
to connect R 12i and R 122 to a positive reference higher
than the most positive input, and drive R 1 3 i and R132This yields high input impedance, bipolar differential and
common-mode range. The compensation depends on the
input method used, as shown in previous sections.
8 -2 6
MC1406L, MCI 506L

FIGURE2S- DIGITALSUMMINGandCHARACTER
GENERATION
FIGURE26 - PEAKDETECTINGSAMPLEandHOLD
(Featuresinfiniteholdtimeandoptional digital output.)
ST*T *?*?*? ?10
r^ n
o-f 4 o-
tfcH
CLOCK
rn :
5t
. " VCC VfE
0ETECT/K9TB
COMPARATOR
Vo-H o i * '02) "0

|R
12/ i t . 2W]
| I I
RI J
"0
*m,2
if
X I
101
1
14006
61
1
MC S
KC
U A jisA sA ilO
O l?
013
014
iA ?A tiA 3A
Ina character generationsystemone MC1506L circuit usesa

fixed reference voltage and its digital input defines the starting
point for a stroke. The secondconverter circuit hasarampinput
for the reference and its digital input defines the slope of the
stroke. Note that this approachdoesnot result ina 12-bit D-to-A
converter (seeAccuracySection).
Positivepeaksmaybedetectedbyinsertingahex inverterbetween
the counter and MC1506L, reversingthe comparator inputs, and
connectingtheoutput amplifierfor unipolaroperation.
FIGURE27 - PROGRAMMABLEPULSEGENERATOR
FIGURE28 - PROGRAMMABLECONSTANTCURRENTSOURCE
Fast rise and fall times require the use of high speed switching
transistors for the differential pair, Q4 and 05. Linear ramps
and sine waves may be generated by the appropriate reference
input.
Current pulses, ramps, staircases, andsinewavesmaybegenerated

by the appropriate digital and reference inputs. This circuit is
especiallyuseful incurvetracer applications.
FIGURE29 - ANALOGDIVISIONBYDIGITALWORD
FIGURE30 - ANALOGQUOTIENTOFTWO
DIGITALWORDS
This circuit yields the inverse of a digital word scaled by a

constant. For minimumerror over therangeof operation, Iq can
beset at 62iAsothat 112 will haveamaximumvalueof 3.938 mA
for adigital bit input configurationof 111 1 1 0 .
Compensation is necessary for loop stability anddependson
the type of operational amplifier used. If a standard 1.0 MHz
operational amplifier is employed, it shouldbe overcompensated
when possible. If this cannot be done, the reference amplifier
can furnish the dominant pole with extra Miller feedback from
pin 14 to 13. If the MC1723 or another widebandamplifier is
used, thereferenceamplifier shouldalways beovercompensated.
8-27
MC1406L, MC1506L
FIGURE31 - ANALOGPRODUCTOFTWODIGITALWORK
(High-SpeedOperation)
*01
1*02
JL. RqV
isou 6v0
MCI5061
MC14061
A
Lew i
0n
"C M C
0
OKC
MC1S0SI
MCU061
o
SpF
T 3 T 7 W
Vo-loiRO
03
r -
1 'A'Ai'i'H
Vtril
ni2i !*} Ro
|8( IVQI
'02* - Rt2j
h e wi
i!L
I
RUj |
m * Ro RI22 wd K > Vni/fllli'

l0 2 * ^ | t | | s |
K cm bt an Mtlog vnublt.
Two Digit BCD Conversion

MC1506L parts which meet the specification for 7-bit
accuracy can be used for the most significant word when
building a two digit BCD D-to-A or A-to-D converter. If
both outputs feed the virtual ground of an operational
amplifier, 10:1 current scaling can be achieved with a
resistive current divider. If current output is desired, the
units may be operated at full scale current levels of 4.0 mA
and 0.4 mA with the outputs connected to sum the currents.
The error of the D-to-A converter handling the least sig
nificant bits will be scaled down by a factor of ten.
FIGURE32- DIGITALQUOTIENTof TWOANALOGVARIABLES

orANALOG-TO-DIGITALCONVERSION
The circuit shown is a simple counterrampconverter. An UP/DOWNcounter

and dual threshold comparator can be
used to provide faster operation and
continuousconversion.
MC1408
MCI508
MOTOROLA
EIGHT-BIT M ULTIPLYING
DIG ITAL-TO-ANALOG
CONVERTER
EIGHT-BIT M ULTIPLYING
. . . designed fo r use where the o u tp u t current is a linear product

of an eight-bit digital w ord and an analog inp u t voltage.
Eight-B it Accuracy Available in Both Tem perature Ranges

Relative Accuracy: 0.19% E rror m axim um
(M C 1408L8, MC1408P8, M C 1508L8)
Seven and S ix-B it Accuracy Available w ith MC1408 Designated

by 7 or 6 S u ffix after Package S u ffix
Fast Settling Tim e 300 ns typical
N oninverting D igital Inputs are M T T L and

CMOS Com patible
O utput Voltage Swing - +0.4 V to -5 .0 V
High-Speed M u ltip ly in g In p u t
Slew Rate 4.0 m A //is
Standard Supply Voltages: + 5 .0 V and

-5 .0 V t o - 1 5 V
tell
M ( 1
Mj
"
L S U F F IX
CASE 620
,6
P S U F F IX
P LA S TIC P AC KAG E
CASE 648
F IG U R E 2 - B LO C K D IA G R A M
FIG U R E 1 - D -to -A T R A N S F E R C H A R A C T E R IS T IC S
RANGE
CONTROL
O A20 A30 A4O *50 A60 A70 A80

|S [6 17 [8 |9 |l0 |H |l2
Current Switches
.| | 1 I I I
i i i i i i i
I
i
8tas Circuit
R2.R Ladder
1
Current
Arnold
(00000000)
T Y P IC A L APPLIC A TIO N S
Tra ckin g A -to -D C onverters
A u d io D ig itiz in g and D ecoding
Program m able Pow er S upplies

A na lo g -D ig ita l M u ltip lic a tio n
2 1 /2 D ig it Panel Meters and D V M s
W a veform S ynthesis
Sam ple and H o ld
A na lo g -D ig ita l D ivision
Peak D e tecto r
Digital A d d itio n and S u b tra ctio n
P rogram m able G ain and A tte n u a tio n
Speech Com pression and E xpansion
C R T C haracte r G eneration
8-29
vcc
MC1408, MC1508
MAXIMUM RATINGS (Ta +25C unless otherwise noted.)
Rating
Symbol
Vcc
VEE
VgthruV12
Vo
'14
Vi4.Vi5
PowerSupplyVoltage
Digital InputVoltage
AppliedOutputVoltage.
ReferenceCurrent.
ReferenceAmplifierInput)
ta
MCI508
MC1408Series
Storage-TemperatureRange
T$tg
Value
+5.5
-16.5
Oto+b.b
+0.5.-5.2
5.0
VGC.VEE
-55 to+125
0to+75
-65 to+150
Unit
Vdc
Vdc
Vdc
mA
Vdc
C
C
(Vcc +5.0Vdc. Vee - -.15Vdc, jjpj-j 2.0 mA,MC1508L8: Ta -55Cto+125C.

MC1408LSeries: Ta* 0to+75Cunless,otherwisenoted. All digital inputsat highlogiclevel.)
(
Characteristic
Figure Symbol
Min Typ
Max
Unit
RelativeAccuracy1(Errorrelativetofull scalelo)'
4
%
Er
_
_
MC15C8L8, MC1408L8, MC1408P8
0.19
_
_
MC1408P7, MC1408L7, SeeNotet
0.39
MC1408P6, MC1408L6, SeeNote1
0.78
SettlingTimetowithin1/2LSBlincludestpLHl(TA+25C)SeeNote2 5
300
ns
S
ns
5 *PLH>*PHL
30,
100
TA+25C
Output Full ScaleCurrent Drift
-2 0
PPM/C
TCI0
Digital Input Logic Levels(MSB)
3
Vdc
HighLevel, Logic"1"
2.0
V|H
LowLevel, Logic"0"
0.8
. V|L
Digital InputCurrent (MSB)
3
mA
HighLevel, V|h5.0V
-.
0.04
0
i 'IH
LowLevel, V||_0.8V
-0.4
-0.8
lL
ReferenceInput BiasCurrent (Pin15)
ttA
3
-1.0
-5.0
*15 .
OutputCurrent Range
3
mA
'O
R
.
rt .
<
'VE-5.0v
O
2.0
2.1
Vee -15 V, TA- 25C
2.0
4.2 .
rt
OutputCurrent
3 k *o
mA
Vr0f =2.000V, R14-1000 n
1.9
1.99
2.1
OutputCurrent
-
3
0
l/A
4.0
'O(min)
(All bitslow)
OutputVoltageCompliance(Er<0.19%at Ta+25C)
3
Vq
Vdc
Pin1 grounded
-0.55, +0.4
Pin1open, Vee below-10V
-5.0. +0.4
ReferenceCurrentSlewRate
mA/jis
6
4.0
SRW
OutputCurrentPowerSupplySensitivity
PSRR(-)
n A /V
0.5
2.7
PowerSupplyCurrent 3
mA
+13.5
+22
i ce
(All bitslow)
-7.5
-13
' EE
3
+4.5 +5.0
+5.5
Vdc
V CCR
(TA - +25C)
-4.5
-15
-16.5
Veer
PowerDissipation
3
mW
Pd
All bitslow
V EE -5.0Vdc
170
1 105
Vee =-15Vdc
190
305
-
A ll bits high
Vee -5-0Vdc
Vee =-i5 vdc
SO
160
Note1. All currentswitchesaretestedtoguaranteeatleast 50%of ratedoutputcurrent.
Note2. All bitsswitched.
8-30
MC1408, MC1508
TEST CIRCUITS
FIGURE3- NOTATIONDEFINITIONSTESTCIRCUIT
v Cc
V | and 11 apply to in put* A1

thru A8
The re tiito r tied to pin IS it to tamperature compensate the
bias current and may n o t b necessary fo r atl application!.
r A1
O K
where K
A2
A3
A4
AS
A6
A7
A8 ,
16
32
64
128
256 -*
+ + I
V r. f
and A| m " 1 " if A ^ is at high level

A(^ * " 0 " If A n is at low level
FIGURE4 - RELATIVEACCURACYTESTCIRCUIT
M SB
E rro r (1 V - 1%l
FIGURES- TRANSIENTRESPONSEandSETTLINGTIME
8-31
MC1408, MC1508
FIGURE6 - REFERENCECURRENTSLEW
RATEMEASUREMENT
vCc
FIGURE7- POSITIVEV*f
vcc
FIGURE8 - NEGATIVEVraf
vCc
8-32
MC1408, MC1508
FIGURE9- MC1408. MC1508SERIESEQUIVALENT

CIRCUITSCHEMATIC
D IG IT A L INPUTS
CIRCUITDESCRIPTION
a low impedance termination of equal voltage for all legs of
theladder.
The R-2R ladder divides the reference amplifier current into
binarily-relatedcomponents, whichare fedtothe switches. Note
that there is always a remainder current which is equal to the
least significant bit. This current is shuntedtoground, andthe
maximumoutput current is 255/256 of the reference amplifier
current, or 1.992 mAfor a 2.0 mAreference amplifier current
if theNPNcurrentsourcepairisperfectlymatched.
The MC1408 consists of a reference current amplifier, an

R-2R ladder, andeight high-speedcurrent switches. For many
applications, only a reference resistor andreferencevoltageneed
beadded.
The switches are noninverting in operation, therefore a high
stateontheinputturnsonthespecifiedoutputcurrent component.
Theswitchusescurrent steeringfor highs0eed, andatermination
amplifier consisting of anactive loadgain stage withunitygain
feedback. Theterminationamplifierhotdstheparasiticcapacitance
of the ladder at aconstant voltageduringswitching, andprovides
8-33
MC1408, MC1508
GENERAL INFORMATION
Reference A m p lifie r Drive and Compensation
The reference amplifier provide* a voltage at pin 14 for con

vertingthereferencevoltagetoacurrent andaturn-aroundcirtuit
or current mirror for feedingtheladder. Thereferenceamplifier
input current, 114, must always flowintopin14regardlessof the
setupmethodorreferencevoltagepolarity.
ConnectionsforapositivereferencevoltageareshowninFigure
7. The reference-voltagesourcesuppliesthefull current 114. For
bipolarreferencesignals, as inthemultiplyingmode, R15canbe
tied to,a negativevoltage corresponding to the minimuminput
level. It is possible to eliminateR1Swithonlyasmatl sacrifice
inaccuracy andtemperature drift. Another methodfor bipolar
inputsisshowninFigure 25.
The compensationcapacitor value most beincreasedwithin
creases in R14 to maintainproper phasemargin; for R14 values
of 1.0, 2.5 and5.0 kilohms, minimumcapacitor values are 15,
37, and 75 pF. The capacitor shouldbe tied toVggas this in
creasesnegativesupplyrejection.
'
Anegative reference voltage may be usedif R14 isgrounded
andthereferencevoltageisappliedto R15 asshowninFigure8.
Ahigh input impedance is the main advantage of this method.
Compensation involves a capacitor to V^g on pin 16, usingthe
values of the previous paragraph. The negativereferencevoltage
must be at least 3.0-volts above the Vgg supply. Bipolar input
signalsmaybehandledbyconnectingR14 toapositivereference
voltageequal tothepeakpositiveinput level atpin15.
Whenadcreferencevoltageisused, capacitivebypasstoground
is recommended. The 5.0-Vlogic supplyis not recommendedas
areferencevoltage. If awell regulated5.0-Vsupplywhichdrives
logic is tobe'usedas the reference, R14 shouldbedecoupledby
connecting it to +5.0 Vthrough another resistor andbypassing
the junction of the two resistors with 0.1 aiF to ground. For
referencevoltagesgreater than5.0 V, aclampdiodeisrecommen
dedbetweenpin14andground.
If pin 14 is driven by a high impedance such as atransistor
current source, none of the above compensation methodsapply
and the amplifier must be heavily compensated, decreasing the
overall bandwidth.
Refer to the subsequent text section on SettlingTime for more

detailsonoutputloading.'
If apower supplyvaluebetween-5.0 Vand-10 Visdesired,
avoltageof between~0and-5.0 Vmaybe appliedto pin1. The
valueof thisvoltagewiil be themaximumallowablenegativeout
putswing.
O utput Current Range
The output current maximumratingof 4.2 mAmaybeused

only for negative supply voltages typically more negative than
-8.0 volts, dueto the increasedvoltagedropacross the350-ohm
resistorsinthereferencecurrent amplifier.
Accuracy
Absoluteaccuracy is themeasureof e8Ch output current level
withrespect to its intendedvalue, andis dependent uponrelative
accuracy and full scale current drift. Relative accuracy is the
measureof eachoutput current level asafractionof thefull scale
current. The relative accuracy of the MC1408 is essentially
constant withtemperatureduetotheexcellent temperaturetrack
ingof themonolithic resistor ladder. The reference current may
drift withtemperature, causingachange intheabsoluteaccuracy
of output current. However, the MC1408 has a very luwfull
scalecurrentdriftwithtemperature.
The MC1408/MC1508 Series is guaranteedaccurate to with
in11/2 LSBat +25Cat afull scaleoutputcurrent of 1.992mA.
This corresponds toa referenceamplifier output current drive to
theladder networkof 2.0 mA, withthelossof oneLSB=8.0fiA
whichistheladderremaindershuntedtoground. Theinput current
to pin 14 has a guaranteedvalue of between 1.9 and2.1 mA,
allowing some mismatch in the NPNcurrent source pair. The
accuracy test circuit is shown inFigure4. The 12-bit converter
iscalibratedfor afull scaleoutput current of 1.992 mA. This is
an optional step since the MC1408 accuracy is essentially the
same between 1.5 and 2.5 mA. Then the MC1408 circuits' full
scalecurrent is trimmedtothesamevaluewithR14sothat azero
valueappearsattheerroramplifieroutput. Thecounter isactivated
andtheerror bandmay bodisplayedonanoscilloscope, detected
bycomparators, orstoredinapeakdetector.
Two 8-bit D-to-Aconverters may not beusedtoconstruct a
16-bit accurate D-to-Aconverter. 16-bit accuracy implies a total
errorof .1/2of onepartin65, 536, or0.00076%, whichismuch
more accurate than the 0.19% specification provided by the
MC1408x8.
O utpu t Voltage Ranga
The voltage onpin4 is restrictedtoarangeof -0.55 to+0.4

volts at +25C, due to thecurrent switchingmethodsemployed
in the MC1408. Whenacurrent switchis turnedoff", theposi
tive voltage on the output terminal can turn "on" the output
diodeandincreasetheoutputcurrentlevel. Whenacurrent switch
is turned "on", the negative output voltage range is restricted.
The base of the terminationcircuit Darlington transistor is one
diodevoltage belowgroundwhenpin 1 isgrounded, soanegative
voltage belowthe specifiedsafe level will drive the lowcurrent
device of the Darlington into saturation, decreasing the output
currentlevel.
The negative output voltage compliance of the MC1408may
beextendedto-5.0 Vvolts byopeningthecircuit at pin1. The
negative supply voltage must be more negative then -10 volts.
Usinga full scale current of 1.992 mAandloadresistor of 2.5
kilohms between pin 4 and groundwill yielda voltage output
of 256 levels between 0 and-4.980 volts. Floating pin 1does
not affect theconverterspeedorpowerdissipation. However, the
value of the loadresistor determines the switching time due to
increasedvoltageswing. Values of R[_upto 500ohmsdonotsig
nificantly affect performance, but a 2.5-kilohtn load increases
"worstcase"settlingtimeto1.2 fis (whenall bitsareswitchedon).
MultiplyingAccuracy
The MC1408 may be used in the multiplying mode with
eight-bitaccuracywhenthereferencecurrent isvariedover arange
of 256:1. The major source of error is the bias current of the
terminationamplifier. Under "worstcase"conditions, theseeight
amplifiers can contribute a total of 1.6 <iAextra current at the
output terminal. If thereferencecurrent inthemultiplyingmode
ranges from16 ffAto 4.0 mA, the 1.6 iiAcontributes anerror
of 0.1 LSB. This is well within eight-bit accuracy referencedto
4.0mA.
Amonotonic converter is one which supplies an' increase in
current for each increment in the binary word. Typically, the
MC1408 is monotonic for all values of reference current above
0.5mA. Therecommendedrangeforoperationwithadcreference
current is0.5 to4.0mA.
8-34
MC1408, MCI 508
GENERAL INFORMATION (Continued)
SettlingTime
The "worst cate" switchingconditionoccurs whenall bitsare
switched "on", whichcorresponds toalow-to-hightransitionfor
all bits. This time is typically 300 ns for settlingtowithin1/2
LSB, for 8-bit accuracy, and 200 ns to 1/2 LSB for 7and6-bit
accuracy. The turnoff is typically under 100 ns. Thesetimes
applywhenR|_<500 ohmsandCo<25 pF.
Theslowestsingleswitchistheleastsignificant bit. whichturns
"on" andsettles in250 ns andturns "off" in80 ns. Inapplica
tions where the D-to-Aconverter functions in a positive-going
rampmode, the "worst case" switchingconditiondoesnotoccur,
anda settling time of less than300 nsmayberealized. Bit A7
turns "on" in200 nsand"off" in80 ns, whilebit A6 turns"on"
in150nsand"off" in80ns.
The test circuit of Figure 5requiresasmallervoltageswingfor

the current switches due tointernal voltageclampingintheMC1408. A 1.0-kilohm load resistor frompin 4 to ground gives
atypical settlingtimeof 400 ns. Thus, it isvoltageswingandnot
the output RC time constant that determines settling time for
mostapplications.
Extra caremust be takeninboardlayout since this isusually
the dominant factor insatisfactory test results when measuring
settling time. Short leads, 100mFsupplybypassingfor lowfre
quencies, andminimumscopeleadlengthareall mandatory.
(Vcc +5.0V, Vee **5 v-TA+25Cunlessotherwisenoted.)

FIGURE11- TRANSFERCHARACTERISTICversusTEMPERATURE
(ASthruA8 thresholdsliewithinrangefor A1thruA4)
FIGURE10- LOGICINPUTCURRENTversusINPUTVOLTAGE
FIGURE12- OUTPUTCURRENTversusOUTPUTVOLTAGE
(Seetext forpin1restrictions)
FIGURE13- OUTPUTVOLTAGEversusTEMPERATURE
(Negativerangewithpin1openis-5.0Vdcoverfull temperaturerange)
1.0
* 0.8
- o.s
C *0.4
S *0.2
h0 0
>
5
- 0.2
___ y Allow*!* Vp FUngeV

tor 8-bit Accuracy 7 /
/ w
(pin 1 groundtd)^J
'///,
1 -0.4
- 0.6
- 0.8
- 1.0
*50
T. TEMPERATURE lC)
8-35
+100
MC1408, MC1508
TYPICAL CHARACTERISTICS (continued)
(Vcc +5.0V, VgEIS V, T/^" +28Cunlessotherwisenoted.)

FIGURE14- REFERENCEINPUTFREQUENCYRESPONSE
versusTEMPERATURE(all bitslow)
T. TEMPERATURE (C)
versusVê ^ >w*l
Unitsothtnwfc*spctilitd:
R14- R151.0ktl
C15pf, pin16toVee
RL*50n.pin4toGNO
CuivtA: largeSignalBandwidth
M
tthodolFigure7
Vr,|- 2.0V(p-p)olfttt1.0Vtbovt6N0
20
_ 18
<
e
5
UJ
CC 14
Cure*B: SmallSignalBandwidth
M
tthodofFigura7 Rl-25011
Vftf50mV(p-p)aflat200mVabovtGND
CitntC: latgtandSmallSigndBandwidth
M
tthodofFiguft25(nosp-ampl,Rl5019
RS"50
Vftf*2-0V
Vs100mV(p-p)ctnttrtdat0V
ft
Icc
12
I 10
| U
>EE
6.0
' 4.0
0 -2.0 -4.0 -6.0 -8.0 .10 -12 -14 -IS -18 -20
VE,NEGATIVEPOW
ERSUPPLV(Vdc)
FIGURE17- OUTPUTCURRENTTOVOLTAGECONVERSION
t6
32
64
128
250)
A d ju tt V rci , R 14 o r H q that V Q w ith a ll digital fn p u tt at high

) l it oqual to 9.9 61 vo lH .
2 V
V0 <6k)
Il1.1t
8
2651
> 9.9 61 V
2561
8-36
16
32
64
'
+
f
128
2661
MC1408, (VIC1508
Voltageoutputsof alarger magnitudeareobtainablewiththis

circuit which use*'anexternal operational amplifierasacurrent
to voltageconverter. This.configurationautomaticallykeepsthe
output of the MCI408 at groundpotential and the operational
amplifiercangenerateapositivevoltagelimitedonlybyitspositive
supplyvoltage. Frequencyresponseandsettlingtimeareprimarily
determinedbythecharacteristics of theoperational amplifier. In
addition, theoperational amplifiermust becompensatedfor unity
gain,andintomecasesovercompensationmaybedesirable.
Notethat thisconfigurationresultsinapositiveoutput voltage
only, the magnitude of whichis dependent onthe digital input.
Thefollowingcircuit shows howthe LM301AGcanbeused
in a feedforward mode resulting ina full scale settling time on
theorderof 2.0 ms.
The positive voltage range maybeextendedbycascadingthe

output withahighbetacommonbasetransistor, Q1 , asshown.
FIGURE20- EXTENDINGPOSITIVE
VOLTAGERANGE
FIGURE18
Analternative methodisto usethe MC1539Gandinputcom

pensation. Respopie of thiscircuit isalsoontheorderof 2.0ps.
FIGURE19
The output voltagerange for this circuit is 0 volts to BVqbO

of the transistor. If pin1 is left open, thetransistor basemaybe
grounded, eliminatingboththe resistor andthediode. Variations
inbeta must be consideredfor wide temperature range applica
tions. Aninvertedoutput waveformmaybeobtainedbyusinga
loadresistor froma positivereference voltage to the collector of
the transistor. Also, high-speedoperationis possible withalarge
output voltageswing, because pin4 isheldat aconstant voltage.
The resistor (R) to Vee maintains the transistor emitter voltage
when all bits are "off" and insures fast turn-on of the least
significant bit.
CombinedOutputAmplifierandVoltageReference
For manyof its applications the MC1408 requiresareference
voltage andan operational amplifier. Normally the operational
amplifier is usedasacurrent tovoltageconverter andits output
needonlygopositive. WiththepopularMC1723Gvoltageregula
tor bothof these functionsareprovidedinasinglepeckage with
theaddedbonusof upto ISOmAof output current. SeeFigure
21. TheMC1723Gusesbothapositiveandnegativepowersupply.
The reference voltage of the MC1723Gis then developedwith
respect to the negative voltage andappears as a common-mode
signal to the reference amplifier in the D-to-Aconverter. This
allows use of its output amplifier as a classic current-to-voltage
converterwiththenon-invertinginput grounded.
Since 15 Vand+5.0 Vare normallyavailable inacombina
tiondigital-to-analogsystem,onlythe-5.0 Vneedbe developed.
Aresistor divider issufficientlyaccuratesincetheallowablerange
on pin 5 is from-2.0 to -8.0 volts. The 5.0 kilohmpulldown
resistor on the amplifier output is necessary for fast negative
transitions.
Full scaleoutput maybe increasedtoasmuchas 32volts by
increasingRo andraisingthe +15 Vsupplyvoltageto35 Vmaxi
mum. The resistor divider shouldbeelteredtocomplywiththe
maximumlimit of 40 volts across the MC1723G. Co may be
decreasedtomaintain'thesameRoCoproduct if maximumspeed
isdesired.
MC1408, MC1508
ProgrammablePowerSupply
Thacircuit of Figure21canbeusedat adigitallyprogrammed
power supplybytheadditionof thumbwheel switchesandaBCDto-binary converter. The output voltagecanbescaledinseveral
mays, including0to+25.5voltsin0.1-volt increments, 0.05volt;
or0 to5.1voltsin20mVincrements, 10mV.
FIGURE22- BIPOLARORNEGATIVEOUTPUT
VOLTAGECIRCUIT
FIGURE21 - COMBINEDOUTPUTAMPLIFIERand
VOLTAGE REFERENCE CIRCUIT
B0 5 k
At
A2
A3 A4 AS
A6
A?
* ~ * * 1 6 * 3 2 * 6 4 *12 8* 2501 ~
(R o 1
FIGURE23- BIPOLARORINVERTEDNEGATIVE
OUTPUTVOLTAGECIRCUIT
A 1A 2 A 3 A 4 A S A 6 A 7 A S
Fo r A - 0 0 0 0 0 0 0 0
b it configuration
Vo - -vf. f
For 5 .0 M tt output rr>g.
BipolarorNegativeOutputVoltage
Thecircuit of Figure 22 isavariationfromthestandardvolt
age output circuit and will produce bipolar output signals. A
positivecurrent may. besourcedintothesummingnodetooffset
the output voltage in the negative direction. For example, if
approximately1.0mAisusedabipolaroutput signal resultswhich
maybedescribed8S a8-bit "1s" complementoffset binary. Vref
may be usedas thisauxiliary reference. Note that Rohas been
doubled to 10 kilohms because of the anticipated 20 V(p-p)
output range.
Vr t 1
R14C R0
-5.00 volts
R I B - 2.5 kfl
37 pF (mini
B ktl
Decrease R q to 2.S k f l fo r a 0 to -S.O-volt outp u t ranga.

This application provides somewhat lower spaed, as previously
discussed in tha O utput Voltage Range section of the General
Inform ation.
MCI408, MC1508
PolaritySwitchingCircuit 8-Bit'Magnitude
PluiSignO-to-AConverter
Bipolaroutputsmayaltobeobtainedbyusingapolarityswitch
ingcircuit. The circuit of Figure 24 gives 8-bit magnitude plus
asignbit Inthisconfigurationtheoperationalorrtptifierisswitched
between a gainof +1.0 and- 1 .0. Althoughanother operational
amplifierisrequired,nomorespaceistakenwhenadualoperational
amplifiersuchasthe MC1658Gis used. The transistorshouldbe
selectedforaverylowsaturationvoltageandresistance.
Panel MeterReadout
The MC1408 can be usedto readout the status of BCDor
binaryregistersorcountersinadigital control system. Thecurrent
output can be tisedto drive directlyananalogpanel meter. Ex
ternal meter shunts may benecessary if ameter of less than2.0
mAfull scele'isused. Full scalecalibrationcanbedonebyadjust
ingR14or Vref.
FIGURE26- PANELMETERREADOUTCIRCUIT
FIGURE24- POLARITYSWITCHINGCIRCUIT
(8-BitMagnitudePlusSignO-to-AConverter)
ProgrammableGainAmplifieror Digital Attenuator

When used in the multiplying mode the MP1408 can be
appliedasadigital attenuator. See Figure 25. Oneadvantageof
this technique is'that if Rg50ohms, nocompensationcapacitor
isneeded. Thesmall andlargesignal bandwidthsarenowidentical
andareshowninFigure14.
The best frequency response isobtainedbynot allowing1)4
to reach zero. However, the high impedance node, pin 16, is
clampedto prevent saturationandinsurefast recoverywhenthe
current throughR14 goes tozero. R canbeset for a.1.0 mA
variationinrelationto114. 114 canneverbenegative.
Theoutputcurrentisalwaysunipolar. Thequiescentdcoutput
currentlevelchangeswiththedigitalwordwhichmakesaccoupling
necessary.
FIGURE2S- PROGRAMMABLEGAINAMPLIFIEROR
DIGITAL ATTENUATOR CIRCUIT
FIGURE27 - DCCOUPLEDDIGITALATTENUATOR
and DIGITAL SUBTRACTION
Vee vcc
vS
Digital Subtraction:
le t
v rl I
BU ',
v ' ^ 7
8-39
v ml 2
Programm able A m p lifie r:

Connect Digital In p u ts A * 0
R14j
RoIW
" H i
vo-
v rof 1 _
R141
V re f 2
R143
MC1408, MC1508
APPLICATIONS INFORMATION (continuad)
FIGURE30 - NEGATIVEPEAKDETECTING
SAMPLEANDHOLD
Thisdigitalsubtractionapplicationisuseful for indicatingwhen

onedigitalwordisapproachinganotherinvalue. Moreinformation
isavailablethanwithadigital comparator.
Bipolar inputscanbeacceptedbyusinganyof thepreviously
described methods, or applieddifferentially to R14i andR142
or RISi andR152- Vo will be abipolar signal definedby the
aboveequation. Notethat thecircuit shownacceptsbipolardiffer
ential signals but does not haveanegativecommon-mode range.
Averyuseful methodisto connect R14j andR142 toapositive
reference higher thanthemostpositiveinput, anddriveR15i and
R152- Thisyieldshighinput impedance, bipolar differential and
common-moderange.
FIGURE28 - DIGITALSUMMINGandCHARACTERGENERATION
V o i i w l - 0 to -5.0 volt!
FIGURE31 - PROGRAMMABLEPULSEGENERATION
v rf 1
0 to 1 0 Volt
in 4.0 mV ittp i
~ Vcci
*V
ee
s.ov -tsv
Fast riseandfall times require theuseof high-speedswitching

transistors for thedifferential pair, 04 and05. Linearrampsand
sine waves may be generatedbythe appropriate reference input.
In a character generationsystemone MC1408 circuit uses a
fixed reference voltage andits digital input defines the starting
point for astroke. Thesecondconvertercircuit hasarampinputfor the reference and its digital input defines the slope of the
stroke. Note that thisapproachdoesnot resultina 16-bit D-to-A
converter (seeAccuracySection).
FIGURE32- PROGRAMMABLECONSTANTCURRENTSOURCE
FIGURE29|POSITIVEPEAKDETECTINGSAMPLEandHOLD
(Featuresindefiniteholdtimeandoptional digital output.)
Clock Ottoct/Hold
Currentpulses, ramps, staircases, andsinewavesmaybegenera

tedby theappropriate digital andreferenceinputs. Thiscircuit is
especiallyuseful incurvetracerapplications.
8-40
MC1408, MC1508
FIGURE33- ANALOGDIVISIONBYDIGITALWORD
FIGURE34 - ANALOGQUOTIENTOFTWODIGITALWORDS
ot
vee
This circuit yields the inverse of a digital wordscaledby a
constant For minimumerror overtherangeof operation, Iocan
be set at 16fiAsothat 114 will haveamaximumvalue of 3.S84
mAforadigital bitinputconfigurationof 00000001.
Compensation is necessary for loop stability anddepends on
the type of operational amplifier used. If a standard 1.0 MHz
operational amplifier it employed, it shouldbeovercompensated
whenpossible. If the MCI733, MCI520 or anyother wideband
amplifier are used, the reference amplifier should always be
overcompensated.
FIGURE35 - ANALOGPRODUCTOFTWODIGITALWORDS
(High-SpeedOperation!
j A | Ro
' 2 "
' R 142
R 142
R 14j ^
Vrf
S in c o R q R 1 4 2 and K = ----R141
it
K can bo an analog variable.
V r .l
'01
R14i
v'*' 1
l,1
---.q2 R14*
*
I R U | 14j
o.-'o. jI-s)J
MC1408, MC1508
FIGURE38- TWO-DIGITBCDCONVERSION
Two8-bit, D-to-Aconverterscanbeusedto builda twodigit

BCDD-to-Aor A-to-Dconverter. If bothoutputsfeedthevirtual
ground of an operational amplifier, 10:1 current scalingcan be
achievedwitharesistivecurrent divider. If current output isde
sired, the units may be operated at full scale current levels of
4.0mAand0.4mAwiththeoutputsconnectedtosumthecurrents.
The error of the D-to-Aconverter handling the least significant
bits will bescaleddownbyafactorof tenandthusanMCI408L6
maybeusedfor theleast significantword.
FIGURE37- DIGITALQUOTIENTOFTWOANALOGVARIABLES
orANALOG-TO-DIGITALCONVERSION
V in
used to provide fatter operation in d continuout conversion.
V|n/0
V ref/R 14
8-42
MOTOROLA
EIGHT-BIT M ULTIPLYIN G
DIG ITAL-TO -ANALO G
CONVERTER
LOW-COST EIGHT-BIT MULTIPLYING

. . . designed fo r use where the o u tp u t cu rren t is a linear product
of an eight-bit digital w ord and an analog in p u t voltage.
Relative Accuracy: 0.5% Error M axim um
Low Price A llow s Use o f a D /A in Many New A pplications
M o no ton icity Guaranteed to 8 Bits
Fast Settling Tim e - 300 ns typical
N oninverting D igital Inputs are M T T L and

CMOS C om patible
O u tp u t Voltage Swing +0.4 V to -5 .0 V
High-Speed M u ltip ly in g Inp u t

Slew Rate 4.0 mA//JS
Standard Supply Voltages: + 5 .0 V and

-5 .0 V t o - 1 5 V
L S U F F IX
CASE 620
F IG U R E 2 - B L O C K D IA G R A M
F IG U R E 1 - D -to -A T R A N S F E R C H A R A C T E R IS T IC S
MSB
LSB
AtO A20 A30 A4p A50 A60 A70 A8O
|5 |(i |?
|B
|9 |lO 111 112
T Y P IC A L A P P LIC ATIO N S
T ra ckin g A -to -D C onverters
A u d io D ig itiz in g and D ecoding
P rogram m able P ow er S upplies

A n a lo g -D ig ita l M u ltip lic a tio n
2 1 /2 D ig it Panel M eters and D V M 's
W a ve fo rm S ynthesis
Sam ple and H o ld
A n a lo g -D ig ita l D ivisio n
Peak D e te cto r
D ig ita l A d d itio n and S u b tra c tio n
P rogram m able Gain and A tte n u a tio n
Speech C om pression and E xpansion
C R T C haracte r G eneration
8-43
MC3408
MAXIMUM RATINGS (T a +25C unless otherwise noted.)
Symbol
VCC
VEE
V5 thruV12
V0
*14
V14.V1S
Ta
Tstg
Tj
' Rating
PowerSupplyVoltage
AppliedOutputVoltage
ReferenceCurrent
ReferenceAmplifierInputs
OperatingAmbientTemperatureRange
JunctionTemperature
Value
7.0
-16.5
Oto+15
0.5.-5.2
5.0
VCC-VEE
0 to+70
-65 to+150
+175
Unit
Vdc
Vdc
Vdc
mA
Vdc
C
C
C
(Vcc " +S-0 Vdc, Vee -15 Vdc, 2.0 mA, Ta " 0 to+70Cunlessotherwisenoted.
All digital inputsat h'ighlogiclevel.)
Min Typ
Max
Unit
Characteristic
Figure Symbol
4
%
0.5
RelativeAccuracy(Errorrelativetofull scale10 * Note1
Er
Monotonicity
G
u
a
ra
n
tee
d
to
8
b
its
SeeMultiplyingAccuracyonPage6
ns
300
5
SettlingTimetowithin *0.5%of Pull Scale [includestp|_n)
S
(TA-+2SC)SceNote2
ns
30
100
5 *PLH.PHL _
TA- +28C
-30
PPM/C
OutputFull ScaleCurrent Drift
TCI0
Vdc
3
Digital Input LogicLevels(MSB)
2.0
HighLevel, Logic"1"
V|H
_
0.8
LowLevel, Logic0"
VlL
mA
3
Digital InputCurrent (MSB)
0.04
0
HighLevel, V|h5.0V
iH
-0.4
-0.8
LowLevel, V||_0.8V
'IL
-5.0
M
A
3
-1.0
is
mA
OutputCurrent Range
3
*OR
0
2.0
2.1
VgE-5 0V
2.0
4.2
0
Vee -15 v (TA- 25C)
mA
3
OutputCurrent
'o
1.99
2.1
1.9
Vref - 2.000V, R14= 1000 n
mA
0
4.0
3
OutputCurrent
*0(min)
(All bitslow)
Vdc
3
OutputVoltageCompliance(Er< 0.5%at Ta+25CI
Vo
-0.5,+0.4
Pin1grounded
-5.0.+0.4
Pin1open, Vee below-10V
4.0
mA/ps
6
ReferenceCurrentSlewRata
SRIref
4.0
jiA/V
PSRRI
)
0.5
Output CurrentPowerSupplySensitivity
mA
3
PowerSupplyCurrent
+22
+13.5
'CC
-13
-7.5
(All bitslow)
ee
Vdc
+5.5
3
+4.5 +5.0
VCCR
-16.5
-15
-4.5
(Ta* +28C)
veer
mW
3
PowerConsumption
PC
All bitslow
170
105
Vee -5-0Vdc
305
190
vee -is vdc
All bits high
90
Vee -5.0Vdc
160
vee -15 vdc
Note1. Fordeviceswithgreateraccuracy, seeMC1508Seriesdatasheet.
Note2. All bitsswitched.
8-44
MC3408
TEST CIRCUITS
FIGURE3- NOTATIONDEFINITIONSTESTCIRCUIT
Vcc
V | and 11 apply to input* A I
thru AB
The resistor tied to pin 15 is to temperature compensate the
bias current and may not be necettary fo r all application*.
r AI
A2
A3
1 2
lO 'K I
A4
A5
16
32
Vref
and A|^ - " 1 " if A ^ i> at high lovel
Afg 0 " if A|y| it at low lovel
FIGURE4 - RELATIVEACCURACYTESTCIRCUIT
MSB
AI
A2
A3
A4
A5
A6
12-Bit
0-fO-A
Conv*rtr
< 1.0.02*
error m *x)
A7
A8
A9 A 1 0 A11 A12
FIGURE5 - TRANSIENTRESPONSEandSETTLINGTIME
8-45
A6
A7
64
139
A8 i
+
* 2
r
SB J
MC3408
FIGURE6 - REFERENCECURRENTSLEW
RATEMEASUREMENT
vCc
FIGURE7- POSITIVEVref
Vcc
FIGURE8 - NEGATIVEVraf
Vcc
8-46
MC3408
FIGURE9 - MC3408EQUIVALENT
CIRCUITSCHEMATIC
D I G I T A L IN P U T S
C O M P E N S A T IO N
V re,(_)
Ee
o u tpu t
g n d
RANGE
CONTROL
CIRCUITDESCRIPTION
a low impedance termination of equal voltage for all legs of
theladder.
The R-2R ladder divides the reference amplifier current into
binarily-relatedcomponents, which are fedto the switches. Note
that there is always a remainder current which is equal to the
least significant bit. This current is shuntedtoground, andthe
maximumoutput current is 255/256 of the reference amplifier
current, or 1.992 mAfor a 2.0 mAreference amplifier current
if theNPNcurrent sourcepair isperfectlymatched.
The MC3408 consists of a reference current amplifier, an

R-2R ladder, andeight high-speedcurrent switches. For many
applications, only a reference resistor andreference voltage need
beadded.
The switches are noninverting in operation, therefore a high
stateontheinputturnsonthespecifiedoutputcurrent component.
Theswitchusescurrent steeringlor highspeed, andatermination
amplifier consisting of an active loadgain stags withunity gain
feedback. Theterminationamplifier holds the parasitic capacitance
of the ladder at aconstant voltage duringswitching, andprovides
8-47
MC3408
GENERAL INFORMATION
Reference A m p lifie r Drive and Com p* n u t ion
The reference amplifier provide* a voltage at pin 14 for con

vertingthereferencevoltagetoacurrent, andaturn-aroundcircuit
or current mirror for feedingthe ladder. Thereferenceamplifier
input current. 114, mutt always flowintopin14regardlessof the
setupmethodorreferencevoltagepolarity.
ConnectionsforapositivereferencevoltageareshowninFigure
7. The referencevoltage sourcesuppliesthefull current 114. For
bipolar reference signals, as inthemultiplyingmode, R15 canbe
tied to a negative voltage corresponding to the minimuminput
level. It is possible to eliminate R15 withonlya small sacrifice
inaccuracyandtemperature drift.
The compensationcapacitor value must beincreasedwith in
crease* in R14 to maintain proper phasemargin; for R14 values
of 1.0, 2.S and 5.0 kilohms, minimumcapacitor values are 15,
37, and 75 pF. The capacitor should be tied to Vgg as this
increase*negativesupplyrejection.
Anegative reference voltage may be usedif R14 isgrounded
andthe referencevoltage isappliedto R15as shown inFigure8.
Ahigh input impedance is the main advantage of' this method.
Compensation involves a capacitor to Vgg on pin 16, usingthe
values of the previousparagraph. The negativereferencevoltage
must be at least 3.0-volts above the Vgg supply. Bipolar input
signalsmay behandledbyconnectingR14 toapositivereference
voltageequal tothepeakpositiveinput level at pin15.
Whenadcreferencevoltageisused, capacitivebypasstoground
isrecommended. The 5.0-Vlogic supplyis not recommendedas
areferencevoltage. If awell regulated5.0-Vsupplywhichdrives
logic is to beusedas the reference. R14 shouldbe decoupledby
connecting it to +5.0 V through another resistor and bypassing
the junction of the two resistor* with 0.1 pF to ground. For
referencevoltagesgreater than 5.0 V, adampdiodeisrecommen
dedbetweenpin14andground.
If pin 14 is driven by a high impedance such as atransistor
current source, none of the above compensation methods apply
and the amplifier must be heavily compensated, decreasing the
overall bandwidth.
OutputVoltageRange
The voltage on pin4 is restricted to a rangeof -0.5 to+0.4
volts at +25C. due to thecurrent switchingmethodsemployed
in the MC3408. Whenacurrent switchisturned"off", the posi
tive voltage on the output terminal can turn "on" the output
diodeandincreasetheoutputcurrent level. Whenacurrent switch
is turned "on", the negative output voltage range is restricted.
The base of the termination circuit Darlington transistor is one
diodevoltage belowgroundwhenpin 1 isgrounded, soanegative
voltage belowthe specified safe level will drive the lowcurrent
device of the Darlington into saturation, decreasing the output
current level.
The negative output voltage compliance of the MC3408may
beextendedto-5.0 Vvolts byopeningthecircuit at pin1. The
negative supply voltage must be more negative than-10 volts.
Usinga full scale current of 1.9S2 mAand load resistor of 2.5
kilohms between pin 4 and groundwill yielda voltage output
of 256 levels between 0 and-4.980 volts. Floating pin 1does
not affect theconverterspeedorpowerdissipation. However, the
value of the loadresistor determines the switching time due to
increasedvoltageswing. Values of Rl upto 500ohmsdonot sig
nificantly affect performance, but a 2.5-kilohmload increases
"worstcase"settlingtimeto1.2 ms(whenall bitsareswitchedon).
Refer to the subsequent text section on SettlingTime for more

detailsonoutputloading.
If apower supplyvalue between-5.0 Vand-10 Visdesired,
avoltageof between0 and-5.0 Vmay beappliedto pin1 . The
value of this voltagewill be themaximumallowablenegativeout
put swing.
OutputCurrent Range
The output current maximumratingof 4.2 mAmay beused
only for negative supply voltages typically more negative than
-8.0 volts, due tothe increasedvoltagedropacross the 350-ohm
resistorsinthereferencecurrentamplifier.
Accuracy
Absoluteaccuracy isthe measureof each output current level
withrespect to its intendedvalue, andis dependent uponrelative
accuracy and full scale current drift. Relative accuracy is the
measureof eachoutput current level asafractionof thefull scale
current. The relative accuracy of the MC3408 is essentially
constant with temperatureduetotheexcellent temperaturetrack
ingof themonolithic resistor ladder. The referencecurrent may
drift with temperature, causingachange intheabsoluteaccuracy
of output current. However, the MC3408 has a very lowfull
scalecurrent drift withtemperature.
The MC3408 isguaranteedaccurate towithin0.5%at +25C
at afull scale output current of 1.992 mA. This correspondstoa
referenceamplifier output current drive'tothe ladder networkof
2.0 mA, with the loss of one LSB= 8.0iAwhichis the ladder
remainder shuntedto ground. The input current to pin 14has a
guaranteed value of between 1.9 and 2.1 mA, allowing some
mismatch in the NPNcurrent source pair. The accuracy test
circuit isshowninFigure4. The 12-bit converteriscalibratedfor
a full scale output current of 1.992mA. This isanoptional step
sincetheMC3408accuracyitessentiallythesamebetween1.5and
2.5 mA. Thenthe MC3408circuits' full scalecurrent is trimmed
to the same value with R14 so that a zerovalueappearsat the
error amplifier output. The counter is activated and the error
band may be displayed on an oscilloscope, detected by com
parators, orstoredinapeakdetector.
Two 8-bit D-to-Aconverters may not be usedtoconstruct a
16-bit accurate D-to-Aconverter. 16-bit accuracy implies a total
errorof 1 12 of onepart in65, 536, or0.00076%, whichismuch
more accurate than the 0.5% specification provided by the
MC3408.
MultiplyingAccuracy
The MC3408 may be used in the multiplying mode with
goodaccuracy when the reference current isvariedover arange
of 256:1. The major source of error is the bias current of the
terminationamplifier. Under "worstcase" conditions, theseeight
amplifiers can contribute a total of 1.6 mAextra current at the
output terminal. If thereferencecurrent inthemultiplyingmode
ranges from16 iAto 2.0mA, the 1.6 pAcontributes anerror
of 0.2 LSBwithrespect tothe2.0mA.
A monotonic converter is one whichsupplies an increase in
current for each increment in the binary word. Typically, the
MC3408 is monotonic for all values of reference current above
0.5mA. Therecommendedrangeforoperationwithadcreference
current is0.5 to2.0mA.
MC3410
MC3510 MC3410C
MOTOROLA
LASER TR IM M E D

Inform ation
TEN BIT, M ULTIPLYING

DIG ITAL-TO-ANALOG
CONVERTER
TEN BIT D TO A CONVERTER
The MC3410 series devices are low-cost, high-accuracy m o no lith ic

D /A converter subsystems. Like th e ir MC1408 series predecessors,
they provide the logic controlled current switches, the R-2R resistor
ladder netw ork and o u tp u t term ina tio n networks. The o utp ut buffer
am plifier and reference voltage have been om itte d from the circuit
to allow greatest system speed, fle x ib ility and lowest cost. This device
is useful in industrial co ntro l and microprocessor based systems.
Relative Accuracy 0.05% Error Maxim um
(MC3510 and MC3410)
Fast Settling Tim e 250 ns Typical
Noninverting D igital Inputs are M T T L and CMOS Compatible

(from 5 to 15 V CMOS)
O u tp u t Voltage Swing +0.2 V to 2.5 V
High Speed M u ltip ly in g In p u t Slew Rate - 20 mA/jus
Standard Supply Voltages
A ll Categories Guaranteed M onotonic Across Temperature
Reference A m p lifie r In te rn a lly Compensated
+5 V and 15 V
TY P IC A L APPLIC ATIO N S
Tra ckin g A -to -D Converters
Program m able Gain and A tte n u a tio n
Program m able Power Supplies
3 -D ig it Panel Meters and D V M 's
A n a lo g-D ig ital M u ltip lic a tio n
W aveform Synthesis
Sam ple and H o ld
Speech Compression and E xpansion
Peak D etector
Sam ple Data Systems
F IG U R E 2 - T E N -B IT D /A C O N V E R T E R
B LO C K D IA G R A M
FIG U R E 1 - D to A T R A N S F E R C H A R A C T E R IS T IC S
<
E
(OOOOOOOOOO)
(1 1 1 1 1 1 1 1 1
INPUT D IG IT A L W ORD
MSB
USB
A 1 A2 A 3 A 4 A5 A 6 A 7 A 8 A 9 A 1 0
MC3410, MC3510, MC3410C
MAXIMUM RATINGS
PowerSupplyVoltage
(TA=+2SCunlessotherwisenoted.)
Rating
Symbol
VCC
VEE
Value
+7.0
-18
+15
+0.5, -5.0
2.5
Unit
Vdc
Vdc
V|.
Vdc
AppliedOutput Voltage
Vo
mA
ReferenceCurrent
REFM6)
ReferenceAmplifier Inputs
Vdc
vref
v cc. vee
ReferenceAmplifier Differential Inputs
0.7
Vdc
VREF(D)
C
Ta
MC3510
-55 to+125
MC3410.C
0 to+70
JunctionTemperature
C
Tj
+175
CeramicPackage
+150
PlasticPackage
ELECTRICAL CHARACTERISTICS (Vcc - +5.0Vdc, Vee -15 Vdc,^ffg- 2.0 m
A,MC3510TA- -55Cto+125C.
MC3410Series: TA 0to+70Cunlessotherwisenoted. All digitel inputset highlogiclevel.)
Max
Unit
Typ
Characteristic
Min
Symbol
%
RelativeAccuracy(Error relativetofull scale lo) TA=25C
Er
MC3510, MC3410
0.05
_
MC3410C
0.1
RelativeAccuracyTemperatureDrift (RelativetoFull ScaleIq)
TCEr
2.5
. PPM/C
Monotonicity(Full TemperatureRange)
Monotonicto 10Bits
SettlingTimetowithin1/2LSB(TA=25C) (All BitsLowtoHigh)
n
s
250
*S
ns
35
*PLH
Ta +25C
20
*PHL
Output Futl ScaleCurrent Drift
MC3410, MC3410C
PPM/*C
60
TCI0
MC3510
70
Digital Input Logic Levels(All Bits)
Vdc
HighLevel, Logic1"
2.0
V|H
LowLevel, Logic"0"
0.8
V|L
Digital InputCurrent.(All Bits)
mA
HighLevel, Vjh5.5V
0.04
l|H
LowLevel, Vil 0.8V
0.4
0.05
lL
jiA
- 1.0
-5.0
'REF(IS)
OutputCurrent Range
mA
4.0
0
5.0
or
OutputCurrent
mA
o
Vraf 2.000V, Ri6 1000ft
3.9S6
3.8
4.2
OutputCurrent
MC3510, MC3410
M
A
0
2.0
(All bitslow) (Ta- 25C)
MC3410C
0
4.0
Output VoltageCompliance(TA25C)
Vdc
Vo
-2.5.+0.2
Er< 0.05%relativetoFSMC3510, MC3410 ' '
Er< 0.10%relativetoFSMC3410C
-2 S.+0.2
ReferenceAmplifierSlewRate
mA/jiS
SRlref
20
_
ReferenceAmplifierSettlingTime
2.0
US
STIref
(0to4.0mA,20.1 %)
OutputCurrent PowerSupplySensitivity MC3510, MC3410

PSRR(-)
0.003
0.01
%l%
MC3410C
0.003
0.02
OutputCapacitance(Vo 0)
pF
C0
25
Digital Input Capacitance(All Bits, InputsHigh)
4.0
pF
C|
_
PowerSupplyCurrent
mA
+10
+18
cc
(All Bits low)
-11.4
-2 0
!ee
+4.75
+5.0
Vdc
+5.25
VCCR
(Ta- +25C)
-14.25
-15
-15.75
Veer
PowerConsumption
mW
PC
All Bits low
220
380
A ll Bits high
200
-
8-50
MC3410, MC3510, MC3410C
t e s t c ir c u T t s
FIGURE3- NOTATIONDEFINITIONSTESTCIRCUITS
Vcc
V | and l| apply to Input* A1

thru A10
v ref (+}
v re {->
The ra iltto r tlod to pin 15 I* to tomperaturo compeniata the

bis* current end may not be neconery fo r all application*.
A1
'O K
A2
A3
A4
4 8 16
AS
32
A6
64
A7 A8 . A9 A10
i128
*n m
s R
i? 1024
256
612
a 2 v ref
TTfe
and Ajg
AN
" 1 " If A n I* at high loval

" 0 " if A im I* at low level
Typical Value*:
R 1 6 - R16 1 k
V r* f () - +2.0 V
v ref
Qnt>
In 4.0 mA
FIGURE5- SETTLINGTIME
VCc
U*a R l to Gnd fo r Turn-O ff Meaturomont
V ee
8-51
MC3410, MC3510, MC3410C
8
FIG U R E 9 - N EG A T IV E V ^ f
FIGURE 8 - POSITIVE V ^ f
V CC,
Vr#f <+>
Vref <->
OW V
A10 r a ~
R15 * R lfl
8-52
MC3410, MC3510, MC3410C
TheMC3410 coniiitf of a reference current amplifier, adfffusedR-2Rladder, alatertrimmingnetwork, endtenhighspeed

current twitches. The trimming method employed makes it
possible to improve the linearity attainable with moderndifffusiontechnologybyas muchasafactoroftensothat ahighly
finear pert results. The trimis performedbycuttingaluminum
links arranged to give incremental variations involtage at the
ladderterminationamplifiers (SeeFigure10). Thisyieldsehigh*
lystabletrimwithnoincreeseinfabricationcomplexity.
The switches are non-inverting inoperation, so that a high
state on an input turns on the specific component of output
current. The twitchet use current tteeringfor tpeed, endinter-
face the R-2R ladder through unity gainfeedbackterm

ination
amplifier!, which provide lowimpedancetermination! of equal

voltageforall legtof theladder.
The R-2Rladder dividesthe referenceamplifier current into
binarily-related components, which are fed to the current
twitchet. The three leatt-tignificant bit twitchet derive their
current through emitter scaling fromthe lest legof the ladder,
Theremainingcurrent, equal toone LSB, isshuntedto Vqq at
the LSB twitch. Therefore, the maximumoutput current it
1023/1024 of the reference amplifier current, or nominally
3.886mAfora2.000mAreferenceinputcurrent,
ReferenceVoltage
To gonerato the precision voltago rofcrcnco Input for the
MC3410, either the MC1403 or tho MC1404 may bo usod.
Tho MC1403 produces a 2.5 V 1 1 * output voltago whllo tho
MC1404 produce* a 10 V 1% output. Both have oxcollont
tomporaturo and long term stability. In ordor to roduco tho
offcct o f roforonco am plifier offsot voltage on overall accuracy,
tho hlghost possible stability roforonco voltago should bo usod.
Therefore, in systems w ith a +15 V supply, tho MC1404 (10 V)
is rocommendod. Whoro tho most positive supply ts only +5 V,
tho MC1403 provides a 2.5 V reference. To sot tho roforonco
current exactly, a low temperaturo coefficient potentiom eter
in serios w ith R l should bo used.
8-53
MC3410, MC3510, MC3410C
GENERAL INFORMATION
ReferenceAmplifier
The reference amplifier allowstheuser toprovideavoltage
anda resistor to Pin 16 to convert the reference voltage to a
current. Acurrent mirror doubles this reference current and
feeds it to the R-2R ladder. Thus for a reference voltageof
2.0 Voltsand1 kll resistortiedtoPin16/thefull-scalecurrent
is approximately 4.0 mA. The reference input current, 116,
must flow into Pin 16 regardless of the setup method or
referencevoltagepolarity.
Connections for a positive reference voltage ere shown in
Figure 8. The referencevoltagesource.suppliesthefull current
116. For bipolar refererencesignals, as inthemultiplyingmode,
R1S can be tied to a negative voltage corresponding to the
minimuminput level.
The reference amplifier is internallycompensatedwitha 10
pF feed-forwardcapacitor, whichgives it its highslewrateand
fast settling time. Proper phase margin Is maintainedwith all
possible values of R16andreferencevoltageswhichsupply2.0
mAreference current into Pin 16. The referencocurrent can
alsobe suppliedbya highimpedancecurrentsourceof 2JOmA.
As R16 increeses, the bandwidth of the amplifier decreases
slightly andsettlingtime increases. For acurrent sourcewitha
dynamic output impedance of 1.0 Mil, the bandwidthof the
reference amplifier is approximately half what it isinthecase
of R16 1.0 kli, andsettling time is 10 (is. The reference
amplifier phase margin decreases os the current source value
decreases inthe case of acurrent source reference, sothat the
minimumreference current supplied froma current source is
OSmAforstability.
Anegativereferencevoltage maybeusedif R16isgrounded
andthe reference voltage isappliedto R15 asshowninFigure
9. AhighInput impedanceisthemainadvantageof thismethod.
The negativereferencevoltagemust boat least 3Voltsabovethe
Vee supply fr properoperation. Bipolar input signalsmaybe
handledby connecting R16 to a positive voltage equal to the
peakpositiveinput level at Pin15.
When a dc reference voltage is used, capacitive bypass to
ground is recommended. The 6-V logic supply is not recom
mendedasa referencevoltage. If awell regulated5.0-Vsupply,
whichdrives logic, istobe usedasthereference, R16shouldbe
decoupledby connectingit tothe+5.0 Vlogicsupplythrough
another resistor andbypassingthejunctionof thetworesistors
witha0.1 mF capacitortoground.
OutputVoltageRange
The voltage on Pin3 is restricted to a range of
2.5 Vto
+0.2 Vdue to the current switchingmethodsemployedinthe
MC3410. Whenacurrent switchisturnedoff, thepositivevolt
ageat theoutput terminal canturnontheoutputdiodeandin
creasetheoutput current. Whenacurrent switchison, thenega
tiveoutput voltage rengeisrestrictedtothe point at whichthe
lowcurrent device of the termination amplifier Darlingtonbe
ginstosaturate, resultinginadecreaseinoutputcurrent.
The output voltage compliance isguaranteedat 25C. Note
fromFigure 14 that the output compliance of the MC3410is
nearlyconstantovertemperature.
Accuracy
Absolute accuracyisa measureof eachoutput current level
withrespect to its intendedvalue. It isdependent uponrelative
accuracy and full scale current drift. Relative accuracy, or
linearity, isthe measureof eachoutput current withrespect to
its intendedfractionof thefull scalecurrent. The relativeaccu
racy of the MC3410 isfairlyconstant over temperaturedueto
theexcellent temperature tracking,of thediffusedresistors. The
full scale current fromthe reference amplifier may drift with
temperature causingachangeintheabsoluteaccuracy. However,
the MC3410hasa lowfull scalecurrent driftwithtemperature.
The MC3510andMC3410are-guaranteedaccuratetowithin
1/2 LSB at 25C and at a full scale current of 3:996 mA.
Input reference current to Pin 16 isguaranteedto be between
13 and2.1 mAtoproduceafull scaleoutput currentof 3.996

mA.The relativeaccuracytest circuit isshowninFigure4. The
14bit D/Aconverteriscalibratedforafull scaleoutput of 3.996
mA. This is 8n optional step as the relative accuracy of the
MC3410isnearlyconstant between3mAend5mAfull scalecur
rent. The MC3410 Is calibrated at full scale with the 14-bit
reference D/Aby adjusting R16 until the error voltagegoesto
zero. The counter is activatedand the error band maybe dis
playedonanoscilloscope,detectedbycomparators, orstoredon
apeakdetector.
Monotonicity
The MC3510, MC3410 and MC3410Care all guaranteedto
be monotonic at temperature. This guarantees that for every
increase in the input digital word, the output current either
remains thesameor increases, but neverdecreases. TheMC3510
and MC3410 are monotonic over their respective temperature
ranges. In the multiplyingmode (whenthe reference current is
varied), monotonicity is typically maintained for all values of
input referencecurrent above0.5mA.
SettlingTime
The worst case switchingconditionoccurs whenall bitsare
switched"on," whichcorrespondstoalow-to-hightransitionfor
all.bits. Thistime istypically250 nsfor the output tosettleto
within i 1/2 LSB for 10-bit accuracy, and 200 ns for 8-bit
accuracy. The turn-off time is typically 120 ns. These times
applywhentheoutput swingis limitedtoasmall (< 0.7 Volt)
swingandtheexternal output capacitanceisunder25pF.
The major carry (MSBoff-to-on, all others on-to-off) settles
in approximately the same time as whenall bits are switched
off-to-on.
The slowest switches are bit A10 (LSB) andbit A9, which
turnon andsettle Intypically 200 ns, andturnoff in100 ns.
Inthe testcircuit of Figure5, theoutput voltageisInternally
clampedinthe MC3410 at about 0.7 Voltsaboveground. The
output is thus limitedtoa0.7 Volt swing. If a loadresistor of
625 Ohms is connectedtoground, allowingtheoutputtoswing
to
2.5Volts, thesettlingtimeincreasesto1.5ms.
Extracaremustbetakeninboardlayoutasthisisusuallythe
dominant factor in satisfactory test results when measuring
settling time. Short leads, 100fiF supply bypassing, andmini
mumscopeleadlengthareall necessary.
MC3S10TERMINOLOGY
RELATIVE ACCURACY Maximumoutput deviation from
the straight line connecting zero and full scale, expressed
asapercentageof full scale.
RELATIVE ACCURACY DRIFT - The average change in
linearity error that will occur with a change in ambient
temperature, expressed inparts per millionof full scaleper
degreeC.
MONOTONICITY - For every increase in the input digital
word,theoutputcurrent eitherremainsthesameorincreases.
SETTLINGTIMEThe elapsedtimefromtheinputtransition
"until the output has settledwithin anerror bandabout its
final value.
OUTPUT FULL SCALE CURRENT DRIFT - The average
changeinfull scalecurrent between25Candeithertempera
tureextreme, expressedinparts per millionof full scale per
degreeC.
REFERENCEAMPLIFIERSLEWRATEThe maximumrate
of change of the full scale output current expressed in
milliamperespermicrosecond.
OUTPUTVOLTAGE COMPLIANCE The maximumvoltage
that canbe appliedto the output pinsothat the specified
changeinoutput current isnot exceeded.
POWER SUPPLY SENSITIVITY - The change in full scele
current causedby a change inVee, expressedasa percent
of full scalecurrent perpercentchangeinVee-
8-54
MC3410, MC3510, MC3410C
FIGURE12- TRANSFERCHARACTERISTIC
versusTEMPERATURE
FIGURE13- OUTPUTCURRENTversus
OUTPUTVOLTAGE(OutputCompiience)
FIGURE14- MAXIMUMOUTPUT
VOLTAGEversusTEMPERATURE
'0. OUTPUT CURRENT (mA)
FIGURE11 - LOGICINPUTCURRENT
versusINPUTVOLTAGE
-75
>
HEW
TIVE OUTPUTM
B)
I
\
A
N
ACurve
ro 20n
Vfifl*) 2 vp.p
Centered it 1.0V
0.1
0.2
0.3
12
\
Curve
ro -lQ 0 Si
V ftfM - pu mvp.p
Centered at +200mv
0.5
1.0
\
Rt 5 - HI i - i 0 k
V
vref
2.0
1
3.0
-25
25
50
TEM
PERATUREI'C)
75
tOO 125
FIGURE16- TYPICALPOWERSUPPLY
CURRENTSversusTEMPERATURE
FIGURE15- REFERENCEAMPLIFIER
FREQUENCYRESPONSE
/
-50
5.0
H
10
f.FREQUENCY(M
Hi)
8-55
MC3410, MC3510, MC3410C
Voltageoutputsareobtainablewiththiscircuitwhichusesan
external operational amplifier as a current to voltage con
verter. This configuration automatically keeps the output of
the MC3410 at ground potential andthe operational amplifier
can generate a positive voltage limited only by its positive
supply voltage. Frequency response and settling time are
primarily determined by the characteristics of the operational
amplifier. In addition, the operational amplifier must be
compensated for unity gain, and insome cases overcompensa
tionmaybedesirable.
Notethat this configurationresults inapositiveoutput volt
age only, the magnitude of which is dependent on the digital
input.
The following circuit shows how the LM301A canbe
usedinafeedforwardmode resultinginafull scalesettlingtime
ontheorderof 2.0 .
FIGURE19- EXTENDINGPOSITIVE
VOLTAGERANGE
ms
FIGURE17
65 pF
-15 V
Theoutput voltagerangefor thistircuit is0 volts to BVcBO

of the transistor. Variations inbetamust beconsideredfor wide
temperature range applications. An invertedoutput waveform
may be obtained by usinga loadresistor froma positive refer
ence voltage to the collector of the transistor. Also, high-speed
operation ispossiblewitha largeoutput voltageswing, because
Pin3isheldat aconstant voltage. Theresistor (R) toVee main
tains the transistor emitter voltage when all bits are "off" and
insuresfastturn-onof theleast significant bit.
An alternative method is to use the MCI539 and input

compensation. Response of this circuit is also on theorder of
2.0 ms.
FIGURE20- OUTPUTCURRENTTO
VOLTAGECONVERSION
ô+isv
FIGURE18
2.5k
i V CC
MC
1404
V , o f 10 V
L k
Digital
Inputs
CMOS
or T T L
Compatible
The positive voltage range may be extended by cascading

the output with a high beta common base transistor, Q1, as
shown.
V r, - 2R0 y , | a 1 . A2 . A 3
H,
r f |^2
4
8
A*
16
A6
32
A6 A7
6 4 *1 2 8
AB
AO A l p l
256 512 1024J
fo r 10 vo lt fullscalo calibration
2(2.5 k ).
V q - 10 V o lt* (0.99901
Rq Full Scalo Adjust
8-56
MC3410, MC3510, MC3410C
APPLICATIONS INFORMATION (Continued)
BipolarorNegativeOutputVoltage
The circuit in Figure 21 isavariationof the standardoutput
voltage circuit in Figure 20. Anegative or offset binary out*
put may be obtained by sourcing current fromthe reference
into the output through Rg. If Rqallows 2 mA(Rg 5 kn
from 10 Volts) then 1000000000 input will generate zero
output voltage.
FIGURE21- OFFSETBINARYOR
BtPOLARDAC
SuccessiveApproximationAtoD
The fastest and most efficient means of Ato Dconversion
using D to A convertors is successive approximation (SA).
Similar inappearance to staircase devices, the SAconverter is
capable of 100 times faster conversions for a 10-bit result. A
complete 10-bit SAcoverter usingMC3410andMC14559B/49B
successive approximation registers is shown in Figure 22. The
complexity which results in higher conversion speeds is con
tainedintheMC14559B/49Bregisters. Quitesimply, theregister
compares the DACoutput resulting fromactivating each bit
with the input voltage. This is done startingwithmost signifi
cant bit snd after 10 comparisons generates the 10-bit binary
output representing that input. The accuracyof the conversion
is fixed by the accuracy of the MC3410andis not dependent
on tolerances of the other components. An EOC outout is
available end can be used to latch the parallel output or to
synchronize the serial output whichis alsoavailable. For more
detailsonSAconverters, seeAN-716.
For Offset Binary O utput From +5 V to S V
R0 a 2-5 kn
R b a 5 k ft
Vo
V re f[7 A l + M
TT|
.+ ~
+ * A 4
A6
A 6 +^ 7
* T r + 3T + ^ T
A8 + A9 + _A 10\
T 2 8 + 2SS
2 F lJ
512 + 1024^
FIGURE22 - SUCCESSIVEAPPROXIMATIONCONVERTER
USINGMC3410ANDMC1404
V re f
<
-1 0 V
Serial Data Out
O0 0 0 60 0000
Binary O utput
8-57
MC3410, MC3510, MC3410C
StaircaseAtoD
Oneadvantage of staircaseconvertors isthe easewithwhich
If highconversion speed is not required, astaircaseAto 0
BCDoutputs maybeobtained. Figure 24 showsa3-digit panel
convertor can be built for somewhat lower coit. Acomplete
meter usingthestaircasetechniqueandanMC14553B3-decadestaircase A/Oconvertor is shown in Figure 23. Herethecom
counter. The circuit function issimilar to Figure 23 but Multi
plicatedSAregisters are replacedwith simplebinarycounters.
plexed BCDoutput is available fromthe MC14553pcounters.
With an input voltage applied, the binary counter is reset by
Parallel BCD may be obtained with equal ease using the
the convert commandpulseandthebeginaccumulatingcounts.
MC14518B2-decadeCMOScounters.
The OACoutput steps upward until the comparator detects
In both thesestaircasedesignsthe systemaccuracyisdeter
that the input is equal to the OACoutput. The counters are
minedbythespecifiedaccuracyof theMC3410.
disabled and the conversion result is heldat thooutput until
thecircuit isresetbytheconvertcommandinput.
FIGURE23- 10-BITSTAIRCASEAtoDUSINGMC3410ANDMC1403
1N914
~ T
MC
1403
_1_3
-----------------------------------
14
12
13
4
2
3 MC14040B
S
J10
j 11
6
7
I12
13 9
la
s5
j6
7
j8
MC3410 9
8-58
MC3410, MC3510; MC3410C

FIGURE25- ALTERNATEAPPROACHSTAIRCASEATOD
BCDDtoAConvertor
BCDoutput AtoDconversionsaremosteasilyaccomplished
byaccumulatingthedigital resultsintwodifferent counters, but
that concept does not extendto BCDDtoAtechniques. Using
the circuit in Figure 26 a three-digit BCDnumber canbe con
vertedto a 10-bit accurate voltage. The MC14008Bs perform
the combinational BCD-to-Bfnaryconversion. The accuracyof
this circuit is also solely dependent on the accuracy of the
MC3410.
FIGURE26- 3-DECADEBCDDAC
8-59
MC3412
MOTOROLA
P roduct Preview
HIGH-SPEED
12-BIT D /A CONVERTER
COMPLETE 12-BIT
HIGH-SPEED MONOLITHIC D/A CONVERTER
The MC3412 is a m o n o lith ic single-chip 12-bit D /A converter.

It contains a high-stability voltage reference and both offset and
span resistors. A ctive laser trim m in g o f the th in -film ladder netw ork
and voltage reference provide accuracy and linearity o f better than
Vi LSB. 12-bit accuracy and fast settling tim e (typ ically better
than 200 ns to 'A LSB) make this converter an ideal display driver
o r fast A /D converter build in g block.
Fast Settling T im e: 'A LSB in 200 ns T yp
F u lly M o no ton ic Over Tem perature Range
Single-Chip C onstruction
H igh-S tability Voltage Reference on Chip
L in e a rity Guaranteed Over Tem perature
Low Power C onsum ption
Replaces A D 56 5
P S U F F IX
CASE 649
B L O C K D IA G R A M
V cc
LSB
NC ( ~
24
NC Q
23
B it 2
V CC C
22
| B it 3
Ref O ut
21
| B it 4
A na l Com
20
B it 5
19 ~ 1 B it 6
R ef In f
18
B it 7
17
B it 8
16
B it 9
10 V Span Q
10
15
B it 10
20 V Span
11
14 ^
B it 11
Dig Com I
(G nd)
12
13
B it 1 2(LS B )
'O u t C
T h is is advance in fo rm a tio n and s p e cifica tio n s are subject to change w ith o u t notice .
8-60
M C 3412
B ip o la r |
8
O ffse t '
Ve
Dig Com
(G nd)
B it 1 (M SB )
MOTOROLA
MC6890
P r o d u c t P r e v ie w
BUS-COMPATIBLE
8-BIT MPU D-TO-A CONVERTER
T h e M C 6 8 9 0 is a s e lf- c o n ta in e d , b u s - c o m p a tib le , 8 -b it
( 0 . 1 9 % a c c u r a c y ) D -to -A c o n v e r te r s y s te m c a p a b le o f in te r f a c
in g d ir e c t ly w ith 8 - b it m ic r o p r o c e s s o r s .
A v a ila b le in b o th c o m m e r c ia l a n d m ilit a r y te m p e ra tu r e
ra n g e s , t h is m o n o lit h ic c o n v e r t e r c o n t a in s m a s te r /s la v e
re g is te r s to p r e v e n t tra n s p a r e n c y to d a ta t r a n s it io n s d u r in g a c
tiv e e n a b le ; a la s e r- trim m e d , lo w -T C , 2.5 V p r e c is io n b a n d g a p
re fe re n c e ; a n d h ig h - s ta b ility , la s e r- trim m e d , t h in - f ilm r e s is to r s
fo r b o th r e fe re n c e in p u t a n d o u t p u t s p a n a n d o f fs e t c o n tr o l.
A r e s e t p in p r o v id e s f o r o v e r r id in g s to r e d d a ta a n d fo r c in g lo u t
to z e ro .
8 -B IT
B U S -C O M P A T IB L E
MPU DAC
1 / 2 LSB N on lin e a rity

A vailable in M ilita ry Tem perature Range
D irect Data Bus Link
Low Power: 130 m W Typ

Fast S ettlin g Time: 140 ns Typ
Single Enable: 10 ns Max Data Hold
Time
S elf-C ontained 2 .5 -V Precision Laser-Trim m ed Voltage
R eference (M ay A lso Be Used Externally)
Reset Pin to O verride Data

O utput Voltage Ranges: +5.0, +10, +20, or
2 .5 , 5 .0 , 1 0 Volts
L S U F F IX
CASE 732
(MSB) D7 ( T
v cc
D6 ( T
7] Ref Out
05 ( T
17] Ref In
D4 [ T
77] Analog Gnd
03 ( T
] ] 20 V Span
02 [T
17] 10 V Span
D1 [ 7
DO [ T
| Bipolar
-111 Offset
Reset [7_
77] Enable
Digital Gnd Q7
8-61
'out
77] v EE
MC6890
MAXIMUM RATINGS
Rating
PowerSupplyVoltsge
Symbol
v Cc
VEE
Vin
vout
ref (19)
Vi7
Digital Input Voltage, Pins 1-9,12

AppliedOutput Voltsge
Reference Current
ReferenceAmplifier Input
OperatingTemperature Range
MC6890
MC6890A
StorageTemperature Range
JunctionTemperature
ta
Tstg
Tj
Unit
Vdc
Vatuo
+7.0
-18
-3.0 to+7.0
VEEto+17
3.5
7.5
Vdc
Vdc
mA
Vdc
C
0 to+70
-55 to+125
-65 to+150
+150
C
C
ELECTRICAL CHARACTERISTICS (Vcc = 5.0 V, VEE = - 1 2 V ,V rof = 2.5V,TA = 25*C unless otherwise noted)
Characteristic
Digital Input Current

Data (V(H - 3.0 V)
(V|L = 0.4V)
Enable, Reset (V|h = 3.0 V)
(V|L = 0-4 V)
Full Scale Output Current Unipolar
Output Resistance Exclusive of Span Resistors
Unipolar Zero Output All Bits Off
Min
Typ
Max
V|H
V|L
2.0
0.8
>IH
'IL
iH
'IL
100
-10
100
-50
nA
MA
nA
mA
-1.50
-1.992
7.0
-
10
0.10
-2.50
mA
Full Scale Output (Unipolar Zero) Temperature Coefficient

(With Internal Reference)
Unipolar Zero
Bipolar Zero
Gain
Resolution
Monotonicity
(0C < T a < +70C)
|-55C < Ta < +125C)
Unit
Symbol
Vdc
Digital Input Logic Levels (Each Bit)

High Level, Logic 1
Low Level, Logic 0
8.0
2.0
35
35
1.0
8.0
8.0
8 Bits Over Temperature
A
ppm/C
Bits
MC6890
MC6890A
' Relative Accuracy

(Error Relative to Full-Scale Output Current)
Differential Nonlinearity
Output Voltage, Full Scale Unipolar with Internal Reference
(10 V Span)
(20 V Span)
(5.0 V Span)
Output Voltage, Half Scale Bipolar Offset Tied to Internal
Reference Direct Input Code = 10000000
(10 V Span)
(20 V Span)
(5.0 V Span)
Power Supply Range
__
__
9.951
19.902
4.976
9.961
19.922
4.981
v0
0.19
(1/2 LSB)
0.29
(3/4 LSB)
vee
%
Vdc
9.971
19.941
4.985
mV
Vo
vcc
-9.8
-19.5
4.9
4.5
16.5
0
0
0
5.0
-12
9.8
19.5
4.9
5.5
-4.5
15
11
12
5.0
10
50
, 100
130
255
2.500
6.25
3.0
Vdc
mA

(VCC = 5.0 V)
(VEE = -5.0V)
(VEE= -1 5 V)
*cc
>EE
EE
PSS
Power Supply Sensitivity

To Vcc (Vcc = 4.5 to 5.5 V. VEE = -5.0 V)
To Vee (Vcc= 5.0, VfeE = -5.0 to -15 V)
Power Dissipation All Bits Low
For VCC = 5.0 V @ VE = -5-0 V
For Ve e = -1 5 V Vcc = 5 0 V
Pd
ppm/FS*
mW
Reference Input Resistor
Rref
Reference Output Voltage

Load = 0 to 3.0 mA
Vref
4.0
ref
Reference Output Current

Reference Output Voltage Temperature Coefficient
TCvo
Full Scale
8-62
5.0
25
U)
Vdc
mA
ppm/C
MC6890
AC SPECIFICATIONS Mcc s B- v>VE6 = -12 V, Ta a 26C unless otherwise noted)

Characteristic
Settling Time
(Enable Positive Edge to 1 /2 LSB Output)
Data Setup Time
Symbol
Min
Typ
Max
Unit
*s
140
ns
tsu(D)
80
ns
Data Hold Time
HD)
-10
ns
Minimum Pulse Widths

Enable
Reset
tW()
tW(R)
60
100
*PLH(f)
tPHKR)
60
140
ns
ns
Propagation Delays
Enable, Low to High
Reset, High to Low
(Iq < 1.0 iA)
FIGURE 1 - TIMING DIAGRAM
FIGURE 2 - BLOCK DIAGRAM
VEE
V cc
-5 V
to - 1 5 V
5V
(11)
(20)
Analog
Ground
Digital
Ground
(18)
(10)
8-63
MC6890
FIGURE 3 - MC6890 IN TYPICAL BIPOLAR 2.6 V OPERATION
07 D8 05 D4 03 02
1 1 t 1 1 1
1 1 1 1 1 1
1 0 0 0 0 0
0 1 1 1 1 1
0 0 0 0 0 0
0 0 0 0 0 0
01
1
1
0
1
0
0
E0 (Volts)
DO H0s =25Q
ROS=
1
+2.490
+2.480
+2.470
+2.460
0
0
+0.010
+0.000
1
-0.010
-0.020
1
-2.470
-2.480
-2.490
-2.500
0
FIGURE 4 TYPICAL APPLICATION FOR OFFSET BINARY 5 .0 V OUTPUT OPERATION
8-64
MC10317L
MOTOROLA
P roduct Preview
HIGH SPEED
7-BIT ANALO G -TO -D IG ITAL
FLASH CONVERTER
SEVEN BIT PARALLEL

HIGH SPEED A /D CONVERTER
(WITH OVERRANGE)
SILICON MONOLITHIC
INTEGRATED CIRCUIT
The M C 10317L is a 7-bit high speed parallel A /D converter

w hich employs ECL processing. The device consists o f 128 parallel
latched comparators across a high q u a lity in p u t reference netw ork.
The 128 com parator outp uts are then fed to a 128-to-7 encoder and
latched to the outp uts w hich are ECL com patible. An overrange b it
is provided to allow overrange sensing, or to facilitate the connection
o f tw o 7-bit converters to produce an 8 -b it A /D converter.
A p p lica tion s include video display and radar signal processing,
high speed instrum e n ta tio n, and T V broadcast video encoding.
7-Bit R eso lu tion /8 -B it Accurate Plus Overrange
D irect In terconnection fo r 8 -B it Conversion
> 3 0 M Hz Sam pling Rate
Binary o r 2's C om p lim e n t O u tp u t
F u lly M o n o lith ic - ECL 10K C om patible
Standard 24-Pin Package
Wide Range of In p u t Voltage - 2.0 Volts
L S U F F IX
CASE 6 23
M C 10317 D E V IC E /A P P L IC A T IO N C O N F IG U R A T IO N
This is advance in fo rm a tio n and s p e cifica tio n s are subjoct to change w ith o u t n otice.
8-65
T y p ic a l 8 -B it A /D
<8>
MC1031SL
MC10318L9
MOTOROLA
Advance Specifications
and Applications Information
HIGHSPEED
8-BIT DIG IT AL-TO -ANALOG CONVERTER
HIGH SPEED
8-BIT DIGITAL-TO-ANALOG
CONVERTER
SILICON MONOLITHIC
INTEGRATED CIRCUIT
The MC10318 is a high speed 8-bit 0 /A converter capable of data

conversion rates in excess of 25 MHz. It is intended for applications
in high speed instrumentation and communication equipment,
display processing, storage oscilloscopes, radar processing, and TV
broadcast systems. The inputs are compatible with MECL 10,000
series logic, while the complementary current outputs have 51 mA
full scale capability. 8-bit accurate (1/2 LSB) and monotonic
over the full temperature range, the outputs typically settle in less
than 10 ns.
FA S T! Settling Time - 10 ns Typ
8-Bit Accuracy (0.19%) MC10318L

9-Bit Accuracy (0.1%) - MC10318L9
Inputs MECL 10,000 Compatible
Complementary Current Outputs
Output Compliance:-1 .3 V t o +2.5 V
Standard: -5 .2 V Supply
Standard 16 Pin Ceramic Package
Low Dissipation - Typically Less Than 500 mW
Low Cost
L SUFFIX
CERAMIC PACKAGE
CASE 620
LSUFFIX
CERAMIC PACKAGE
CASE 690
Motorola reserves the right to supply

thisdeviceineitheroftheabovepackages.
PIN CONNECTIONS
L S8 B8
(T
B 7 [2
B6
QF
BS [7
B4
[?
[3 'out
>*1 'out
is] NC
iH
v f+
B 3 [6
Til Comp
[7
To] v r. f -
B2
M S B B1 [j[
8-66
to] Ond
U V ee
MC10318L, MC10318L9
Ha +25Cunlessotherwisenoted.)
Rating
Value
Symbol
PowerSupplyVoltage
-6.0 to+0.5
Vee
Digital Input Voltage
o toV ee
V|
AppliedOutputVoltage
+5.0
v0
ReferenceCurrent
'refM2)
5.0
Output Current
'75
'PS
ReferenceAmplifier Input Range
+0.5 toVee
Vref
ReferenceAmplifier Differential Inputs
i 5.0
Vret<D)
0to+70
ta
-65 to+150
Tstg
JunctionTemperatureCeramicPackage
+175
Tj
MAXIMUM RATINGS
Unit
Vdc
Vdc
Vdc
mA
mA
Vdc ,
Vdc
C
C
C
CHARACTERISTICS
These specifications apply for Vgg ~ -5.2 V,

IpS 51 mA,T/\" 0Cto+70Cafterthermal
equilibriumisreached.
@Test
Temperature
0C
25C
70C
V|Hmax
-0.845
-0510
-0.727
TESTVOLTAGEVALUES(Note 1)
Volts
Vmmin V|HAmin V|LAmax
-1568
-1.151
-1.516
-1550
-1.105
-1.505
-1.052
-1.480
-1530
Characteristics
Symbol
Min
-5.46
Vee
PowerSupplyCurrent
ee
(Pins1thru8Open, Ipg=51 mA)
Monotonicity
8.0
Nonlinearity
MC10318L
MC10318L9
SettlingTimeto1/2 LSB
s
(All BitsSwitchedOnorOff, TA- 25C, Note3)
Full ScaleOutput TemperatureDrift
TCIps
Full ScaleCurrent Figure1
46.000
fs
(R3, R4" 3.300Ml, Vref = 10.560V, Note2)
ZeroScaleCurrent (Note2)
- <ZS
Full ScaleSymmetry(IFS15' 'FS14- Note2)
Ifss
HSA
Half ScaleAccuracy
MC10318L
(lHS25.5mA)
MC10318L9
Output VoltageCompliance(Note2)
-1.3
Voc
Full ScaleCurrent Change< 99mA
MC10318L,
50pA
MC10318L9
PowerSupplySensitivity(of Full ScaleCurrent)
PSSlFS
(Vee -4.94 Vto-5.46 V)

ReferenceBi8SCurrent, Pin10
<10
(Iraf 3.2mA)
PropagationDelay50%to50%
.
*P
(All BinSwitchedLowtoHigh, HightoLow)
NOTES: 1. Logicinput levelsarecompatiblewithMECL10,000 logicseries.
2. Output characteristicsapplytobothpins 14and15, lou( andlou(.
3. Seecommentsonconstructionandevaluationtechniques inFigure2andtext.
8-67
Vee
-5.2
-5.2
-5.2
Typ
-5.2
90
Max
-4.94
130
Unit
V
mA
8.0
-
Bits
%FS
10
0.19
0.10
-
50
51
150
56.000
ppm/C
mA
5.0
15
50
100
*50
25
2.5
iA
M
A
M
10.002
0.02
%/%
6.0
15
PA
3.0
ns
ns
MC10318L, MC10318L9
FIGURE 1 - FULL SCALE AND HALF SCALE CURRENT TEST CIRCUIT
For Ipg
V in - -1 .1 0 5 V
16
15
'out M
Ip s
r 'h s
- a
13
For l HS
V in - -1 .6 0 5 V
}-=
12
11
-)l
- * 10.660 V
v r, |
= 1 1
10
0.1 I l f i p
IF S 1 5 Tosted Sim ilarly
FIGURE2- TYPICALCONNECTIONSFOR50 12TRANSMISSIONLINE
Inputs are
MECL 10K
Compatible
15 V
(12.S to 40.0 V max)
MC1404U-10
10 V o lt Reference
-5 .2 V
-2 .0 V 6
^ 0 0 1
* H2 and R3 are
< SO ppm /C .
pF
^ lO M F
NOTE: Lino impedance* and term ination impedance m u tt be homogeneous 50.00 SI. A n y deviation w ill cause reflection*
which w ill seriouily offoct settling time. Optim um performance cannot be realized w ith socket*. G ood 1.0 GHz
m icro ttrip lin e techniques must be used.
8-68
MC10318L, MC10318L9
FIGURE 3 - TYPICAL CONNECTIONS FOR 75 n TRANSMISSION LINE AND TTL-COMPATIBLE INPUTS
/51 m A - 270 f t 5%
75
0.01 %
75 I I Tran*m i**ion Lina
TTL
Compatibla
In p u tt
O
MC1404U-10
10 V o lt Raforenco
* R2 and R3
are < 50
ppm /C
NOTE: Soo caution on lino and term ination impedance in Figure 2 and text.
APPLICATION INFORMATION
Functional Test Circuit Construction
Test circuits used to evaluate this device or circuit
designs used in actual practical situations must employ
good 1.0 GHz RF microstripline practices if optimum
performance is to be achieved from this device. Both line
and termination impedances must be matched to within
0.19% to minimize reflections which will appear as
increased settling time. The use of sockets for initial
evaluation is not recommended if specified settling time is
to be obtained.
Applications information can be obtained by con
tacting:
Application Engineering
(602) 244-3021
If desired, test circuit artwork and board specifications
will be supplied by contacting:
Linear Interface Marketing
(602) 962-2294
Successive Approximation A /D Converter

The circuit shown in Figure 4 uses the MC10318 in
a successive approximation analog-to-digital converter.
The circuit as shown will operate at a clock frequency
above 30 MHz if proper attention is given to layout.
The full-scale voltage (Vpg) for the circuit as shown
is 10.20 V. This full-scale voltage may be changed by
changing the 200
resistor to a value given by:
r
= V p s-
IFS
VFS
51 mA
However, at low values of V f s the resolution of the

comparator must be considered to maintain a 1 /2 LSB
accuracy.
00
MC10318L, MC10318L9
FIGURE 4 - SUCCESSIVE APPROXIMATION A/D CONVERTER USING MC10318
8-70
MC10318L, MC10318L9
FIGURE S - MC10318 EQUIVALENT CIRCUIT
8-71
V o ltag e R eferences
VOLTAGE REFERENCES
Temperature Range
Commercial
Military
MC1400, A
MC1403, A
MC1404, A
MC1500, A
MC1503, A
MC1504, A
Page
Precision Voltage References .................................................. 9-3
Precision Low-Voltage References........................................... 9-4
Precision Low-Drift Voltage References................................... 9-8
MC1400 MC1400A
MC1500 MC1500A
MOTOROLA
Product Preview
PRECISION
VO LTAGE REFERENCES
TIGHT-TOLERANCE, LOW-DRIFT
VO LTAGE REFERENCE FAM ILY
2 .5 , 5 .0 , 6 .2 5 , and IO -V O L T
O UTPUT VO LTAG ES
The M C1400 series o f ICs is a fa m ily o f temperature-compensated

voltage references fo r precision data conversion and instrum entation
applications. Advances in th in -film resistors, laser-trimming tech
niques, ion-im planted devices, and m o n o lith ic fa brication techniques
make this reference both tem perature and tim e stable in applications
demanding accuracy to the 16-bit level.
These devices o ffe r simple, no-external-com ponent operation as
three-term inal, positive-voltage references, and also simple, oneexternal-resistor operation as either positive or negative references.
U nique c irc u itry permits these devices to either source or sink
greater than 10 m A o f load current w ith excellent regulation. This
feature means that the b u ffe r am plifiers and current sources n or
m ally required fo r precision zener references can be elim inated.
Four D iffe re n t O u tp u t Voltages: 2.5, 5.0, 6.25, 10 V

Tight Absolute Accuracy: 0.2% M axim um In itia l Tolerance
Single-Component O u tp u t T rim m ing W ith o ut Degrading Temper
ature C oe fficie n t
Wide Inp u t Voltage Range: V r e p +1.0 V t o +40 V
U S U F F IX
CASE 6 93
..........
nc
Three-Terminal O peration:
Positive References That Can Source and Sink C urrent
Tw o-Term inal O peration:

Positive or Negative References
L A S E R -T R IM M E D S ILIC O N
M O N O L IT H IC IN T E G R A T E D C IR C U IT
~8~[ NC
|~i~
V in jT
~7~| NC
V TEM P ^
Gnd
Floating References
L o w Current C onsum ption: 0.75 m A T ypical
V e ry Low Tem perature C oe fficie n t: 5 ppm / C Typical
Low O u tp u t Noise Voltage
Excellent R ipple R ejection: 100 dB T ypical at 120 Hz
Excellent Long Term S ta b ility : 25 ppm / 1000 Hrs Typical
j [ ] v out
[7
~5~| T R IM
O R D E R IN G IN F O R M A T IO N
P A C K A G E ( A L L TY PE S )
C eram ic DIP
Device
V CC
p
S IM P L IF IE D D E V IC E D IA G R A M
M C 15 00 U 2
M C 1500A U 2
U)
T e m p eratu re Range
2 .5 V o lts
U)
M C 14 00 U 2
M C 1400AU2
- 5 5 C to + 1 25C
- 5 5 C to + 1 2 5 C
0 C to +7 0 C
0 C to +7 0 C
5 .0 V o lts
M C 15 00 U 5
- 5 5 C to + 1 2 5 C
M C 1500AU 5
M C 1400U 5
M C 1400AU5
- 5 5 C to + 125 C
0 C to + 7 0 C
0 C to + 7 0 C
6 .2 5 V o lts
R
^ O llt
V TE M P O 2 .5 V
5 k ll
5.0
15 k
6 .25
20 k
35 k
10.0
V ee
T h is is advance in fo rm a tio n and s p e cifica tio n s aro subje ct to change w ith o u t notice .
9-3
M C 15 00 U 6
M C 1500AU 6
M C 14 00 U 6
M C 1400A U 6
-5 5 C
-5 5 C
0 C
0 C
to + 1 25 C
to + 1 2 5 C
to + 7 0 C
to + 7 0 C
10 V o lts
M C 1500U 10
M C 1500A U 10
- 5 5 C to + 125 C
- 5 5 C to + 1 2 5 C
M C 1400U 10
M C 1400AU10
0 C to + 7 0 C
0 C to + 7 0 C
MC1403,A
MC1503,A
MOTOROLA
LOW VOLTAGE REFERENCE

A precision band-gap voltage reference designed for critical
instrumentation and D/A converter applications. This unit is
designed to work with Motorola MC1506, MC1508, and MC3510
D/A converters, and MC14433 A/D systems. Low temperature drift
is a prime design consideration.
Output Voltage = 2.5 V 25 mV

Input Voltage Range = 4.5 V to 40 V
Quiescent Current = 1.2 mA typ
Output Current - 10 mA
Temperature Coefficient = 10 ppm/C typ
Guaranteed Temperature Drift Specification
Equivalent to AD580
Standard 8-Pin DIP Package
PRECISION LOW-VOLTAGE
REFERENCE
LASER TRIMMED
SILICON MONOLITHIC
INTEGRATED CIRCUIT
USUFFIX
CERAMIC PACKAGE
CASE 693
Typical Applications
Voltage Reference for 8 -1 2 Bit D/A Converters

Low T c Zener Replacement
High Stability Current Reference
Voltmeter System Reference
(Ta* 25Cunlessotherwisenoted.)
Symbol
Value
Input Voltage
40
V|
StorageTemperature
-65 to150
T Stq
JunctionTemperature
+175
Tj
OperatingAmbient TemepratureRange
Ta
MC1S03.A
-55 to+125
MC1403.A
Oto+70
MAXIMUM. RATINGS
Rating
Unit
V
C
C
C
C
FIGURE1- AREFERENCEFORMOTOROLAMONOLITHICD/ACONVERTERS
FullScale
MC1403,
Series
Adjustr
1.0 k
2.5 V
V W R1
0.1 m f
Cl
-*X v
soon I
-O-------- \
14
Pins Numbers fo r
MC1508/1408/3408
Sorias; device
could also be
M C I506/1406 or MC3510/3410
recommended to provide means for full-scale adjust on the

D/Aconverter.
The resistor R3 improves temperature performance by
matching the impedanceonboth inputs of the D/Areference
amplifier. The capacitor decouples any noise present on the
reference line. It isessential iftheD/Aconverter islocatedany
appreciabledistancefromthereference.
Asingle MC1403/1503 referencecanprovidethe required
current input for upto fiveof themonolithicD/Aconverters.
PROVIDINGTHEREFERENCECURRENT
FORMOTOROLAMONOLITHICD/ACONVERTERS
The MC1403/1S03 makes an ideal reference for the
Motorola monolithic D/A converters. The MCI406/1506,
MCI408/1508. MC3410/3510 andMC3408D/Aconvertersall
require a stable current reference of nominally2.0 mA. This
can be easily obtained from the MCI403/1503 with the
addition of a series resistor, R1. Avariable resistor. R2, is
9-4
MCI403, A, MCI503, A
ELECTRICAL CHARACTERISTICS (V| 15 V ,T A 26C union otherwise noted.)

Charactarittie
Output Voltage
(lO 0 mA)
Temperature Coefficient of Output Voltage
MCI 603
MC1603A
MC1403
MC1403A
Output Voltage Change
(over specified temperature range)
MC1503 _ggoc t0 +125C
MCI503A )
MC1403A I1 c t0 +70c
Une Regulation
< 1 5 V < V |< 4 0 V ),
(4.5 V < V| < 15 V)
Load Regulation
(0mA<lo<10mA)|
Quiescent Current
(iQ-Om A)
Symbol
Min
Typ
Max
Unit
V0
2.475
2.50
2.525
55
25
40
25
ppm/c
AV0 MT
-
10
10
mV
AV0
25
11
7.0
4A
mV
Rain
_
-
Resioad
>l
FIGURE2- MC1403/1603SCHEMATIC
9-5
1.2
0.6
4.5
3.0
10
mV
1.2
1.5
mA
MC1403, A, MC1503, A
FIGURE4 - CHANGEINOUTPUTVOLTAGE
versusLOADCURRENT
(NORMALIZEDTOVout vin" 15V, lout - 0 mA)
.W oul< CHAflGE IN Vou, (mV)
FIGURE3- TYPICALCHANGEINVoutvarau*Vj
(NORMALIZEDTOVj= 15VTc 2SC)
V,n. INPUT VOLTAGE (VOLTS)
loul. OUTPUT CURRENT (mA)
FIGURE6 - CHANGEINVout versusTEMPERATURE

(NORMALIZEDTOVoutVj- 15V)
I,. QUIESCENT CURRENT (mA)
FIGURES- QUIESCENTCURRENTversusTEMPERATURE
(V;B15V, lout 0 mA)
Ta . TEMPERATURE (OC)
FIGURE7- CHANGEINVout versusTEMPERATURE

(NORMALIZEDTOTA l0. Vin- 15V. I0ut - 0 mA)
-75
- 50
- 25
25
50
75
TA< TEMPERATURE (C)
9-6
100
125
150
175
MCI403, Af MCI503, A
This is done by dividing the EOC pulse rate by 2 with

1/2 MC14013B flip-flop and blanking the display using
the blanking input of the MC14543B.
The display uses an LED display with common anode
digit lines driven with an MC14543B decoder and an
MC1413 LED driver. The MC1413 contains 7 Darlington
transistor drivers and resistors to drive the segments of
the display. The digit drive is provided by four MPS-A12
Darlington transistors operating in an emitter-follower
configuration. The MC14543B, MC14013B and LED
displays are referenced to V e e via Pn 13 f the MC14433.
This places the full power supply voltage across the
display. The current for the display may be adjusted by
the value of the segment resistors shown as 150 ohms
in Figure 8.
3-1/2-DIGIT VOLTMETER - COMMON ANODE

DISPLAYS, FLASHING OVERRANGE
An example of a 3-1 /2-digit voltmeter using the
MCI 4433 is shown in the circuit diagram of Figure 8.
The reference voltage for the system uses an MC1403
2.5 V reference IC. The full scale potentiometer can
calibrate for a full scale of 199.9 mV or 1.999 V. When
switching from 2 V to 200 mV operation, R| is also
changed, as shown on the diagram.
When using Rq equal to 300 kl, the clock frequency
for the system is about 66 kHz. The resulting conversion
time is approximately 250 ms.
When the input is overrange, the display flashes on
and off. The flashing rate is one-half the conversion rate.
FIGURE 8 - 3-1/2-DIGIT VOLTMETER
+5V
-5V
o .^ l
5V
|0.1j<F
300 k [
0.1i f T 0
11 10
Vxo-
12 24
23
5V
i
0.1/jF
4 1
2
o
n
3
tn
5
o
22
21
20
16
10
11
12
13
14
7,S
Segment R atlttors
150 ft (7)
7
10
11
12
:
3
2
1
-5V
15
16
J
Minus Sign
0 .1 m F
-5 V *
15 19 IS 17 16
------wv------
g o d c b a
MPS-A12 Plu* Sign
WV
51 k
MC14013B +5V
Common
Anodo
LED
Display
80|iPji~^!0.tpF
BBB
uuuu
MPSA12
(4)
* R| * 470 k f t fo r 2 V Range
R| * 27 k f t fo r 200 m V Rang#
'M y la r Capacitor
9-7
(g>
MC1404 MC1404A
MC1504 MC1504A
MOTOROLA
PRECISION LOW-DRI FT
VOLTAGE REFERENCES
VOLTAGE REFERENCE FAMILY

The M C1404 series o f ICs is a fa m ily o f temperature-compensated
voltage references fo r precision data conversion applications, such as
A /D , D /A , V /F , and F /V . Advances in laser-trimming and ionim planted devices, as well as m o n o lith ic fabrication techniques,
make these devices stable and accurate to 12 bits over both m ilita ry
and commercial tem perature ranges. In a ddition to excellent tem
perature sta b ility, these parts o ffe r excellent long-term sta b ility and
low noise.
5 .0 , 6 .2 5 , and 1 0 -V O L T O U T P U T V O L T A G E S
LASER T R IM M E D S ILIC O N
M O N O L IT H IC IN T E G R A T E D C IR C U IT
O u tp u t Voltages: Standard, 5.0 V, 6.25 V, 10 V
Trim m able O u tp u t: > 6%
Wide In p u t Voltage Range: V r e p + 2.5 V to 40 V
Low Quiescent C urrent: 1.25 m A Typical
Temperature C oefficie n t: 10 p p m /C Typical
Low O u tp u t Noise: 1 2 m V p -p T yp ica l
Excellent R ipple R ejection: > 80 dB Typical
U S U F F IX
CASE 693
T Y P IC A L A P P LIC ATIO N S
Voltage Reference fo r 8 - 1 2 B it D /A Converters
L o w T c Zener Replacement
High S ta b ility Current Reference
MPU D /A and A /D A pplications
NC
~8~[ NC
v in [ T
T |
NC
] >
V TE M P ^
oul
F IG U R E 1 - V O L T A G E O U T P U T 10 B IT DA C U S ING M C 14 04 U 1 0
G nd ^
~5~| T R IM
+5
O R D E R IN G IN F O R M A T IO N
P A C K A G E ( A L L TY PE S )
Ceram ic DIP
Device
T e m p eratu re Range
5 .0 V o lts
M C 15 04 U 5
M C I 504AU5
- 5 5 C to + 1 2 5 C
- 5 5 C to + 1 25 C
M C 14 04 U 5
M C 1404A U 5
0 C to + 7 0 C
0 C to + 7 0 C
6 .2 5 V o lts
M C 15 04 U 6
- 5 5 C to + 12 5 C
M C 1504AU 6
- 5 5 C to + 1 2 5 C
0 C to + 7 0 C
0 C to + 7 0 C
M C 14 04 U 6
M C 1404AU 6
10 V o lts
M C 15 04 U 1 0
- 5 5 C to + 1 2 5 C
M C 1504A U 10
M C 1404U 10
- 5 5 C to + 1 2 5 C
0 C to + 7 0 C
0 C to + 7 0 C
M C 1404A U 10
9-8
MC1404, MC14Q4A, MC1504, MC1504A
Output Voltage
(l0 0mA)
Characteristic
(Vjn 15Volts, TA " 25CandTrimTerminal not connectedunlessotherwisenoted)

MCI504,A
MC1404.A .....
Unit
Min Typ Max Min Typ Max
Symbol
Volt
Vo
US, AU5
4.95 5.00. 5.05 4.95 5.00 5.05
6.19 6.25 6.31 6.19 6.25 6.31
U6, AU6
U10, AU10
9.90 10 10.10 9.90 10 10.10
%
0.1 1.0 0.1 1.0
%
- 6.0 AVtrim 16 .O -
Output VoltageTolerance
OutputTrimRange(Figure10)
(Rp- 100ktl)
Output VoltageTemperatureCoefficient,
Over Full TemperatureRange
MCI404, MC1504
MC1404A,MC1504A
MaximumOutput VoltageChange
OverTemperatureRange
MC1404U5, MC1504US
MC1404AU5, MC1504AU5
MC1404U6, MC1504U6
MC1404AU6, MC1604AU6
MC1404U10, MC1504U1O
MC1404AU10, MC1504AU10
LineRegulation(1)
(Vjn" Vout +2.5Vto40 V, lout 0mA)
LoadRegulation(1)
(0< l0< 10mA)
Quiescent Current
(l0-0 mA)
Short Circuit Current
LongTermStability
Note1: Includesthermal effects.
ppm/C
av0/at
40
25
55
25
2.0
14
9.0
17.5
28
18
6.0
2.0
50
23
62
28
99
45
6.0
mV
10
10
mV
<1
1.2
1.5
1.2
1.5
mA
Uc
-
15
-
20
25
30
-
25
30
-
mA
ppm/1000 hrs
10
10
R69LINE
RegLOAD
AV0
11
(V;n- 15V, TA* 25Call voltagerangesunlessotherwisenoted)

MC1404.A
MC1504.A
Min Typ Max Min Typ Max
Characteristic
Symbol
Turn-OnSettlingTime
50
50
*S
(to0.01%)
Output NoiseVoltagePtoP
12
12
*n
(Bandwidth0.1 to10Hz)
Small-Signal Output Impedance
fo
120 Hz
0.15 0.15 500 Hz
0.2
0.2
PowerSupplyRejectionRatio
PSRR
70 80
70 80
-
mV
DYNAMIC CHARACTERISTICS
9-9
Unit
us
uV
a
dB
MC1404, MC1404A, MC1504, MC1504A
FIGURE2 - SIMPLIFIEDDEVICEDIAGRAM
-75
FIGURE4- OUTPUTVOLTAGEversusTEMPERATURE
MC1404U10
-50
- 25
0
+25
* 50
+75
TA. AMBIENT TEMPERATURE (C)
+J0Q
+125
FIGURES- LOADREGULATIONversusTEMPERATURE
Ta . AMBIENT TEMPERATURE <C)
TA. AMBIENT TEMPERATURE <C)
FIGURE6- POWERSUPPLYREJECTIONRATIO
versusFREQUENCY
PSRR. POWER SUPPLY REJECTION RATIO (dB)
FIGURE7- QUIESCENTCURRENTversusTEMPERATURE
>50 -25
0 +25 +50 +75 +100 +125
TA. AMBIENT TEMPERATURE lC)
I. FREQUENCY (kHz)
9-10
MCI404, MC1404A, MC15Q4, MC1504A
FIGURE8- SHORTCIRCUITCURRENTvanusTEMPERATURE
FIGURE9- VtEMPOUTPUTversusTEMPERATURE
T A. AMBIENT TEMPERATURE |CI
TA. AMBIENT TEMPERATURE ICI
FIGURE10- OUTPUTTRIMCONFIGURATION
FIGURE11- PRECISIONSUPPLYUSINGMC1404
O V+
O O utput
5.0, 6.26,
10 V 9 1/2 Am p.
Output Adjustment
Output PowerBoosting
Tho MC1404 trim tormlnal can ba used to adjust the output

voltago over a 6% rango. For oxamplo, the output can bo to t to
10.000 V or to 10.240 V fo r binary applications. For trimm ing.
Bourns type 3059, 100 kSl or 200 kO trim p o t it rocommondod.
The addition o f a power transistor, a rasistor, and a capacitor
convorts tho MC1404 into a procision supply w ith ono ampere
current capability. A t V+ - 15 V, the M C1404can carry in oxcess
o f 14 m A o f load current w ith good regulation. If the power
transistor curront gain exceeds 75, a one ampere supply can
be roalizod.
FIGURE12- ULTRASTABLEREFERENCEFORMC1723VOLTAGEREGULATOR
Supply
/R 0 + 4 .7 k \
\
Iomox 9o V
9-11
*-7k
MC1404, MC1404A, MC1504, MC1504A
FIGURE 13 - 5.0 V. 6.0 AMP, 25 kHz SWITCHING REGULATOR WITH SEPARATE ULTRA-STABLE REFERENCE
+ 10 to + 30 In
FIGURE 14 - HIGH SPEED 8-BIT D/A CONVERTER USING MC1404U10

Ip s >* 101 to 51.000 mA w ith R1
50.0 1I
I
~ T ra n tm iisio n Line
S5
J j
|0 .0 1 % ^ -* ^ /
50
V oot - 1.28 V FS Settling Timo.
0.01%
-W V |
Typically 10n
Inputs ars
MECL 10K
Compatible
15 V
(1 2 .5 to 4 0 .0 V m axi
MC1404U10
10 V o lt Roferonco
* R 2 and R 3 are
< 50 ppm /C.
-2.0 VO
1^0.01 lfe10<iF
I * f h
9-12
Linear IC S e le c to r G u ides
I f f M i
(ill
OPERATIONAL AMPLIFIERS
Motorola offers a broad line of operational amplifiers to meet a wide range of usages. From
low-cost industry-standard types to high precision circuits, the span encompasses a large range of
performance capabilities. These linear integrated circuits are available as single, dual, and quad
monolithic devices in a variety of package styles as well as standard chips.
Single Operational Amplifiers

NONCOMPENSATED
: '|B VIO TCvio *IO Afoi BW(Av1) SR(Aw1|* SupplyVoltage

V
fl*A iriV jiV/C tiA v/v MHt v/pt :
Device..
.jnwtj. :tWL: to* .mln *VP
*VP.. j mln max
MilitaryTemperatureRange(-55Cto+125<,C)
LM101A 0.07S 2.0 10 10 50K 1.0
0.5
3.0 22
LM108 0.002 2.0 3.0 0.2 50K 1.0
0.3
13.0 20
LM108A 0.002 0.5 1.0 0.2 80K 1.0
0.3
13.0 i20
MC1520 2.0 10 15 100 1K
5.0
10
14.0 8.0
MC1530 10 5.0 15 2.0mA4.5K 3.0
1.0
4.0 19.0
1.0
MCI531 IS 10 15 25 2.5K 2.0
14.0 19.0
MCI533 1.0 5.0 15 150 40K 0.8
2.0
14.0 120
MCI539 0.5 3.0 15 60 50K 2.0
4.2
14.0 118
MCI709 0.5 5.0 15 200 25K 1.0
0.3
i3.0 H8
MC1709A 0.6 3.0 5.0 100 25K 1.0
0.5
13.0 118
MC1712 5.0 2.0 15 500 2.5K 7.0
1.5
+6.0 +14
-3.0 -7.0
0.5
MCI748
5.0 15 200 50K 1.0
0.5
3.0 122
Industrial TemperatureRange(0Cto+70C)
LM301A 0.25 7.5 10 50 25K 1.0
0.5
13.0 18
LM308
7.0 7.5 15 1.0 25K 1.0
0.3
3.0 18
LM308A 7.0 0.5 5.0 1.0 80K 1.0
0.3
3.0 18
MC1420 4.0 15 15 200 750
10
5.0
4.0 8.0
1.0
MC1430 15 10 15 4.0fiA 3K 3.0
4.0 8.0
MC1431 0.3 15 15 100 1.5K 2.0
1.0
4.0 8.0
2.0
30K
MC1433
7.5 15 50
2.0
0.8
4.0 H8
4.2
6.0 118
MC1439 1.0 7.5 15 100 15K 2.0
0.3
3.0 H8
MC1709C 1.5 7.5 15 500 15K 1.0
.
MC1712C 7.5
MC1748C 0.5
5.0
6.0
15 2.0jiA 2K
15 200 20K
7.0
1.0
1.5
0.5
10-2
+6.0 +14
-3.0 -7.0
3.0 18
Description
Packed*
General Purpose
Precision
Precision
Differential Output
General Purpose
General Purpose
(DarlingtonInput)
General Purpose
HighSlewRate
General Purpose
HighPerformance
MC1709
WidebandDC
Amplifier
General Purpose
601.693
601.606.693
601.606,693
603,606
603B, 606,632
603B.606, 632
6038,606,632
601,632
601,606,
632,693
601,606,632
601,606, 632
601,693
General Purpose
Precision
Precision
Differential Output
General Purpose
General Purpose
(DarlingtonInput)
General Purpose
HighSlewRate
General Purpose
601,626,693
601,606,
626,693
601,606,
626,693
603,606
603B, 606.
632,646
603B, 606,
632,646
603B, 606,
632,646
601,626,
632,646
601,606,
626,632,
646,693
601,606,632
601.626,693
WidebandDC
Amplifier
General Purpose
Single Operational Amplifiers

IN T E R N A L L Y C O M P E N S A T E D
Description
Packagn
S'
Device
^Srol' BW(A*-1) SRtAw-1) St^pply.Votoge

*|B V(o TCV<0 : ' ro
V
: nA
MHz
V/ ms
y /v
HA
min max.
typ
njx max Jftrp ' max: friin
1YP
mperatureRange t-BSC to+125C)
LF155 lOOpA 5.0 5.0 20pA 50K

LF155A 50pA 2.0 3.0 lOpA 50K
LF156 100pA 5.0 5.0 20pA 50K
LF156A SOpA 2.0 3.0 lOpA 50K
LF157 lOOpA 5.0 5.0 20pA 50K
LF157A SOpA 2.0 3.0 lOpA 50K
10 50K
LM107 0.075 2.0 10
MC1536 0.02 5.0 10 3.0 100K
MCI556 0.015 4.0 10 2.0 100K
3.0mA SO
MC1733 0.20 - MC1741 0.5 5.0 15 200 50K
MC1741N 0.5 5.0 15 200 50K
MC1741S 0.5 5.0 15 200 SOK
MC1776 0.0075 5.0 15 3.0 20CK
MC35001 lOOpA 10 10 lOOpA 25K
MC35001A 75pA 2.0 10 25pA SOK
MC35001B 100pA 5.0 10 50pA 50K
Industrial TemperatureRange(0aCto+70C)
LF355 200pA 10 5.0 50pA SOK
LF355A SOpA 2.0 1.0 10pA 50K
LF356 200pA 10 5.0 50pA 50K
LF356A 50pA 2.0 1.0 lOpA 50K
LF357 200pA 10 5.0 50pA SOK
LF357A SOpA 2.0 1.0 10pA 50K
50 25K
LM307 0.25 7.5 10
10 70K
MC1436 0.04 10 12
10 70K
MCI456 0.03 10 12
5.0mA 80
MC1733C 30
6.0 15 200 20K
MCI741C 0
6.0 15 200 20K
MC1741NC 0.5
6.0 15 200 20K
MC1741SC 0.5
MC1776C 0.003 6.0 15 3.0 100K
25 50K
MC3476 0.05 6.0 15
MC34001 200pA 10 10 lOOpA 25K
MC34001AlOOpA 2.0 10 50pA SOK
MC34001B 200pA 5.0 10 lOOpA 50K
1.0
1.0
2.0
2.0
3.0
3.0
1.0
1.0
1.0
90
1.0
1.0
1.0
1.0
4.0
4.0
4.0
5.0
5.0
15
15
75
75
0.5
2.0
2.5
0.5
0.5
10
0.2
13
13
13
5.0
t5.0
5.0
5.0
5.0
5.0
3.0
15
3.0
4.0
3.0
3.0
3.0
1.5
5.0
5.0
5.0
601
FETInput
22
601
FETInput
22
601
FETInput
22
601
FETInput
22
601
22 WidebandFETInput
601
22 WidebandFETInput
601,693
22
General Purpose
601
40
HighVoltage
601,632
HighPerformance
22
603,632
8.0 Differential Wideband
VideoAmp
601,606,
22
General Purpose
632,693
601,606,
22
LowNoise
632, 693
601,632,693
H
ig
h
S
lew
R
ate
22
601,632
18 MPowerProgrammable
TRIMFETInput
601,693
22
601,693
22
TRIMFETInput
TRIMFETInput
601,693
22
1.0
1.0
2.0
2.0
3.0
3.0
1.0
1.0
1.0
90
1.0
1.0
1.0
1.0
1.0
4.0
4.0
4.0
5.0
5.0
15
IS
75
75
0.5
2.0
2.5
0.5
0.5
10
0.2
0.2
13
13
13
5.0
5.0
5.0
5.0
5.0
5.0
3.0
15
3.0
4.0
3.0
3.0
3.0
1.5
1.5
5.0
5.0
5.0
18
FETInput
18
FETInput
FETInput
18
FETInput
18
18 WidebandFETInput
18 WidebandFETInput
General Purpose
18
34
HighVoltage
18
HighPerformance
8.0 Differential Wideband
VideoAmp
General Purpose
18
LowNoise
18
HighSlewRate
18
18 MPower, Programmable
owCost
18 MPower,LP
rogrammable
18
TRIMFETInput
TRIMFETInput
18
TRIMFETInput
18
10-3
601
601
601
601
601
601
601,626,693
601
601,632
601,632,646
601,632,626,
646,693
601,632,626.
646,693
601,632,626,
646,693
601
601.626
601,626.693
601.626.693
601.626.693
Dual Operational Amplifiers

IN TER N ALLY COMPENSATED
Device
*18
AlA
m ax
v .o
TC V IO
mV
m ax
nV IC
ty p
'lO
nA
m ax
A vol B W (A v=1)
MHz
V /V
mm
ty p
S R (A v=1) S up p ly V o lta g e I
V
Mln s
ty p
m in
max |
D e scrip tio n
Packages
M ilita r y T e m p e ra tu re Range l- 5 5 'C to + 1 2 5 )

0 .15
5 .0
10
30
50K
1.0
0 .6
= 1.5
+3.0
= 18
+36
S p lit S upplies
Single S up p ly
(L o w Power
C o n su m p tio n )
6 01 . 6 32 . 693
M C 1558
M C 15 58 N
M C 1558S
M C 1 747
M C 35 58
05
0.5
0.5
0.5
0.5
5 .0
5 .0
5 0
5.0
5.0
10
10
10
10
10
200
200
200
200
50
50K
50K
50K
50K
50K
1.1
1.1
1.0
1.0
1.0
0.8
0.8
10
0.5
0.6
0.5
1 00pA
7 5p A
100pA
150pA
5.0
10
2.0
5 .0
2.0
10
10
10
10
5 .0
200
100pA
2 5p A
50pA
70pA
50K
25K
50K
50K
25K
4 .0
4 .0
4 .0
4 .0
4 .0
1.5
13
13
13
13
=22
= 22
= 22
=22
= 18
+36
= 22
= 22
=22
= 22
= 22
M C 35 02 2 A
60pA
0 .5
5 .0
2 5p A
50K
4 .0
13
= 5.0
=22
M C 35 02 2 8
7 5p A
1.0
5 .0
50pA
50K
4 .0
13
= 5.0
=22
Dual MC1741
L o w Noise
High Slew Rate
D ual MC1741
S p lit Supplies
Single S up p ly
High F requency
T R IM F E T In p u t
Precision
Precision
Precision
6 0 1 . 6 32 . 6 93
6 0 1 , 6 3 2 . 693
6 0 1 . 6 32 , 693
6 01 , 632
6 0 1 .6 3 2 ,6 9 3
M C 45 58
M C 35 00 2
M C 35002A
M C 35002B
M C 35022
=3.0
3.0
=3.0
= 3.0
1.5
+3.0
= 3.0
=5 .0
= 5.0
* 5 .0
=5.0
S p lit Supplies
Single S upply
(L o w P ow er C o n su m p tio n )
Dual MC 1741
6 0 1 .6 2 6 ,6 9 3
LM 158
6 0 1 . 6 32 . 693
601, 6 93
6 0 1 .6 9 3
6 01 , 693
6 0 1 .6 9 3
6 0 1 .6 9 3
6 0 1 . 693
In d u s tria l T e m p eratu re Range 10 C to +70 C)

LM 358
0.25
6 0
7.0
50
25K
1.0
0 .6
1.5
+3.0
= 18
+36
= 18
M C I 458
0.5
6.0
10
200
20K
1.1
0.8
=3.0
M C 14 58 N
0 .5
6 .0
10
2 00
20K
1.1
0.8
=3.0
18
L o w Noise
M C 1458S
0 .5
6 .0
10
2 00
20K
1.0
10
=3.0
*1 8
High Slew Rate
M C 1747C
M C 34 58
0.5
0.5
6 0
10
10
7.0
2 00
50
25K
20K
1.0
1.0
0.5
0.6
=3.0
i 1.5
* 3 .0
= 18
= 18
+36
M C 4558C
M C 34 00 2
M C 34 00 2 A
M C 34002B
M C 34 02 2
0.5
1 00 pA
7 5p A
100pA
15 0 p A
6 .0
10
2.0
5 .0
2 .0
10
10
10
10
5 .0
2 00
100pA
5 0p A
7 0p A
7 0p A
2 0K
2 5K
5 0K
25K
25 K
3 .0
4 .0
4 .0
4 .0
4 .0
1.5
13
13
13
13
= 3.0
= 5.0
= 5.0
= 5.0
*5 .0
18
= 18
= 18
18
= 18
M C 34 02 2 A
7 5p A
0 .5
5 .0
30pA
50K
4 .0
13
=5 .0
18
M C 340228
15 0 p A
1.0
5 .0
7 0p A
5 0K
4 .0
13
=5.0
= 18
Dual MC 1741
S p lit Supplies
Single S up p ly
(L o w Crossover
D is to rtio n )
High F requency
Precision
Precision
Precision
1.0
0.6
=1.5
+3.0
1 8
+36
S p lit S upplies
Single S up p ly
6 0 1 . 6 26 , 6 3 2 .
6 46 , 693
6 0 1 .6 2 6 .6 3 2 .
6 4 6 . 6 93
6 0 1 ,6 2 6 , 6 32
6 4 6 . 693
6 0 3 , 6 32 , 6 46
6 0 1 , 6 26 , 6 93
6 0 1 ,6 2 6 ,
6 0 1 , 6 26 ,
6 0 1 .6 2 6 .
6 0 1 , 6 26 ,
6 0 1 , 6 26 ,
693
693
693
6 93
6 93
6 0 1 . 6 26 . 693
6 0 1 . 6 26 . 693
A u to m o tiv e T e m p eratu re Range l- 4 0 JC to + 8 5 "C )

M C 33 58
5.0
8 .0
10
75
2 0K
I
j
6 26
NONCOMPENSATED
M ilita r y T e m p eratu re Range (-5 5 C to +125 C)
M C 1535
3 .0
3 .0
10
300
4K
1.0
0.01
=2.0
= 10
General Purpose
MC 1537
0.5
5 .0
10
200
25K
1.0
0.25
=3.0
18
Dual M C 17 09
6 0 3 B. 606,
6 32
6 32
In d u s tria l T e m p eratu re Range (0 C to + 7 0 C)

M C 14 35
5 .0
5 .0
10
5 00
3.5 K
1.0
0.01
= 2.0
=9.0
G eneral Purpose
M C 14 37
1.5
7.5
10
500
15K
1.0
0.25
=3 .0
= 18
Dual M C 17 09
10-4
6 03 B , 607,
632
6 3 2 . 6 46
Quad Operational Amplifiers

IN TER N ALLY COMPENSATED
1IB
jiA
max
Device
v IO TCV IO
m V # iV / c
max
ty p
to
nA
max
A vol B W (A =1)
V /V
MHz
m in
ty p
S R (A v *1 ) S u p p ly V olta g e
V
V / ms
m in
max
ty p
D e scrip tio n
Packages
M ilita r y T e m p eratu re Range I-5 5 C to + 1 2 5 C I

LM 124
0 .15
5 .0
7.0
0 .5
5 .0
7.0
5 .0
10
2.0
5 .0
15
10
10
10
M C 35 03
MC 4741
M C 35 00 4
M C 35004A
M C 35 00 4 8
0.5
1 00 pA
7 5p A
100 pA
30
50K
50
50K
1.0
0.6
50K
25 K
50 K
50 K
1.0
4 .0
4 .0
4 .0
0.5
13
13
13
25K
1.0
0.6
1K
5 .0
0.6
2 00
100pA
25pA
50pA
1.0
0 .6
11.5
+3.0
11.5
+ 3.0
3.0
5.0
5.0
5.0
16
+32
18
+ 36
22
22
22
22
L o w Pow er
C o n su m p tio n
General Purpose
L o w Power
Q uad M C I 741
T rim m e d F E T In p u t
6 32 , 6 46
: 1.5
+3.0
-1.5
+3.0
1.5
+3.0
3 .0
=5.0
:5 .0
: 5 .0
16
+32
18
+36
18
+36
18
18
18
18
L o w P ow er
C o n su m p tio n
N o rto n In p u t
6 3 2 , 6 46
N o Crossover
D is to rtio n
Quad M C I 741
6 3 2 , 6 46
1.5
+3.0
2 .0
+4.0
1.5
+3.0
13
+26
15
+28
18
+36
6 3 2 , 6 46
6 3 2 , 6 46
6 32
632
632
Ind u stria l T e m p eratu re Range (0 C to 7 0 t>C)

LM 324
0 .25
6 .0
7.0
M C 3401
0 .3
0.5
M C 34 03
M C 4741C
M C 34 00 4
M C 34004A
M C 3400B
0 .5
200pA
1 00 pA
200pA
10
7.0
6 .0
10
2 .0
5 .0
15
10
10
10
50
50
2 00
lOOp A
50pA
1 00 pA
20K
1.0
0.6
20K
25K
50K
50K
1.0
4 .0
4 .0
4 .0
0.5
13
13
13
6 3 2 , 6 46
632,
632,
632.
632,
646
6 46
6 46
6 46
A u to m o tiv e T e m p e ra tu re Range (-4 0 C to +85 C)

LM 2902
0 .5
10
50
1.0
0.6
M C 3301
0.3
IK
4 .0
0.6
M C 33 03
0.5
8 .0
10
75
20K
1.0
0 .6
D iffe re n tia l
L o w P ow er
N o rto n In p u t
6 46
D iffe re n tia l
General Purpose
6 46
6 46
Package Styles
601
603
6036
6 06
6 26
M A T E R IA L
CASE
M etal
M etal
M etal
Ceram ic
Plastic
S U F F IX a fte r ty p e n um be r
G, H
G, H
G. H
P. P I, N
CASE
M A T E R IA L
S U F F IX a fte r ty p e num be r
632
6 46
693
Ceram ic
Plastic
Ceram ic
J, L
P. P2
J. U
10-5
VOLTAGE REGULATORS
Fixed Output Voltage Regulators
Low-cost monolithic circuits for positive and/or negative regulation at currents from
100 mA to 1.5A
Ideal for on-card regulation of subsystems
Internal current limiting thermal shutdown and safe-area compensation
FIXED-VOLTAGE, 3-TERMINAL REGULATORS FOR POSITIVE OR NEGATIVE POLARITY POWER SUPPLIES.

A V q /A T
1v rt
2
3
5
T o l.t
V o lt*
1 n iA
Mm .
0.1
1500
0.15
10.3
0.5
0.25
0.4
D w ic e T V P * ;
P p titfta O a tp u t
-
MC79L05C
MC79L05AC
MC7905.2C
MC7906C
_
_
-
5.2
0.26
1500
0.3
0.35
0.3
0.24
500
1500
MC78M06C
M C 7806*
MC7806C
M C 7806A *
M C7806AC
L M 140-6
L M 3 4 0 6
0.3
0.8
100
0.4
500
1500
0.3
0.4
1.2
0.6
100
500
1500
0.5
0.6
6.7/30
MC78L05C
MC78L05AC
MC78M05C
LM109
LM209
LM309
M C 7805*
MC7805C
M C 780 5A *
M C7805AC
L M 1 4 0 5 *
LM340-S
0.25
12
5.5/35
100
10.25
0.35
0.25
0.2
MC7902C
MC79L03AC
MC79L03C
100
500
1500
MC78L08C
MC78L08AC
MC78M08C
M C 7808*
MC7808C
* M C7808A
M C7808AC
LM 140-8
L M 3 4 0 8
MC78L12C
MC78L12AC
MC78M12C
M C 7812*
MC7812C
M C 7812A *
M C7812AC
LM 140-12*
L M 3 4 0 12
V t
DvtcaTypo
Ourtftut .
m #/C
mV.
tvp
40
120
1.0
1, 221A
60
80
4.7/30
200
150
100
7/35
niy .
'' C a n
72
29. 79
60
29. 79
100
1.0
1.1
'
79. 221A
1. 79
_
MC7905C
_
8.0/35
7/35
7.5/35
50
1.0
100
10
0.6
1.0
0.6
7/35
50
50
100
50
1
1. 221A
1
1. 221A
1
MC7908C
-
7.2/35
105
105
1.0
1, 221A
8/35
9/35
8/35
8.6/35
100
60
120
11
120
100
120
50
100
60
1.0
0.7
79. 221A
1
1. 221A
1
1. 221A
1
8/35
60
80
29. 79
1.0
80
160
100
160
50
100
80
79. 221A
1
1. 221A
1
1. 221A
1
13.7/35
250
100
29. 79
14/35
15.5/35
14.5/35
14.8/3S
100
120
240
18
1.0
1.5
14.5/35
120
240
120
240
50
100
120
79. 221A
1
1. 221A
1
1. 221A
1
200
175
100
80
160
13
9.7/30
10/35
11.5/35
10/35
10.6/35
10.5/35
MC79L12C
MC79L12AC
_
MC7912C
-
_
-
1.5
1979 New Product Introductio n.

T j - -55 to +150 C
tO u tp u t Voltage Tolerance fo r Worst Cate
(continued)
10-6
Fixed Output Voltage Regulators (continued)

Vout
Vote
IS
Tolft
Vote
11.5
0.75
1o
mA
: M t*
100
500
1800
0.6
0.75
18
1.8
0.9
100
500
1500
0.7
0.9
20
24
1.0
2.4
1.2
500
100
500
1500
1.0
1.2
DtvEca Typ*.
Po*ltlv*Outjut
MC78L16C
MC78L15AC
MC78M15C
MC7816*
MC7815C
MC7815A*
MC7815AC
* LM140-15*
*LM340-15
MC78L18C
MC78M8AC
MC78M18C
*MC7818*
MC7818C
MC7818A*
MC7818AC
LM140-18*
* CM340-18
MC78M20C
MC78L24C
MC78L24AC
MC78M24C
MC7824*
MC7824C
MC7824A*
MC7824AC
LM 140-24*
*LM340-24
D*vte* Typ*
;Ns*tfVf Output
MC79L16C
MC79L15A
, - v tn .
M(n/Max
16.7/36
_
_
MC7915C
_
R*loacl
rtIV
150
mV
300
300
160
300
50
17/35
18.6/35
17.5/35
17.9/35
150
300
17.5/35
160
150
19.7/35
325
170
100
360
180
360
50
100
22
AVo/AT
rpV/#C
Typ
-
1.0
1.8
100
Cm *
29, 79
79. 221A
1
1. 221A
1
1. 221A
1
MC79L18C
MC79L18AC
_
20/35
22/35
21/35
MC7918C
180
360
31
1.0
79. 221A
2.3
1
1. 221A
1
1. 221A
1
79. 221A
29, 79
100
_
-
29, 79
180
180
10
400
1.1
350
300
200
100
240
480
36
480
240
480
50
240
240
MC79L24C
MC79L24AC
_
22/40
25.7/40
26/40
28/40
27/40
27.3/40
27/40
MC7924C
_
_
1.2
79. 221A
3.0
1
1. 221A
1
1. 221A
1
100
*1979 Now Product Introductio n!

T j - -56 to + 150C
tO u tp u t Voltago Tolerance for Worst Caso
Variable Output Voltage Regulators

POSITIVE OUTPUT REGULATORS
; n
mA
Max
s
u
K
' Davtea
Typ*
l!X
V ln Vout
Differ... Vout :
V|n
ntiii
Volt*
Vote
Vote
Min
Max Min iMix'i Min
8.5
50
3.0
37
5.0
40
3.0
37
9.5
40
3.0
20
LM305
LM205
LM105
4.5
40
100
L M 3 1 7 L
L M 2 1 7 L
L M 1 1 7 L *
H,Z
1.2
150
M CI 723
CP
CG
G
CL
L
2.0
PD
- Max - . . T A * J 6 r C
T)t? :
TC*
TC LbM
2B*C asc Lina
0.4
0.68
30
250
MC1469
M CI 569
2.5
32
37
9
8.5
600
MC1469
M CI 569
2.5
32
37
1500
LM317
LM317
LM217
LM117*
T
H, K
1.2
37
9.0
8.5
35
40
35
40
3.0
2.7
3.0
2.7
5.0
40
3.0
Regulation
? Vout.
1.3
1.6
2.7
Interr ally
Limited
0.65
0.8
_
2.1
1.0
0.68
1.8
3.0
14.0
Internally
Lim ited
10-7
Cata
0.06
0.1
0.007
85
100
150
601
0.04
0.02
0.5
0.3
0.006
0.004
0.003
125
150
29,79
0.1
0.1
0.2
0.1
0.2
0.3
0.003
0.003
0.002
0.003
0.002
150
646
603C
175
632
0.03
0.015
0.03
0.015
0.13
0.002
150
603
0.05
0.002
150
614
1.5
0.006
125
221A
79. 1
1.0
0.004
0.003
150
0.07
0.05
T j - -55 to +150C
* * 1979 New Product Introductions
T C -V ^ V
c
Typ
-Max
WC
Variable Output Voltage Regulators (continued)

N E G A TIV E O U TPU T R EG U LATO R S
V in
V out
Differ-
s
o
mA
Max
u
F
F
1
Device
Type
Vout
V o lti
v in
V olt*
PD
Watts
Max
TC
25C
TC "
25 C
Min
Max
M in
Max
Min
LM 3 04
LM 2 04
LM 104
0 .035
0 .015
30
40
8 .0
40
50
2.0
0.4
0.68
2 50
MC 1463
M C I563
3.8
3.6
32
33
9 .0
8.5
35
40
3 .0
2.7
600
M C 1463
M C I 563
3.8
3.6
34
37
9 .0
8.5
35
40
3.0
2.7
20
Regulation
V o u t
TA ' 25 C
Typ
T C V oul
T |"
Typ
Line
Load
VC
Max
Case
1.3
1.6
2.7
0 1
0.05
0.007
80
100
150
603
0 68
1.8
0.03
0.015
0.05
0.13
0.002
150
603
2.4
9 .0
0.03
0.015
0.05
0.002
175
614
Switching Regulators
Used as the co ntro l c irc u it in PWM, push-pull, bridge and series type sw itchm ode supplies. The
devices include the reference, oscillator, pulse-width m odulator, phase sp litter and o u tp u t sections.
Frequency and d u ty cycle are independently adjustable.
v cc
'o
<o
kHz
Volts
im A
Max
M in
Max
M in
Max
Device
Number
40
10
30
2.0
100
M C 3420
p
L
M C 3520
Suffix
Case
0 to 70
648
6 20
6 20
-5 5 to +125
Special Regulators
F L O A T IN G V O L T A G E A N D C U R R EN T REGULATORS
Designed fo r laboratory typ e power supplies. Voltage is lim ited o n ly by the breakdown voltage
o f associated, external, series-pass transistors.
S
u
V out
Volts
'o
v aux
Volts
F
I
Min
Max
Max
Type
M in
Max
M C 1466
M C 1566
L
L
21
20
30
35
PD
Watts
Max
0.75
^ r e f 'V r e f
A IL/ I L
%
Load
%
Max
0.015
0.004
0.2
0.1
Line
0.015
0.004
i
|
TC V out
%rc
Typ
Case
0.01
0 006
632
D e pe n de n t on characteristics o f exte rn a l series-pass elements.
D U A L 15 V T R A C K IN G R EG U LATO R S.
Internally, the device is set fo r 15 V , b u t an external adjustm ent can change both outputs
sim ultaneously, fro m 8.0 V to 20 V.
TC
% /C
V out
Volts
Min
Max
'o
mA
Max
14.8
1 5 .2
1100
u
F
F
V in
Volts
Min
Max
17
30
Device
PD
Watts
Type
X
G
L
R
G
L
R
MC 1 4 6 8
MC 1 5 6 8
*T low to
Reload
mV
Thigh'
Ty p
ta
Max
Reline
mV
0.8
10
10
3 .0
0 to * 75
1.0
2.4
0.8
1.0
2.4
10-8
-5 5 to 125
Case
603C
632
614
603C
632
614
Special Regulators (continued)

LOW TEM P E R A TU R E D R IF T , LOW V O L T A G E REFERENCE
v
4V
ou M T
out
V o lti
Typ
mA
Max
p p m /C
Max
Device
Type
2.5 2 5 m V
10
40
25
55
25
MC 1403
M C 14 03 A
MC 1503
M C 1503A
40
25
55
25
M C 1404 U5
MC 14 0 4 A U 5
M C 1504U 5
M C 15 04 A U 5
40
25
55
25
40
25
55
25
M C 1404U 6
M C 1404AU 6
M C 1504U 6
M C 15 04 A U 6
M C 14 04 U 1 0
MC 1 4 0 4 A U 10
M C 15 04 U 1 0
M C 1504AU 10
5 .0 i 50 m V
6.25 * 6 0 m V
10 1 100 m V
Notes:
Suffix
u
R#Sirw
mV
Max
ReS|oad
mV
Max
3 /4 .5
(N ote 1)
10
(N o te 3)
t a
Can
0 to * 7 0
6 93
-5 5 to +125
0 to * 70
6.0
(N ote 2)
-5 5 to *1 2 5
0 to + 70
-5 5 to * 125
0 to * 70
-5 5 to *1 2 5
1. 4 .5 < V , < 15 V /1 5 V < V , < 4 0 V

2- V i n - V o u t + 2 . 5 V t o 4 0 V
3. O m A < l 0 < 10 m A
Package
Styles
CASE
M A T E R IA L
S U F F IX
1
(T 0 -3 )
29
(TO -92)
79
(TO -39)
221A
(TO -220)
601
603
(TO -5 T yp e)
603C
6 14
(TO -6 6 )
M etal
Plastic
Metal
Plastic
Metal
M etal
M etal
M etal
G, H
G. H
G. H
646
648
693
701
726
S K .K ,K C
P.
,f> AA
14
CUD C
CASE
M A T E R IA L
S U F F IX
620
626
632
(TO -116)
Ceram ic
Plastic
Ceramic
Plastic
Plastic
Ceram ic
Ceram ic
Plastic
J. L
P or PI
P o r P2
N, P
CIRCUITS FOR
CONSUMER APPLICATIONS
. . . reflecting Motorola's continuing commitment
to semiconductor products necessary for consumer system designs. This tabulation is arranged
to sim plify first-order selection of consumer
integrated circuit devices that satisfy the primary

functions for Television, Audio, Radio, Citizens
Band, Automotive and Organ applications,
Television C ircuits
SO UND
Function
Features
Case
Type
80 /iV, 3 dB L im itin g S ensitivity, 3.5 V (RMS) O u tp u t,

S u ffic ie n t fo r S ing le T ra n sis to r O u tp u t Stage
In te rch a ng e a ble w ith ULN2111A
646
MC1351
646
M C1357
S ound IF D etector,
dc V olum e C o n tro l,
P re a m p lifie r
E xce lle n t AM R , Interch a ng e a ble w ith C A3065
646
M C1358
S ound IF, L ow Pass Filter,

D etector, dc V olum e
C o n tro l, P re am p lifie r,
Power A m p lifie r
C om p lete TV Sound System ; 100 ^V, 3 dB L im itin g

S e n sitivity; 4 W atts O u tp u t; V q q = 24 V; R L = 16 f l
722A
T D A 1190Z
750 mW O u tp u t
648
TD A1190P
1st and 2nd V ide o IF

A m p lifie r
IF G ain @ 45 M Hz = 60 dB typ, AG C Range = 70 dB m in
626
626
M C1350
1st and 2nd V ide o IF, A G C

K eyer and A m p lifie r
3rd IF. V ideo D etector,
V ide o B uffe r, and
AFC B u ffe r
IF G ain @ 45 M Hz = 53 dB typ, A G C Range = 75 dB m in,

"F o rw a rd A G C " P rovided fo r T uner
646
M C1352
L ow -Level D etection, Low H a rm o n ic G e n e ratio n .

Z e ro S ignal dc O u tp u t Voltage o f 7.0 to 8.2 V
626
M C1330A1
Sam e as MC1330A1 except zero sign a l dc o u tp u t

vo ltag e o f 7.8 to 9.0 V
626
M C1330A2
H ig h G ain AFT System, In te rch a ng e a ble w ith CA3064

A FT C irc u it that Provides an AFT V oltage and an
A m p lifie d 4.5 MHz In te rca rrie r Sound S ignal
646
646
M C1364
C hro m a IF A m p lifie r and

S u b ca rrie r System
In clud e s C om p lete C hro m a IF, A G C , dc G ain and T in t

C o n tro ls In je ctio n Locked O scilla to r, Low P eripheral
Parts C o u n t
646
M C1398
C hro m a IF A m p lifie r and

S u b ca rrie r System (PLL)
In clu d e s C om p lete C hro m a IF, A G C , dc C hro m a and

H ue C on tro ls, P hase-Locked Loop (PLL) O s c illa to r,
C o lo r K ille r T h re sho ld A d ju stm e n t
648
M C1399
Dual C hro m a D e m o d u la to rs
D ual D o u b ly-B ala nce d D e m o d u la to r w ith RGB M a trix

and C hrom a D river Stages
646
M C1324
Dual D o u b ly-B ala nce d D e m o d u la to r w ith RG B M a trix

and PAL S w itch
646
M C1327
T rip le D o u b ly-B ala nce d D e m o d u la to r w ith

A d ju sta b le O u tp u t M atrix, C o n ta in s Thre e
In d e pe n d en t D em odulators
648
M C1323
In clu d e s Lin e a r Balanced Phase D etector, O s c illa to r

and Predriver, A d ju stab le d c Loop G ain
Same as MC1391 except designed to a ccep t negative
sa w too th syn c pulse
626
MC1391
626
M C1394
In clud e s O s c illa to r and C o m p lem e n ta ry D river, L ow

Therm al D rift, R etrace Pulse fo r E ffective B la n k in g
648
M C 1393A
In clud e s C hro m a O s c illa to r and C lo c k D river, Lead

and Lag N etw ork, C hrom a M o du la to r, RF O s c illa to r,
and M odulator.
In clud e s RF O s c illa to r and M o d u la to r
646
MC1372
626
M C1373
S o u nd IF, D etector, Lim ite r,

A u d io P re a m p lifie r
S ound IF D e te cto r
VIDEO
A u to m a tic Fine T u n in g
A u to m a tic Fine T u n in g w ith
In te rc a rrie r M ix e r/A m p lifie r
IF G ain @ 45 M Hz =50 dB ty p ,A G C Range = 60 dB m in
M C1349
CA3139
CH RO M A
T rip le C hro m a D e m o d u la to r
DEFLECTIO N
H o rizo n ta l Processor
V e rtical P rocessor
TV G AM ES/D ISP LAY

C o lo r TV V ide o M o d u la to r
10-10
C IR C U IT S FOR C O N S U M E R A P P L IC A T IO N S
A udio C ircuits
POWER AMPLIFIERS
Feature*
A u d io P o w e r A m p lifie rs
Po
Watt*
Vcc
Vdc Max
0.5
0.25
15
12
8.0
28
V|n
@ rated Pq
mV Typ
3.0
3.0
50
d
mA Typ
Rl
Ohma
C ate
Type
4.0
3.0
8.0
16
626
626
M C1306
55
2.0
3 1 4 A ,3 1 4 B
TD A2002
M C3360
Radio C ircuits
IF AMPLIFIERS
Function
IF A m p lifie r
Recovered
Gain
3 dB Limiting
Power
Audio Output
@ 10.7 MHz @ 10.7 MHz
Supply
1 = 75 kHz
AMR
dB Typ
Volts Max
mV (RMS) typ dB Typ
mV (RMS)
Case
Type
690
18
626
M C1350
45
480
18
646
M C1355
45
480
16
646
M C1357
500
18
626
M C3310
350
(f = 3 .0 kHz)
8.0
648
MC3357
58
0.175
60
L im itin g FM -IF A m p lifie r
0.600
L im itin g IF A m p l/Q u a d
D etecto r
53
0.4
IF A m p lifie r
42
60
50
0.005
50
L o w -P o w e r FM -IF fo r D ual
C on ve rsio n S ca n nin g
R eceivers
DECODERS
Function
FM M u ltip le x S tereo D e co d e r
Channel
Separation
dB Typ
THD
% Typ
47
0.06
StereoIndicator
Lamp Driver
mA Max
Features
Case
Type
M C 1309
50
C oille ss O p e ra tion ;
4.5 V O p e ra tion
646
C oille ss O p e ra tio n
646
M C1310
V ariable S e p ara tio n
648
TC A 4500A
40
0.3
75
45
0.2
100
AM RECEIVER
Features
AM R adio S ubsystem
Function
RF A m p lifie r, AG C , M ixer, O scilla to r, 1st IF A m p lifie r,
2nd IF A m p lifie r and D etecto r
10-11
Case
Type
648
H A1199
C IR C U IT S FOR C O N SU M ER A P P LIC A TIO N S
Organ C ircuits
FREQUENCY DIVIDER
VCC
Range
Function
7-Stage D ivid er
Vdc
f Tog
MHz Typ
v OH
Vdc Min
C ate
Type
6 -16
1.0
12.0/15.0
646
M C1302
ATTENUATOR
Function
E le c tro n ic A tte n u a to r
VC C
Range
Vdc
9 .0-18
Attenuation
TH D
% Typ
Ay
dB Typ
Range
dB Typ
Case
0.6
13
90
626
Type
M C3340
A utom otive C ircuits

O PERATIO NAL AM PLIFIER
Vcc
Range
Function
Vdc
Q uad O p e ra tion a l A m p lifie r
4 .0-28
3.0-26
D ual O p e ra tion a l A m p lifie r
3.0-26
Unity Gain
A vO I
V/V Min
*IB
fiA Max
Bandwidth
M H z Typ
1000
0.3
4.0
0.25
0.25
Case
Type
1.0
646
646
MC3301
LM 2902
1.0
626
LM2904
COM PARATO RS
vcc
Range
Function
Q uad C om p a ra to rs
Vdc
2.0-28
2.0-36
Sink
VIO
'lO
mV Max
nA Max
(IB
nA Max
Current
mA Typ
Case
Type
20
7.0
5.0
2.0
500
6.0
646, 632
50
250
16.0
646
646, 632
M C3302
LM2901
646, 632
LM 239
LM 239A
VO LTAGE REG ULATO R

Function
Features
Case
Type
A u to m o tiv e V oltage
R e g u lator
D esigned fo r use w ith NPN D a rlin g to n ; O ve rvo lta ge

P ro te ctio n ; "O p e n Sense" S hut D ow n; S electable
T e m p era ture C o e fficie n t fo r Use in a F lo atin g Field
A lte rn a to r C ha rg in g System
646
M C3325
F lip -C h ip A u to m o tive
V olta ge R e g u lator
Sam e as MC3325
M C CF3326
646
MC3333
M CCF3333
646, 632
M C3344
ELECTR O N IC IG N ITIO N
E le c tro n ic Ig n itio n C irc u it
D esigned fo r use in H igh Energy Variable D w ell

E le ctro n ic Ig n itio n System s w ith Variable
R eluctance Sensors. D well and S park E nergy are
E xte rn a lly A d ju stab le
F lip -C h ip E le ctro n ic
Ig n itio n C irc u it
Same as MC3333
SPECIAL FUNC TIO N

P ro gra m m a b le F requency
S w itch
(E n gin e RPM S w itch )
W ide In p u t Frequency Range (10 Hz to 100 kHz)

A d ju sta b le H ysteresis
W ide S u p ply O p e ra ting Range (7 to 24 V)
10-12
C IR C U IT S FOR C O N S U M E R A P P L IC A T IO N S
T ransistor Arrays
G ENERAL-PURPOSE
c (m ax)
mA
v CEO
Volta Max
VC BO
Volta Max
v EBO
Volta Max
Caae
Type
O ne D iffe re n tia lly C on n e cte d p a ir

and T h re e Iso late d T ra n sistors
50
15
20
5.0
646
M C3346
M C 3386
Dual In d e p e n d e n t D iffe re n tia l

A m p lifie rs w ith A ssociated
C o n sta n t C u rre n t T ra n sistors
50
15
20
5.0
646
C A3054
Function
Special Functions
Caae
Type
E m itte r-C o u p le d A sta b le

M u ltiv ib ra to r
U seful as D C -D C C onverter. Power R eg u lator o r

M u ltivib ra to r. To g g le Freq= 100 kHz (typ)
626
M C 3380
P hase-Locked L oo p
C o n ta in s Voltage C o n tro lle d O s c illa to r and

D ouble Balanced Phase D etecto r
646
NE565
Function
Featurea
Package Styles
8
AAAA
Lead
Configuration
P
j
vvvv
1
14
14
ji
18
A A A A A A A-A-A
16
Ic
1
C IZ 3
vvvvvw vv
1
Caae
M aterial
626
P lastic
632
C eram ic
646
Plastic
648
P lastic
701
P lastic
Suffix
after Type Num ber
P o r PL
Caae
Material
Suffix
after Type Num ber
722A
724
314A
314B
P lastic
P lastic
P lastic
P lastic
10-13
I SPECIAL PURPOSEI
CIRCUITS
The linear-integratsd<ircuits listed in this section were developed by Motorola for the system
design engineer to fill special-purpose requirements.temperature ranges and package availability are
tailored to provide price/performance versatility.
Linear Four-Quadrant
Multipliers
Timing Circuits
MC1555/MC1455/MC1422
These devices are highly stable timing circuits
capable of producing accurate time delays or
oscillation. Additional terminals are provided for
triggering or resetting if desired. In the time delay
mode of operation, the time is precisely controlled
by one external resistor and capacitor. For a stable
operation as an oscillatpr, the free running fre
quency and the duty 'cycle are both accurately
controlled with two external resistors and one
capacitor. The circuit may be triggered and reset
, on; falling waveforms, and the output structure
' can source or sink up to 200 mA or drive MTTL
circuits. Timing from Microseconds through Hours.
The MC1422 has variable threshold level, adjust
able externally.
Timing Error (typ)
MC1555
0.5%
MC1455
1.0%
MC1422
1.0%
MC1594/1494
This device is designed for use where the output
voltage is a linear product of two input voltages.
Typical applications include: multiply, divide,
square root, mean square, phase detector, fre
quency doubler, balanced modulator/demodulator,
electronic gain control.
The MC1594/MC1494 is a variable transconduc
tance multiplier with internal level-shift circuitry
and voltage regulator. Scale factor, input offsets
and output offset are completely adjustable with
the use of four external potentiometers. Two
complementary regulated voltages are provided to
simplify offset adjustment and improve powersupply rejection.
MC1595/MC1495
Similar to the MC1594/1494, but without internal
level shift and voltage regulator circuits.
MC35S6/MC3456
Dual Version of the MC1555/MC1455
Balanced
Modulator-Demoduiator
Low Frequency
Power Amplifier
MC1596/MC1496
Designed for use where the output voltage is a
product of an input voltage (signal) and a switching
function (carrier). Typical applications include
suppressed carrier and amplitude modulation,
synchronous detection, FM detection, phase
detection and chopper applications.
MC15S4/MC1454
One-watt power'amplifier for single or split supply
operation/ Typical voltage gain of 1 0 ,1 8 , or 36
V /V with 0.4% THD.
Power Control Circuits

MC3370
CA3059/3079
Electronic switch for triac triggering applications.

Features zero-crossing detector to eliminate RFI,
differential input with dual sensor inputs, input
open and short protection, and built-in regulator
permitting AC line operation.
------
10-14
Zero voltage switches designed for thyristor

control in a variety of ac power switching applications for ac input voltages of 2 4 V, 120 V,
208/230 V ,- and 277 V a t-50/60 and 400 Hz.
SPECIAL PURPOSE CIRCUITS
Package Styles
Monolithic Dual OP Amp

and Dual Comparator
O perating
T em p eratu re Range
M C 3505/M C 3405
-5 5 to + 1 2 5 C
O to + 7 0 C
Case
M C 1554
M C 1454
603B
M C I 455
6 01 . 6 26 . 693
M C I 594
M C 1494
6 20
M C 1595
M C 14 95
6 32
6 03 . 6 32
M C 14 96
M C 14 22
603 , 6 32 . 646
601. 626
M C 34 05
6 32 . 646
693
M C 34 23
6 2 6 . 6 93
632
M C 3456
6 32 , 6 46
M C 33 70
626
C A 3059*
C A3079*
6 46
This device contains tw o d iffe re n tia l inp u t opera

tional a m plifiers and tw o com parators each set
capable o f single supply operation. This operational
am plifier-com parator c irc u it w ill fin d its applica
tions as a general purpose prod u ct fo r autom otive
circuits and as an industrial "b u ild in g b lo c k ".
Op A m p Equivalent in Performance to MC3403
C om parator Sim ilar in Performance to LM 339
Op Amps are In te rn a lly Frequency Compensated
Supply O peration 3.0 V o lts to 36.0 V olts
Dual Supply O peration also Available
6 01 . 693
M C I 555
M C I 596
632
M C 3505
M C 3523
M C 3556
Overvoltage
Protection Circuit
-- ,o+ c
40
85
M C 3523/M C 3423
OVPs prote ct sensitive c irc u itry from transients or regulator failures when used w ith an external
"c ro w b a r" SCR. They sense the overvoltage and q uickly "c ro w b a r" or short c irc u it the supply, forcing
it in to cu rren t lim itin g o r opening fuse or CB.
Voltage threshold is adjustable and OVPs can be programmed fo r m inim um dura tio n before trip p in g ,
supplying noise im m u n ity.
lO
mA
V cc
Vol,s
VSense V o lts
M ax
M in
M ax
M in
M ax
Device N um ber
S u ffix
3 00
4 .5
40
2.45
2.75
M C 3423
0 to +70
6 26
0 to +70
693
- 5 5 to + 1 2 5
693
M C 3523
ta
Case
10
10-15
HIGH FREQUENCY
AMPLIFIERS
A variety o f high-frequency circuits w ith features ranging fro m tow -cost s im p lic ity to m u lti-fu n c tio n
ve rsatility marks M o to rola 's lin e o f integrated R F /IF am plifiers. Devices described here are intended
fo r ind u stria l a nd com m unications applications. F o r devices especially dedicated to consum er products,
i.e., T V a nd entertainm ent radio, see C ircuits fo r Consumer A p p lic a tio n s ".
NON-AGC Amplifiers
AGC Amplifiers
S E/N E592 D iffe ren tia l Tw o Stage Video A m p lifie r
MC1550 Low Cost B uilding B lock
A m o n o lith ic , tw o state d iffe re n tia l o u tp u t, w id e

band video a m plifier. It offers fixed gains o f 100
and 400 w ith o u t external components and ad
justable gains fro m 400 to 0 w ith one external
resistor. The inp u t stage has been designed so that
w ith the a dd itio n o f a few external reactive ele
ments between the gain select term inals, the
c irc u it can fu n ctio n as a high pass, low pass, or
band pass filte r. This feature makes the circu it
ideal fo r use as a video o r pulse a m plifier in
com m unications, magnetic memories, display and
video recorder systems.
Single-stage cascade connected a m p lifie r w ith

delayed AGC characteristics, fo r operation at
frequencies to 100 MHz. Has typ ical power gain o f
25 dB @ 60 MHz.
M C 1545/M C 1445 Gated 2-Channel In p u t
D iffe ren tia l inp u t and o u tp u t a m p lifie r w ith gated
2-channel inp u t fo r a w ide variety o f switching
purposes. Typical 75 MHz b andw idth makes i t
suitable fo r high-frequency applications such as
video switching, FSK circuits, m ultiplexers, etc.
Gating c irc u it is useful fo r AGC co n tro l.
MC1590 Wide-Band General Purpose
M C 1733/M C 1733C Video A m p lifie r
Has d iffe re n tia l inputs and o utp uts w ith unneu

tralized power gain as high as 35 dB typical at 100
MHz in tuned a m plifier service. E ffective AGC
voltage range fro m 5 to 7 volts fo r a 30 dB gain
reduction.
D iffe ren tia l in p u t and o u tp u t a m p lifie r provides

three fixe d gain options w ith bandw idth to 120
MHz. External resistor perm its any gain setting
fro m 10 to 4 00 v/v. E xtrem ely fast rise tim e (2.5
ns ty p ) and propagation delay tim e (3.6 ns typ)
makes this u n it p a rticu la rly useful as pulse a m pli
fie r in tape, drum , or disc m em ory read applications.
Electrical Specifications
AGC A M P L IF IE R S
M C 1552/M C 1553 Low D isto rtio n A m p lifie r
O pe ra tin g
Tam peratura Rang*
-6 5 to
0 to
+ 1 2 5 C
+ 7 5 C
A high performance a m p lifie r w ith internal series

feedback fo r stable voltage gain and low d isto rtio n .
Tem perature compensation stabilizes operating
p o in t. Has selectable gain o p tio n and well charac
terized data th a t perm its accurate response shaping.
Useful fo r critical applications such as wideband
linear am plifiers or fast-rise pulse am plifiers.
Ay
dB
Band
w id th
MHz
Vcc/
v Ee
Vdc
Casa
M C I 550
22 M in
22
+ 6 /-
6 0 3 8 ,6 0 6
M C 1590
44 T y p @
4 Typ @
10
100
+ 1 2 /-
601
M C 1545
M C 1445
19 T yp @
75
+ 5 /-B
6 0 3 .6 0 7
632
NON AGC A M P L IF IE R S
S U F F IX
40
90
120
+ 6 /-6
6 0 3 .6 3 2
46
52
35
15
+6Z-6
603 B
40
35
+ 6 /-6
6038
40
90
+ 6 /-6
6 0 3 .6 3 2
M C 1653
M C I 552
34
40
N E 592
55
45
Package Styles
M A T E R IA L
<s>
M C 1733C
S E592
CASE
52
40
20
M C I 733
<5>
<P
601
603
6 03 B
606
607
6 32
M etal
Metal
M etal
Ceram ic
C eram ic
Ceram ic
a lta r ty p e n um ber
10-16
CASE OUTLINE DIMENSIONS

The packaging availability for each device type is indicated on the individual data sheets
and the Selector Guide. All of the outline dimensions for the packages are given in this
section. Outline dimensions for non-encapsulated standard linear device chips and flip-chip
devices are found in the Chips Data Book.
The maximum power consumption an integrated circuit can tolerate at a given operating
ambient temperature can be found from the equation:
n
T j(m a x ) T a
pD(TA) *
Rj a OV p )
Power Dissipation allowable at a given operating ambient temperature.
This must be greater than the sum of the products of the supply voltages
and supply currents at the worst case operating condition.
Tj(m ax) = Maximum Operating Junction Temperature as listed in the Maximum
Ratings Section. See individual data sheets for T j(max) information.
T a = Maximum Desired Operating Ambient Temperature
R0JA(Typ) = Typical Thermal Resistance Junction to Ambient
where: pD(TA )
CASE 60104
Metal Package
MILLIMETERS
DIM M
IN MAX
A
NOTE:
1. LEADSWITHIN0.25ram(0.010)
, \~1 N
DIAOFTRUEPOSITIONAT
.u
SEATINGPUNEATMAXIMUM
MATERIALCONDITION.
3.51 9.40
7.75 8.51
4.19 4.70
0.41 0.48
0.25 1.02
1.02
025
5.08 BSC
B
C
D
E
F
G
H 0.71 0.86
J 0.74 1.14
K 12.70
L 105 4.08
M 45 BSC
N 2.41 12.67
-
INCHES
MIN
MAX
01335
0305
0165
0370
0335
0185
0019
0040
0040
0016
ooto
0010
0200 BSC
0028 0034
0029 0045
0500
0120 0160
45 BSC
0095 10105
-
CASE 603 04
Metal Package
DIMI7TI7BV-WM E^TTTIU7MM
A 8.51 9.39 0335 1Q37QI
B 7.75 8.51 0305
C 4.19 4.70 0165
D 0.407 0533 0.016
E
1.02
F 0.406 0.483 0016
G 1 5.84BSC 1 0231)BSC
H 0.712 0.884 0.028 0034
J 0.737 1.14 0.029 0.045
K 12.70
0500
L 6.35 12.70 0250 0.500
M1 36 BSC 1 36PBSC
1.27
0.050
P
a 3.56 4.06 0140 0160
R 6.254 I.Oi O
lO
IO- 0.040
-
11
NOTE:
LEADSWITHIN0.18mm(0.007) RADIUSOF
TRUEPOSITIONATSEATINGPLANE
ATMAXIMUMMATERIALCONDITION.
All JEDEC dimensions and notes apply
11-2
CASE 620-02
Ceramic Package
r o
D IM
M ILLIM ETERS
MAX
MIN
A
B
C
D
F
G
H
J
K
L
M
N
19.81
19.05
6.98
6.22
5.08
4.06
0.51
0.38
1.40_1 1.65
2.54 BSC
1.14
0.51
0.30
0.20
4.06
3.18
7.37
7.87
_
15
1.02
0.51
DIM
M ILLIM ETERS
MIN
MAX
INCHES
MAX
MIN
0.750
0.245
0.160
0.015
0.055
0.100
0.020
0.008
0.125
0.290
-
0.020
0.780
0.275
0.200
0.020
0.065
BSC
0.045
0.012
0.160
0.310
15
0.040
NOTES:
1 LEADS W ITHIN 0.13 mm (0.005) RADIUS
OF TRUE POSITION A T SEATING PLANE
AT M AXIM UM M A TE R IA L CONDITION
2 PKG. INOEX: NOTCH IN LEAD
NOTCH IN CERAMIC OR IN K DOT
3 DIM " L " TO CENTER OF LEADS
WHEN FORMED PA R ALLEL
CASE 620-06
Ceramic Package
n n n n n n n n
u u u u u t o t j
A
B
C
O
F
G
H
J
K
L
M
N
INCHES
MIN
M AX
19.94
7.49
5.08
0.38
0.53
1.40
1.78
2.54 BSC
0.51
1.14
0.20
0.30
5.08
3.18
7.62 BSC
_
15
0.51
1.02
0.785
0.295
0.200
0.021
0.015
0.070
0.055
0.100 BSC
0.020
0.045
0.012
0.008
0.125
0.200
0.300 BSC
_
15
0.040
0.020
M ILLIM E TE R S
MAX
MIN
INCHES
MIN
MAX
31.24
32.77
12.70
15.49
5.59
4.06
0.41
0.51
1.27
1.52
2.54 BSC
0.20
0.30
4.06
2.29
15.24 BSC
15
0
1.27
0.51
1.230
1.290
0.500
0.610
0.220
0.160
0.016
0.020
0.050
0.060
0.100 BSC
0.008
0.012
0.090
0.160
0.600 BSC
0
15
0.050
0.020
19.05
6.10
_
0.750
0.240
_
1. LEADS W ITH IN 0.13 mm (0.005) RADIUS

OF TRUE POSITION A T SEATING PLANE
AT M AXIM UM M A TE R IA L CONDITION.
2. PACKAGE IN D EX: NOTCH IN LEAD
NOTCH IN CERAMIC OR INK DOT.
3. DIM V ' T O CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIM " A " AND "B " DO NOT INCLUDE
GLASS RUN OUT.
5. DIM " F " M AY NARROW TO 0.76 mm
(0.030) WHERE THE LEAD ENTERS
THE CERAMIC BODY.
CASE 623-04
D IM
Ceramic Package
A
B
C
D
F
G
J
K
L
M
N
NOTES:
1. DIM " L " TO CENTER OF
LEADS WHEN FORMED
PARALLEL.
2. LEADS W ITH IN 0.13 mm
(0.005) RADIUS OF TRUE
POSITION A T SEATING
PLANE AT M AXIM UM
M A TE R IA L CONOITION.
(WHEN FORMED PA R ALLEL)
S E A T IN G P L A N E
11-3
CASE 626-04
Plastic Package
Pi
rl
DIM
M ILLIM ETERS
M IN
MAX
INCHES
M IN
MAX
A
B
C
0
F
G
H
J
K
L
M
N
9.40
10.16
6.10
6.60
3.94
4.45
0.38
0.51
1.02
1.52
2.54 BSC
0.76
1.27
0.20
0.30
2.92
3.43
7.62 BSC
10
0.51
0.76
0.400
0.370
0.240
0.260
0.155
0.175
0.015
0.020
0.040
0.060
0.10C BSC
0.030
0.050
0.008
0.012
0.115
0.135
0.300 BSC
_
10
0.020
0.030
NO TE 4
NOTES:
1. LEADS W ITHIN 0.13 mm
POSITION AT SEATING
PLANE A T M AXIM UM
M A TE R IA L CONDITION.

LEADS WHEN FORMED
PARALLEL.
3. PACKAGE CONTOUR
OPTIONAL (ROUND OR
SQUARE CORNERS)
j-JW-
KJ
SEA TIN G PLANE
CASE 632-02
DIM
Ceramic Package
V ?
-----------------A ---------
J -l
V.
A
B
C
D
F
G
J
K
L
M
N
P
M ILLIM ETERS
MIN
M AX
16.8
5.59
19.9
7.11
_
5.08
0.584
0.381
0.77
1.77
2.54 BSC
0.203
0.381
2.54
7.62 BSC
15
0.51
0.76
8.25
INCHES
MAX
MIN
0.785
0.280
0.200
0.015
0.023
0.070
0.030
0.100 BSC
0.015
0.008
0.100
0.300 BSC
15
0.030
0.020
0.325
0.660
0.220
All JEDEC dimensions and notes apply.

NOTES:
1. A LL RULES AND NOTES ASSOCIATED
WITH M0 001 AA OUTLINE SHALL APPLY.
2. DIMENSION "L''TO CENTER OF LEADS
WHEN FORMED P A R ALLE L
3. LEADS WITHIN 0.25 mm (0.010) DIA
OF TRUE POSITION AT SEATING PLANE
AND MAXIMUM M ATERIAL CONDITION.
CASE 646-05
Plastic Package
A A A A A A A
NOTES
1 LEADS W ITHIN 0.13 mm
POSITION A T SEATING
PLANE AT M AXIM UM
2. DIMENSION " L " T O
CENTER OF LEADS
3. DIMENSION '8" DDES NOT
WHEN FORMED
INCLUDE MOLD FLASH.
PA R ALLEL.
4. ROUNDED CORNERS OPTIONAL
11-4
DIM
A
B
C
O
F
G
H
J
K
L
M
N
M ILLIM ETERS
MIN
MAX
18.16
19.56
6.10
6.60
4.06
5.08
0.38
0.53
1.02
1.78
2.54 BSC
2.41
1.32
0.20
0.38
2.92
3.43
7.62 BSC
100
0
0.51
1.02
INCHES
MIN
MAX
0.715 0.770
0.240
0.260
0.160
0.200
0.015
0.021
0.040
0.070
0.100 BSC
0.052
0.095
0.008
0.015
0.115
0.135
0.300 BSC
10O
0
0.020
0.040
CASE 648-05
M ILLIM E TE R S
DIM
Plastic Package
NOTES:
1. LEADS W ITHIN 0.13 mm
POSITION AT SEATING
PLANE AT MAXIMUM
M ATER IA L CONDITION.
2. DIMENSION " L " T 0
CENTER OF LEADS
WHEN FORMED
3. DIMENSION "B " DOES NOT

INCLUDE MOLD FLASH.
4. F" DIMENSION IS FOR FULL
LEADS. "H A LF " LEADS ARE
OPTIONAL AT LEAD POSITIONS
1,8, 9. and 16).
5. ROUNDED CORNERS OPTIONAL.
PARALLEL.
A
B
C
D
F
G
H
J
K
L
M
N
MIN
M AX
21.34
18.80
6.60
6.10
4.06
5.08
0.53
0.38
1.02
1.78
2.54 BSC
2.41
0.38
0.38
0.20
2.92
3.43
7.62 BSC
0<>
100
1.02
0.51
D IM
M ILLIM ETERS
MAX
MIN
INCHES
MAX
MIN
0.840
0.260
0.200
0.021
0.070
BSC
0.095
0.015
0.135
BSC
10
0.040
0.740
0.240
0.160
0.015
0.040
0.100
0.015
0.008
0.115
0.300
0
0.020
O
If I
O P T IO N A L L E A D
C O N F IG . (1, 8, 9, 8< 16)
-NOTE 5
CASE 649-03
Plastic Package
--- -----------------------------------
--------------------------------- J
24
13
)
I
|0
NOTES:
1. LEADS W ITHIN 0.13 mm (0.005)
RADIUS OF TRUE POSITION AT
SEATING PLANE AT M AXIM UM
2. DIMENSION " L " T 0 CENTER OF
LEAOSWHEN FORMED PARALLEL.
u
h
12
v
A
B
C
D
F
G
H
J
K
L
M
N
P
Q
31.50
13.21
4.70
0.38
1.02
2.54
1.65
0.20
2.92
14.99
-
0.51
0.13
0.51
32.13
13.72
5.21
0.51
1.52
BSC
2.16
0.30
3.43
15.49
10
1.02
0.38
0.76
INCHES
MAX
MIN
1.240
0.520
0.185
0.015
0.040
0.10C
0.065
0.008
0.115
0.590
-
0.020
0.005
0.020
1.265
0.540
0.205
0.020
0.060
BSC
0.085
0.012
0.135
0.610
10
0.040
0.015
0.030
CASE 690-12
Ceramic Package
,<
1
I__I
1-I
I I__a __ii
I-I
IJ
8
I--1 I__ 1 LJ lJ
--------------
-----------
I -
DIM
M ILLIM E TE R S
MIN
MAX
A
B
C
O
F
G
H
J
K
L
M
N
20.07
20.57
7.11
7.62
3.94
2.67
0.38
0.53
0.76
1.40
2.54 BSC
0.76
1.78
0.20
0.30
3.18
5.08
7.62 BSC
10
0.38
1.40
INCHES
MAX
MIN
0.790
0.280
0.105
0.015
0.030
0.100
0.030
0.008
0.125
0.300
-
0.015
1. LEADS W ITH IN 0.13 mm (0.005) RADIUS

OF TRUE POSITION, AT SEATING PLANE
-1
AND M A XIM U M M A T E R IA L CONDITION.
j ^
G j
11-5
M
-SEATING PLANE
0.810
0.300
0.155
0.021
0.055
BSC
0.070
0.012
0.200
BSC
10
0.055
CASE 693-02
Ceramic Package
1. LEADS W ITH IN 0.13 mm (0.005)

RAD OF TRUE POSITION AT
SEATING PLANE AT M AXIM UM
2. DIMENSION " L " TO CENTER
OF LEADS WHEN FORMED
PARALLEL.
SEATING PLANE
CASE 701-01
Plastic Package
NOTES:
1. LEADS W ITH IN 0.13mm
(0.005) RADIUM OF TRUE
POSITION AT SEATING
PLANE AT M AXIMUM
M A TER IA L CONDITION
(DIM "G").
2. DIMENSION " L " TO CENTER
OF LEADSWHEN FORMED
PARALLEL.
M
PLANE
CASE 710-02
Plastic Package
. l"i i" i
11
1.
POSITIONAL TOLERANCE OF LEADS (D),

SHALL BE W ITH IN 0.25mm(0.010) A T
M AXIM UM M A TE R IA L CONDITION, IN
RELATION TO SEATING PLANE AND
EACH OTHER.
2.
DIMENSION L TO CENTER OF LEADS

WHEN FORMED PARALLEL.
DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
3.
11-6
CASE 724-02
Plastic Package
fAi r Ai i ni r ni r ni r Ai r Ai f ni r ni i ni f ni i Ai
24
13
lO
12
T
?
DIM
A
B
C
D
F
G
H
J
K
L
M
N
M ILLIM E TE RS
MAX
MIN
31.24
32.13
6.86
6.35
4.57
4.06
0.38
0.51
1.52
1.02
2.54 BSC
1.60
2.11
0.30
0.18
3.43
2.92
7.87
7.37
10
1.02
0.51
INCHES
MAX
1.265
0.270
0.180
0.020
0.060
BSC
0.083
0.012
0.135
0.310
10
0.040
0.020
MIN
1.230
0.250
0.160
0.015
0.040
0.100
0.063
0.007
0.115
0.290
NOTE:
1. LEADS. TRUE POSITIONED W ITHIN
0.25 mm (0.010) DIA A T SEATING
PLANE AT M AXIM UM M A TE R IA L
CONDITION (DIM D).
CASE 726-01
M ILLIM E TE R S
DIM
A
B
C
D
F
G
H
J
K
L
M
N
Ceramic Package
NOTES:
1. LEADS,TRUE POSITIONED
W ITH IN 0.25 mm (0.010) DIA.
A T SEATING PLANE, A T
M A XIM UM M A TE R IA L
CONDITION.
LEADS WHEN FORMED
PARALLEL.
3. DIM " A " & "B INCLUDES
MENISCUS.
MIN
22.35
6.63
MAX
23.11
7.24
5.08
0.41
0.51
1.40
1.65
2.54 BSC
0.76
1.02
0.38
0.13
4.44
7.37
8.00
0
15
0.51
0.76
INCHES
MIN
0.880
0.261
M AX
0.910
0.285
0.200
0.020
0.016
0.055
0.065
0.100 BSC
0.030
0.040
0.005
0.015
0.175
0.290
0.315
0
15
0.020
0.030
S E A T IN G P L A N E
CASE 732-02
Ceramic Package
20
11
>
1
I V
10
V
V M
B-
-- ------------------
-------------------- -
NOTES:
1. LEADS W ITH IN 0.25 mm (0.010)
D IA , TRUE POSITION AT
SEATING PLANE. A T M AXIM UM
2. DIM L TO CENTER OF LEADS
3. DIM A AND B INCLUDES
MENISCUS.
11-7
DIM
A
B
C
O
F
G
H
J
K
L
M
N
M ILLIM E TE R S
MAX
MIN
24.38
25.15
7.49
6.86
4.32
5.08
0.38
0.56
1.40
1.65
2.54 BSC
1.40
0.89
0.20
0.30
4.06
3.18
7.62 BSC
15
0.76
0.51
INCHES
MIN
MAX
0.960
0.990
0.295
0.270
0.170
0.200
0.015
0.022
0.055
0.065
0.100 BSC
0.035
0.055
0.012
0.008
0.125
0.160
0.300 BSC
50
15
0.020
0.030
CASE 733-02
Ceramic Package
DIM
M ILLIM E TE RS
MIN
MAX
INCHES
MIN
MAX
36.45
37.85
1.435
1.490
12.70
15.37
0.500
0.605
0.230
4.06
5.84
0.160
0.38
0.56
0.015
0.022
1.27
1.65
0.050
0.065
2.54 BSC
0.100 BSC
0.20
0.30
0.008
0.012
2.54
4.06
0.100
0.160
15.24 BSC
0.600 BSC
15
15
0.51
1.27
0.020
0.050
NOTES:
1. DIM P a H IS DATUM.
2. POSITIONAL TO L FOR LEADS:
28
15
14
I 0 0.25 (0.010) @ 1 T I A (0)1
3. G H ] IS SEATING PLANE.
4. DIM A AND B INCLUDES MENISCUS.
5. DIM
L- TO CENTER OF LEADS
6. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5.1973.
_ 4 -
CASE 738-01
Plastic Package
l0
DIM
A
B
C
D
F
G
J
K
L
M
N
fm
NOTES:
1. D IM G a D IS DATUM.
2. POSITIONAL TOL FOR LEADS;
X I U 'U
UX1 u
1 [ 0 0.25 (0.01Q)@jT |A 0~
3. G U I
Ea D
IS SEATING PLANE.
4. DIM " 8 " DOES NOT INCLUDE MOLO FLASH.

5. DIM Q D
TO CENTER OF LEADS WHEN
FORMED PARALLEL.
6. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5, 1973.
11-8
M ILLIM ETERS
MIN
MAX
25.65 27.18
6.10
6.60
3.94
4.19
0.38
0.56
1.27
1.78
2.54 BSC
0.20
0.38
2.79
3.56
7.62 BSC
0
15
0.51
1.02
INCHES
MIN
MAX
1.010
1.070
0.240
0.260
0.155
0.165
0.015
0.022
0.050
0.070
0.100 BSC
0.008
0.015
0.140
0.110
0.300 BSC
0
15
0.040
0.020
APPLICATION NOTE ABSTRACTS

The application notes listed in this section have been prepared to acquaint the circuits and systems engi
neer with Motorola Linear integrated circuits and their applications. To obtain copies of the notes, simply list the
AN number or numbers and send your request on your company letterhead to: Technical Information Center,
Motorola Semiconductor Products Inc., P.O. Box 20912, Phoenix, Arizona 85036.
A N -245A A n I n te g r a t e d C o re M em ory
S e n s e A m p lifie r
This application note discusses core memories
and related design considerations for a sense ampli
fier. Performance and environmental specifications
for the amplifier design are carefully established so
th at the circuit will work with any computer using
core memories. The final circuit design is then ana
lyzed and measured performance is discussed. The
amplifier features a small uncertainty region (6 mV
max), adjustable voltage gain, and fast cycle time
(0.5 us).
A N -273A M o re V a lu e o u t o f I n te g r a te d
O p e ra tio n a l A m p lifie r D a ta S h e e ts
The operational amplifier is rapidly becoming a
basic building block in present day solid state elec
tronic systems. The purpose of this application note
is to provide a better understanding of the open loop
characteristics of the amplifier and their significance
to overall circuit operation. Also, each parameter is
defined and reviewed with respect to closed loop
considerations. The importance of loop gain stability
and bandwidth is discussed a t length. Input offset
circuits are also reviewed with respect to closed loop
operation.
A N -2 9 0 B M o u n tin g P ro c e d u r e fo r, a n d
T h e rm a l A sp e c ts of, T h e rm o p a d P la s tic
P o w e r D e v ic e s
Many Motorola power devices are now available
in the Plastic Thermopad packages. Three package
types are presently available. This application note
provides information concerning the handling and
mounting of these packages, as well as information
on some thermal aspects.
A N -401 T h e M C 15S4 O n e -W a tt M onolithic

I n te g r a t e d C irc u it P o w e r A m p lifie r
This application note discusses four different
applications for the MC1554, along with a circuit
description including DC characteristics, frequency
response, and distortion. A section of the note is also
devoted to package power dissipation calculations
including the use of the curves on the power ampli
fier data sheet.
A N -404 A W id eb a n d M o n o lith ic V ideo

A m p lifie r
This note describes the basic principles of AC
and DC operation of the MC1552G and MC1553G,
characteristics obtained as a function of the device
operating modes, and typical circuit applications.
A N -411 T h e M C 1535 M o n o lith ic D u a l Op

Amp
This note discusses two dual operational ampli
fier applications and an input compensation scheme
for fast slew rate for the MC1535. A complete AC
and DC circuit analysis is presented in addition to
many of the pertinent electrical characteristics and
how they might affect the system performance.
A N -421 S e m ic o n d u c to r N o ise F ig u re
C o n s id e ra tio n s
A summary of many of the important noise fig
ure considerations related with the design of low
noise amplifiers is presented. The basic fundamen
tals involving noise, noise figure, and noise figurefrequency characteristics are then discussed with the
emphasis on characteristics common to all semicon
ductors. A brief introduction is made to various
methods of data sheet presentation of noise figure
and a summary is given for the various methods of
measurement. A discussion of low noise circuit de
sign, utilizing many of the previously discussed
considerations, is included.
A N -471 A n a lo g -to -D ig ita l C o n v e rsio n

T e c h n iq u e s
The subject of analog-to-digital conversion and
many of the techniques th a t can be used to accom
plish it are discussed. The paper is written in
general terms from a system point of view and is
intended to assist the reader in determining which
conversion technique is best suited for a given appli
cation.
A N -489 A n a ly s is a n d B a sic O p e ra tio n o f

th e M C 1595
The MC1595 monolithic linear four-quadrant
multiplier is discussed. The equations for the anal
ysis are given along with performance th a t is
characteristic of the device. A few basic applications
are given to assist the designer in system design.
12-2
APPLICATION NOTE ABSTRACTS (Continued)

AN-491 Gated Video Amplifier
Applications Using The MC1545
This application note reviews the basic operation
of the MC1545 and discusses some of the more pop
ular applications for the MG1545. Included are
several modulator types, temperature compensation
of the active gate, AGC, gated oscillators, FSK sys
tems, and single supply operation.
AN-513 A High Gain Integrated Circuit RFIF Amplifier with Wide Range AGC;
This note describes the operation and application
of the MC1590G, a monolithic RF-IF amplifier. In
cluded are several applications for IF amplifiers, a
mixer, video amplifiers, single and two-stage RF
amplifiers.
AN-522 The MC1556 Operational

Amplifier and its Applications
This application note discusses the MCI556, a
second generation, internally compensated mono
lithic operational amplifier. Particular emphasis is
placed on its distinct advantages over the early 709type amplifier and the more recent 741-type ampli
fier.
Along with a description of its operation this
note presents a discussion on various applications of
the MC1556, highlighting its capabilities, and points
out its characteristics so the reader may make feffecr
tive use of the device.
AN-531 MC1596 Balanced Modulator

The MC1596 monolithic circuit is a highly versa
tile communications building block. In this note,
both theoretical and practical information are given
to aid the designer in the use of this part. Applica
tions include m odulators for AM, SSB, arid
suppressed carrier AM; demodulators for the pre
viously mentioned modulation forms; frequency
doublers and HF/VHF double balanced mixers.
AN-533 Semiconductors for Plated-Wire

Memories
An introduction to the operation and electrical
characteristics of plated'Wire memories is provided
in conjunction with the applications of semiconduc
tors th at interface with the plated-wire memories.
Devices discussed include drivers, sense ampli
fiers, and decoders. Memory organization and
memory-related semiconductor applications are also
mentioned.
AN-543A Integrated Circuit IF Amplifiers

for AM/FM and FM Radios
This application note discusses the design and
performance of four IF amplifiers using integrated
circuits. The IF amplifiers discussed include a high
performance circuit, a circuit utilizing a quadrature
detector, a composite AM/FM circuit, and an econ
omy model for use with an external discriminator.
AN-545 Television Video IF Amplifier

Using Integrated Circuits
This applications note considers the require
ments of the video IF am plifier section of a
television receiver, and gives working circuit sche
matics using integrated circuits which have been
specifically designed for consumer oriented prod
ucts. The integrated circuits used are the MC1350^
MC1352, MC1353 and the MC1330.
AN-547 A High-Speed Dual Differencial

Comparator, The MC1514
This application note discusses a few of the many
uses for the MC1514 dual comparator. Many appli
cations such as' sense amplifiers, multibvibrators,
and peak level detectors are presented.
AN-553 A New Generation of Integrated

Avionic Synthesizers
The need to generate signals of a multitude of
different frequencies for avionic systems has re
sulted in complex solutions in the past. With the
introduction of certain standard "product integrated
circuits, frequency synthesis using digital phase
locked loop techniques presents a more practical
solution. Several d iffe ren t' types of servo phase
locked loop systems are discussed and a practical
design example is given. Results of design examples
are presented along with possible applications.
AN-557 Analog-to-Digital Cyclic Converter

The A/D cyclic converter discussed in this note
provides medium speed (l-5*ts/ bit) and medium
accuracy (7 or 8 bits) operation. A Cyclic converter
uses the successive approximation technique in
which an unknown analog input voltage is succes
sively compared to a reference voltage to determine
each bit of the digital output.
The cyclic converter offers continuous operation,
automatic generation of the digital output in Graycode form, and a building block structure. This
structure uses a separate but identical circuit for
each resolution b it The cyclic converter finds use
primarily in control and process applications.
AN-559 Simple Ramp A/D Converter

A simple single ramp A/D converter which incor
porates a calibration cycle to insure an accuracy of
12 bits is discussed. The circuit uses standard ICs
and requires only one precision partthe reference
voltage used in the calibration. This converter is
useful in a number of instrumentation and measure
ment applications.
AN-564 An ADF Frequency Synthesizer

Utilizing Phase-Locked Loop Integrated
Circuits
This application note describes an IC phase
locked-loop frequency synthesizer suitable for the
local osciallator function in aircraft Automatic
Direction Finder (ADF) equipm ent

AN-587 Analysis and Design of the Op Amp
Current Source
AN-710 Communication SystemTransmission Losses
A voltage controlled current source utilizing an

operational amplifier is discussed. Expressions for
the transfer function and output impedances are
developed using both the ideal and non-ideal op
mp models. A section on analysis of the effects of
op amp parameters and temperature variations on
circuit performance is presented.
This report shows the derivation of the equations

used to calculate the insertion loss associated with
various component parts of a communications chan
nel. The combinations of components form a system
whose overall loss may not be equal to the sum of
the losses of the various parts.
AN-590 Servo Motor Drive Amplifiers
AN-711 The Recovery of Recorded Digital

Information in Drum, Disk and Tape
Systems
'
The design of transformerless, AC servo ampli

fiers using power darlington transistors and IC op
amps are discussed. Two types of power amplifiers
are illustrated, one using single +28 Volt power sup
ply, the second using high voltage transistors in
complementary configuration for operating directly
off the line.
Four different op amp preamplifiers and 90
phase shifters are also described.
AN-599 Mounting Techniques for Metal

Packaged Power Semiconductors
For. cooler, more reliable operation, proper
mounting procedures must be followed if the inter
face thermal resistance between the semiconductor
package and heat sink is to be minimized. Discussed
are aspects of preparing the mounting surface, using
thermal compounds, and fastening techniques. Typi
cal interface thermal resistance is given for a
number of packages.
AN-702 High Speed Digital-To-Analog and

Analog-To-Digital Techniques
A brief overview of some of the more popular
techniques for accomplishing D/A and A/D tech
niques. In particular those techniques which lead
themselves to high speed conversion.
AN-703 Designing Digitally-Controlled

Power Supplies
This application note shows two design ap
proaches; a basic low voltage supply using an
inexpensive MC1723 voltage regulator and a high
current, high voltage, supply using the MC1466
floating regulator with optoelectronic isolation. Var
ious circuit options are shown to allow the designer
maximum flexibility in an application.
AN-708A Line Driver and Receiver

Considerations
This report discusses many line driver and re
ceiver design considerations such as system
description, definition of terms, important parame
te r m e a s u re m e n ts , d e sig n p ro c e d u re s an d
application examples. An extensive line of devices is
available from Motorola to provide the designer with
the tools to implement the data transmission re
quirem ents necessary for almost every type of
transmission system.
THe use of magnetic recording techniques has

long been an important means of sorting digital information, as evidenced by the wide variety of
equipment currently in use. Representative systems
utilize drums, disks and tape as the recording me
dium.
All three techniques share the common problem
of recovering the recorded digital information. The
analog signal obtained by passing the recording
medium by a magnetic sensor (Read Head) must be
converted to a suitable digital format,
This application note reviews the general prob
lem and discusses a number of specific circuit
approaches.
AN-713 Binary D/A Converters can

Provide BCD-Coded Conversion
This note describes the application and use of
integrated circuit D/A converters for use in provid
ing a BCD-coded conversion. The technique is
illustrated using a 2-1/2 digit digital voltmeter.
AN-714 A Personalized Heart^Rate

Monitor with Ditigal Readout
Using the micropower operational am plifier
MC1776 and CMOS digital integrated circuits, en
tirely self-contained p o rtab le electro-m edical
monitoring equipment can be built. This note de
tails the construction of a heart-rate monitor giving
a digital indication, beat-by-beat.
AN-716 Successive Approximation A/D

Conversion
Recent advances in integrated circuit design and
technology have resulted in reduced cost of high
performance successive approximation analog to dig
ital converters. This note: describes and illustrates
two examples of how modern IC components have
changed this well known technique.
AN-717 Battery Powered 5-MHz

Frequency Counter
T his application note describes a batterypowered 5-MHz frequency counter using the
McMOS* logic family for low-power operation. The
basic Counter is optimized, at a 12-volt supply for
maximum performance with a linear input-signal

conditioner. Several Options are discussed which op
tim ize the basic counter for minimum power
dissipation: These-options include a CMOS input
signal-conditio'ner and multiplexed LED displays.
A N -719 A N ew A p p ro a ch to S w itc h in g
R e g u la to rs
This article, describes a ;24-Volt,r 3-Ampere
switching mode supply. I t operates a t 20 kHz from a
120 Vac line with an overall efficiency of 70%. New
techniques are used to shape the load line. The con
trol portion ûses a quad comparator and an opto
coupler and features short circuit protection.
A N -720 . I n te r f a c in g w ith M ECL 10,000 This article, describes some of the MECL circuits
used to interface with signals not meeting MECL
input or output requirements. The characteristics of
these circuits such as; input impedance, output
drive, gain and bandwidth allow the system designer
to use these parts to optimize his system. MECL
interface circuits overcome a problem area of many
system designs, which is the efficient coupling of
non-compatible signals.
A N -732A A N o n -V o latile M ic ro p ro c e sso r
M em o ry U sin g 4K N -C h a n n e l MOS RAM s
NMOS .semiconductor technology has made in
roads into high density/high performance circuit
design. T he orie-chip microprocessor, Random Ac
cess Memories, and Read Only Memories, are
changing system implementation from random logic
designs to software and fitmware programmable
microcomputing systems. Such systems frequently
require relatively large amounts of memory.
This paper describes the design of an 8192-byte
non-volatile Random Access Memory system using
the MCM6605A 4Kxl RAM. The syste is designed
to work with the Motorola MC6800, an 8-bit micro
processor.
A N -737A S w itc h e d M ode P o w e r
S u p p liesH ig h lig h tin g A 5-V, 40-A I n v e r te r
D esig n
This application note identifies the features of
various regulator circuits that are in use today in AC
to DC power supplies. The note also illustrates how
these circuits may be used as complementary build
ing blocks in a system design. Primary emphasis is
on switched mode regulators because they fill the
present need for energy and space savings.
A complete 5-V, 40-A line operated inverter sup
ply is d escribed in d e ta il including design
procedures for the magnetic components. The in
verter itself is a state-of-the-art design which
features CMOS logic, high voltage power transistors,
Schottky rectifiers and an optoelectronic coupler. It
operates with a full load efficiency of 80% at a fre
quency of 20 kHz.
A N -739 A S y n th e tic S p e c tru m T u n in g

S y stem f o r TV
A tuning system is described which uses a com
plete spectrum of TV channel markers to achieve
precise tuning to any channel.
A N -741 I n te r f a c e C o n s id e ra tio n s fo r
N u m eric D isp la y S y ste m s
This application note describes several methods
of multiplexing multi-digit, seven-segment displays.
The logic devices illustrated are primarily CMOS
with two examples describing TTL. The displays
discussed are liquid crystal, LED, gas discharge, in
candescent and fluorescent. How to interface
between the logic and these displays, and what the
interface considerations are, are described in detail.
A N -744 A P h a s e -L o c k e d L oop T u n in g
S y ste m fo r T e le v isio n
This note describes a frequency domain tuning
system which utilizes direct digital countdown of the
varactor tuners local oscillator to obtain the proper
local oscillator frequency for the channel number
selected. The system features direct-channel access
with equal ease of tuning and .an exact channel rea
dout for all VHF and UHF channels.
A N -746 A 3V4 D ig it DVM U s in g a n
I n te g r a te d C irc u it D u a l R a m p S y ste m
This application note describes the design of a
3 Vi -digit DVM (digital voltmeter) using the MC1405
and the MC14435 dual ramp A/D system. The per
formance criteria is th at of a lab quality DVM with
both 3 -i-digit resolution and accuracy while still
retaining a low cost and low parts count instrument.
Features of the DVM include circuitry for a high
impedance input, autopolarity and overrange indica
tion.
A N -751 A D is a s s o c ia te d I n te r c a r r ie r
T elev isio n V ideo IF A m p lifie r
This application note discusses a unique video IF
system, incorporating the MC1331, low-level multi
plier detector. Problem areas in IF design are
discussed and the specific solutions are shown.
A N -752 An 8 0 -W a tt S w itc h in g R e g u la to r
fo r CATV an d I n d u s tr ia l A p p lic atio n s
This application note describes a 24-Volt, 3Ampere switching, regulated power supply th at op
erates above 18 kHz from a 40-to 60-Volt, 60-Hz
square wave source (CATV power line from a ferroresonant transformer) or a dc standby source with
input output isolation. The control circuit consists
of a dual operational amplifier and a linear inte
grated circuit timer which are used to vary the on
time of a new high-speed power transistor. The cir
cuit provides good efficiency, good regulation, low
output ripple and incorporates input and output
voltage over shutdown protection.
AN-757 Analog-to-Digital Conversion

Techniques with the MC6800
Microprocessor System
AN-765 An Approach To A Low-Noise TV

IF System
This application note describes several analog-todigital conversion systems implemented with the
M6800 microprocessor and external linear and digi
tal |C s. Systems consisting of an 8* and lOrbit
successive approximation approach, as well as dual
ramp techniques of 3 '/2 -and 4 V&digit BCD and 12bit binary, are shown with flow diagrams, source
programs and fikrdware schematics. System tra
deoffs of the various schemes and programs for
binary-to-BCD and BCD-to-7 segment code'are dis
cussed.
'
This note describes a technique of measurement

of the IF contribution and ways ofm inim ization of
the IF noise. An IF design, following these proce
dures, is described to m eet the desired noise
performance. >-,
AN-767 A Line Operated, Regulated

5 V/50A-Switching Power Supply
This application note describes a regulated 220 V
ac to 5 Vdc converter using high voltage switching
transistors and Schottky barrier rectifiers. The con
trol functions are all performed by integrated
circuits.
AN-760 Application of The MC3416

Crosspoint Switch
' -r
r > AN-775 M6800 Syste'ms Utilizing the
The operation and application of the MC3416 4 x MC6875 Clock Generator/Driver
4 balanced crosspoint switch is described in detail.

Special emphasis is given to balanced switching sys
tems like those in space division PABX. Discussion
of the total system design using the MC3416 is also
included.
AN-763 The MC1323A Fully

Programmable Demodulator
The MC1323 is a monolithic integrated circuit

demodulator specifically designed for decoding the
NTSC color, television signal, even when non
standard receiver display tube phosphor primaries
are used. The uiiique design allows independent
adjustment of demodulator conversion gains and
demodulation axes. This note describes the circuit
operation of the MC1323 and several applications
including low cost driving of unitized gun picture
tubes and obtaining R-G-B demodulated outputs.
This application note describes the use of the

MC6875 clock generator/driver in M6800 based sys
tem s: Design exam ples will d em o n strate th e
capabilities of the driver in systems using slow
and/or dynamic memories. M ultiprocessing and
DMA methods are also covered:
AN-781 Revised D ata-interface Standards

Revised data-interface standards permit faster
data rates and longer cables. New chips, and RS232
adapters, simplify their use.
AN-787 An M6800 Clock System That

Handles DMA and Memory Refresh Cycle
Stealing
Dynamic memory and three-state cycle stealing
for Direct Memory Access transfers require a clock
generator and priority logic to maintain proper re
fresh times of the dynamic MPU and dynamic
memory. The design presented here demonstrates
use of the MC6875 clock generator witli an MC6800
MPU.
ENGINEERING BULLETIN ABSTRACTS

EB-20 Multiplier/Op Amp Circuit Detects
True RMS
EB-57 An Economical FM Transmitter

Voice Processor from a Single IC
Two op amps and two multipliers are used in the

circuit described by EB-20 to obtain the true rms of
an input voltage ranging from 2 to 10 Vpk.
An MC3401 Q uad OP-A m p is used as a

Microphone/Modulation interface in an FM trans
mitter.
EB-21 DAC Key To Inexpensive 2% Digit

Voltmeter.
EB-58 Analog Data Acquisition Network

for Digital Processing Using the MC1405MC14435 A/D System
EB-21 presents an idea for the core of an econ

omical 2% digit voltmeter. Built around Motorolas
MC1408 8-bit D/A converter, the meter can measure
to 2.55 V in 10 mV steps.
EB-24A Input Buffer Circuits For The

MC1505 Dual Ramp A-To-D Converter
Subsystem
Several bipolar op amp buffers of medium-high
impedance are described in this bulletin. It also dis
cusses FET input op amp buffers providing high
impedance and temperature drift under 1 mV over
the 0C to 50C range.
EB-50 Build This Simple, Battery-Powered

3V4 Digit DVM From Standard Parts
An MC1405-MC14435 combination is used to

form a dual-slope A/D converter for analog data
acquisition.
EB-66 A Symmetry Correcting Circuit for

Use with the MC3420
EB-66 shows a method of implementing an exter
nal symmetry-correction circuit with the MC3420
Switchmode Regulator Control IC to insure bal
anced operation of the power transformer in pushpull inverter configurations.
EB-78 NEW ICs In Switching Supplies

This bulletin describes a regulated 220 Vac to 5
Vdc converter design incorporating the MC3420 and
MC3423 for the control and ancillary functions.
EB-50 describes a simple, battery-powered 3 Vi

digit D VM capable of measuring up to 20 volts that
EB-85 Full-Bridge Switching Power

Supplies
can be built from readily obtained standard parts.

Sufficient information is provided to construct the
circuit including schematic, PC board layout, parts
list and calibration instructions.
This bulletin provides selection information on

devices for a full-bridge configuration supply in the
500-1000 watt power range.
EB-51 Successive Approximation BCD A/D

Converter
EB-86 Half-Bridge Switching Power

Supplies
A successive approximation A/D converter in

which a digital-to-analog converter in a feedback
loop produces a BCD digital output from an analog
input is described in EB-51.
EB-52 Control Your Switching Regulator

With The MC3380 Astable Multivibrator
Engineering Bulletin EB-52 describes the opera
tion and characteristics of the MC3380 astable
multivibrator and details the design of a 200 volt
switching regulator circuit for gas discharge displays
using this device as the control element.

devices for a half-bridge configuration supply in the
EB-87 Flyback Switching Power Supplies

devices for a flyback configuration supply in the
EB-88 Push-Pull Switching Power Supplies

devices for a push-pull configuration supply in the
Master Index and Cross-Reference Guide

Selector Guide
Drivers/Receivers
Communication Interface (Telephony)
Voltage Comparators
Data Conversion
Voltage References
Linear 1C Selector Guides
Package Information
Application Notes and Engineering Bulletins
M O T O R O L A
&
S e m ic o n d u c to r P ro d u c ts In c.
B O X 2 0 9 1 2 P H O E N IX . A R IZ O N A 8 5 0 3 6 A S U B S ID IA R Y OF M O T O R O L A INC.

Motorola SeminarsandApplicationBooksLinearIntegratedCircuits 1979 DL

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Master Index and Cross-Reference Guide

Reliability Enhancement Programs

This Linear interface Data Book contains technical information on a portion

Motorola reserves the right to make changes to any products herein to

MDTU, MECL, MECL 10,000, MHTL, MRTL, mW MRTL,

and Cross-Reference Guide

Quad RS-422 Line with Three-State O utp u t............................................ .............................. 5-3

General-Purpose Operational A m p lifie r............................................................................. Linear

Peripheral Driver A rra y .................................................................................................................5-25

Dual Operational Amplifier ................................................................................................... Linear

10 -Bit D-to-A Converter ................ ............................................................................................ 8-49

M6800 Clock G enerator Driver

Negative Voltage Regulator (1.5 A) ................................................................................... Linear

LINEAR INTEGRATED CIRCUITS CROSS REFERENCE

. . . provides a complete interchangeability list linking over 3000

ture range. The "Motorola Functional Equivalent" column provides a

LINEAR INTEGRATED CIRCUITS CROSS REFERENCE

LINEAR INTEGRATED CIRCUITS CROSS REFERENCE

LINEAR INTEGRATED CIRCUITS CROSS REFERENCE

LINEAR INTEGRATED CIRCUITS CROSS REFERENCE

LINEAR INTEGRATED CIRCUITS CROSS REFERENCE

LINEAR INTEGRATED CIRCUITS CROSS REFERENCE

LINEAR INTEGRATED CIRCUITS CROSS REFERENCE

LINEAR INTEGRATED CIRCUITS CROSS REFERENCE

LINEAR INTEGRATED CIRCUITS CROSS REFERENCE

LINEAR INTEGRATED CIRCUITS CROSS REFERENCE

LINEAR INTEGRATED CIRCUITS CROSS REFERENCE

LINEAR INTEGRATED CIRCUITS CROSS REFERENCE

LINEAR INTEGRATED CIRCUITS CROSS REFERENCE

LINEAR INTEGRATED CIRCUITS CROSS REFERENCE

Reliability Enhancement Programs

Motorolas reliability and

SETTER PROCESSING STANDARD PRODUCT PLUS:

TEMP CYCLE. 10 CYCLES

'N M O S <Xxt Functional and tic 100% at 100*C.

BETTER AQL GUARANTEES

HIGH TEMPERATURE FUNCTIONAL

The Standard Motorola part number with the corre

The Motorola JEDEC Program

Standardization of environmental and electrical test procedures.

MIL-M-38510 JAN-Qualifled Product

Case Outline Table

DIP (1/4 x 7/8)

20-lead DIP (1/4 x 1-1/16)

18-lead DIP (.300" x 1")

Reserved for use with special non-standard case

Lead Finish Table_____

JEDEC Processed Product

Case Outline Table

DIP (1/4" x 7/8")

20-lead DIP (1/4" x 1-1/16")

Dual-in-line packages not listed above

18-lead DIP (.300" x 1")

Lead Finish Table_____

Him, Screening Procedures

For MIL-M-38510 Jan-Qualified and JEDEC Processed Product

application. Selection of a level better than

Device Class Table

Final Electrical Tests

This family of devices is designed to extend the

DATA BUS EXTENDERS

Quad, Bidirectional, with 3-State Outputs

# These devices may be

BIDIRECTIONAL BUS SWITCH