Krypton it solutions,

H no: 8-3-162/A/82,Sanjay Nagar,

Yousufguda, Hyderabad.
Ph.: +91-9676700758,9160516001
Mail:Kryptonitsolutions@gmail.com

VLSI LIST
1. Design and Implementation of an on-chip permutation network for
multiprocessor system on chip
2. All

optical

reversible

multiplexers

design

using

mech-zehunder

interferometer
3. Product code schemes for error correction in MLC NAND flash memories
4. Low power pulse triggered flip flop design based on a signal feed through
scheme
5. Implementation of high speed low power combinational and sequential
circuits using reversible logic
6. Area delay efficient binary adders in QCA
7. High performance 64 bit binary comparator
8. A low power single phase clock distribution using vlsi technology
9. A decimal/binary multi operand adder using a fast binary to decimal
converter
10. Leakage Power Reduction and Power Delay Product (PDP) Improvement
Using Dual Stack Method
11. Design and simulation of power efficient traffic light controller
12. Design of an energy efficient high speed low power full subtractor using
GDI technique
13. Area delay power efficient fixed point lms adaptive filter with low adaption
delay
14. A novel approach to realize built in self test enabled uart using vhdl

Krypton it solutions,
H no: 8-3-162/A/82,Sanjay Nagar,
Yousufguda, Hyderabad.
Ph.: +91-9676700758,9160516001
Mail:Kryptonitsolutions@gmail.com

15. Built in self test technique for diagnosis of delay faults in cluster based field
programmable gate arrays
16. Low power square and cube architectures using vedic sutras
17. Data encoding techniques for reducing energy consumption in network on
chip
18. Fast radix 10 multiplication using redundant bcd codes
19. Area delay power efficient carry select adder
20. An optimized modified booth recorder for efficient design of the add
multiply operator
21. Comments on selfchecking carry select adder design based on two rail
encoding
22. A low power high speed hybrid cmos full adder for embedded system
23. Achieving reduced area by multibit flip-flop design
24. Implementation of restartble BIST controller for fault detection in CLB of
FPGA
25. Vlsi based Robust router architecture
26. Design of High Performance 64 Bit MAC Unit
27. Design and Characterization of Parallel-Prefix Adders
28. Shift Register Design Using Two Bit Flip-Flop
29. Multi operand redundant adders on fpga
30. Pipelined architecture for Vedic multiplier
31. Optimal Built-In Self Repair Analyzer for Word-Oriented Memories
32. Design of High Performance 64 Bit MAC Unit

Krypton it solutions,
H no: 8-3-162/A/82,Sanjay Nagar,
Yousufguda, Hyderabad.
Ph.: +91-9676700758,9160516001
Mail:Kryptonitsolutions@gmail.com

33. Shift Register Design Using Two Bit Flip-Flop

34. Vlsi based Robust router architecture
35. Design and Characterization of Parallel-Prefix Adders
36. Achieving reduced area by multibit flip-flop design
37. Area delay power efficient carry select adder
38. A novel approach to realize built in self test enabled uart using vhdl
39. Implementation of high speed low power combinational and sequential
circuits using reversible logic