2016

WORKBOOK
Detailed Explanations of

Try Yourself Questions

Instrumentation Engineering
Digital Electronics

1
Find the value of x.
(135)x + (144)8 = (214)x + 2

[x = 7]
T2.

Write gray code for binary numbers from 0000

to 1111.

T3.

In a particular number system the cubic equation

x3 + bx2 + cx 190 = 0
has roots x = 5, x = 8, and x = 9.Find the base
of number system.
[15]

T4.

Consider the addition of numbers with different

bases
(X)7 + (Y)8 + (W)10 + (Z )5 = (K)9
If X = 36, Y = 67, W = 98 and K = 241 then find
the value of Z.
[34]

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T1.

Number Systems and Codes

T5.

Consider a System S as shown in the figure

below

I0
I1
I2
I3

System S
1s
compliment

Y0
Y1
Y2

2s
compliment

Y3

System S performs 1s compliment of the input

and then 2s compliment to produce output.
A new System H is designed in which 3 System

S are cascaded
System H
O0

I0
I1
I2
I3

System
S

System
S

System
S

O1
O2

Output

O3

If the applied input (I3 I2 I1 I0) is 1010, then what

is the output (O3 O2O1 O0).
[1101]

Copyright

Find minimum number of two input NAND

gates needed to implement the boolean
function f (A,B,C, D) = ABCD .
[7]

T2.

T3.

T4.

A bank has 3 locks with 1 key for each lock.

Each key is owned by a different person. In order
to open the vault atleast two people must insert
their keys into the assigned locks. All the keys
are not inserted at the same time. If the system
is to be designed with only two input NAND
gates, then find the number of NAND gates
required.
[6]
A Boolean expression containing 3 variable is
true only if any of the following conditions is
satisfied.
1. A is true and either B is true or C is false.
2. A is false and B is true
3. C is true and either A is true or B is false
Find the minimized Boolean expression.
[A + B + C]
A car alarm system is to be designed
considering 4 inputs, door closed (D), key in
(K), seat pressure (S) and seat belt closed (B).
The alarm (A) should sound if
1. the key is in and door is not closed or
2. the door is closed, the key is in, driver in
the seat and seat belt is not closed.
The system is to be designed with 2 input basic

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T1.

Boolean Algebra and Logic Gates

gates and inputs are available in basic form only.

Find the number of gates required.
[6]
If the waveforms A, B, C shown in figure below
are applied to the Ex-NOR gates. Find the
frequency of output.

T5.

A
B
C

C
1 s

[125 kHz]

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Combinational Logic Circuits

Design 4 2 priority encoder using basic gates

only.

T2.

Design 4 1 multiplex using only 2 input NAND

gates.

T3.

Design a logic circuit for detecting equality of

2-bit binary numbers.

T4.

Design a combination circuit that accepts a 2

bit number as input and generate binary number
equal to square of the input number.

T5.

Consider the logic circuit given below:

I 0
I1

I0
I1
MUX
16 1

I13

I15

De MUX
1 16

S3

S2

S1

S0

S3

B B

S2

In

S1

S0

I15

Input at line I13 in 16 1 Mux corresponds to

output at line n of 1 16 De Mux. Find the
value of n.
[n = 7]

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T1.

Copyright

4
Reduce the following state diagram and also
write the reduced state table.
0/0
0/0

0/0

1/0
0/0

0/0

b
1/0

1/1

c
1/0
0/0

1/1
1/1
f

0/0

1/1

[20 marks : 2013]

T2.

T3.

Draw finite state machine model for S R ,

J K , D and T flip-flops.
Consider the circuit given below.
LSB
I1

BCD
Clock

Up
Counter

I0
MSB

Y3
2x4
Decoder

Y2
Y1
Y0

Find the duty cycle of Y2 .

[30%]

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T1.

Sequential Circuits

T4.

Consider the circuit given below

C2

C1

A1
A0

MSB

A>B

MOD 10
Ripple Up
Clock

A3
A2

MOD 10
Ripple
Down
Counter

Counter

Comp-arator

LSB

C3

A=B
A<B

MOD 10
Ripple
Up
Counter

B3
B2
B1
B0

MSB and LSB of MOD 10 ripple up counter acts

as clock to 4 bit ripple down and up counter
respectively.
Initially all the counter were cleared and output
of comparator was A = B. The clock pulse is
applied. Find the minimum number of clock
pulses required to make A = B again.
[17]
T5.

Consider the circuit given below

C1

MSB

4 bit Ripple
Up Counter

Clk
LSB
C2

MSB

b
g

e e
f

4 bit Ripple
Down Counter

7 segment
display
c

LSB
Enable

If Enable = 0 ; 7 segment display 11 (b = c = e

= f = 1)

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Instrumentation Engineering Digital Electronics

Enable = 1 ; 7 segment display data according
to Inputs
Initially both the counter were cleared. After 78
clock pulses find the data displayed on the 7
segment display.
[11]

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Memories

T1.

Consider the ROM shown below

(MSB)
X3

X2

BCD

to

X1

X0

Decimal decoder

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
Y3 (MSB)
Y2
Y1
Y0

If the coding scheme for X3 X2 X1 X0 is BCD then

find coding scheme for Y3 Y2 Y1 Y0 .
T2.

Consider the digital circuit given below.

D0

X
X

A0

D1
D2

3:8
A1 Decoder

D3
D4
D5

A2

D6
D7

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Find the simplified expression for D4 output

of decoder.
[0]

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6
Consider the circuit given below.
Vdd

Y
E

B
D

Find the Boolean expression for Y .

[ABC + ADF + (E + G) F ]

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T1.

Integrated-Circuit Logic
Families

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7
With a neat block diagram, explain the operation
of 8-bit successive approximation ADC. What
is the maximum conversion time for this type of
ADC?
[10 marks : 2004]
T2.

Consider the circuit given below.

MSB

MSB

Gray
Code
Converter

Input 6 bits
LSB

Digital to
Analog
Converter

Va

LSB

The full scale reading of Digital to Analog

converter is 10.5 V. Each bit of Gray code
converter output is given to digital to analog
converter through an invertor. If input to the
circuit is 110011, then corresponding output
voltage Va is _____ Volts.
[3.45 V]
T3.

Consider the system shown in figure below.

V1

V2

Ideal op-amp
3 bit
Synchronous
Up Counter

Clock

LSB Y
0
Y1 Output
Y
MSB 2

If V1(t) = 2sin(0.1 t) + 1
V2(t) = 4sin(0.1 t)
Clock

t sec

The output of ideal opamp and clock act as input

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Copyright: Subject matter to MADE EASY Publications, New Delhi. No part of this book may be reproduced or utilised in any form without the written permission.

T1.

ADC and DAC

to AND gate. If counter is positive edge

triggered. If the output of the counter was
cleared at t = 0, then output (Y2 Y1 Y0 ) of the
system at t = 10 sec is _______.
[100]
T4.

Consider the system given below

MSB
3 bit
up
counter

MSB

I12
LSB
MSB

0
4 Bit
Clock

LSB

4 bit
up
counter

MSB

3 bit
down
counter

I21
I10
I9

14 bit
DAC

I8
LSB

Ring 2
Counter
3

I13

MSB

I7
Step Size
I6 = 1 mV

Output

I5
LSB
MSB

4 bit
down
counter

I4
I3
I2
I1

LSB

I0
LSB

The clock input is connected to the 4 bit ring

counter. The output of the ring counter acts as
the clock for the other counters. All the counters
shown in figure are positive edge triggered.
The output of all counters act as input to a 14
bit DAC with step size (D) equal to 1 V. If initially
all counter are cleared then find the output of
DAC after 20 clock pulses.
[10.96 V]

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Instrumentation Engineering Digital Electronics

10

EXPLANATIONS
CHAPTER1
T1.

(x = 7)
Converting into decimal number system
x2 + 3x + 5 + 82 + 4 8 + 4 = 2(x+2)2 + x + 2 + 4
x2 + 3x + 105 = 2x2 + 8 + 8x + x + 6
x2 + 5x 91 = 0
(x + 13) (x 7) = 0
x = 13, 7
base cant be negative
x=7

T2.
Binary No.
0000
0001
0010
0011
0100
0101
0111
1000
1010
1011
1100
1101
1110
1111
T3.

Gray Code.
0000
0001
0011
0010
0110
0111
0100
1100
1101
1110
1010
1011
1001
1000

(15)
5 8 9 = (360)10 = (190)8
360 = B2 + 9 B
B = 23, 15
Base cant be negative. So B = 15.

T4. (34)

(36)7
(67)8
(98)10
(Z)5
(241)9
(Z)5
(Z)5

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=
=
=
=
=
=
=

(27)10
(55)10
(98)10
(Z)5
(199)10
(199)10 (27)10 (55)10 (98)10
(19)10

= 34

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Electronics Engineering
T5.

(1101)
Let a number N is given to the system
output after 1s compliment = 15 N
output after 2s compliment = 16 15 + N = N + 1
3 such systems are connected in cascade.
so final output = Input + (3)10 = 1010 + 0011
= 1101

T1.

(7)

11

CHAPTER2

A
B

C
D

Minimum NAND Gates required are 7.

T2.

(6)
Let the 3 locks are A, B, C
0 - key not inserted
1 - key inserted

A
0
0
0
0
1
1

B
0
0
1
1
0
0

C
0
1
0
1
0
1

Y
0
0
0
1
0
1

1
1

1
1

0
1

1
X

BC
A 00 01 11 10
0
1
1

Y = AB + BC + AC

The expression for Y is similar to carry in full adder circuit.

So, Number of NAND Gates required are = 6.
T3.

(A + B + C)
1. A.(B + C )
2. AB
3. C ( A + B )
Expression = AB + AC + AB + AC + CB

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Instrumentation Engineering Digital Electronics

12

= A + B + BC = A + B + C
T4

(a)

A = KD + KDSB
A = KD + KSB
K
D

S
B

T5

(125)
A

C
1 s

8 s

Frequency of output =

1
= 125 kHz
8 s
CHAPTER3

T1.
I3
0
0
0
1

I2
0
0
1
x

I1
0
1
x
x

I0
1
x
x
x

Y1
0
0
1
1

Y0
0
1
0
1

Y1 = I 3 I 2 + I 3 = I3 + I2
Y0 = I 3 I 2 I 1 + I 3 = I 3 + I 1I 2

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Electronics Engineering

13

I0
I1
Y0

I2
Y1
I3
4 2 Priority Encoder

T2.

I0

I1

I2

I3

S1

S0

T3.

A1
0
0
1
1

A0
0
1
0
1

B1
0
0
1
1

B0
0
1
0
1

Y
1
1
1
1

Y = A1A 0B1B 0 + A1A 0B1B 0 + A1A 0B1B 0 + A1A 0B1B 0

= A1B1(A 0B 0 + A 0B 0 ) + A1B1(A 0B 0 + A0B 0 )
= (A1B1 + A1B1) + (A 0B 0 + A 0B 0 )
=

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( A1 e B1) ( A0 e B0 )

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Instrumentation Engineering Digital Electronics

14

A1
B1

A0
B0

T4.
Y3

X1

Y2

Combinational
Circuit

Y1

X0

Y0

X1
0
0
1
1

X0
0
1
0
1

Y = x0

Y3
0
0
0
1
Y1 = 0

Y2
0
0
1
0

Y1
0
0
0
0

Y0
0
1
0
1

Y2 = x1x 0

Y3 = x1x0

Y3
Y2

x1

Y1
x0
Y0

T5.

(7)
I 0
I1

I0
I1
MUX
16 1

I13

I15

S3

S2

S1

De MUX
1 16

S0

S3
A

S2
B

In

S1
C

S0

I15

D
A

B B

I13 A B C D
1 1 0 1
A = A B = 1 1 = 0
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Electronics Engineering

15

B = B D = 1 1 = 1
C = D = D = 1
D = CA = 0.1 = 1
In A B C D
0 1 1 1
( A B C D ) = 7
n = 7

CHAPTER4
T1.
0/0
a
0/0

1/0
0/0
1/0
g

1/0

0/0

0/0

c
1/0
0/0

1/1
1/1
0/0

f
1/1

Considering the input sequence 01010110100 starting from the initial state a. Each input of 0 or 1 produces
an output of 0 or 1 and causes the circuit to go the next state. From the state diagram, we obtain the output
and state sequence for the given input sequence as follows. With the circuit in initial state a, an input of 0
produces an output of 0 and circuit remains in state a. With present state at a and input of 1 and the output
is 0 and the next state is b. With present state b and an input of 0, the output is 0 and the next state is c.
Continuing this process, we find the complete sequence to be as follows:
State

a a b c d e f

g a

Input

0 1 0 1 0 1 1 0 1 0 0

Output 0 0 0 0 0 1 1 0 1 0 0

In each column, we have the present state, input value and output value. The next state is written on top of
the next column.

We now proceed to reduce the number of states. Two states are said to be equivalent if, for each
member of the set of inputs, they give exactly the same output and send the circuit either to the same
state or to an equivalent state. When two states are equivalent one of them can be removed
without altering the input-output relationship.

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Instrumentation Engineering Digital Electronics

16

State T
able:
Table:

Present state

Next state
Output
x =1 x = 0 x = 1
a
b
0
0
c
d
0
0
a
d
0
0
e
f
0
1
a
f
0
1
g
f
0
1
a
f
0
1

x=0

a
b
c
d
e
f
g

Now apply the statement written above under inverted comma, we look for two present states that go
to the same next state and have the same output for both input combinations. Such states are g and e.
They both go to states a and f and have outputs of 0 and 1, for x = 0 and x = 1 respectively. Therefore
states g and e are equivalent, and one of these states can be removed. The row with present state g
is removed, and state g is replaced by state e.

Reducing State T
able:
Table:

Present state
a
b
c
d
e
f

Next state
Output
x = 0 x =1 x =0 x = 1
a
b
0
0
c
d
0
0
a
d
0
0
e
f
0
1
a
f
0
1
e
f
0
1

Present state f now has next states e and f and outputs 0 and 1 for x = 0 and x = 1, respectively. The
same next states and outputs appear in the row with present state d. Therefore states f and d are
equivalent, and state f can be removed and replaced by d. The final reduced table is shown below:

Reduced State T
able:
Table:

Present state
a
b
c
d
e

Next state
Output
x = 0 x =1 x = 0 x = 1
a
b
0
0
c
d
0
0
a
d
0
0
e
d
0
1
a
d
0
1

The state diagram for the reduced table consists of only five states. This state diagram satisfies the
original input-output specifications and will produce the required output sequence for any given input
sequence.
State

a a b c d e d d e d e a

Input

0 1 0 1 0 1 1 0 1 0 0

Output 0 0 0 0 0 1 1 0 1 0 0

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Electronics Engineering

17

Reduced state diagram:

0/0
a
0/0

0/0

b
1/1

0/0

1/0

1/0

0/0

1/0

d
1/1

T2.
(i) SR flip - flop
S=1
S=0
R=X

R=1

S=0

R=1

J=1

K=X

S=X
R=0

(ii)J- K flip - flop

J=0
K=X

J=X

J=X
K=0

K=1

(iii) D flip - flop

D=1
D=1

D=0
0

D=0

(iv) T flip - flop

T=1
T=0

T=0
0

T=1

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Instrumentation Engineering Digital Electronics

18
T3.

(30%)
Output of counter
D3 D2 D1 D1

I1

I0

Y2

0
0

0
0

0
0

0
1

0
1

1
1

0
0

Duty cycle =
T4.

3
100 = 30%
10

(17)
All the counters are positive edge triggered. In 10 clock pulses MSB of counter C1 goes from low to high
once. LSB of counter C1 goes from low to high 5 times.
Output of C1

C2

C3

After 17 clock pulse

Count of C2 = 9
Count of C3 = 9
Minimum 17 clock pulses are required to make A = B high again.
T5.

(11)
After 78 clock pulse
Output of counter C1 = (1110)2 = (14)10
Output of counter C2 = (0010)2 = (2)10
7 segment display
a b c d e f g
Enable
1 1 1 0 0 0 1
0

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Electronics Engineering

19

g
e

Data displayed on 7 segment is 11

CHAPTER5
T1.
X3

X2

X1 X 0

Y3

Y2

Y1 Y0

Clearly Y3 Y2 Y1 Y0 is a 2421 code.

T2.

A2 = XZ XY = X(Z Y)
A1 = YZ XZ = Z (X Y)
A0 = XY YZ = Y(X Z)

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20

Instrumentation Engineering Digital Electronics

D4 = A2 A1 A0
YZ
X

= f2(X, Y, Z) = (5, 6)

A2 =
1

YZ
X
1

= f1 (X, Y, Z) = (0, 1, 2, 4, 6, 7)

A1 =

YZ
X

= f0 (X, Y, Z) = (0, 1, 2, 4, 5, 7)

A0 =

D4 = A2 A1 A0 = f2 f1 f0 = 0
CHAPTER6
T1.

(d)
Drawing switch equivalent
Y

B
F
C

From this Y is

Y = [ADF + ABC + (E + G) DBC + (E + G) F ]

Y = [ADF + ABC + (E + G) (DBC + F )]

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Electronics Engineering

21

CHAPTER7
T1.

Input analog
voltage Vin

Comparator
V0

D7
MSB

V DAC

SOC

Control
D0
LSB

Successive
Approximation
Register (SAR)
Or UP-DOWN
CK
synchronous counter

8-bit
DAC
ladder
type

D0

D7

CK

EOC

TC

CL

Buffer
register
D7

D0

SOC

Start of Conversion

EOC

End of Conversion

Digital output

The operation of successive approximation A/D converter is as follow:

(i) The SOC goes low, counter is cleared and the digital output is 0000 0000.
(ii) At the same time the input analog voltage is applied such that V0 goes high and the EOC signal goes
high and the conversion starts.
(iii) During the first clock pulse, the control circuit loads a high MSB into the SAR whose output is then
1000 0000.
(iv) If Vin > VDAC, the positive output of the comparator indicates that the MSB is to remain set.
(v) If Vin < VDAC, the negative output of the comparator signals the control circuit to reset the MSB.
(vi) The next lower bits are then handled in the same way. This process is continued until the SAR tries all
the bits.
(vii) When the conversion is complete, the control circuit sends a low EOC signal.
(viii) At the falling edge of the EOC signal the digital equivalent is loaded into the buffer register.
(ix) Thus the buffer register contains the digital output.
So the conversion speed of successive approximation A/D converter is slower than that of parallel A/
D converter but faster than that of dual slope A/D converter.
The maximum conversion time for this type of ADC is nTC where n is the number of bits and TC is the time
period of one clock pulse.

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Instrumentation Engineering Digital Electronics

22
T2.

(3.45)
Input
110011
Gray code
101010
Input to Digital to Analog converter 010101 = 21
10.5
Analog voltage =
21 = 3.45 V
26

T3.

(100)
v2(t)
v1(t)
t1

t2
10

At t1 and t2

20

v1(t) = v2(t)
2 sin(0.1 t ) + 1 = 4 sin(0.1 t )
t =

5 25
,
, .......
3 3

t1 =

5
sec
3

t2 =

25
sec
3
Logic 0

Output of op-amp

Vsat

Logic 0
5
3

25 10
3

20

10

20

(sec)

(sec)

(sec)

Clock

Output of AND gate = Clock to the counter

The clocks applied to the synchronous up counter are 4.

Output of counter is 100.
T4.

(10.94)
In 4 clock pulses each output of ring counter is complemented once.
So in 20 clock pulses each output is complemented 5 times.
output of every counter connected at input of DAC will change 5 times
So Input to 14 bit DAC is

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Electronics Engineering
I13 I12 I11 I10 I9 I8
1 0 1 0 1 0
Binary equivalent
Analog output voltage

23

I7 I6 I5 I4 I3 I2 I1 I0
1 0 1 1 1 0 1 1
= 10939
= Step size Binary equivalent
= 1 103 10939
= 10.94 Volts

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