Optimization of CMOS Based Analog Circuit Using Particle Swarm Optimization Algorithm

IPASJ International Journal of Electronics & Communication (IIJEC)
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ISSN 2321-5984
A Publisher for Research Motivation........
Volume 3, Issue 8, August 2015
Optimization of CMOS based Analog Circuit

Using Particle Swarm Optimization Algorithm
Pankaj P. Prajapati1, Dr. Mihir V. Shah2
1
Gujarat Technology University, Ahmedabad
Gujarat Technology University, Ahmedabad
ABSTRACT
We know that the world is basically analog in nature so that design of CMOS analog circuits are very significant in electronic
system design. Day by day design complexity of electronic circuit is increased. So that the optimization procedures should be
automatic using great precision. The key problems concern with electronic design automation are robustness and cost. Usually,
optimization is a very exciting and time consuming task with many conflicting benchmarks and a wide range of design
parameters. In this graft Particle swarm optimization (PSO) is presented as an effective process to explore the search space and
to handle constrained optimization difficulties. Effectiveness of PSO algorithm is tested with some standard benchmark
function. PSO algorithm has been used for the optimum design of CMOS analog circuits with high optimization skill in small
computational time. Parameters values obtained from PSO algorithm are verified using spice circuit simulator. In this work, C
code of PSO algorithm has been interfaced with Ngspice circuit simulator for circuit optimization. In this effort different
CMOS based analog circuits like CMOS triple cascode current mirror, CMOS voltage divider, CMOS cascode amplifier and
CMOS differential amplifier with current mirror load are optimized using different CMOS technologies.
Keywords: Optimization, Automation, PSO, Ngspice.
1. INTRODUCTION
Design of CMOS analog circuits is a challenging method which contains the representation of complex compromises
between nonlinear objectives and also sustaining required limitations. Those objectives are involved of design
parameters which are ideally accepted as variables and optimum solution set is searched. Though, as the circuit
complication increases the search space enlarges such that obtaining the optimal combination of design parameters by
hand becomes a time consuming and unaffordable process. Considering CMOS analog circuits design process, there are
some relationships that should be maintained between length, width and width/length ratios of MOS transistors to
guarantee that the search space is smooth and the optimization process is reliable. Therefore, efficient optimization
methods are required for automation of optimal sizing of CMOS analog IC design. Optimization of an electronic
circuits is a method used to select the circuit design parameter values in such a way that the actual circuit performances
meet the design requirements (the values of circuit performances imposed by design specifications). There are various
optimization techniques have been reported in the past and the recent times for automatic design of analog circuits.
The gradient-based optimization methods [1] would generally give locally optimum solution. Convex optimization
techniques [2] require a very good knowledge of circuit design to find globally optimum solution, which would be very
difficult looking at the current state-of-the-art MOSFET models. The evolutionary algorithms [4] can be used to solve
multimodal optimization problems to discover the solution space more powerfully. These algorithms do not suffer from
difficulties associated with the gradient-based and convex optimization methods. These algorithms do not require
knowledge of circuit design and physical models. These algorithms also do not need to calculate complex mathematical
calculation even though they give global optimum solution. Holland has developed genetic algorithm (GA) [5] with an
inspiration from biological evolution, has been reported several times for automatic analog circuit design. Few recent
citations are also found in [4], [6]. Kennedy and Eberhart had proposed particle swarm optimization (PSO) algorithm
[7], [8]. They had been observed to give better accuracy compared to GA in most of the applications [9]. In this work
we present a simulation based approach to optimize some basic CMOS based Analog circuits using PSO algorithm.
This algorithm has been implemented in C language. Hence, a proper interface between GCC compiler and Ngspice
circuit simulator has been established. This paper is arranged as follows: in Section II, the PSO algorithm is described.
Effectiveness of PSO with some standard benchmark functions is represented in Section III. In Section IV, the method
of optimizing some basic CMOS based analog circuits using PSO is presented. In section V conclusions are given.
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2. PARTICLE SWARM OPTIMIZATION
Particle swarm optimization algorithm was first presented through Kennedy and Ebehart [7]. It is an evolutionary
computation technique founded on the social behavior and movement of swarm searching for the optimum and finest
location in a multidimensional search space. It is robust algorithm to solve continues nonlinear optimization
complications [8]. This algorithm mimics the behavior of birds flocking in search of food. The PSO algorithm depends
on community conduct of elements in the group. So it will find the global best result by just regulating the trajectory of
each individual toward its own best location and toward the best particle of the entire swarm at each time step
(generation). PSO has the advantage of being very simple in concept, easy to implement and computationally efficient
algorithm. Since updates in algorithm consist of simple adding and multiplication operators and no derivation
operation is included, computation time is dramatically decreased compared to other heuristic algorithms. In order to
avoid premature convergence, PSO utilizes a distinctive feature of controlling a balance between global and local
exploration of the search space which prevents from being stacked to local minima. The pseudo code for PSO algorithm
is given below [9], [13].
For each particle
Initialize particle
End
Do
For each particle
Calculate fitness value
If the fitness value is better than its personal best set current value as the new pbest
End
Choose the particle with the best fitness value of all as gbest
For each particle
Calculate particle velocity according equation (3)
Update particle position according equation (2)
End
While maximum iterations or minimum error criteria is not attained
In particle population matrix, containing N number of particles, i th particle with a feature number of D is denoted as xi
= [xi1, xi2,. . .,xiD]. For each iteration, the velocity and the position vector of the ith particle in N x D dimension of the
search space are updated as follows [9], [13]:
vidk+1 = v idk + c1 * rand1 ( ) * (pbest idk - x idk + c2 * rand2 ( ) * (gbest dk - x idk )
xidk+ = x idk + vidk+
(1)
(2)
Here, the range of i, d and k indices are defined as {1. . .N}, {1. . .D} and {1. . .max iteration number} respectively.
The acceleration factors c1 and c2 indicate the relative attraction toward pbest and gbest respectively. Following rand1
and rand2 are random numbers uniformly distributed between zero and one. To balance global optimum and local
optimum solution equation (a) is modified [10], [11] as,
vidk+1= w * v idk + c1 * rand1 ( ) * (pbest idk - x idk + c2 * rand2 ( ) * (gbest dk - x idk )
(3)
Here inertia weight, parameter w controls the tradeoff between the global and the local search capabilities of the swarm.
Initially w should be selected less than one and should be decreased linearly in each iteration. The success of the PSO
algorithm in finding the global optimum depends extremely on the initial values of the control parameters (c1, c2, w) of
the PSO algorithm, the size of swarm value, and the maximum iteration number. In the tests made in this paper,
number of particles = 30, c1 = 1.47, c2 = 1.47 and w varies from 0.9 to 0.4 linearly with iterations [11], [14].
3. TESTING OF PSO WITH STANDARD BENCHMARK FUNCTION

There are number of benchmark functions are used to test performance of optimization algorithms. Main commonly
used benchmark functions are listed in table 1 [12], [13]. Initialization and optimum solution of benchmark functions
are listed in table 2 [12], [13].
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Table 1: Standard benchmark functions

Function
Type
Global optimum
solution
Type
Sphere
Minimize
Origin
Unimodal
Rosenbrock
Minimize
[1,1,1,1,1,1]n
Unimodal
Rastrigin
Minimize
Origin
Multimodal
Griewank
Minimize
Origin
Multimodal
Ackley
Minimize
Origin
Multimodal
Schaffer
Maximize
Origin
Multimodal
Table 2: Initialization and optimum solution of benchmark functions

Function
Sphere
Rosenbrock
Rastrigin
Dimension
s (n)
Initialization
Range
30
(50, 100)n
30
(50, 30)
n
n
30
(2.56, 5.12)
Griewank
30
(300, 600)
Ackley
30
(15, 32)n
Schaffer
(15, 30)
Search Space
Goal
f0
(-100, 100)n
10-6
(-100, 100)n
10-6
(-10, 10)
(-600, 600)
10-6
n
(-32, 32)n
(-100, 100)
10-6
10-6
Plot of error function with number of iterations for Sphere, Rosenbrock, Rastrigin, Greinwank functions are shown in
figure 1 (a), (b), (c), (d), respectively.
(a) Sphere funciton ( No of Iterations = 371)
(c)
(b) Rosenbrock function (No of Iterations = 401)
Rastrigin (No of Iterations = 9830)

(d) Griewank (No of Iterations = 4575)
Figure 1 Plot of Error Function Vs Number of Iterations
Plot of error function with number of iterations for Ackley and Schaffer functions are shown in figure 2 (a), and figure
2 (b) respectively.
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(a) Ackley function (No of Iterations = 8172)

ISSN 2321-5984
(b) Schaffer (No of Iterations = 296)
Figure 2 Plot of Error Function Vs Number of Iterations
4. CMOS ANALOG CIRCUIT DESIGN USING PSO

The test setup for automatic CMOS analog circuit design is shown in figure 3. There are different 12 files are used to
optimize CMOS analog circuit design. The optimizer developed using PSO algorithm is tested for CMOS triple cascode
current mirror, CMOS voltage divider, CMOS cascode amplifier and CMOS differential amplifier with current mirror
load. Here we can find the value of w for NMOS and PMOS without knowledge of their basic equation.
Figure 3 Test Setup for Automatic Circuit Design

The circuit diagram for CMOS triple cascode current mirror is shown in figure 4. Desired and obtained specifications
and parameters with help of developed optimizer are listed in table 3. For this circuit 100 iterations are performed in
158 s and gives 0.000469 error function.
Figure 4 CMOS Triple Cascode Current Mirror [17]
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Table 3: Desired and obtained Specifications and Parameters for Triple Cascode Current Mirror
Sr.
No.
1
2
Desired
Specifications
Iref = 10 uA
Iout = 10 uA
Parameters
Range
w1 = 1 um to 1000
um = 1 k to 1000
R1
Obtained
Parameters
w1 = 384.761187
um = 91.632083
R1
k
Obtained
Specifications
Iref = 9.996649 uA
Iout = 9.996947 uA
The circuit diagram for CMOS voltage divider is shown in figure 5. Desired and obtained specifications and parameters
with help of developed optimizer are listed in table 4. For this circuit 100 iterations are performed in 216 s and gives
0.000003 error function. This indicates as numbers of dimension is increased in PSO algorithm, optimization problem
becomes complex and consumes more time to optimize the problem.
Figure 5 CMOS Voltage Divider [17]
Table 4: Desired and obtained Specifications for CMOS voltage divider

Sr.
No.
1
2
3
4
Desired
Specifications
Vbias1 = 0.8 V
Vbias2 = 1.2 V
Vbias3 = 1.7 V
Parameters
Obtained
Obtained
range
Parameters
Specifications
w1 = 0.1 um to 1000
w1 = 0.159062 um
Vbias1 = 0.7999781 V
um
umum
w2= 0.1 um to 1000 um w2 = 358.347945 um Vbias2 = 1.200003 V
w3 = 0.1 um to 1000
w3 = 2.504302 um
Vbias3 = 1.699968 V
um = 0.1 um to 1000
w4
w4 = 36.398769 um
um
The circuit diagram for CMOS Cascode amplifier is shown in figure 6 (a). Desired and obtained specifications with
CMOS 180 nm and 90 nm technology with help of developed optimizer are listed in table 5. Simulation results of
frequency response, voltage transfer characteristics (VTC) and input/output wave form for the same circuit are shown
in figure 6 (b), figure 7(a) and figure 7(b) respectively. Obtained parameters for the same circuit using CMOS 180 nm
and 90 nm technology are listed in table 6.
Sr.
No.
1
2
3
4
5
6
Table 5: Desired and obtained Specifications for Cascode Amplifier

Obtained
Obtained
Desired Specifications
Outcomes (180 nm) Outcomes (90 nm)
Vout (max) = 1.8 V
1.799 V
1.799 V
Vout (min) = 0 V
0.051 V
0.050 V
AV > 20 dB
27.21 dB
20.51 dB
UGB > 10 MHz
26.77 MHz
23.21 MHz
Pdiss < 1 mW
0.334 mW
0.329 mW
Slew rate > 10 V/us
16.26 V/us (+Ve)
16.74 V/us (+Ve)
25.64 V/us (-Ve)
29.83V/us (-Ve)
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Figure 6 (a) Circuit of Cascode CMOS Amplifier [17] (b) Frequency Response of Cascode CMOS Amplifier
Figure 7 (a) VTC of Cascode CMOS Amplifier (b) I/O waveform Cascode CMOS Amplifier
Table 6: Obtained Parameters for Cascode Amplifier
Obtained
Obtained
Sr.
Design Parameters
Parameter
Parameters
No.
Rang
s (180 nm)
(90 nm)
1
W1 = 1 to 100 um
54.11 um
34.86 um
2
W2 = 1 to 100 um
56.15 um
97.06 um
3
W3 = W4 = 1 to 100 um 18.79 um
12.45 um
4
W5 = 1 to 100 um
16.43 um
27.62 um
5
Cload = 1 to 100 pF
14.83 pF
58.86 pF
The circuit diagram for CMOS differential amplifier with current mirror load is shown in figure 8. Desired and
obtained specifications with CMOS 180 nm and 90 nm technology with help of developed optimizer are listed in table
7. Simulation results of VTC and input/output wave form for the same circuit are shown in figure 9 (a) and figure 9 (b).
Simulation results of frequency response and CMRR are shown in figure 10(a) and figure 10(b) respectively. Obtained
parameters for the same circuit using CMOS 180 nm and 90 nm technology are listed in table 8.
Sr.
No.
1
2
3
4
5
6
7
8
Table 7: Desired and obtained Specifications for Differential Amplifier with Current Mirror Load
Obtained
Obtained
Results
Desired Specifications
Outcomes (180 nm)
Outcomes (90 nm)
(0.35 um) [11]
Vos < 50 mV
-36 mV
-66 mV
45.91 mV
AV > 25 dB
29.11 dB
20.77 dB
42 dB
UGB > 10 MHz
62.00 MHz
46.50 MHz
12.3 MHz
Phase Margin > 45
90.20
93.57
83.8
Slew rate > 10 V/us
49.06 V/us (+ve)
38.25 V/us (+ve)
---38.94 V/us (-ve)
25.18 V/us (-ve)
22.4 V/us
CMRR > 40 dB
46.47 dB
52.18 dB
84.2 dB
Pdiss < 1 mW
0.408 mW
0.247 mW
1.2 mW
Total Transistor Area < 300
46.43 um2
33.62 um2
296 um2
2
um
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Figure 8 CMOS Differential Amplifier with Current Mirror Load [17]
Figure 9 (a) VTC of CMOS Differential Amplifier
(b) I/O wave for CMOS Differential Amplifier
Figure 10 (a) Frequency response of CMOS Differential Amplifier (b) CMRR of CMOS Differential Amplifier
Sr.
No.
1
2
3
4
Table 8: Obtained Parameters for Cascode Amplifier

Design Parameters
Obtained
Obtained
Obtained
Rang
Parameters (180 nm) Parameters (90 nm)
Parameters (0.35 um) [11]
W1 = W2 = 1 to 100 um
54.11 um
41.11 um
W1/L1 = 29.4 /3.5
W3 =W4 = 1 to 100 um
56.15 um
10.78 um
W3/L3 = 11.3/3.5
W5 = W6 =1 to 100 um
18.79 um
41.45 um
W1/L1 = 4.2 /1.4
Cload = 1 to 100 pF
14.83 pF
77.50 pF
5 pF
5. CONCLUSION
PSO algorithm is tested to design different analog circuits like CMOS triple cascode current mirror, CMOS voltage
divider, CMOS cascode amplifier, CMOS differential amplifier with current mirror load and using 180 nm and 90 nm
CMOS technology. PSO based results satisfy almost all design specifications As number of desired specifications of a
circuit increase, optimization problem becomes more complex and takes more time to design a given circuit. It is easy
and efficient to design an analog circuit using optimization procedure compared to using manual design even though
designer has not detailed knowledge of a given circuit. This methodology can also be applied to optimize other circuit
and can be inserted into any electronic computer aided design software.
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References
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AUTHOR
Pankaj Prajapati received the B.E. degree in Electronics and Communication Engineering from
L.D. College of Engineering and M.Tech. degree in Electronics and Communication Engineering
with specialization of VLSI Design Institute of Technology, Nirama University in 2001 and 2009,
respectively. He has completed his dissertation work at ISRO during M.Tech. He has total 13 years
teaching experiences at various colleges. He is currently working as an assistant professor at L.D.
College of Engineering since June 2011. He is currently pursuing PhD in Gujarat Technological
University.
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IPASJ International Journal of Electronics & Communication (IIJEC)

Web Site: http://www.ipasj.org/IIJEC/IIJEC.htm

A Publisher for Research Motivation........

Volume 3, Issue 8, August 2015