Development of FPGA Based Smart Controller For Speed Control of BLDC Motor

IPASJ International Journal of Electrical Engineering (IIJEE)
Web Site: http://www.ipasj.org/IIJEE/IIJEE.htm

Email: editoriijee@ipasj.org
ISSN 2321-600X
A Publisher for Research Motivation........
Volume 3, Issue 8, August 2015
Development of FPGA based smart controller

for speed control of BLDC Motor
KanhuCharan Patra , Priyabrata Nayak , Pradeep Kumar
Department of Electrical engineering, NIT Calicut, Kerala, India
ABSTRACT
This paper presents a FPGA based controller for BLDC motor. The controller is utilized to control the speed of machine under
different loading conditions and variation of various performance like power factor, efficiency, output power of the machine.
Recent development in power electronics area made the BLDC motor an attractive choice for high speed applications. FPGA
has the ability to process several process in parallel. The use of pulse width modulation in power electronics the ease way of
generating PWM using Hardware Description language and implementing in FPGA board. The implementation for PWM
generation using FPGA for speed control under different loading conditions is economic and reliable as compared to other
devices. The proposed method for control the speed can be realized in hardware.
Keywords:- Hall sensors, BLDC motor, smart controller. FPGA
1. INTRODUCTION
Brushless DC motors drives have gained widespread use in electrical drives that are rapidly gaining popularity by its
utilization in various industries, such as appliances, automotive, aerospace, consumer, medical, industrial automation
equipment and instrumentation and industrial drives partly as result of demand for variable speed drives because of
development of power electronics devices. It gaining popularity due to their low cost, ruggedness, good dynamic
response and low maintenance and are widely used in different applications which requires high torque with good
speed response.
The existence of solid state power switching technology also stimulated an interest in possible alternative and simpler
motor configurations. The motor speed depends on the average voltage of the waveform .This is achieved by altering
the duty cycle of the base PWM signal .PWM technique is simple and used for industrial applications because of their
superior and simpler performance. Most of the BLDC motor drives uses Inverters which is simple and mostly used for
industrial applications because of their simple and superior performance.
The use of pulse width modulation in power electronics to control energy saving and the ease of PWM generation using
Hardware Description language and implementing in FPGA board [2][3]. The paper presents FPGA based controller
is utilized to control the speed of the BLDC motor under different loading conditions, the performance analysis of
BLDC machine under different loading conditions such as efficiency, power factor , power and current profiling of the
machine and the speed control of BLDC motor, which can be done using the software XILINX with the help of VHDL
programming.in this paper the closed loop speed control of BLDC motor under different loading conditions so that the
motor close to the reference speed at any dynamic conditions.
2. PRINCIPLE OF OPERATION
The BLDC motor have similarities between induction motor and brushless dc motor. The working principle as same as
brushed DC motor but in BLDC motor it commonly achieved with hall sensors and optical encoders. The operation of
BLDC motor completely depends on hall sensors signals.
If the magnetic field direction is reversed, the voltage developed will reverse as well. For Hall-effect sensors used in
BLDC motors, whenever rotor magnetic poles (N or S) pass near the hall sensor, they generate a HIGH or LOW level
signal, which can be used to determine the position of the shaft. From the position of the shaft, the rotor position find
out from the hall sensor outputs
The Windings in a stator of BLDC machine can be arranged in two patterns; i.e. a star pattern (Y) or delta pattern
(). The major difference between the two patterns is that the Y pattern gives high torque at low RPM and the
pattern gives low torque at low RPM
A rotor which consists of an even number of permanent magnets. By increasing the number of poles does give
better torque but it reduces the maximum possible speed higher the flux density of the material gives the higher
torque
Hall Sensors are placed every 120 for the estimation of the rotor position in the motor
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Brushless DC motors are used in a growing number of motor applications as they have many advantages
1. They have no brushes so they require little or no maintenance.
2. They generate less acoustic and electrical noise than universal brushed DC motors.
3. PROPOSED SMART CONTROLLER

The proposed controller working on the basis of rotor position input from BLDC motor. The three Hall Sensors are
placed 120 apart from each other for the estimation of the rotor position in the motor.
The opto-coupler generates an opt coupler edge for every 7.5 degree of mechanical rotation .for every 45 degree of
mechanical rotation the signal pattern repeats correspondence to electrical cycle of the BLDC motor.
Based on the low or high combination of three hall sensor signals the rotor position decided by using the smart
control algorithm
Figure 1Speed Control Algorithm
4.MODELING OF BLDC MOTOR

Modeling of a BLDC motor can be developed in the similar manner as a three-phase synchronous machine. Since there
is a permanent magnet mounted on the rotor, Consider a cylindrical rotor and the stator have three phase winding a, b,
and c. The rotor is the permanent magnet rotor, and hence the air gap is uniform.Stator has 3 phases with distributed
winding structure with star connected. The three basic equation of phase a,phase b,phase c, are follows as
di
di
di
Van Rs L a M b M c ea
dt
dt
dt
(1)
dib
dic
dia
Vbn Rs L
M
M
eb
dt
dt
dt
(2)
dic
dic
dib
Vcn Rs L
M
M
ec
dt
dt
dt
(3)
Where
L is armature self-inductance [H],
M is armature mutual inductance [H],
R is armature resistance [],
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Van , Vbn and Vcn are terminal phase voltage [V],

ia , ib and ic are motor input current [A],
ea , eb and ec are motor back -EMF [V].
These are three equations, the rotor is a permanent magnet, and the rotor does not have any winding. So, rotor structure
not having any equation. These three equations can be represented in the form of a matrix.
5. HARDWARE IMPLEMENTATION USING FPGA

5.1 Experimental Set-Up:The Voltage Source Inverter fed to BLDC Motor drive is shown in below figure 2. The inverter has six switches, S1,
S2, S3, S4, S5 and S6 and a DC Link connected to a Diode Bridge rectifier.
Figure 2 Hardware setup for BLDC motor

5.2 System Description
A complete overview of the system can be seen on Figure 2 which includes the transformer, power circuit, a three phase
inverter, a Brushless DC motor, and Hall sensor attached to the motor [8]. The entire System is interfaced through a
PC. PC acts a Man-Machine Interface which uses Xilinx ISE 12.1 in which the user can set the reference speed of the
motor and the current regulation also carried out.
5.3Functions of FPGA:
The use of FPGA in the motor control applications is being increased rapidly because of the robustness and the
customizability of the FPGA.
This task of the controlling the motor was previously implemented using the microcontrollers, which implement the
computation algorithms executed by the softwares. The typical challenges taken to implement using these
microcontrollers are response time, a fixed number of PWM channels, limited communication interferences and per
determined analog triggering. The solution to these problems can be implemented using a FPGA [6][2].
5.4 HDL code generation:
The HDL code is the hardware description language which describes the hardware of the control circuit which is to be
implemented. This HDL code written should be verified with the test bench written. This test bench written should
contain all the test inputs which show the operation of the control logic according to the desired output .This HDL code
is then optimizes using the Simulink software and then routed to the desired FPGA. The optimization of the control
logic is done by the software packages which do not need human intervention which saves a lot of time. Here we
havechosen the Xilinx ISE which optimizes the logic written and then generates the electronic bit file and then maps
this logic onto the FPGA board.
5.4.1XILINX software overview.
The Xilinx ISE (Integrated software environment) is a software produced by the Xilinx for the synthesis, optimization
and analysis of the hardware description languages [7].
The design flow of the FPGA includes the following steps:
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1. Design entry: In this design entry all the design entities such as timing constraints, area constraints and the pin
location on the FPGA and the user constraint file of the FPGA are assigned.
2. Design synthesis: In the design synthesis the hardware circuit described in the HDL language is synthesized. This
synthesis of the circuit involves the optimized circuit without any human effort.
3. Implement Design: Following the synthesis step is the Implementation of the circuit. This includes the translation,
mapping and Place and route of the circuit on the required target board.
4. Design verification: The design verification is used to verify the correctness of the proposed algorithm and check
the timing analysis. If the timing analysis is not up to the mark the above procedure is repeated by making the
suitable changes in the proposed algorithm.
5. Xilinx device programming: The programmer bit file is generated and then it is programmed on to the Spartan 3E
board.
5.4.2Principle of generating PWM.
The principle of generating PWM waveform is shown in Fig.3 .A simple method is used where a saw-tooth waveform
and a carried data are required. A comparator compare two values in order to generate PWM. Counter is used generate
triangular wave .The value of compare register is compared with triangular wave .If the value of compare register is
less than the value of triangular wave ,then PWM is 1, else PWM is0[4].Hardware description language (VHDL) is
used to generate the required signals in FPGA and needs fast sequential execution[6].
5.5 Experimental Results.
Figure 3 No load closed loop speed
Figure 430% load torque disturbance
Figure 5 60% load torque disturbance
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ISSN 2321-600X
Figure 690% load torque disturbance

In the Experimental work the components used are an FPGA board, Personal Computer, Inverter module, and BLDC
motor.The speed control of BLDC motor is verified under 30%, 60%, 90% load torque disturbance according to load
condition is carried out the performance analysis under different load torque conditions carried using. FLUKE power
logger for measurement of current, power factor, voltage and the results are showed in Table 1.
Figure 7 Harmonics waveform

gure 7 showing the THD value is 15.7%, lower THD means low peak current reduces which will reduce the heating
losses and core loss of the motor so the harmonics level reduces and it is in the satisfactory level. The table 1 shows the
ac voltage, current, input power, efficiency of the machine under different load conditions.
Table 1
V
(Volt)
230
230
I
(Amp)
0.831
0.976
Power
(Watt)
130.3
159.8
Efficiency
230.4
230.4
229
230
230.7
230.2
230
230.1
230.4
0.5
230.1
0.994
1.011
1.137
1.359
1.583
1.720
1.827
1.868
2.08
2.145
2.250
186.9
202.11
241.7
290.9
344.5
375.8
399.9
430
450.7
470.8
495.5
Power
(Watt)
103.4
137.7
PF
80.92
86.80
Torque
(N-m)
0.489
0.710
0.89
0.90
Speed
(rpm)
2000
1995
83.90
85.70
86.80
85.82
86.76
85.30
84.45
83.22
81.46
77.30
72.96
0.799
0.902
1.200
1.738
1.987
2.310
2.510
2.890
2.99
3.153
3.396
159.3
175.4
250.4
297.7
320.9
343.9
367.3
377.8
389.7
389.5
389.2
0.902
0.925
0.955
0.936
0.959
0.950
0.964
0.958
0.954
0.943
0.967
1839
1795
1675
1579
1474
1339
1239
1224
1219
1189
1098
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230.4
230.5
230.1
230.4
2.370
2.770
2.645
2.730
521.3
547.2
584
612.1
70.95
63.20
56.10
53.23
3.599
3.710
4.210
4.380
385.9
374.6
363.7
349.8
0.969
0.935
0.968
0.978
1029
975
887
830
Figure 8 Power vs Efficiency
Figure 9Torque vs Speed

From the Figure 8 it has been conclude that when the load increasing the speed decreases from no load value but the
efficiency maintains constant at 85% to 84%. So the machine possess satisfactory efficiency level at different loading
conditions.
Fordifferent load the above parameters are obtained. From the above waveforms it has been understood that by varying
the load the efficiency increases speed reduces, Power factor increases but after certain percentage of loading the speed
decreases marginally, efficiency reduces, input current increases.
6. CONCLUSION
In this paper for different load torque speed control is verified using simulation and hardware. The performance
analysis also carried out under different loading conditions are obtained. From the above waveforms it has been
concluded thatby varying the load torque the efficiency increases speed reduces, Power factor increases but after certain
percentage of loading the speed decreases marginally, efficiency reduces, input current increases.
As the load on the motor increases, then
The output of motor increase.
The power factor increases.
The efficiency increase up to certain load and then decreases
The speed decreases marginally.
This paper presents the design of FPGA based smart Controller for BLDC motor drive. PWM control is successfully
implemented by the use of FPGA.The BLDC Motor drive using FPGA controller is successfully implemented and
carried out the real-time experiment with theuse of FLUKE power logger and XILINX 12.1 is used for software
interface and the hardware implementation is carried out using SPARTAN-3E processor. VHDL program is developed
in XILINX to generate the controlled PWM pulses to drive the system [2], [3].
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ISSN 2321-600X
REFERENCES
[1] Srgio Sousa, V. Ferno Pires, Manuel Guerreiro, FPGA Implementation of a Speed Controller for Three Phase
Induction Machines based on the Inversion of the Electromagnetic Field Proceedings of the 2011 International
Conference on Power Engineering, Energy and Electrical Drives, Torremolinos (Mlaga), Spain. May 2011.
[2] Dayu Wang, Kaiping Yu and Hong Guo, Functional design of FPGA in a Brushless DC Motor system based on
FPGA and DSP, IEEE Vehicle Power and Propulsion Conference (VPPC), September 3-5, 2008.
[3] Jayaram Bhasker, VHDL-Primer, 3rd Edition, Pearson Prentice Hall,1999 Xilinx 12.1 application notes.
[4] Nalin Kant Mohanty, Ranganath Muthu, A Novel Implementation of Xilinx FPGA Based Four Switch Three
Phase IGBT Inverter Fed Induction Motor Drive Using PWM European Journal of Scientific Research- Euro
Journals Publishing, Inc. 2011, Vol.48 No.3 (2011), pp.424-433.
[5] Bo, Sun Chunxiang Mo. "design of control system of brushless dc motor based on dsp." Intelligent Computation
Technology and Automation (ICICTA), 2010 International Conference on, 2010.
[6] O. Al-Ayasrah, T. Alukaidey, G. Pissanidis. DSP Based N-Motor Speed Control of Brushless DC Motors Using
External FPGA Design. IEEE International Conference on Industrial Technology, 2006. ICIT 2006.
[7] Z. Bielewicz, L. Debowski, and E. Lowiec, "A DSP and FPGA based integrated controller development solutions
for high performance electric drives", Proceedings of the IEEE International Symposium on Industrial Electronics,
Vol
2, pp: 679 - 684, June, 1996.
[8] Phan Quoc Dzung, Le Minh Phuong, Pham Quang Vinh,Nguyen Minh Hoang, Tran Cong Binh New Space
Vector Control Approach for Four Switch Three Phase Inverter (FSTPI) International Conference on Power
Electronics and Drive Systems- IEEE PEDS 2009,Thailand.
AUTHOR
Kanhu Charan Patra received the B-Tech in Electrical and Electronics engineering from National
institute of science and technology, Berhampur and M-Tech degree in Electrical engineering from
National institute of technology (NIT) Calicut, Kerala
Priyabrta Nayak received his B Tech degree in Electrical Engineering from Bijupatnaik University
of Technology, Orissa in 2012 and M Tech degree from NIT Calicut, Kerala, India in Power Systems
Specialization in Electrical Engineering department in 2015.
Pradeep Kumar received his B Tech degree in Electrical and Electronics Engineering from
Maharaja Agrasen Institute of Technology, New Delhi in 2012 and M Tech degree from NIT Calicut,
Kerala, India in Power Systems Specialization in 2015.
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IPASJ International Journal of Electrical Engineering (IIJEE)

Web Site: http://www.ipasj.org/IIJEE/IIJEE.htm

A Publisher for Research Motivation........

Volume 3, Issue 8, August 2015