Professional Documents
Culture Documents
Microprocessor Systems
Teaching Assistants
Ashraf Suyyagh, Zaid Al-bayati, Harsh Aurora
Andrey Tolstikhin, Loren Lugosch
Course Format
Lectures:
Monday, 10:05 AM - 11:25 AM, Trottier 0060
Tutorials:
Friday, 11:35 AM 12:55 PM, Trottier 0060
Start: Sep. 11
Labs
Other Logistics
Course communications all through myCourses
Lectures, labs, manuals, discussion,
Respect others, use common sense
If you do feel the need to email me directly about course-related
matters, please include ECSE-426 in the subject line
Grading
Labs 48%
4 labs in pairs of two : demonstrations and reports
Late reports: 5 percent per day penalty (Fri-Mon: one day)
Missed demo: reschedule for 65 percent of grade
Project 40%
Group of 4: demonstration and report
Quizzes 12%
Four 15 minute quizzes in class
Short answer & multiple choice
covers current lab and tutorial and recent lectures
Mark Coates, Fall 2015
Grading
Demos
Academic Integrity
McGill University values academic integrity. Therefore all students
must understand the meaning and consequences of cheating,
plagiarism and other academic offences under the Code of Student
Conduct and Disciplinary Procedures.
See http://www.mcgill.ca/integrity/ for more information.
Avoid Plagiarism
Please make sure to reference any text, code, or online resources
you use to develop your solution
If you reproduce any figures, clearly state this in the figure caption:
Reproduced from [1]
If you re-use code from another source, clearly indicate this in your
code with appropriate comments
10
Microprocessors
Enabling technology for general purpose computers and embedded
systems
Many, many applications
General purpose computers
PCs, workstations, servers, supercomputers
Embedded systems
Phones, medical, aviation, automobile, industrial
Real-time systems
10-Sep-15
ECSE 426
Microprocessor Systems
Course Goals
Provide the necessary understanding and skills to design and build
microprocessor systems.
By the end of the course, you should:
understand the organization and design principles of modern
microprocessor-based systems;
be proficient in assembly and high-level (C language) programming
for embedded systems;
understand the performance impact of the embedded software,
including the energy and memory-limited design techniques;
know how to connect peripheral devices and networking interfaces,
and how to write programs for the efficient interface use;
have experience in developing a realistic embedded system solution
through teamwork;
Mark Coates, Fall 2015
12
13
Lecture Structure
Background
Computer architecture basics
ECSE 426
Microprocessor Systems
Lab Structure
Four experiments + final project.
Experiment
Experiment
Experiment
Experiment
1 : Assembly and C
2: Intro. to hardware interfacing; drivers, timing
3: I/O, Interrupts, Servo-motors, Advanced Sensor Use
4: Real-time OS, Networking
Project:
10-Sep-15
ECSE 426
Microprocessor Systems
Class Schedule
Week
Lecture Material
Tutorials
1 (Sep 7)
Introduction
2 (Sep 14)
Tutorial A
Assembly and C
Tutorial 1
Introduction to IDE and
assembly
3 (Sep 21)
Linker, loader,
processor architecture
4 (Sep 28)
Processor
Microarchitecture; Q1
Embedded Processors
Tutorial 2 - Introduction to
embedded C, IDE and drivers
IO/Processor
Interfacing; Q2
Buses, Networking,
Operating System; Q3
Tutorial 3 - Introduction to
timers, interrupts and MEMS
5 (Oct. 5)
6 (Oct 12)
7 (Oct 19)
8 (Oct 26)
Lab 1
Lab 2
Embedded OS
Services
16
3 (Sep 21)
Linker, loader,
processor architecture
4 (Sep 28)
Processor
Microarchitecture; Q1
Embedded Processors
Tutorial 2 - Introduction to
embedded C, IDE and drivers
IO/Processor
Interfacing; Q2
Buses, Networking,
Operating System; Q3
Tutorial 3 - Introduction to
timers, interrupts and MEMS
Embedded OS
Services
Real-time processing;
Q4
Project Intro
5 (Oct. 5)
6 (Oct 12)
7 (Oct 19)
8 (Oct 26)
9 (Nov 2)
10 (Nov 9)
Lab 1
Class Schedule
11 (Nov 16)
12 (Nov 23)
Project
Project
13 (Nov 30)
Project
Project Demo
14 (Dec 7)
As with any plan, this schedule is subject to some change.
Mark Coates, Fall 2015
17
Intro Material
18
Computer Architecture
Application of design principles on state-of-art architecture
19
Applications
Deciding Factors: cost, size, power, quantity
20
Example: Camera
Computer system with:
Image control
Hardware (lenses, motors)
Interfaces
Added sophistication to
consumer electronics
Expandability (of functions)
Connectivity
Lens
Optical
sensors
A/D
conversion
Motor
User
switches
Image
storage
System
controller
LCD
screen
Flash
unit
Computer
interface
Cable to PC
21
22
Translation (Compiler)
Assembly Language Level
Translation
(Assembler)
lw $15, 0($2)
lw $16, 4($2)
sw $16, 0($2)
sw $15, 4($2)
OS - Partial Interpretation
Instruction Set Architecture Level
Interpreter
Microarchitecture Level
0000
1010
1100
0101
1001
1111
0110
1000
1100
0101
1010
0000
0110
1000
1111
1001
1010
0000
0101
1100
1111
1001
1000
0110
0101
1100
0000
1010
1000
0110
1001
1111
Hardware
23
Computer Organization
Processor
Microprocessor
Memory
Peripherals
Common Bus
24
Microprocessor Operation
Start here at power-on or when a reset signal is
received
Reset
Fetch
Decode
Execute
2. Execute instruction
3. if necessary, write results to memory
25
Common Processors
Mainly von Neumann
architecture
Arithmetic-logic unit
Registers
Auxiliary registers
27
28
29
Microprocessor
Data
Cache
Memory
Bus
RAM
Bus
Interface
Unit
I/O
System
Bus
Control
Unit
Arithmetic
& Logic
Unit
Instruction
Decoder
Registers
Instruction
Cache
Mark Coates, Fall 2015
Floating
Point
Unit
Registers
30
31
Instruction Decoder
Receives the programming instructions
Decodes them into a form that is understandable by
the processing units, i.e., the ALU or FPU
Passes on the decoded instruction to the ALU or FPU
32
33
34
Registers
Small amount of super-fast private memory placed
right next to ALU & FPU for their exclusive use
The ALU & FPU store intermediate and final results
from their calculations in these registers
Processed data goes back to the data cache and
then to main memory from these registers
35
Control Unit
The brain of the microprocessor
Manages the whole uP
Tasks
fetching instructions & data
storing data
managing input/output devices
36
37
38
Pipelining - Reference
Pipeline
Connect data processing elements in series
Output of one element is input of the next
Execute in parallel (using time-slices)
Pipelining effects
Does not decrease processing time for a single datum
Increases throughput of the system when processing a stream of data
Using many pipelining stages causes increase in latency
39
40
Superscalar Architectures
Common solution for modern processors
Multiple execution units
41
Multiple-core architectures
Intel slide
42
Multiple-core architectures
Intel slide
43
Memory
Hierarchy of memory units
Speed vs. size
Solutions
Caching
Virtual memory
44
45
46
47
boost in performance
48
Cache
Datapath
Register
Speed: Faster
Size: Smaller
Cost: Higher
2nd Cache
Main
Memory
Hard disk
(Virtual
Memory)
Slowest
Biggest
Lowest
49
50
51
Characters
Display
Communication
File
Reproduced from
Tanenbaum & Austin
52
Registers:
r0 - r3, pc
Addressing Modes:
ldr
r12, [r1,#0]
mov r1, r3
How to access data in registers
and memory
Memory:
80000004 ldr r0,[r2,#0]
80000008 add r2, r3, r4
8000000B 23456
80000010 AEF0
Memory mapped I/O
80000100 input
80000108 output
Programmers
Model
Loader
Linker
Assembler
Executable
Image File
Run-Time Library:
Boot
Process
Read-Write
Memory (RAM)
CPU
PC
ALU
System bus
Memory bus
Main
memory
I/O
bridge
Bus interface
I/O bus
USB
controller
Mouse Keyboard
Graphics
adapter
Display
Disk
controller
Disk
Reproduced from
Tanenbaum & Austin
CPU
PC
ALU
System bus
Memory bus
Main
memory
I/O
bridge
Bus interface
I/O bus
USB
controller
Graphics
adapter
Mouse Keyboard
Display
User types
"hello"
Disk
controller
Disk
CPU
PC
ALU
System bus
Memory bus
Main
memory
I/O
bridge
Bus interface
I/O bus
USB
controller
Mouse Keyboard
Graphics
adapter
Display
Disk
controller
Disk
"hello,world\n"
hello code
CPU
PC
ALU
System bus
Memory bus
Main "hello,world\n"
memory
hello code
I/O
bridge
Bus interface
I/O bus
USB
controller
Mouse Keyboard
Graphics
adapter
"hello,world\n"
Display
Disk
controller
Disk
Operations
performed
Many possible
implementations
Given by
Resources
Processor Registers
Execution Units
Address
Bus
CPU
Data
Bus
Memory
Control
Bus
Operations
Instruction Types
Data Types
Addressing Modes
Operands and
results stored
HW
SW
60
Assembly versus C
Efficiency of compiled code
Source code portability
Program maintainability
Typical bug rates (say, per thousand lines of code)
The amount of time it will take to develop the solution
Availability and cost of compilers and other development tools
Your personal experience (or that of the developers on your team)
with specific languages or tools
Dont rule out Java or C++ if you have the memory to play with.
61
Problem
Designer has left the company and provided few notes or comments
62
63