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g)Name TWO types of oxidation and write the chemical response reaction for both
types.
j) What is layout?
A process where engineering schematics are transposed into graphic symbols that
will be used to make a mask.
Symbol
Schematic
Layout
k)State FOUR governing rules in CMOS design for all logic gates.
1.For each input node, there must be 2 transistors, one P-MOS and one N-MOS.
The gate nodes of each must be electrically common. Example: Inverter one
input, two transistor, one P-mos and one N-mos.
2. The Nmos transistors always match the logical function of the gate.
3. The Pmos transistors will always be in a complementary configuration to the
Nmos.
4. The ordering dot on the logic symbol determine which transistor is placed
closest to the output node.
l)State TWO advantages of node sharing.
1)Minimizes cell area
Diffusion/Node sharing between two devices allows them to be placed closer
together. This plays a critical role in minimizing cell area.
2)Reduces routing congestion
Each instance of diffusion/node sharing eliminates the need for a wire to connect
the two diffusion terminals. Therefore, it plays a role in reducing routing
congestion in a cell.
3) Improves parasitics
As a result of the cell size and routing minimization, there is a parasitic (RC)
reduction. This is beneficial from an electrical standpoint.
PART B
1)Explain the contact guidelines.
There are 2 contact guidelines that is partially covered and fully covered.
Partially covered- cannot carry as much current as fully covered contact. A partially covered
contact has 0.0 metal coverage past the edge of the contact
Fully covered- A fully covered contacts has at least 0.16u coverage on all sides.
5)Draw the examples to show multiple cell instances placed with the same orientation, with
flipping and no stepping.
Understand constraints
Basic Wire Planning
Block sizing fundamentals
Block Placement fundamentals
Datapaths definition
Basic Datapath pitch planning
Estimating time
Stepped cells
-The example below shows multiple cell instances placed with the same orientation (no flipping)
and same distance between neighbors.
The origin of the instantiated cell is determined by the small triangle in the lower left
corner.
Origin at X:0, Y:0 of child cell
Top down
Bottom-up
Middle-out
In bottom-up planning the area of focus is on leaf cells or cell studies (layouts done early
in the project).
This planning is used after the cluster level planning is finished.
Repeated structures such as datapath, memory arrays and decoders are sized to help with
the final sizing of each block.
12)
Metal Layers
Metal Widths/spacings
Shielding
Explain about the shielding and draw the example if the signal is fully shielded.
13)
14) State the steps for standard routing flow and explain one of them.
Detail Route
Use p+ guard rings connected to ground around nMOS transistors and n+ guard rings
connected to VDD around pMOS transistors to reduce Rw and Rsub and to capture injected
minority carriers before they reach the base of the parasitic BJTs.
Place substrate and well contacts as close as possible to the source connections of MOS
The actual product design is done. All layout work completed. Design timing/power
requirements etc. met. Full chip layout assembled and verified. Database sent for fracturing.
Circuit layout is translated into Electron Beam (E-beam) readable data for process of mask
generation by Fab
Release of Fracture data to Mask vendors, this is the start of manufacturing of the product
New Stepping: B0, C0, A full set with design change to an existing product. All layers are
taped out.
Retrofit (Dash stepping):A1, A2, B1, B2 ... Some layers are modified on an existing
product. Only those layers that are changed are taped out.
Device layout
Dummification
PART C
1)
2)
Answer:
Answer:
5 nodes:
Vout
Vin
Vout2
Vdd
Vss