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Logic Gates

Rassiel Mex Dzib - Rodrigo Canepa Cruz

Victor Baas Argaez - Victor Chan Ortiz

Ingenieria Mecatronica
Facultad de Ingeniera
Umiversidad Autonoma de Yucatan (UADY)
Mrida, Mxico

Ingenieria Mecatronica
Facultad de Ingeniera
Umiversidad Autonoma de Yucatan (UADY)
Mrida, Mxico
II. PROCEDURE

Abstract In this laboratory practice we are going to probe


basic logic functions of Boolean algebra using a software
simulation and hardware implementation with a dispositive
called Field Programmable Gate Array (FPGA).

I.

INTRODUCTION (HEADING 1)

The logic gates are physic implementation of logic


operators, these devices consist internally by transistors that
act like tiny electronic switches with the purpose of handling
electrical input and output signals, equivalent to logic 1 and
logic 0. In this way we have the logic gates AND, OR and
NOT, allowed to basic logic operators AND, OR and NOT [1].

Through the Project Navigator program that is included in


the Xilinx ISE Design Suite software package, we create a
new project and add a new text file with the VHDL code
shown in Figure II-1, that is an example called
compuerta_AND, this have two inputs and one output, all
BIT types and his output function f is given by the logic
operation AND of the x and y inputs.

Figure II-1 Gate logic AND code

Table I-1Truth table for basic logic gates.

Also of this basic gates exists other variants frequently


used into Digital Circuits:

NAND

OR exclusive (XOR)

NOR exclusive (XNOR)

We wrote the code synthesis and check the RTL schematic


diagram of the code that must match one the shown in Figure
II-2.

Figure II-2 Gate logic AND picture

Add a new test bench file and write the code showed in
Figure II-3.
.
Table I-2 NOR logic gate truth table

Table I-3 NOR, XOR, XNOR logic gates truth tables

In the following pictures we could see the waveforms of each


logic gates.

Figure III- 6 NAND waveform

Figure III- 7 NOR waveform


Figure II- 3 Gate logic AND test bench code.

Select the simulation menu on the Project Navigator


window and run the simulation shown in the test bench. After
setting the time scale and must observe the waveforms shown
in the picture x.x. Verify that this corresponds to the behavior
of the gate AND.

Figure III- 8 NOT waveform

Figure III-9 XOR waveform

Figure III- 10 XNOR waveform

Figure III-11 OR waveform


Figure II-4 Gate logic AND waveform

After, we created the constraint file for the test in the


FPGA circuit, for this we need to look at the BASYS 2 and
find the correct connection between input and output pines,
like Figure II-5 shown. We used switch values for the test,
then we write in the constraint file the letters and numbers
corrects and repeat this for all gates logics.

B. Questions

1. How many LUTs have been used in


synthesis?
R.- We used 1 LUT
2. How many Flip Flops have been used
in synthesis?
R.- We used 1 Flip Flop
3. How many IOBs have been used in
synthesis?
R.- We used 1 IOB
4. What is the total percentage of logic
gates used in the design?
R.- We used between 0.002% - 0.003%

Figure II-5 FPGA Basys

III.

ANALISIS RESULTS

A. Conclusions
In the implementation we probe that implementation results
of logic gates (AND, OR, NOT, XOR, NOR, XNOR) were
the same that truth tables.

References
[1]

A. Castillo Atoche, M. Lopez Sanchez, Manual de Prcticas


Sistemas Digitales, 2012, pp.12.

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