Professional Documents
Culture Documents
Model:
PDP4206EM1
Safety Precaution................................................................................1-2
Technical Specifications...................................................................3-11
Block Diagram................................................................................12-13
Circuit Diagram................................................................................14-31
Basic Operations & Circuit Description...........................................32-36
Main IC Specifications....................................................................37-57
Panel Information............................................................................58-96
Spare Part list..................................................................................97-98
Exploded View...................................................................................99
If You Forget Your V-CHIP Password..............................................100
Software Upgrade..............................................................................101
This manual is the latest at the time of printing, and does not
include the modification which may be made after the printing,
by the constant improvement of product.
Safety Precaution
CAUTION
PRECAUTIONS DURING
SERVICING
WARNING:
SAFETY INSTRUCTION
The service should not be attempted by anyone
unfamiliar with the necessary instructions on this
apparatus. The following are the necessary
instructions to be observed before servicing.
1. An isolation transformer should be connected in
the power line between the receiver and the
AC line when a service is performed on the
primary of the converter transformer of the set.
2. Comply with all caution and safety related
provided on the back of the cabinet, inside the
cabinet, on the chassis or picture tube.
explode.
1101
list.
hazards.
9. Must be sure that the ground wire of the AC
2101
Technical
1.
Specifications
PDP4206EM1
Ambient light
1.2
Viewing distance
1.3
Warm up time
30 minutes
1.4
no restricted
1.5
Measuring Equipment :
1.6
Magnetic field
no restricted
1.7
Control settings
1.8
Power input
100~120Vac
1.9
Ambient temperature :
60Hz
1.11.1
With image sticking protection of PDP module, the luminance will descend
by time on a same still screen and rapidly go down in 5 minutes. When
measuring the color tracking and luminance of a same still screen, be sure t
o accomplish the measurement in one minute to ensure its accuracy.
1.11.2
Due to the structure of PDP, the extra-high-bright same screen should not
hold over 5 minutes for fear of branding on the panel.
3101
Technical
Specifications
PDP4206EM1
ELECTRICAL CHARACTERISTICS
2.
3.
Power Input
Voltage
100 ~120VAC
2.2
Input Current
5.0 /2.5A
2.3
:
:
2.4
Frequency
60Hz(3Hz)
2.5
Power Consumption
Test condition
:
:
330W Typical
full white display with maximum brightness and
contrast
2.6
Power Factor
Meets IEC1000-3-2
2.7
Withstanding voltage
:
:
:
:
:
:
:
42 Plasma display
16:9
852x480
1500 cd/m (Typical, Panel only)
10000:1 (Ratio, Typical, in a dark room, Panel only)
Over 160
English,French,Spanish.
Display
3.1
3.2
3.3
3.4
3.5
3.6
3.7
4.
60Hz
2.1
Screen Size
Aspect Ratio
Pixel Resolution
Peak Brightness
Contrast Ratio (Dark room)
Viewing Angle
OSD language
Signal
4.1
:
:
:
:
4.1.5EDID compatibility
4.1.6 I/P frequency
:
:
AV
S-Video
YPbPr, HDMI,VGA compatible
Analog: D-sub 15pin detachable cable
Digital:HDMI
DDC 1.3
fH: 31.5kHz to 60kHz/fV: 56.25Hz to 75Hz(1024x768
recommended)
4101
Technical
Specifications
5.
Environment
5.1 Operating environment
5.2
6.
PDP4206EM1
5.1.1 Temperature
:
5.1.2 Relative humidity:
5 to 33C
20% to 85%(non-condensing)
Panel Characteristics
6.1
6.2
Type
Size
:
:
6.3
6.4
6.5
6.6
6.7
6.8
Aspect ratio
:
Viewing angle :
Resolution
:
Weight
:
Color
:
Contrast
:
6.9
Peak brightness :
SDI V4
42,932.94mm(W)X532.80mm(H)
(W/Ostand)
16:9
Over 160
852X480
33.6kg 0.5 kg (Net)w/o stand
16.7 millions of colors (R/G/B each 256 scales)
Average 60:1 (In a bright room with 150Lux at center)
Typical 10000:1 (In a dark room 1/100 White Window
pattern at center).
Typical 1500cd/ (1/25 White Window)
5101
Technical
Specifications
PDP4206EM1
:
:
MENU Button
SOURCE Button
7.2
STANDBY Button
7.3
8.
OSD Function
6101
Technical Specications
9. Agency Approvals
Safety
:
Emissions
:
PDP4206EM1
10. Reliability
MTBF : 20,000 hours(Use moving picture signal at 25C ambient)
11. Accessories
User manual x1, Remote control x1, Stand x 1, Battery x 2, AC Cable x 1
12. Remote Control
1 Standby( ): Press this button to turn off to
standby and turn on from standby.
2 Mute( ): Press this button to quiet the sound
system. Press again to reactivate the
sound system.
3 P. Still: Press this button to hold on the
screen. Press again to normal.
4 P. Size: When the input source is YPbPr 1,
YPbPr 2, VGA or HDMI, press this button,
the picture will change according to Fill All,
Force 4:3, Letter Box, Wide or Anamorphic.
When the input source is AV or S-Video, press
this button, the picture will change according to
Fill All, 4:3, Letter Box, Wide or Anamorphic.
5 S. Sele: Press this button to select the sound
output from Main Window or Sub Window.
6 P. Mode : Press the button to select different
picture effect.
7 Time: Press this button to pop up the Clock
Set menu.
8 Sleep: Press this button to select the sleep
time.
9 Display: Press the button to display the
source information.
10 Auto: The Display automatically adjusts the
phase, vertical / horizontal position when
pressing this button in VGA mode.
11 Layout: Press this button to pop up Layout
menu.
12 C/C: Press this button to enter the Closed
Caption Function. (Only for AV or S-Video)
(Continued on next page)
7101
Technical Specications
PDP4206EM1
8101
Technical Specications
PDP4206EM1
Mode
VGA Mode
HDMI Mode
HDTV Mode
(YPbPr1/YPbPr2)
Horizontal
Frequency
(kHz)
31.50
37.90
48.40
64.00
33.75
45.00
31.468
33.75
45.00
31.468
15.734
Resolution
640 x 480
800 x 600
1024 x 768
1280 x 1024
1080i
720p
480p
1080i
720p
480p
480i
Vertical
Frequency
(Hz)
60.00
60.32
60.00
60.01
60.00
60.00
59.94
60.00
60.00
59.94
59.94
Dot Clock
Frequency
(MHz)
25.18
40.00
65.00
108.00
74.25
74.25
27.00
74.25
74.25
27.00
13.50
PIP
PBP
Main
Large
Sub
Middle
Small
Main
Sub
VGA (Max.)
1024
1024
1024
1024
1024
1024
x
x
x
x
x
x
768
768
768
768
768
768
HDMI/YPbPr1/YPbPr2
720p
1080i
480p
OK
OK
OK
OK
OK
OK
X
OK
OK
X
OK
OK
OK
OK
OK
OK
OK
OK
Note:
- X means out of range (can not show).
- When the signal received by the Display exceeds the allowed range, a warning
message shall appear on the screen.
- You can conrm the input signal format from the on-screen.
- VGA 1280 x 1024 Mode dont recommend working in PIP/PBP Screen Mode.
9101
Technical
Specifications
PDP4206EM1
PHYSICAL CHARACTERISTICS
14. Power Cord
Length
1.8m nominal
Type
optional
15. Cabinet
15.1 Color
15.2 Weight(W/Ostand)
Net weight
(W/O stand&speaker)
15.3 Dimensions
Width
Height
Depth
33.6kg
:
:
:
1050mm
657mm
99.5mm
10101
Block Diagram
LVDS Input
Control Signal
(Serial Interface)
Input
Interface
Controller
Vs(180V~190V)
Memory
Controller
Va(55V~65V)
Vcc(+5V)
Driver
Timing
Controller
APL Data
Scan Driver
Address Driver
Applied Voltage level is specified at the time when Full-White pattern is displayed on the panel.
11101
Block Diagram
MAIN/AUDIO BOARD
CS4344
Audio DAC
12101
Circuit Diagram
- Power supply board of Audio Amplifier, MPT012A
- Main (Video) board
- Audio/Tuner board
- Keypad board
- Remote control receiver board
- Remote control board
13101
14101
15101
16101
6
JP902
OVDD3.3V#
GND
INPUT OUTPUT
C910
TAB
PLL1.8V
L900
C916
4
C901
C917
OVDD3.3V#
TVDD3.3V
C918
5V
L914
AVDD3.3V
L915
C954
C907
C904
C911
AVDD3.3V#
L903
CVDD1.8V
L901
L904
OVDD3.3V
C919
4
C913
C902
C920
C921
DDC5V
82
83
DDC5V
R903
R906
46
R908
D902
HD1_R/Pr
VCLK
SCL
SDA
GND
62
8
1
2
3
VCC
NC1
NC2
NC3
HD1_G/Y
JP901
GYCbCr_Y
HDMI_D1+
HDMI_D1-
GYCbCr_Y
C943
C944
HD2_Cr
HD2_Y
77
71
70
66
60
63
C945
HD2_Cb
GYCbCr_Cb
HDMI_D0+
HDMI_D0-
GYCbCr_Cb
C946
R909
HDMI_CK+
HDMI_CK-
U901
RAIN1
GAIN1
SOG1
BAIN1
VS1
HS1
DE
HSOUT
SOGOUT
VSOUT/A0
FIELD
DCLK
R944
GYCbCr_Cr
R945
GYCbCr_Y
R946
GYCbCr_Cb
RP909
DDC_SCL3
DDC_SDA3
HDCP_SCL
HDCP_SDA
D904
HDMI_D0-
D905
HDMI_D1+
D906
HDMI_D1-
D907
HDMI_D2+
D908
HDMI_D2-
D909
HDMI_CK+
SDA#SO
SCL#SO
R912
TVDD3.3V
20mA 36mW
Vd
270mA 891mW
92
93
94
95
96
97
98
99
ADCR7
ADCR6
ADCR5
ADCR4
ADCR3
ADCR2
ADCR1
ADCR0
RP905
2
3
4
5
6
7
8
9
ADCG7
ADCG6
ADCG5
ADCG4
ADCG3
ADCG2
ADCG1
ADCG0
RP903
12
13
14
15
16
17
18
19
ADCB7
ADCB6
ADCB5
ADCB4
ADCB3
ADCB2
ADCB1
ADCB0
RP901
88
87
86
85
84
89
ADC_DE
ADC_HS
ADC_SOG
ADC_VS
ADC_FIELD
ADC_DCLK
28
S/PDIF
GRE[7..0]
GRE7
GRE6
GRE5
GRE4
GRE3
GRE2
GRE1
GRE0
RP906
C
GGE[7..0]
GGE7
GGE6
GGE5
GGE4
GGE3
GGE2
GGE1
GGE0
RP904
GBE[7..0]
GBE7
GBE6
GBE5
GBE4
GBE3
GBE2
GBE1
GBE0
RP902
RP907
GPEN
GFBK
GHS
GVS
FIELD
GCLK
GSOG
R918
R917
R916
GPEN
GFBK
GHS
GVS
FIELD
GCLK
GSOG
PWRDN
I2S_MCLK
I2S_SCLK
I2S_LRCLK
I2S_DATA
R929
20
21
22
23
27
26
25
24
RP908
I2S_SCLK
I2S_LRCLK
I2S_DATA
R938
SCLK R928
R927
R926
R937
R936
R935
DATA/R
LRCK/L
OVDD3.3V
C955
DATA/R
LRCK/L
AVDD3.3V
81
R930
R933
1
R914
2
U907A
R931
3
R932
4
U907B
SPDIFOUT
R934
C953
R913
7
6
5
4
VCLK
SCL
SDA
GND
VCC
NC1
NC2
NC3
8
1
2
3
A
JP903
Title
C934
U906
SGND
HDMI_CK-
DDC_SCL5
DDC_SDA5
3
2
1
Size
9-HDMI-R
Number
Revision
B
Date:
File:
1
C2
V2
Y2
HDMI_D0+
PVd
55
58
65
69
75
78
D903
SGND
HPD_DET
DDC_SCL
DDC_SDA
MCL
MDA
53
HPD_DET
49
50
51
52
PGND1
PGND2
AGND1
AGND2
AGND3
AGND4
R915
R943
MCLKIN
MCLKOUT
SCLK
LRCLK
I2S0
I2S1
I2S2
I2S3
ALGND
HD1_B/Pb
TGND1
TGND2
TGND3
HD1_G/Y
36
39
42
HDMI_5V
R942
CGND1
CGND2
2
D911
S/PDIF
31
47
DDC_SCL5
DDC_SDA5
60mA 108mW
DDC_SDA3
I2S_MCLK
RX0RX0+
RX1RX1+
RX2RX2+
RXC+
RXC-
DGND1
DDC5V
34
35
37
38
40
41
43
44
29
5V
HDMI_D0HDMI_D0+
HDMI_D1HDMI_D1+
HDMI_D2HDMI_D2+
HDMI_CK+
HDMI_CK-
HD1_R/Pr
R922
AVDD1
AVDD2
AVDD3
AVDD4
PVDD1
PVDD2
B7
B6
B5
B4
B3
B2
B1
B0
R910
R941
TVDD3.3V
R925
67
72
76
80
54
56
59
30
32
48
RAIN0
GAIN0
SOG0
BAIN0
VS0
HS0
OGND1
OGND2
OGND3
20
21
22
23
79
74
73
68
61
64
HD1_B/Pb C942
C930
D910
COAST/EXTCK
1
11
91
T1
T2
T3
T4
HD1_G/Y C940
VGA_VS
VGA_HS
GYCbCr_Cr
GYCbCr_Cr
HDMI_D2+
HDMI_D2-
L913
G7
G6
G5
G4
G3
G2
G1
G0
C941
C929
HD1_B/Pb
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
RTERM
HD1_R/Pr C939
U905
7
DDC_SCL5 6
DDC_SDA5 5
4
C947
SCL
SDA
R907
GCOAST
C948
R921
R924
R7
R6
R5
R4
R3
R2
R1
R0
C937
C938
DDC5V
R947
FILT
ALVDD
57
DVDD
R904
C936
CVDD1
CVDD2
C923
C906
R905
DDC5V
14
C915
C903
TVDD1
TVDD2
C922
C935
OVDD1
OVDD2
OVDD3
GND
DVDD1.8V
L902
33
45
10
90
100
HDMI-1.8V
TAB
DDC_SCL3
Q902
DDC_SDA5
SCL_H5V
SDA_H5V
Q901
C908
C905
PLL1.8V
INPUT OUTPUT
DATA2+
DATA2S
DATA2DATA1+
DATA1S
DATA1DATA0+
DATA0S
DATA0CLK+
CLKS
CLKCEC
NC
SCL
SDA
CEC/GND
+5V
HPDET
R919
R920
D3V3B
D901
U904
GND
TAB
DDC_SCL5
AVDD3.3V#
INPUT OUTPUT
C914
GND
1
5V
VCC
C909
SGND
U903
C912
VIN
R923
D
3
SPDIFOUT
U902
5V
17101
21-Jan-2006
F:\4238\PC_B\4238.DDB
Sheet of
Drawn By:
6
D3V3D
D
D0_SRAM
D1_SRAM
D2_SRAM
D3_SRAM
D4_SRAM
D5_SRAM
D6_SRAM
D7_SRAM
D5_SRAM
D4_SRAM
SDA_S3V
R1515
D3_SRAM
D2_SRAM
SCL_S3V
SCL_S3V
D1_SRAM
C1513
R1506
/WR_SRAM
5
30
R1513
3450_rest
81
80
79
78
77
76
83
82
D3V3D
SDA_S3V
D0_SRAM
C1512
SC2_SW1
SC1_SW0
SC1_SW1
SC2_SW0
RP1502
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
R1527
RP1501
D6_SRAM
R1514
D3V3D
6
A15_SRAM
A14_SRAM
/RD_SRAM
/WR_SRAM
A7_SRAM
SCL_NVRAM
SDA_NVRAM
A6_SRAM
C1511
U1501
/CE1
CE2
/OE
R1505
X1501
9
10
7
11
4
12
1
31
2
3
13
14
15
16
17
18
19
20
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
A17_SRAM
A16_SRAM
RP1503
A15_SRAM
A14_SRAM
A13_SRAM
A12_SRAM
RP1504
A11_SRAM
A10_SRAM
A9_SRAM
A8_SRAM
RP1505
A7_SRAM
A6_SRAM
A5_SRAM
A4_SRAM
RP1506
A3_SRAM
A2_SRAM
R1508
R1509
A1_SRAM
A0_SRAM
C
XTALOUT
C1504
XTALIN
C1505
A8_SRAM
A9_SRAM
A10_SRAM
A11_SRAM
D3V3D
U1503
SDA_NVRAM
SCL_NVRAM
TT_VVVS
7
D3V3D
TT_VVHS
TT_FSO
SDA
GND
SCL
NC2
WP
NC1
VCC
NC0
D3V3D
R1516
SC1_SW1
3
2
D1501
R1517
A16_SRAM
A17_SRAM
A0_SRAM
R_OUT
G_OUT
B_OUT
A1_SRAM
A2_SRAM
A3_SRAM
R1501
A12_SRAM
C1501
A13_SRAM
CVBS1
CVBS0
A4_SRAM
A5_SRAM
SC1_SW
D3V3D
R1522
SC2_SW1
R1525
SC2_SW0
Q1503
D3V3D
Q1504
D1503
R1523
R1526
D1504
TT_R
R1511
TT_G
R1512
TT_B
SGND
R1504
C1518
C1517
R1503
R1502
R1521
C1515
C1514
C1516
C1502
TV_CVBS_S#
D1502
SGND
R1510
C1503
TV_CVBS_M#
R1520
SC2_SW
R1529
C1519
D3V3_TT_A
SGND
D3V3D
Q1502
C1510
SGND
R1519
SC1_SW0
Q1501
R1528
B
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
32
/WE
GND
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VDDP
NC
RESET
/RESET
XTALOUT
XTALIN
OSCGND
NC
A8
A9
A10
A11
VDDC
VSSC
NC
VSSP
P3.6
NC
NC
NC
VSYNC
P3.5
HSYNC
VDS
RAMBANK0
R1507
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
24
P1.4
SDA
/RD_SRAM
SCL
P1.3
P1.2
P1.1
A16_LN
P1.0
P2.7
P3.0
A17_LN
P3.1
P3.2
P3.3
A15_LN
A14
/RD
/WR
VSSC
VSSP
P0.5
NC
A7
SCL_NVRAM
SDA_NVRAM
P0.2
NC
NC
VPE
P0.3
A6
P0.4
P3.7
A5
A4
P0.6
P0.7
VSSA
CVBS0
CVBS1
A15_BK
SYNC_FILTER
IREF
A13
A12
A3
A2
A1
FRAME
VPE
/COR
P3.4
VDDA
B
G
R
A0
RAMBK1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
P2.0
VSSC
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
P1.5
D3V3D
VCC
29
28
27
26
25
23
22
21
D7_SRAM
GPIO_P33
GPIO_P32
GPIO_P31
GPIO_P30
TT_SEL
U1502
D3V3D
SGND
Title
Size
15_TELETEXT_DECODER
Number
Revision
B
Date:
File:
1
18101
14-Oct-2005
Sheet of
F:\4228\4228_temp_ddb\4228_Temp.DDB Drawn By:
6
5
A5V
U1101
5V
L1112
VV33
4
R1121
C1114
C1113
C1109
C1112
TV_CVBS_M#
C1105
C1108
C1111
TAB
R1112
C1110
INPUT OUTPUT
GND
R1114
CVBS_O
D
C1164
Q1101
R1113
C1171
R1103
R1104
3230_VO
R1106
C1163
5VVV
MREST
3230_VO
SGND
RP1105
R1101
C1141
C1124
SDA_S3V
SCL_S3V
C1142 C1143
C1146
C1145
R1102
SGND
5VVV
SGND
RP1106
C1148
74
V_TVCVBS
C1117
73
C1150
R1116
C1151
C1115
75
C1118
71
C1119
72
C1120
C1121
SGND
L1102
C1128
R1117
V_SVideo_C
C1149
VIN3
VIN4
CIN
U1102
Y2/G2
U2/B2
SGND
C1156
R1118
V_TT_B
SGND
V_TT_R
V_TT_FSO
C1167
C1168
62
63
XTALI
XTALO
R1127
R1119
RP1101
RP1102
RP1103
RP1104
LLC2
LLC
HS
INTLC
AVO
HCLP
VS
VREF
VRT
SGND
31
32
33
34
37
38
39
40
RP1107
VUV7
VUV6
VUV5
VUV4
VY7
VY6
VY5
VY4
VY3
VY2
VY1
VY0
VUV7
VUV6
VUV5
VUV4
VUV3
VUV2
VUV1
VUV0
C1139
41
42
43
44
47
48
49
50
27
28
56
53
54 #VPEN
R1107
55
R1105
57
R1108
VUV3
VUV2
VUV1
VUV0
VY[7..0]
VB3
VB2
VB1
VB0
VB[7..0]
RP1109
#VPEN
VVVS
VVHS
VVCLK
VPEN
VVS
VHS
VCLK
VUV[7..0]
R1109
VVCLK
VVHS
R1123
R1110
VVCLK
VVHS
X1101
L1105
VVVS
78 REF_V
66
A5V
C1137 C1135
5V
C1138 C1136
C1103
C1123
L1103
5VVV
L1101
SGND
C1106
C1104
C1107
SGND
C1140
VYCbCr_Cb
C1134
C1130
C1131
SGND
SGND
A
L1106
VYCbCr_Cr
Title
SGND
Size
Number
Revision
B
Date:
File:
SGND
2
11-DECODERV
R1125 R1126
C1127
C1126
C1125
C1174
C1173
R1124
C1172
TT_VVHS
VVVS
TT_VVVS
C1133
VYCbCr_Y
C1132
L1104
VG[7..0]
VB7
VB6
VB5
VB4
RP1108
GND
ASGND
ASGND
PLGND
YGND
CGND
SPGND
AFGND
ISGND
ISGND
ISGND
I2CSEL
VGAV
TEST
OE#
C1154
Y1/G1
U1/B1
V1/R1
FBIN1
UV7
UV6
UV5
UV4
UV3
UV2
UV1
UV0
11
7
64
30
35
46
51
65
68
77
80
67
17
16
18
2
1
3
79
APGND
CLK5
FPDAT
CLK20
APVDD
C1166
25
60
58
24
26
V_TT_G
V_SVideo_Y
ADR:0x88
V2/R2
GNDCAP
12
C1122
L1111
VDDCAP
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
VIN2
VIN1
C1147
10
29
36
45
52
19
20
21
22
23
69
76
59
VDD
PLVDD
YVDD
CVDD
SPVDD
FFIE
FFWE
FFRST
FFRE
FFOE
AFVDD
ISVDD
VSTBY
C1116
SGND
L1108
70
R1115
C1159
VOUT
C1160
SCL
SDA
RST#
13
14
15
VV33
VG3
VG2
VG1
VG0
VY3
VY2
VY1
VY0
L1107
V_AVCVBS
VG7
VG6
VG5
VG4
VY7
VY6
VY5
VY4
C1144
19101
14-Oct-2005
Sheet of
F:\4228\4228_temp_ddb\4228_Temp.DDB Drawn By:
6
A5V
U1401
5V
GV33
D
R1412
C1409
C1405
C1414
4
C1413
TAB
L1412
C1412
C1411
GND
INPUT OUTPUT
C1410
R1414
CVBS_S_O
C1463
C1464
5VVG
Q1401
SGND
C1441
R1403
C1442 C1443
C1446
C1445
C1444
C1471
R1413
R1404
R1421
TV_CVBS_S#
MREST
C1424
SGND
G_AVCVBS
L1407
G_AVCVBS
5VVG
SGND
R1406
TV_CVBS_S
R1401
SDA_S3V
C1448
GV33
R1402
SGND
10
29
36
45
52
19
20
21
22
23
69
76
59
R1415
C1459
70
C1460
13
14
15
SCL_S3V
SGND
VDD
PLVDD
YVDD
CVDD
SPVDD
FFIE
FFWE
FFRST
FFRE
FFOE
AFVDD
ISVDD
VSTBY
L1408
VIN3
VOUT
74
SCL
SDA
RST#
C1416
G_TVCVBS
C1450
C1451
L1402
C1417
73
C1415
75
C1418
71
C1419
72
C1420
C1421
C1422
C1466
C1467
2
1
3
79
C1468
62
63
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
VIN2
R1416
SGND
G_SVideo_C
VIN4
C1449
SGND
U1402
VIN1
SGND
31
32
33
34
37
38
39
40
41
42
43
44
47
48
49
50
UV7
UV6
UV5
UV4
UV3
UV2
UV1
UV0
CIN
R1417
C1428
Y2/G2
RP1402
GBE7
GBE6
GBE5
GBE4
GBE3
GBE2
GBE1
GBE0
RP1403
RP1404
L1405
GYCbCr_Cb
G_TT_R
G_TT_FSO
R1427
R1425 R1426
C1432
R1419
C1427
C1426
C1425
C1474
C1473
R1424
X1401
11
7
64
30
35
46
51
65
68
77
80
67
17
16
18
25
60
58
24
26
R1409
R1410
R1408
R1407
R1422
R1405
GHS R1423
GCLK
GHS
FIELD
GPEN
TT-GHS
GVS
GHS
TT-GHS
C1437 C1435
C1438 C1436
C1433
5V
C1423
C1440
REF_G
78
66
VREF
VRT
L1406
GYCbCr_Cr
C1472
XTALI
XTALO
GYCbCr_Cr
GBE[7..0]
GND
ASGND
ASGND
PLGND
YGND
CGND
SPGND
AFGND
ISGND
ISGND
ISGND
I2CSEL
VGAV
TEST
OE#
G_TT_B
12
GYCbCr_Cb
L1404
Y1/G1
U1/B1
V1/R1
FBIN1
APGND
CLK5
FPDAT
CLK20
APVDD
G_TT_G
27
28
56
53
54
55
57
LLC2
LLC
HS
INTLC
AVO
HCLP
VS
ADR:0x8E
V2/R2
GNDCAP
R1418
U2/B2
VDDCAP
C1456
SGND
GYCbCr_Y
GGE[7..0]
C1439
GYCbCr_Y
GGE7
GGE6
GGE5
GGE4
GGE3
GGE2
GGE1
GGE0
RP1401
L1411
G_SVideo_Y
C1454
TV_CVBS_S
C1447
R1420
SGND
5VVG
SGND
5VVG
L1401
SGND
C1403
C1406
C1404
C1407
C1434
SGND
SGND
C1430
C1431
SGND
A
Title
Size
14-DECODER_G
Number
Revision
B
Date:
File:
1
20101
14-Oct-2005
Sheet of
F:\4228\4228_temp_ddb\4228_Temp.DDB Drawn By:
6
C860
C861
U803
6
SGND 5
TT_VVHS
3230_VO
C855
R857
7
8
9
SCK
SEN
I2C/SEL
SMS
SDO
HIN
BOX
VIDEO
VDD
CSYNC
LPF
V_TT_R
R861
V_TT_G
R862
V_TT_B
V_TT_R
D
V_TT_G
V_TT_B
1
16 SGND
R815
R863
17
V_TT_FSO
V_TT_FSO
5V_V_CCD
12
SCL_S5V
SCL_S5V
10
RREF
11
VSS(A)
R854
Q801
SCL_S3V
V33SW
5V
5V_V_CCD 4
R860
C865
15
SDA
18
C864
R856
R867
SCL_S5V
Vin/INTRO
C863
14
R866
R855
C862
SDA_S5V
R865
TT_VVVS
R864
13
R852
SGND
A5V
R853
L801
C
C856
C857
C858
C859
R858
Q802
C
R859
C804
C806
C803
C807
SDA_S5V
SDA_S5V
SDA_S3V
R814
SGND
C814
SGND
C815
U802
4
6
SGND 5
TT-GHS
TV_CVBS_S
C809
R803
7
8
9
SEN
I2C/SEL
SMS
SDO
HIN
BOX
VIDEO
VDD
CSYNC
RREF
LPF
G_TT_R
R807
G_TT_G
R808
G_TT_B
G_TT_R
G_TT_G
G_TT_B
1
16
B
R809
17
G_TT_FSO
G_TT_FSO
12
10
11
VSS(A)
C820
5V_G_CCD
SCK
R806
C819
15
18
R813
R802
C818
SCL_S5V
SDA
R812
14
R811
R801
C817
SDA_S5V
Vin/INTRO
R810
13
GVS
R804
SGND
A5V
5V_G_CCD
C810
C811
C812
C813
L802
R805
C802
C808
SGND
C805
C801
SGND
Title
Size
8-CCD_DECODER
Number
Revision
A4
Date:
File:
1
21101
14-Oct-2005
Sheet of
F:\4228\4228_temp_ddb\4228_Temp.DDB Drawn By:
4
4
D3V3B
5
D3V3B
R1305
U1301D
R1322
R1308
GRO[7..0]
GGO[7..0]
GBO[7..0]
GGE0
GGE1
GGE2
GGE3
GGE4
GGE5
GGE6
GGE7
C11
B12
B11
A8
B8
C8
A7
B7
GBE0
GBE1
GBE2
GBE3
GBE4
GBE5
GBE6
GBE7
B18
A20
B17
A19
B16
A17
A16
A15
GRO0
GRO1
GRO2
GRO3
GRO4
GRO5
GRO6
GRO7
A6
C7
B6
A5
D7
B5
C6
A4
GGO0
GGO1
GGO2
GGO3
GGO4
GGO5
GGO6
GGO7
C13
B15
A14
B14
A13
C12
B13
A12
GBO0
GBO1
GBO2
GBO3
GBO4
GBO5
GBO6
GBO7
C18
E17
C17
B19
E16
C16
C15
D14
GRE0
GRE1
GRE2
GRE3
GRE4
GRE5
GRE6
GRE7
X1301
C1302
GBE0
GBE1
GBE2
GBE3
GBE4
GBE5
GBE6
GBE7
GRO0
GRO1
GRO2
GRO3
GRO4
GRO5
GRO6
GRO7
R1303
U1301B
E1
E3
F3
D1
N2
VCLK
VVS
VHS
FIELD
VPEN
VR[7..0]
VG[7..0]
VB[7..0]
GGO0
GGO1
GGO2
GGO3
GGO4
GGO5
GGO6
GGO7
V11
W11
IR_181
NMI
C1301
GGE0
GGE1
GGE2
GGE3
GGE4
GGE5
GGE6
GGE7
Y12
V12
RXD
TXD
VR0
VR1
VR2
VR3
VR4
VR5
VR6
VR7
E2
F1
F2
G3
G2
H3
H2
G1
VG0
VG1
VG2
VG3
VG4
VG5
VG6
VG7
J4
H1
J3
J2
J1
K3
K2
K1
VB0
VB1
VB2
VB3
VB4
VB5
VB6
VB7
L2
L1
L3
L4
M3
M1
N1
M2
VCLK
VVS
VHS
FIELD
VPEN
R1304
GAFEOE
MUTE
SEL1
SEL0
REMARK:
HARDWARE I2C: SDA1 SCL1
SOFTWARE I2C: VSDA VSCL
VR0
VR1
VR2
VR3
VR4
VR5
VR6
VR7
D1302
R17
W18
V18
Y18
U18
Y19
W19
T18
KEY0
KEY1
KEY2
KEY3
KEY4
KEY5
KEY6
SP_RELAY
D3V3B
R1309
D3V3B
Q1303
T17
V16
W16
Y16
V17
U17
W17
Y17
R1310
3450_rest
P1
Y2
M4
N3
R1332
R1331
VB0
VB1
VB2
VB3
VB4
VB5
VB6
VB7
D3V3B
D3V3B
R1326
SCL_H5V
SCL_H5V
U16
N4
T5
P2
R1313
U15
R1315
PORTC0
PORTC1
PORTC2
PORTC3
PORTC4
PORTC5
PORTC6
PORTC7
CPUTMS
CPUTCK
CPUDI
CPUDO
MODE0
MODE1
MODE2
MODE3
ADR24B
INPUT OUTPUT
C1303
TAB
C1324
S
RD
WR
BHEN
ROMOE
ROMWE
RAMOE
RAMWE
CS1
CS0
EXTINT
NMI
DNC1
DNC2
DNC3
V10
Y10
Y9
W9
V9
Y8
W8
V8
W7
U8
V7
W6
Y6
V6
U7
U6
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
W3
Y3
W12
V5
W4
W5
Y5
Y4
V4
U10
W10
DRE1
DRE5
DRE6
DRE0
DCLK
DVS
DHS
DEN
DRE7
DRE3
DRE2
DRE4
DGE1
DGE0
DGE3
DGE2
DGE7
DGE6
DGE5
DGE4
D[15..0]
DBE0
DBE3
DBE1
DBE2
DBE4
DBE7
DBE6
DBE5
Y20
W20
V20
V19
DR1 RP1302
DR5
DR6
DR0
DRE1
DRE5
DRE6
DRE0
U20
U19
R16
R18
DR7 RP1303
DR3
DR2
DR4
DRE7
DRE3
DRE2
DRE4
T20
T19
R20
R19
DG1 RP1304
DG0
DG3
DG2
DGE1
DGE0
DGE3
DGE2
P20
P19
P18
M18
DG7 RP1305
DG6
DG5
DG4
DGE7
DGE6
DGE5
DGE4
M17
L17
N20
M20
DB0 RP1306
DB3
DB1
DB2
DBE0
DBE3
DBE1
DBE2
M19
L20
L19
K17
DB4 RP1307
DB7
DB6
DB5
DBE4
DBE7
DBE6
DBE5
K19
DRO0
K20
DRO1
K18
DRO2
J20
PW181 Display Port
DRO3
J18
DRO4
J19
DRO5
H20
DRO6
H19
DRO7
DGO0
DGO1
DGO2
DGO3
DGO4
DGO5
DGO6
DGO7
ROMOEn
ROMWEn
DBO0
DBO1
DBO2
DBO3
DBO4
DBO5
DBO6
DBO7
B20
C19
V14
H18
H17
G20
G19
G18
F20
F19
F18
E20
E19
E18
F17
D20
D19
D16
D17
C1304
4
C1355
DR1
DR5
DR6
DR0
DR7
DR3
DR2
DR4
DG1
DG0
DG3
DG2
DG7
DG6
DG5
DG4
DB0
DB3
DB1
DB2
DB4
DB7
DB6
DB5
V25
L1302
RP1308
DGE[7..0]
RP1309
RP1310
RP1311
RP1312
RP1313
DRE[7..0]
DRE3
DRE7
DRE0
DRE2
DRE1
DRE5
DRE4
DRE6
DGE3
DGE2
DGE5
DGE4
DGE[7..0]
DGE1
DGE0
DGE7
DGE6
DBE[7..0]
DBE2
DBE5
DBE3
DBE4
DBE6
DBE1
DBE0
DBE7
C1325
C1326
SDA_H3V
DBE[7..0]
D0
D1
D2
D3
D4
D5
PW181 MISC
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
A[19..1]
U1302
5V
Q1302
SDA_H5V
PORTB0
PORTB1
PORTB2
PORTB3
PORTB4
PORTB5
PORTB6
PORTB7
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
RNMI2
D3V3C
R1317
R1318
R1319
R1320
DRE[7..0]
U4
T4
V3
U3
Y1
W2
T3
V2
U2
W1
R4
V1
P4
R3
T2
U1
T1
R2
R1
P3
SCL_H3V
R1316
SDA_H5V
PORTA0
PORTA1
PORTA2
PORTA3
PORTA4
PORTA5
PORTA6
PORTA7
Q1301
R1314
5Vstby
IRRCVR0
IRRCVR1
R1324
R1311
R1312
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
RXD
TXD
R1325
R1334
GBO0
GBO1
GBO2
GBO3
GBO4
GBO5
GBO6
GBO7
RESET
MCKEXT
DCKEXT
XI
XO
R1333
COMMUNIC
P_SCLK
P_SDATA
P_SLE
DTXON
HPD_DET
MREST
VG0
VG1
VG2
VG3
PW181 Video Port
VG4
VG5
VG6
VG7
V13
W13
Y13
Y14
W14
Y15
W15
V15
SDA_H3V
SCL_H3V
SDA_H3V
SCL_H3V
SDA_S3V
SCL_S3V
GND
GBE[7..0]
E4
C3
B1
F4
C2
C1
D3
D2
R1301
GGE[7..0]
GRE0
GRE1
GRE2
GRE3
GRE4
GRE5
GRE6
GRE7
Y11
E5
D6
A3
C5
VGASEL
A11
D10
C14
A18
C9
GFBK
GREF
GBLKSPL
GCOAST
GHSFOUT
GCLK
GPEN
GVS
GHS
GSOG
J17
C20
D18
N19
R1323
U1301A
A10
B9
A9
C10
B10
8
C1354
DCLK
DVS
DHS
DEN
R1321
R1307
GCLK
GPEN
GVS
GHS
GSOG
GRE[7..0]
7
U1301C
RESET
R1306
GCOAST
GBLKSPL
GFBK
R1329
181 LVDS
R0
R6
R1
R7
R2
R0
R3
R1
R4
R2
R5
R3
R6
R4
R7
R5
D3V3B
R1335
U1303
D3V3B
V25
V15p
V15
D3V3B
3
TAB
V15
L1304
C1313
C1314 C1315
4
C1357
C1312
C1344
T15
T14
T13
T12
T11
T10
T9
T7
T6
R15
R14
R13
P16
P15
P6
P5
N16
N15
N6
N5
L5
K16
K5
J5
H16
H5
F16
E15
E14
E13
E12
E11
E10
E9
E7
C4
B4
VPP2
VPP1
VDD35
VDD34
VDD33
VDD32
VDD31
VDD30
VDD29
VDD28
VDD27
VDD26
VDD25
VDD24
VDD23
VDD22
VDD21
VDD20
VDD19
VDD18
VDD17
VDD16
VDD15
VDD14
VDD13
VDD12
VDD11
VDD10
VDD9
VDD8
VDD7
VDD6
VDD5
VDD4
VDD3
VDD2
VDD1
U13
U11
U9
U5
T16
A2
VCC6
VCC5
VCC4
VCC3
VCC2
VCC1
VIO19
VIO18
VIO17
VIO16
VIO15
VIO14
VIO13
VIO12
VIO11
VIO10
VIO9
VIO8
VIO7
VIO6
VIO5
VIO4
VIO3
VIO2
VIO1
T8
R8
R7
R6
M16
M5
L16
J16
G16
G15
G6
G5
F15
F14
F7
F6
F5
E8
E6
GND
INPUT OUTPUT
U1301E
V15
C1333 C1334 C1335 C1336 C1337 C1338 C1339 C1340 C1341 C1342 C1343
V15p
L1301
GND59
GND58
GND57
GND56
GND55
GND54
GND53
GND52
GND51
GND50
GND49
GND48
GND47
GND46
GND45
GND44
GND43
GND42
GND41
GND40
GND39
GND38
GND37
GND36
GND35
GND34
GND33
GND32
GND31
GND30
GND29
GND28
GND27
GND26
GND25
GND24
GND23
GND22
GND21
GND20
GND19
GND18
GND17
GND16
GND15
GND14
GND13
GND12
GND11
GND10
GND9
GND8
GND7
GND6
GND5
GND4
GND3
GND2
GND1
C1349 C1350
C1332
Y7
U14
U12
R5
P17
N18
N17
N13
N12
N11
N10
N9
N8
M13
M12
M11
M10
M9
M8
L18
L13
L12
L11
L10
L9
L8
K13
K12
K11
K10
K9
K8
K4
J13
J12
J11
J10
J9
J8
H13
H12
H11
H10
H9
H8
H4
G17
G4
D15
D13
D12
D11
D9
D8
D5
D4
B3
B2
A1
C1346
Title
Size
Date:
File:
1
13-SCALER
Number
Revision
A3
22101
14-Oct-2005
Sheet of
F:\4228\4228_temp_ddb\4228_Temp.DDB Drawn By:
7
31RAMA0 40
31RAMA1 38
31RAMA2 36
31RAMA3 34
31RAMA4 33
31RAMA5 35
31RAMA6 37
31RAMA7 39
31RAMA8 41
31RAMA9 43
31RAMA10 42
31RAMA11 45
31RAMA12 46
31RAMA13 44
U1201A
VUV[7..0]
95
96
97
98
99
100
101
102
VUV0
VUV1
VUV2
VUV3
VUV4
VUV5
VUV6
VUV7
109
110
111
112
113
114
115
116
105
106
107
108
VVCLK
VVVS
VVHS
DG0
DG1
DG2
DG3
DG4
DG5
DG6
DG7
VG0
VG1
VG2
VG3
VG4
VG5
VG6
VG7
VR0
VR1
VR2
VR3
VR4
VR5
VR6
VR7
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
RP1201
VR0
VR1
VR2
VR3
VR4
VR5
VR6
VR7
RP1202
149
150
151
152
153
154
155
156
RP1203
139
140
141
142
143
144
145
148
RP1205
RP1204
ADSVM
ADR
ADG
ADB
VREFIN
VREFOUT
RSET
COMP
127
128
129
130
131
125
126
117
118
VB[7..0]
R1203
132
MREST
R1215
C1244
73
72
135
X1201
74
136 R1212
PW1231 VIDEO BLOCK
DCLK
137 R1211
DVS
138 R1213
DHS
PVCLK
CREF
PVVS
PVHS
U1201B
R1204
R1205
R1206
R1207
R1208
119
120
VB0
VB1
VB2
VB3
VB4
VB5
VB6
VB7
RP1206
V33SW
C1201 C1202
VG[7..0]
VG0
VG1
VG2
VG3
VG4
VG5
VG6
VG7
V33SW
R1201 R1202
C1241
VCLK
VVS
VHS
12
21
18
15
C1218
81
TDO
TCK
TDI
TMS
TRST
I2CA1
I2CA2
V33SW
51
MCLK
R1209 R1210
C1204
TESTCLK
TEST
CGMS
MACRO
38
C1203
V25SW
3
INPUT OUTPUT
R1214
25
TAB
31RAMA0 23
31RAMA1 24
31RAMA2 25
31RAMA3 26
31RAMA4 29
31RAMA5 30
31RAMA6 31
31RAMA7 32
31RAMA8 33
31RAMA9 34
31RAMA10 22
31RAMA11 35
2
C1242
AV331
U1204
C1211
5V
V33SW
INPUT OUTPUT
GND
C1243
TAB
2
4
C1245
31RAMA12 20
31RAMA13 21
C1222
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
BA0
BA1
U1203
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
CKE
8
71
104
134
1
9
53
79
91
122
147
78
76
123
11
29
32
17
20
23
14
VSS0
VSS1
VSS2
VSS3
U1201D
PVSS0
PVSS1
PVSS2
PVSS3
PVSS4
PVSS5
PVSS6
DPAVSS
DPDVSS
MPAVSS
ADDVSS
ADAVSS
ADGVSS
AVS33B
AVS33G
AVS33R
VDD0
VDD1
VDD2
VDD3
PVDD0
PVDD1
PVDD2
PVDD3
PVDD4
PVDD5
PVDD6
DPAVDD
DPDVDD
MPAVDD
7
70
103
133
30
52
80
90
121
146
160
AVS33SVM AVD33SVM
31RAMD0
31RAMD1
31RAMD2
31RAMD3
31RAMD4
31RAMD5
31RAMD6
31RAMD7
31RAMD8
31RAMD9
31RAMD10
31RAMD11
31RAMD12
31RAMD13
31RAMD14
31RAMD15
2
4
5
7
8
10
11
13
42
44
45
47
48
50
51
53
37
B
C1226
V25SW
V33SW1
V33SW
V25SW
AV25A V33SW
L1201
AV331
L1205
C1249
77
75
C1250
AV25p2
124
V33SW
L1203
16
19
22
V33SW1
V25SW
AV25P1
L1204
AV331
C1247
V25SW
AV25P2
L1202
C1224 C1225
C1246
Title
13
Size
12-DEINTERLACE
Number
Revision
B
Date:
File:
1
6
12
28
41
46
52
54
19
15
39
36
40
16 31WEn
17 31CASn
18 31RASn
V33SW
VssQ
VssQ
Vss
Vss
VssQ
VssQ
Vss
/CS
DQML
DQMH
NC
NC
WE
CAS
RAS
CLK
U1202
24
R1216
R1217
R1218
V33SW
DEN
C1251
26
27
48
49
50
MRAS
MCAS
MWE
U1201C
RESET
5V
ADR:0x64
47
SCL
SDA
1
3
9
14
27
43
49
VY[7..0]
VY0
VY1
VY2
VY3
VY4
VY5
VY6
VY7
SVHS
SVVS
SVCLK
157
158
159
2
3
4
5
6
31RAMD15
31RAMD14
31RAMD13
31RAMD12
31RAMD11
31RAMD10
31RAMD9
31RAMD8
31RAMD7
31RAMD6
31RAMD5
31RAMD4
31RAMD3
31RAMD2
31RAMD1
31RAMD0
68
MD15
66
MD14
64
MD13
62
MD12
60
MD11
58
MD10
56
MD9
54
MD8
55
MD7
57
MD6
59
MD5
61
MD4
63
MD3
PW1231 MEMORY
65 BLOCK
MD2
67
MD1
69
MCLKFB
MD0
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
MA12
MA13
Vdd
VddQ
VddQ
Vdd
Vdd
VddQ
VddQ
92
93
94
DR0
DR1
DR2
DR3
DR4
DR5
DR6
DR7
GND
VB0
VB1
VB2
VB3
VB4
VB5
VB6
VB7
SCL_S3V
SDA_S3V
82
83
84
85
86
87
88
89
VR[7..0]
23101
14-Oct-2005
Sheet of
F:\4228\4228_temp_ddb\4228_Temp.DDB Drawn By:
6
R104
5V
C1026
D
2
3
S1A
S2A
HD1_R/Pr
DA
INPUT OUTPUT
C102
TAB
YPbPr_Pb
VGA B
S1B
S2B
11
10
VGASEL
HD1_G/Y
HD1_B/Pb
DC
C110
HD1_G/Y
I2S_DATA
12
DD
IN
EN
3
R101
I2S_MCLK
SCLK
VA
LRCK
GND
MCLK
VQ
10
AOUTR
LRCK/L
C111
9
8
C109
L
AQUTL
R103
DATA/R
C112
FILT+
C108
C107
C106
R102
TVDD3.3V
14
SGND
R1005
R1007
1
VGAHS
R1009
U1007A
R1015
C104
DATA
I2S_SCLK
HD1_B/Pb
I2S_LRCLK
S1D
S2D
1
15
DB
S1C
S2C
14
13
VGASEL
U1004
U102
C105
YPbPr_Pb
5
6
YPbPr_Y
VGA G
GND
YPbPr_Y
C103
HD1_R/Pr
1
YPbPr_Pr
VGA R
C101
VCC
YPbPr_Pr
SGND
Audio DAC
U101
16
L1004
L101
GND
A5V
VGA_HS
VGA_HS
U1007B
C1041
R1010
10
13
U1007C
R1016
5V
VGA_VS
12
5V
VGA_VS
U1007D
C1042
D1006 R1019
D1007
R1020
R1021
D1015
5V
5V
D1001
5V
VGA5V
2
R1008
11
R1006
VGAVS
5V
D1002
D1004
D1005
3
D1003
VGA5V
JP1001
U1008
7
6
5
4
DDCC
15
VGAVS
14
VGAHS
13
DDCC
DDCD
5
10
4
9
3
8
2
7
1
6
12
DDCD
11
L1001
C1003
VGA G
L1003
SC102
SC101
SC103
SC104
VGA R
R1011
R1013
Title
Size
Date:
File:
AGND
2
24101
Number
Revision
A4
SGND
10-PROGRESSIVE_ADC
16
R1012
SGND
8
1
2
3
VCC
NC1
NC2
NC3
R1022
L1002
A
17
VGA B
VCLK
SCL
SDA
GND
21-Jan-2006
F:\4238\PC_B\4238.DDB
Sheet of
Drawn By:
4
ADR:0xA0/MEMORY
ADR:0xD0/COMPANION
U401
26
28
11
12
14
47
ROMOEn
ROMWEn
RESETn
D3V3B
R401
CE
OE
WE
RESET
NC
BYTE
25
24
23
22
21
20
19
18
8
7
6
5
4
3
2
1
48
17
16
D3V3B
37
Vdd
29
31
33
35
38
40
42
44
30
32
34
36
39
41
43
45
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
R402
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
13
NC
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
C401
C418 C419
SW402
U402
D3V3B
1
R408
R404
NMI
R407
C406
46
27
L401
C417
R410
D15
D14
D5
D4
D3
D2
D9
D8
2
1
U404
3
4
D3V3B
C410
A1
A3
A5
A7
A8
A10
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
R411
R412
R413
TXD
TXD
R417
RXD
R416
11
10
RXD
12
9
C415
C2+
V-
C412
JP403
C2T1_IN
T1_OUT
T2_IN
T2_OUT
R1_OUT
R1_IN
R2_OUT
R2_IN
14
L403
232_IN
7
13
1
6
2
7
3
8
4
9
5
232_OUT
L402
8
C413
C414
B
10
C416
C411
V+
C1-
GND
R418
A13
A15
A16
A18
C1+
15
A17
A19
NC0
5V#
C420
JP402
A12
A14
NC1
VCC
D3V3B
WP
4
3
L405
C409
A9
A11
NC2
D3V3B
2
4
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
GND
SCL
5V
A2
A4
A6
SDA
C402
Vss
Vss
JP401
1
3
L404
5V
R409
SCL_H5V
R405
5Vstby
FLASH_8M
SDA_H5V
9
10
15
A19
NC
RY/BY
11
16
A[19..1]
VCC
D7
D6
D13
D12
JP404
D3V3B
R419
TXD
RXD
D11
D10
R414
C405
7
R420
R421
R415
U403
SW401
D1
D0
2
RSTINn
TLCCT
3
1
C408
C407
SENCE Vdd
RESin
RESET
CT
RESET
CONTROL
GND
5V
SDA#SO
SCL#SO
4
3
2
1
SDA#SO
SCL#SO
R422
6
RESET
RESET
RESETn
4
R406
D[15..0]
A
Title
Size
4-FLASH
Number
Revision
A3
Date:
File:
1
25101
14-Oct-2005
Sheet of
F:\4228\4228_temp_ddb\4228_Temp.DDB Drawn By:
7
TX0+
TX1-
C523
C525
SCL_S3V
C502
R501
L505
PDPGO
R511
TX2-
10
TX2+ 11
12
P_SDATA#
13
14
P_SCLK#
CK+ 15
16
P_SLE#
TX3- 17
18
P_DISPEN#
TX3+ 19
20
CKC501
R513
R510
TX1+
P_SDATA
D
P_SCLK
C528
SDA_S3V
L506
IRQ
P_SLE
P_SLE
C529
L503
PDWN
P_DISPEN
P_DISPEN
RS
C526
R502
For LG panel standard LVDS jack
31
SGND
DCLK
DCLK
DRE[7..0]
DGE[7..0]
DBE[7..0]
DHS
DVS
DEN
DHS
DVS
DEN
DRE2
DRE3
DRE4
DRE5
DRE6
DRE7
DRE0
DRE1
DGE2
DGE3
DGE4
DGE5
DGE6
DGE7
DGE0
DGE1
DBE2
DBE3
DBE4
DBE5
DBE6
DBE7
DBE0
DBE1
51
52
54
55
56
3
50
2
4
6
7
11
12
14
8
10
15
19
20
22
23
24
16
18
27
28
30
25
TxCLK_IN
TxIN0
TxIN1
TxIN2
TxIN3
TxIN4
TxIN6
TxIN27
TxIN5
TxIN7
TxIN8
TxIN9
TxIN12
TxIN13
TxIN14
TxIN10
TxIN11
TxIN15
TxIN18
TxIN19
TxIN20
TxIN21
TxIN22
TxIN16
TxIN17
TxIN24
TxIN25
TxIN26
TxIN23
TxOUT0TxOUT0+
TxOUT1TxOUT1+
TxOUT2TxOUT2+
TxOUT3TxOUT3+
TxCLKOUTTxCLKOUT+
U501
PWR_DWN
R_FB
48
47
46
45
42
41
38
37
40
39
TX0TX0+
TX1TX1+
TX2TX2+
TX3TX3+
CKCK+
32 DTXON
17
LVD33
/ DS90C385AMTD
PLL_GND
PLL_GND
LVDS_GND
LVDS_GND
LVDS_GND
1
2
3
4
5
6
7
TX28
TX2+
9
CK10
CK+
11
TX312
TX3+
13
14
15
16
17
18
19
20
21
22
23
24
25
26
p_dispen# 27
p_sdata# 28
p_sclk#
29
p_sle#
30
31
TX0TX0+
TX1TX1+
For LG panel
35
33
R508
49
43
36
DTXON
R509
NC
U502
5V
LVD33
3
INPUT OUTPUT
GND
LVD_VCC
C521
TX0-
P_SDATA
C527
TAB
2
4
C507
C505
C510
SGND
Title
5
13
21
29
53
Size
5-LVDS&TMDS
Number
Revision
00
A4
Date:
File:
1
26101
C506
1
NC
L502
C524
22
C522
21
TX3TX3+
C520
L504
CPUGO
R504
44
34
CKCK+
JP501
LVDS_VCC
PLL_VCC
TX2TX2+
R503
LVD_PLL33
1
9
26
TX1TX1+
L501
VCC
VCC
VCC
R512
LVD33
GND
GND
GND
GND
GND
TX0TX0+
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
14-Oct-2005
Sheet of
F:\4228\4228_temp_ddb\4228_Temp.DDB Drawn By:
4
ANDY
3
U604
D3V3B
5V
D3V3#
C623
C614
C622
TAB
D3V3#
5VSC
C613
1
OUTPUT INPUT
TAB
C601
RELAY_ON#
C603
U603
5Vstby#
D3V3C
1
2
3
4
5
6
7
8
9
D605
C621
5
JP608
D6V
OUTPUT INPUT
GND
L606
R630
L602
5V
D
5VSC
L607
JP607
L608
C624
C618
C626
C625
R628
C617
1
2
3
4
5
6
7
8
9
10
11
L605
5Vstby
RELAY_ON
L623
R629
C630
C651
C654
C655
C612
C602
VS_ON
5VDetect
RELAY_ON#
5Vstby#
L624
VS_ON#
L625
C649
D3V3_TT_A
R635
U601
PA3
PA4
PA2
PA5
18
mut#
MUTE
R627
SB_5VCN
17
key_stby
key_stby
17
Q606
Q605
5VDetect
PA1
PA6
16
SDA#
5VDetect
PA1
PA6
16 SDA#
R617
SDA_H5V
D3V3B
5Vstby
R624
5Vstby
PA0
PA7
15 SCL#
R618
SCL_H5V
C629
P_DISPEN
COMMUNIC 6
PB2
OSCO
PB1/_BZ
OSCI
PB0/BZ
VDD
14
OSCO
13
OSCI
P_DISPEN
COMMUNIC
P_DISPEN
COMMUNIC
R616
PB2
OSCO
PB1/_BZ
OSCI
PB0/BZ
VDD
14
OSCO
13
OSCI
5V_mcu
7
VSS
/RES
C608
RST
VSS
/RES
R622 R623
IR_mcu
R631
R633
Q607
X601
12
11 RST
C610
R620
C611
5Vstby
B
9
PC0/_INT PC1/TMR
IR_mcu
10
PC0/_INT PC1/TMR
D3V3B
C609
R606
RELAY_ON
R610
C633
Q601
R607
R603
JP604
To Key Board
Q602
A
13
12
11
10
9
8
7
6
5
4
3
2
1
STANDBY
P+
PVV+
MENU
INPUT
L611
L612
L613
L614
L615
L616
L617
C635
R602
P_ON/SLEEP
D602
D603
D604
KEY0
KEY1
KEY2
KEY3
KEY4
KEY5
KEY6
R605
C634
5Vstby
R601
R609
R615
D3V3B
D3V3B
10
R608
IR_mcu
IR_5V
R632
R625
5V_mcu
12
11
R621
IR_181
R626
8
R619
C640
P_ON/SLEEP
R611
PA7
SCL#
C636
PA0
15
LED_G
L620
L621
L622
C628
P_ON/SLEEP 4
5V
C641
VS_ON
R614
PA5
mut#
R613
PA2
18
C639
PA4
LED_R
R612
PA3
D601
C644
Q603
U602
C632
R643
R642
R641
R640
R639
5Vstby
C637
VS_ON
SGND
1
VS_ON#
RELAY_ON#
C642
C648
D610
L629
C643
C650
C638
C631
L601
5V_mcu
R604
Title
Size
6-POWER MANAGE
Number
Revision
B
Date:
File:
1
From pannel
GND
27101
14-Oct-2005
Sheet of
F:\4228\4228_temp_ddb\4228_Temp.DDB Drawn By:
6
5V_E
R765
V_TVCVBS
R705
Cr
Q733
Q734
C760
GYCbCr_Cr
C762
R749
C701
C763
GYCbCr_Y
C765
R763
C766
R767
SGND
A5V
SGND
5V_E
R787
L738
JP701
VCC
C711
C702
C710
R721
R719
SGND
GYCbCr_Cb
4 Pb_in
R730
Cb
R741
Q701
A5V
VYCbCr_Cb
R736
R720
C753
R722
Cb_in#
SGND
Cr_in#
C738
GYCbCr_Cr
VYCbCr_Cr
R751
R737 R724
L752
TT_R
TT_R
SC1_R
2
3
TT_G
TT_G
SC1_G
5
6
TT_B
SC1_B
11
10
TT_FSO
SC1_BOX
14
13
TT_SEL
1
15
Q702
D702
YUV_Y_in
R709
S1A
S2A
R726
SGND
SGND
TT_B
C739
C754
TT_FSO
TT_SEL
5V_E
C709
U704
DB
S1C
S2C
DC
S1D
S2D
V_TT_G
V_TT_B
V_TT_R
V_TT_B
DVI_L_IN#
R776
DVI_L_IN 3
V_TT_FSO
DVI_R_IN#
R780
DVI_R_IN 2
AGND
SGND
JP707
5V
VGA_L4#
SC2_BOX
R784
V2
R791
VYCbCr_Y
R738
D704
R753
R728
C714
C752
C755
C713
C715
C716
C718
R788
R773
SC2_R
R785
C2
R774
SC2_G
R786
Y2
R775
SC2_B
VGA_R4#
R713
Q703
YPbPr_Pb
5V
C746
R772
C729
L753
SGND
R777
VGA_L4
R781
VGA_R4
3
4
2
1
C733
A5V R794
R732
R714
Pb_in
C2
V2
Y2
JP705
GYCbCr_Y
C751
V2
C2
Y2
AGND SGND
SGND
R729
R727
D703
R752
A5V
V_TT_G
5V
C744
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
JP703
12 V_TT_FSO
DD
IN
EN
YUV_Y_in#
SGND
4 V_TT_R
DA
S1B
S2B
V_AVCVBS
V_SVideo_C
V_SVideo_Y
A5V
L739
R731
Cr
5V
C742
R707
16
R723
49
47
45
43
41
39
37
35
33
31
29
27
SDA_S5V 25
3450_rest 23
21
MUTE
SP_RELAY 19
3230_VO 17
15
TV_M
TV_S
13
V_AVCVBS11
V_SVideo_C 9
V_SVideo_Y 7
AV_LOUT 5
AV_ROUT 3
1
+8V
SDA_S5V
3450_rest
MUTE
SP_RELAY
3230_VO
R711
L751
R725
GPIO_P32
GPIO_P33
SC2_BOX
SC2_R
SC2_G
SC2_B
SC1_SW
SC1_BOX
SC1_R
SC1_G
SC1_B
R768
R769
R770
R771
A5V
R708
C708
SGND
D701
R750
Cr_in
GND
C706
5V_E
5V
C740
VCC
R706
R790
Cb_in
VOUT
SC2_SW
GPIO_P31
GPIO_P30
VF
RFC
AGND
L750
SGND
G_TVCVBS
C707
VCC
SGND
C737
GSEL
ENABLE
L749
R742
SGND
VIN
C736
5 YUV_Y_in
7
C705
TV_S
GND
6 HD_Y_in
GPIO_P32
GPIO_P33
G_TT_FSO
G_TT_R
G_TT_G
G_TT_B
SC1_SW
U703
SGND
3 Cb_in
G_TVCVBS
R710
1 Cr_in
SCL_S5V
SCL_S5V
SC2_SW
GPIO_P31
GPIO_P30
R704
R702
V_AVCVBS
R743
G_AVCVBS
G_AVCVBS
GND
R701
R733
R703
C704
V_SVideo_C
R744
G_SVideo_C
G_SVideo_C
VOUT
V_SVideo_Y
R734
C703
VF
RFC
4
SGND
GSEL
ENABLE
L748
A5V
R745
G_SVideo_Y
G_SVideo_Y
VIN
Q735
GYCbCr_Cb
C759
R735
V_TVCVBS
U702
Y
TV_M
R761
Cb
R712
R748
5V_E
C728
5V_E
C732
SGND
SGND
SGND
AGND
JP704
SGND
8V_4052
YPbPr_Y
DVI_L_IN#
C719
VGA_L4#
C720
YPbPr_L_IN#
C721
5V
C750
R755
D706
AV_L1
AV_L2
AV_L3
AV_L4
1
5
2
4
Y0A
Y1A
Y2A
Y3A
Y0B
Y1B
Y2B
Y3B
ZA
ZB
A1
A0
E
13 R_O C756
AV_ROUT
AV_LOUT
L_O C757
YUV_L_IN#
R740
R739
AV_L2
R77
AV_L3
R78
AV_L4
R79
R71
9
10
AGND
6
SEL1
SEL1
C743
R792
R793
Q704
Q705
SEL0
Date:
File:
4
28101
7-VIDEO&AUDIO IN
Number
Revision
A3
C725
AGND
Size
C741
SGND
2
YPbPr_R_IN 2
Title
SEL0
AGND
1
YPbPr_L_IN 4
R782
AV_L1
YUV_R_IN 1
R778
YPbPr_R_IN#
R718
12
14
15
11
R76
R783
YPbPr_L_IN#
C731
AV_R1
AV_R2
AV_R3
AV_R4
R75
YUV_R_IN#
R717
C726
AV_R4
R70
C735
C724
YUV_R_IN#
VDD
YPbPr_R_IN#
VSS
VEE
HD_Y_in
SGND
8
7
L755
8V_4052
AV_R3
R74
R716
AGND
AGND U701
R73
C730
C723
R72
AV_R2
R715
R759
AV_R1
YUV_L_IN 3
C734
VGA_R4#
C787
C780
L_O
D705
C790
R758
R779
C781
C722
YUV_L_IN#
L756
C789
AGND
DVI_R_IN#
R754
8V_4052
R757
YPbPr_Pr
5V
C748
+8V
R756
16
L754
Pr_in
R_O
SGND
14-Oct-2005
Sheet of
F:\4228\4228_temp_ddb\4228_Temp.DDB Drawn By:
7
29101
30101
31101
SET
There are 6 pc.s PCBs including 1 pc. AUX. PSU Board, 1 pc. Keypad board, 1 pc.
Remote Control Receiver board, 1 pc. L/R Speakers and 1 pc. Main (Video) board in the SET.
32101
Audio
33101
PCB function
1. Power:
(1). Input voltage: AC 100V~120V, 45Hz~60Hz.
Input range: AC 90V(Min)~265V(Max) auto regulation.
(2). To provide power for PCBs.
2. Main (Video InterFace) board: To converter TV signals, S signals, AV signals, Y Pb/
Cb Pr/Cr signals, DVI signals and D-SUB signals to digital ones and to transmit to
Control board.
3. Control board: Dealing with the digital signal for output to panel.
4. Y-Sustainer / Z-Sustainer board:
(1). Receiving the signals from Control and high voltage supply.
(2). Output scanning waveform for Module.
5. Y-Drive board: Receive signal from Y sustainer, output horizontal scanning waveform to the panel.
6. X extension board (6pcs): Output addressing signals.
: Process and Amplifying the audio signal to speakers and
7. Tuner/Audio Board:
convert TV RF signal to video/audio signal and send to Main board.
34101
35101
2. The micro Processor memorize the last state of Power, When the last state of
power is on or receive power on signal from local Key or Remote control, Micro
Processor will send on control signal to power. Then Power sends (5Vsc, 9Vsc,
24V and RLYON, Vs ON) to PCBs working. This time VIF will send signals to
display Image, OSD on the panel and start to search available signal sources.
If the audio signals input, them will be amplified by Audio AMP and transmitted to
Speakers.
3. If some abnormal signals are detected (for example: over volts, over current, over
temperature and under volts), the system will be shut down by Power off.
36101
Main IC Specifications
37101
PW181
Product Specification
General Description
The PW181 ImageProcessor is a highly integrated
system-on-a-chip that interfaces computer graphics and
video inputs in virtually any format to a fixed-frequency flat
panel display.
Video
Input
TV
Signal
ADC/
TMDS
PW181
Com puter
TV
Signal
Display
ADC/
TMDS
TV Tuner
Video
Decoder
Video
Input
ROM
Features
Crystal
TV Tuner
Com puter
Video
Decoder
Applications
Multimedia Displays
Plasma Displays
Digital Television
Device
Application
PW181-10V
Up to XGA Displays
PW181-20V
Up to UXGA Displays
Package
352 PBGA
38101
PRELIMINARY / CONFIDENTIAL
FEATURES
140 MSPS Maximum Conversion Rate
300 MHz Analog Bandwidth
0.5 V to 1.0 V Analog Input Range
500 ps p-p PLL Clock Jitter at 110 MSPS
3.3 V Power Supply
Full Sync Processing
Sync Detect for Hot Plugging
Midscale Clamping
Power-Down Mode
Low Power: 500 mW Typical
4:2:2 Output Format Mode
RAIN
CLAMP
A/D
GAIN
CLAMP
A/D
BAIN
CLAMP
A/D
ROUTA
GOUTA
BOUTA
MIDSCV
HSYNC
APPLICATIONS
RGB Graphics Processing
LCD Monitors and Projectors
Plasma Display Panels
Scan Converters
Microdisplays
Digital TV
COAST
CLAMP
DTACK
SYNC
PROCESSING
AND CLOCK
GENERATION
HSOUT
VSOUT
SOGOUT
FILT
REF
SCL
SDA
A0
GENERAL DESCRIPTION
SERIAL REGISTER
AND
POWER MANAGEMENT
REF
BYPASS
AD9883A
140 MHz. PLL clock jitter is 500 ps p-p typical at 140 MSPS.
When the COAST signal is presented, the PLL maintains its
output frequency in the absence of Hsync. A sampling phase
adjustment is provided. Data, Hsync, and clock output phase
relationships are maintained. The AD9883A also offers full sync
processing for composite sync and sync-on-green applications.
A clamp signal is generated internally or may be provided by
the user through the CLAMP input pin. This interface is fully
programmable via a 2-wire serial interface.
Fabricated in an advanced CMOS process, the AD9883A is
provided in a space-saving 80-lead LQFP surface-mount plastic
package and is specified over the 0C to 70C temperature range.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
39101
PW1231A
Product Specification
General
Crystal
Video
Video
Decoder
PW1231A
System Block Diagram
PW1231A
PW1231AL
Digital
Output
SDRAM
Features
Applications:
For use with Digital Displays
Device
Application
Package
PW1231A
PW1231AL
Up to XGA
160-pin PQF
PRELIMINARYCONFIDENTIAL
40101
Preliminary Datasheet
AD9880
3/26/2004
FEATURES
Analog Interface
R/G/B or YPbPrIN0
R/G/B or YPbPrIN1
HSYNC 0
HSYNC 1
HSYNC 0
HSYNC 1
SOGIN 0
SOGIN 1
COAST
CLAMP
CKINV
CKEXT
FILT
2:1
MUX
2:1
MUX
2:1
MUX
2:1
MUX
Clamp
or YCbCr
2
Sync
Processing and
Clock
Generation
DATACK
HSOUT
VSOUT
SOGOUT
REFOUT
REFIN
Ref
SCL
SDA
R/G/B 8X3
YCbCr (4:2:2
or 4:4:4)
2
DATACK
HSOUT
VSOUT /A0
SOGOUT
DE
Digital Interface
R/G/B 8X3
or YCbCr
RX0+
2
RX0RX1+
RX1RX2+
RX2-
DATACK
DE
Hsync
HDMI Receiver
Vsync
SPDIF OUT
RXC+
RXCRTERM
MCL
MDA
DDCSCL
8 Channel
I2S OUT
MCLK
LRCLK
HDCP
AD9880
DDCSDA
PLL clock jitter is typically less than 500 ps p-p at 150 MHz. The
AD9880 also offers full sync processing for composite sync and
Sync-on-Green (SOG) applications.
Digital Interface
The AD9880 contains a HDMI 1.0 compatible receiver and
supports all HDTV formats (up to 1080p) and display resolutions
up to SXGA (1280 x 1024 at 75 Hz). The receiver features an
intra-pair skew tolerance of up to one full clock cycle. With the
inclusion of HDCP, displays may now receive encrypted video
content. The AD9880 allows for authentication of a video receiver,
decryption of encoded data at the receiver, and renewability of that
authentication during transmission as specified by the HDCP 1.1
protocol.
Fabricated in an advanced CMOS process, the AD9880 is provided
in a space-saving 100-lead LQFP surface-mount plastic package
and is specified over the 0 C to 70 C temperature range.
R/G/B 8X3
A/D
Analog Interface
MUXES
41101
VPC 323xD
1. Introduction
The VPC 323xD is a high-quality, single-chip video
front-end, which is targeted for 4:3 and 16:9, 50/60-Hz
and 100/120 Hz TV sets. It can be combined with other
members of the DIGIT3000 IC family (such as
DDP 331x) and/or it can be used with 3rd-party products.
high-performance adaptive 4H comb filter Y/C separator with adjustable vertical peaking
I2C-bus interface
integrated high-quality A/D converters and associated clamp and AGC circuits
CIN
VIN1
Adaptive
Comb
Filter
Analog
Front-end
VIN2
Color
Decoder
NTSC
PAL
SECAM
Cr
Cb
VIN3
VIN4
NTSC
PAL
AGC
2 ADC
VOUT
Mixer
Saturation
Tint
2D Scaler
PIP
Output
Formatter
Cr
Panorama
Mode
ITU-R 656
ITU-R 601
Cb
Contrast
Brightness
Memory
Control
Peaking
FB
RGB/
YCrCb
Processing Y
Analog
Component U/B
Cr
Matrix
Front-End
Contrast
V/R
Saturation Cb
Brightness
4 x ADC
FB
FB
Tint
I2C Bus
Clock
Gen.
Micronas
42101
CrCb
OUT
YCOE
Y/G
RGB/
YCrCb
Y OUT
Sync
+
Clock
Generation
FIFO
CNTL
LL Clock
H Sync
V Sync
AVO
4'.+/+0#4; 41&7%6#2'%+(+%#6+10
<
+0'
'%1&'4
! "
Minimal Communications and Control Overhead Provide Simple Implementation of Violence Blocking,
Closed Captioning, and Auto Clock Set Features
Programmable, On-Screen Display (OSD) for Creating Full Screen OSD or Captions inside a Picture-inPicture (PiP) Window
Complete Stand-Alone Line 21 Decoder for ClosedCaptioned and Extended Data Services (XDS)
#$
%
& %
"
'
Capable of processing Vertical Blanking Interval (VBI)
data from both fields of the video frame in data, the Z86229
Line 21 Decoder offers a feature-rich solution for any television or set-top application. The robust nature of the
Z86229 helps the device conform to the transmission format
defined in the Television Decoder Circuits Act of 1990, and
in accordance with the Electronics Industry Association
specification 608 (EIA608).
The Line 21 data stream can consist of data from several data
channels multiplexed together. Field 1 consists of four data
channels: two Captions and two Texts. Field 2 consists of
five additional data channels: two Captions, two Texts, and
Extended Data Services (XDS). The XDS data structure is
43101
MSP 34x0G
1. Introduction
The MSP 34x0G family of single-chip Multistandard
Sound Processors covers the sound processing of all
analog TV-Standards worldwide, as well as the NICAM
digital sound standards. The full TV sound processing,
starting with analog sound IF signal-in, down to processed analog AF-out, is performed on a single chip.
Figure 11 shows a simplified functional block diagram
of the MSP 34x0G.
This new generation of TV sound processing ICs now
includes versions for processing the multichannel television sound (MTS) signal conforming to the standard
recommended by the Broadcast Television Systems
Committee (BTSC). The DBX noise reduction, or alternatively, Micronas Noise Reduction (MNR) is performed alignment free.
Other processed standards are the Japanese FM-FM
multiplex standard (EIA-J) and the FM Stereo Radio
standard.
ADC
Sound IF2
Demodulator
I2S1
Preprocessing
Prescale
I2S2
Source Select
Sound IF1
Loudspeaker
Sound
Processing
DAC
Headphone
Sound
Processing
DAC
Loudspeaker
Subwoofer
Headphone
I2S
SCART1
DAC
SCART2
SCART3
SCART
DSP
Input
Select
SCART1
ADC
Prescale
SCART4
MONO
Micronas
DAC
SCART
Output
Select
SCART2
PI5V330
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
Product Features:
High-performance, low-cost solution to switch
between video sources
Wide bandwidth: 200 MHz
Low ON-resistance: 3
Low crosstalk at 10 MHz: 58 dB
Ultra-low quiescent power (0.1 A typical)
Single supply operation: +5.0V
Fast switching: 10 ns
High-current output: 100 mA
Packages available:
16-pin 300-mil wide plastic SOIC (S)
16-pin 150-mil wide plastic SOIC (W)
16-pin 150-mil wide plastic QSOP (Q)
Product Description:
Pericom Semiconductors PI5V series of mixed signal video
circuits are produced in the Companys advanced CMOS
low-power technology, achieving industry leading performance.
The PI5V330 is a true bidirectional Quad 2-channel
multiplexer/demultiplexer that is recommended for both
RGB and composite video switching applications. The
VideoSwitch can be driven from a current output
RAMDAC or voltage output composite video source.
Low ON-resistance and wide bandwidth make it ideal for
video and other applications. Also this device has exceptionally high current capability which is far greater than most
analog switches offered today. A single 5V supply is all that
is required for operation.
The PI5V330 offers a high-performance, low-cost solution
to switch between video sources. The application section
describes the PI5V330 replacing the HC4053 multiplier and
buffer/amplifier.
DA
S1B
S2B
DB
IN
S1A
S1C
S2C
DC
S2A
DA
S1B
S1D
S2D
S2B
DD
DB
GND
1
2
3
4
5
6
7
8
16
15
14
16-PIN 13
Q16
12
S16
11
W16
10
9
VCC
EN
S1D
S2D
DD
S1C
S2C
DC
DECODER/DRIVERS
IN
Pin Name
S1A, S2A
S1B, S2B
S1C, S2C
S1D, S2D
IN
EN
DA, DB,
DC, DD
GND
VCC
Truth Table
EN
0
0
1
IN
0
1
X
ON Switch
S1A, S1B, S1C, S1D
S2A, S2B, S2C, S2D
Disabled
45101
Description
Analog Video I/O
Select Input
Enable
Analog Video I/O
Ground
Power
PS7032C
08/07/97
46101
47101
48101
49101
50101
51101
Features
Low-Voltage and Standard-Voltage Operation
2-Wire
Serial EEPROM
32K (4096 x 8)
64K (8192 x 8)
AT24C32
AT24C64
Description
The AT24C32/64 provides 32,768/65,536 bits of serial electrically erasable and programmable read only memory (EEPROM) organized as 4096/8192 words of 8 bits
each. The devices cascadable feature allows up to 8 devices to share a common 2wire bus. The device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential. The AT24C32/64 is
available in space saving 8-pin JEDEC PDIP, 8-pin JEDEC SOIC, 8-pin EIAJ SOIC,
and 8-pin TSSOP (AT24C64) packages and is accessed via a 2-wire serial interface.
In addition, the entire family is available in 5.0V (4.5V to 5.5V), 2.7V (2.7V to 5.5V),
2.5V (2.5V to 5.5V) and 1.8V (1.8V to 5.5V) versions.
Pin Configurations
8-Pin TSSOP
Pin Name
Function
A0 - A2
Address Inputs
SDA
Serial Data
SCL
WP
Write Protect
A0
A1
A2
GND
1
2
3
4
8
7
6
5
8
7
6
5
VCC
WP
SCL
SDA
2-Wire, 32K
Serial E2PROM
8-Pin SOIC
8-Pin PDIP
A0
A1
A2
GND
1
2
3
4
VCC
WP
SCL
SDA
A0
A1
A2
GND
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
Rev. 0336G04/01
52101
Block Diagram
Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive
edge clock data into each EEPROM device and negative
edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for
serial data transfer. This pin is open-drain driven and may
be wire-ORed with any number of other open-drain or open
collector devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1
and A0 pins are device address inputs that are hard wired
or left not connected for hardware compatibility with
AT24C16. When the pins are hardwired, as many as eight
32K/64K devices may be addressed on a single bus system (device addressing is discussed in detail under the
Device Addressing section). When the pins are not hardwired, the default A2, A1, and A0 are zero.
WRITE PROTECT (WP): The write protect input, when tied
to GND, allows normal write operations. When WP is tied
high to V CC, all write operations to the upper quandrant
(8/16K bits) of memory are inhibited. If left unconnected,
WP is internally pulled down to GND.
Memory Organization
AT24C32/64, 32K/64K SERIAL EEPROM: The 32K/64K is
internally organized as 256 pages of 32 bytes each. Random word addressing requires a 12/13 bit data word
address.
AT24C32/64
53101
HT48R06A-1/HT48C06
8-Bit Cost-Effective I/O Type MCU
Features
Operating voltage:
fSYS=4MHz: 2.2V~5.5V
fSYS=8MHz: 3.3V~5.5V
consumption
Up to 0.5ms instruction cycle with 8MHz system clock
at VDD=5V
Allinstructionsinoneortwomachinecycles
Watchdog Timer
63 powerful instructions
General Description
The HT48R06A-1/HT48C06 are 8-bit high performance, RISC architecture microcontroller devices specifically designed for cost-effective multiple I/O control
product applications. The mask version HT48C06 is
fully pin and functionally compatible with the OTP version HT48R06A-1 device.
The advantages of low power consumption, I/O flexibility, timer functions, oscillator options, HALT and
wake-up functions, watchdog timer, buzzer driver, as
well as low cost, enhance the versatility of these devices
to suit a wide range of application possibilities such as
industrial control, consumer products, subsystem controllers, etc.
Block Diagram
IN T /P C 0
In te rru p t
C ir c u it
S T A C K 0
P ro g ra m
R O M
P ro g ra m
C o u n te r
T M R
S T A C K 1
IN T C
P r e s c a le r
M P
U
X
D A T A
M e m o ry
W D T S
W D T P r e s c a le r
P B C
S T A T U S
fS
/4
X
R C
O S C
P C 0 ~ P C 1
C 1
P O R T B
P B
S h ifte r
P A C
Rev. 1.30
B Z /B Z
A L U
O S
R E
V D
V S
W D T
P O R T C
P C
M U X
T im in g
G e n e ra to r
O S C 2
Y S
P C 1
P C C
In s tr u c tio n
D e c o d e r
Y S
T M R C
P C 0
In s tr u c tio n
R e g is te r
fS
T M R /P C 1
X
P A
A C C
P O R T A
P B 0 ~ P B 2
P A 0 ~ P A 7
54101
August 7, 2003
HT48R06A-1/HT48C06
Pin Assignment
P A 3
1
1 8
P A 4
P A 3
1
1 6
P A 4
P A 2
2
1 7
P A 5
P A 2
2
1 5
P A 5
P A 1
3
1 6
P A 6
P A 1
3
1 4
P A 6
P A 0
4
1 5
P A 7
P A 0
4
1 3
P A 7
P B 2
5
1 4
O S C 2
P B 0 /B Z
5
1 2
O S C 2
P B 1 /B Z
6
1 3
O S C 1
V S S
6
1 1
O S C 1
P B 0 /B Z
7
1 2
V D D
P C 0 /IN T
7
1 0
V D D
V S S
8
1 1
R E S
P C 1 /T M R
8
R E S
P C 0 /IN T
1 0
P C 1 /T M R
H T 4 8 R 0 6 A -1 /H T 4 8 C 0 6
1 6 S S O P -A
H T 4 8 R 0 6 A -1 /H T 4 8 C 0 6
1 8 D IP -A /S O P -A
Pad Assignment
HT48C06
P A 1
P A 2
P A 3
P A 4
P A 5
P A 6
1 8
1 7
1 6
1 5
1 4
1 3
(0 ,0 )
1
P A 0
1 2
P B 2
P B 1 /B Z
1 1
O S C 2
1 0
O S C 1
V D D
V S S
R E S
P B 0 /B Z
P C 1 /T M R
P C 0 /IN T
P A 7
Rev. 1.30
55101
August 7, 2003
HT48R06A-1/HT48C06
Pad Description
Pad Name
PA0~PA7
I/O
I/O
Options
Description
Pull-high*
Wake-up
PB0/BZ
PB1/BZ
PB2
I/O
Pull-high*
I/O or BZ/BZ
VSS
PC0/INT
PC1/TMR
I/O
Pull-high*
RES
VDD
OSC1
OSC2
I
O
Crystal
or RC
OSC1, OSC2 are connected to an RC network or Crystal (determined by options) for the internal system clock. In the case of RC operation, OSC2 is the
output terminal for 1/4 system clock.
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Rev. 1.30
56101
August 7, 2003
HT48R06A-1/HT48C06
D.C. Characteristics
Symbol
VDD
IDD1
Parameter
Operating Voltage
Ta=25C
Test Conditions
VDD
Conditions
5.5
fSYS=8MHz
3.3
5.5
0.6
1.5
mA
mA
0.8
1.5
mA
2.5
mA
mA
mA
10
mA
mA
mA
3V
Operating Current (RC OSC)
No load, fSYS=4MHz
No load, fSYS=4MHz
5V
ISTB1
5V
No load, fSYS=8MHz
3V
No load, system HALT
5V
ISTB2
Unit
2.2
3V
Max.
fSYS=4MHz
IDD3
Typ.
5V
IDD2
Min.
3V
Standby Current (WDT Disabled)
VIL1
0.3VDD
VIH1
0.7VDD
VDD
VIL2
0.4VDD
VIH2
0.9VDD
VDD
VLVR
LVR enabled
2.7
3.0
3.3
IOL
mA
10
20
mA
-2
-4
mA
-5
-10
mA
3V
VOL=0.1VDD
5V
IOH
3V
I/O Port Source Current
VOH=0.9VDD
5V
RPH
Rev. 1.30
3V
40
60
80
kW
5V
10
30
50
kW
Pull-high Resistance
57101
August 7, 2003
A/S Manual
CUSTOMERS
A/S
MANUAL
58101
A/S Manual
2. Precaution
2-1 Handling Precaution for Plasma Display,
2-2 Safety Precautions for Service (Handling, prevention of a electrical shock, measure against
5. Disassembling / Assembling
5-1 Tools and measurement equipment
5-2 Exploded View
5-3 Disassembling & Re-assembling
7. Operation Check
7-1 Adjustment Specification, Checking Position etc.
7-2 Adjusting procedure
59101
A/S Manual
1. Overview
1-1 Model Name of Plasma Display
60101
A/S Manual
SCREW 3X10
61101
A/S Manual
1-4 Specifications
No
Item
Pixel
Number of Cells
Pixel Pitch
Cell Pitch
Specification
852 (H) 480 (V) pixels
Display size
Screen size
Screen aspect
16 : 9
Display color
Viewing angle
Over 160
(Angle with 50% and greater brightness perpendicular to PDP
module)
10
Dimensions
11
Weight
Module 1
About 15.4 kg
12
Packing weight
Module 1
13
Packing size
Broadcasting reception
14
Vertical frequency
and
Video/Logic Interface
62101
A/S Manual
2. PRECAUTIONS
** To prevent the risks of unit damage, electrical shock and radiation, take the
following safety, service, and ESD precautions.
2-1 Handling Precautions for Plasma Display
PDP module use high voltage that is
dangerous to human. Before operating
place.
minute.
2-2 Safety Precautions for Service (Handling, prevention of a electrical shock, measure
against power outage, etc)
( Safety Precautions )
Before replacing a board, discharge forcibly
The remaining electricity from board.
connected.
circuit operations.
63101
A/S Manual
and voltage-insulation.
preparing damage.
partitioning type.
64101
A/S Manual
prevent charging.
installed on.
ESD.
the ESD.
65101
A/S Manual
7
1
4
16
14
11
13
12
15
No.
Location
Name
SMPS
SMPS
LOGIC-MAIN Board
LOGIC + Y-MAIN
FFC CABLE-FLAT
10
LOGIC + X-MAIN
FFC CABLE-FLAT
11
FFC CABLE-FLAT
12
FFC CABLE-FLAT
13
LOGIC BUF(E) +
LOGIC BUF(F)
LEAD CONNECTOR
14
LEAD CONNECTOR
15
LEAD CONNECTOR
16
SMPS + Y-MAIN
LEAD CONNECTOR
17
SMPS + X-MAIN
LEAD CONNECTOR
66101
10
17
A/S Manual
1. SMPS
2. L-Main
3. X-Main
4. Y-Mian
5. Y-Buffer (Upper)
6. Y-Buffer (down)
7. E-Buffer
8. F-Buffer
67101
A/S Manual
9. Logic + Y-Main
68101
A/S Manual
L VDS
IN PU T
( CL OCK
R,G,B Data
V, H Sync.
DE)
I2C
Interface
Signal
ASIC
SPS -S101
X, Y
FET
Control
TCP
CL K, DATA
Control
128K
DDR
69101
128K
DDR
A/S Manual
with logic
main board timing and supplies the X electrode of the panel with the drive signal through the
connector.
1)
2)
3)
.Y-main board : The Y-main board generate a drive signal by switching the FET in synchronization with the logic
Main Board timing and sequentially supplies the Y electrode of the panel with the drive signal
through the scan driver IC on the Y-buffer board. This board connected to the panels
Y terminal has the following main functions.
1)
2)
3)
Logic main board : The logic main board generates and outputs the address drive output signal and the X ,Y
drive signal by processing the video signals. This Board buffers the address dirve output
signal and feeds it to the address drive IC (TCP module)
(video signal- X Y drive signal generation , frame memory circuit / address data rearrangement)
.Logic buffer(E,F) : The logic buffer transmits data signal and control signal.
.Y-buffer board (Upper, Lower) : The Y-buffer board consisting of the upper and lower boards supplies the
Y-terminal with scan waveforms. The board comprises 8 scan driver ICs
(ST microelectronics STV 7617 : 64 or 65 output pins) , but 4 ICs for the SD class
.AC Noise Filter : The AC Noise filter has function for removing noise(low Frequency) and blocking surge.
It effects Safety standards(EMC,EMI)
.TCP( Tape Carrier Package ) : The TCP applies Va pulse to the address electrode and constitutes address
discharge by the potential difference between the Va pulse and the pulse
applied to the Y electrode. The TCP comprise 2 data driver Ics(STV7620A
:96 pins output pins) 14 TCPs are required for signal scan
.
70101
A/S Manual
Serial No.
* PANEL S/N
1
Serial No : 00001~99999
Date : 01~31
Month : 1~C
Year :
(Oct-A,Nov-B,Dec-C))
0 (2000) ~ 9 (2009)
Line No : 1 ~ 9
(0 : Pilot Line)
71101
A/S Manual
No voltage output
Check Voltage at CN8001/2pin
Connect [ 220Vac or 110Vac]
AC Input
220Vac or 110Vac
No
Reconnect it
Yes
PSU
No
Yes
Protection?
PSU
Yes
72101
No
Check
output voltage
No
A/S Manual
PSU
No
Check F201&F301,F401,F501
Replace PSU.
73101
Goto No display.
Replace PSU.
A/S Manual
No Display
Y Main
Logic Main
X Main
Broken panel
Check
NG
Logic Bd
Replace Logic Bd
LVDS Cable
LED 2000;Green
OK
NG
Y-Main
Replace Logic Bd
OK
Check
F5001 for Vdd (5V)
F5002 for Vcc (15V)
OPEN
17 /Fuse
39
F5004 for Vs
74101
OK
A/S Manual
Check
SHORT
Q5011,13,14,15,16,17
Replace Y-Bd
Q5018,20,21,27
Q5028,29,32
X-Main
OK
Check
F4001 for Vdd (5V)
F4002 for Vcc (15V)
OPEN
Fuse
Replace X-Bd
F4003 for Vs
OK
SHORT
Check
FET
Replace X-Bd
Q4010 ~ Q4017
OK
Panel
Replace PDP
4-1-3 Abnormal Display (Abnormal Image is on Screen. (except abnormality in Sustain or Address)
Abnormal Display is related with Y-MAIN, X-MAIN, Logic Main and so on.
This page shows you how to check the boards, and the following pages show you how to find the
defective board.
Abnormal
Display
18 / 39
Logic Main
[LED 2000 Blinks]
Y Main
75101
X Main
A/S Manual
Y-Main
OK
Check
F5001 for Vdd (5V)
F5002 for Vcc (15V)
OPEN
Fuse
Replace Y-Bd
F5004 for Vs
OK
SHORT
Check
Q5011,13,14,15,16,17
FET
Replace
Q5018,20,21,27
Y Bd
Q5028,29,32
OK
X-Main
OK
Check
F4001 for Vdd (5V)
F4002 for Vcc (15V)
OPEN
Fuse
Replace X-Bd
F4003 for Vs
OK
SHORT
Check
FET
Q4010 ~ Q4017
76101
OK
Replace X-Bd
A/S Manual
[Logic Main]
LED 2000 Blinks
(Motion of Vsync)
Regular
NG
Abnormal
Logic main
Normal State
OK
Replace
board
NG
77101
A/S Manual
After
Replace PDP
Changing
OK
Done
(Defect is from buffer)
78101
A/S Manual
[Y-FPC]
Sustain Open
After
NG
Changing
Replace PDP
OK
Done
(Defect is from buffer)
Address Open
Line Open
Data Block Open
TCP Block Open
[ Logic Main/FFC ]
[ Logic Buffer ]
Changing necessary
Parts (E/F)
79101
A/S Manual
1 Line or
NG
1 Block
Half Block/
Half of
OK
OK
Replace
PDP
Replace
Logic Main/
NG
Done
Address Buffer
OK
(E/F)
[ Logic Main/FFC ]
[ Logic Buffer ]
Changing necessary
Parts (E/F)
80101
A/S Manual
NG
1 Line or
Half Block/
1 Block
Half of
OK
OK
Replace
PDP
Replace
Logic Main/
NG
Done
Address Buffer
OK
(E/F)
Condition Name
No Voltage Output
No Display
Abnormal Display
Sustain Open
Sustain Short
Description
Related Board
SMPS
Address Open
Address Short
81101
A/S Manual
Cause
Cause
TCP defect
82101
A/S Manual
83101
A/S Manual
gradation patter
Cause
manufacturing : Panel electrode short/Foreign
material.
repair failed
84101
A/S Manual
Cause
Cause
aging condition
cell pitch/phosphor
85101
A/S Manual
damage level.
86101
A/S Manual
5. Disassembling / Assembling
5-1 Tools and measurement equipment
5-1-1.
Tools
1)
2)
Air Blower
3)
Earth Ring
Removal procedures
1) Full out the FPC from Connector by holding the lead of the FPC with hands.
87101
A/S Manual
Assembling Procedures
1) Push the lead of FPC with same strength until to be connected completely.
* Notice : Be careful do not get a damage on the connector pin during connecting by mistake.
connector.
2. Assembling Procedure
1)
88101
A/S Manual
5-3-3 Assembling & Disassembling the FFC and TCP from Connector
1. Disassembling of TCP
1)
2.
Assembling of TCP
1)
2)
Notice :
1) Checking whether the foreign material is on the Connector inside before assembling of TCP.
2) Be careful do not get a damage on the board by ESD during handling of TCP.
89101
A/S Manual
3. Misassembling of TCP
1) The misassembling of TCP is the cause of defect.
90101
A/S Manual
( Photo 1 )
( Photo 2 )
1) Remove the screws in order of 2-4-1-5-3 from heat sink and then get rid of heat sink. ( Photo 1 )
2) Remove the TPC, FFC and power cable from the connectors.
3) Remove all of the screws from defected board.
4) Remove the defected board.
5) Replace the new board and then screw tightly.
6) Get rid of the foreign material from the connector.
7) Connect the TCP,FFC and power cable to the connector.
8) Reassemble the TCP heat sink.
9) Screw in order of 3-1-5-2-4. ( Photo 2 )
If you screw too tightly, it is possible to get damage on the Driver IC of TCP.
91101
A/S Manual
5) Remove the connector of CN5005, CN5006, CN5007 and CN5008 among YBU, YBL and YM.
6) Remove the YBL and YBU from Y-main.
7) Replace the defected board.
92101
A/S Manual
Check Item
Specification
Remarks
TCP Assembling
condition
Module
assemble
check
Drive board
Securely connected or
Y BUFFER
tightened
Securely connected
Material Mixing
No material mixing
b.
c.
2) Turn on the power to PDP module, and then check that LED lights up and the SET is working well.
3) Check the power voltage after turn on the power, and then check the Display condition by tapping slightly the Y-FPC 2 or 3 times.
5) If something wrong, each voltage should be set to the standard voltage by using Multi-Tester and adjusting tools.
6) Adjust the waveform, using Oscilloscope for the waveform adjusting point.
7) Check the discharge of front panel by changing the image for each pattern.
8) Check the Low-discharge, Over-discharge and panel condition by adjusting the Pattern Generator Level.
93101
A/S Manual
7. Operation Check
7-1 Adjustment Specification, Checking Position etc.
V4 TCP Ramp Waveform Inclination Adjustment ( Y-Board )
<Falling Ramp>
94101
A/S Manual
VR5003 Adjustment :
Falling Ramp flat time => Typ. 80usec
VR5001 Adjustment :
Rising Ramp flat time: Typ. 60usec
2)
95101
A/S Manual
Output voltage(V)
VS
207V 1%
195V ~ 215V
VA
70V 1.5%
50V ~ 70V
VE
110V 1.5%
70V ~ 110V
VSET
198V 1.5%
180V ~ 210V
VSCAN
-185V 1.5%
-170V ~ -190V
VSB
5V 5%
Fixed
VG
15V 5%
Fixed
D5VL
5.2V 5%
Fixed
D3V3
3.3V 5%
Fixed
96101
Date: 2006/01/05
Part Number
Usage /
Unit
unit
1
piece
Part Description
E6205-42SA02
900-420101-01B
piece
771E42AA02-04
MAIN PCBA
set
771L42AA02-04
AUDIO PCBA
set
771-42AB01-01
KEY PCBA
set
771-42D110-01
IR RECEIVE PCBA
piece
E7801-080001
POWER PCBA
set
771-50AA05-01
set
786-SPA103-01
set
10
E4101-027001
POWER SWITCH
piece
11
E4801-116002
SPEAKER
piece
12
E3219-002003
POWER SOCKET
piece
13
E3301-017002
TERMINAL PUSH
piece
14
E3404-157001
AC POWER CORD
piece
15
E3421-927006
piece
16
E3421-927021
piece
17
E3421-926042
piece
18
E3421-926034
piece
19
E3421-926041
piece
20
E3421-926077
piece
21
E3421-926069
piece
22
E3421-926068
piece
23
E3421-926071
piece
24
E7501-052001
REMOTE
set
25
E7301-010002
piece
26
200-42AA01-SMK01A
piece
piece
piece
27
208-SPA101-01R
WP2-19
28
209-SPA101-01R
29
277-42D101-01S
FUNCTION KNOB
piece
30
263-42D101-01S
POWER LENS
piece
97101
CABINET
Date: 2006/01/05
Part Number
Usage /
Unit
unit
1
piece
Part Description
31
269-42D101-01L
IR LENS
32
481-50AA03-01S
piece
33
483-50AA01-01
piece
34
436-42AA07-01S
TERMIAL SHEET
piece
35
402-42AA01-01S
BACK COVER
piece
36
248-46D201-01
piece
37
734-BM0501-02
STAND BASE
set
38
510-42AA01-SMU01K
CARTON BOX
piece
39
518-42AA01-01K
BTM TRAY
piece
40
300-42AA03-01C
POLYFOAM SHEET
piece
41
300-42AA01-02C
piece
42
300-42AA02-02C
piece
43
244-34B811-01
piece
44
310-504004-01
piece
45
310-151404-01T
INSTRUCTION
MANUAL
15"X14"X0.04MM
piece
46
580-P42AAES-MU01L
piece
47
599-BM0502-01
IB SHEET E
piece
48
388-42D103-01H
CAUTION LABEL
piece
49
388-50AA01-01H
piece
50
388-50AA01-02H
piece
51
387-42AA01-SMU01H
MODEL PLATE
piece
52
579-SPA101-15
piece
53
579-SPA101-16
piece
54
384-42AA01-SMU01H
piece
55
590-42AA01-05
WARRANTY CARD
piece
56
593-42AA01-03
INSERTION CARD
piece
57
579-42D102-09
piece
58
579-50AA02-01
piece
59
579-42AA01-07
piece
60
579-42D105-01
piece
61
568-P46T02-02
WARNING LB EN
piece
POLYBAG
INSTRUCTION MANUAL
OF TEARDOWN
98101
(-/+)
99101
Software upgrade
- Connect the RS-232C input jack to an external control device (such as a computer) and software upgrade.
Pin name
No connection
RXD (Receive data)
TXD (Transmit data)
DTR (DTE side ready)
GND
DSR (DCE side ready)
RTS (Ready to send)
CTS (Clear to send)
No Connection
9
6
RS-232C configurations
3-wire configuration
(For PDP software upgrade)
7-wire configuration
(Standard RS-232C cab
RXD
TXD
GND
DTR
DSR
RTS
CTS
PC
PDP
2
3
5
4
6
7
8
3
2
5
6
4
8
7
D-Sub 9
D-Sub 9
TXD
RXD
GND
DSR
DTR
CTS
RTS
RXD
TXD
GND
DTR
DSR
RTS
CTS
100101
PC
PDP
2
3
5
4
6
7
8
3
2
5
4
6
7
8
D-Sub 9
D-Sub 9
TXD
RXD
GND
DTR
DSR
RTS
CTS
101101