Abstract Form

Presentation Title: Lossless Compression Algorithms for Post-OPC I.C. Layout Data

Presenter, University: Allan Gu, University of California at Berkeley

Presenter's Expected Graduation Date: 05/2010

Author(s), Organization(s): Allan Gu, University of California at Berkeley

Avideh Zakhor, University of California at Berkeley

SRC Research Task ID: 460.011

Task Leader: Avideh Zakhor

Presentation type: Paper/Poster

Abstract Text:
An important step in today's Integrated Circuit (IC) manufacturing is optical proximity correction
(OPC). While OPC increases the fidelity of pattern transfer to the wafer, it also results in
significant increase in IC layout file size. To help alleviate the growing volume of layout data, a
new layout data format, Open Artwork System Interchange Standard (OASIS), was introduced in
2001 by SEMI's Data Path Task Force. Although OASIS is more efficient than previous industry
standard format GDSII, there is still room for improvement by applying compression techniques.
In this paper, we propose two techniques for compressing OPC layout data while remaining
complaint with existing industry standard formats such as OASIS and GDSII. The reason for such
compliance is that the compressed files can be viewed, edited, and manipulated by any CAD tool
without the need for a decoder. Our approach is to eliminate redundancies in the representation of
the geometrical data by finding repeating groups of geometries between multiple cells and within
a cell. We refer to the former problem as ''intercell sub-cell detection'' and latter as ''intracell sub-
cell detection''. Both are NP hard, and as such, we propose two sets of heuristics to solve them.
We show the results of our algorithms on actual IC layouts for 90nm and 130nm feature size
circuit designs. Our algorithm results in a 2X reduction in file size for Poly layer and 1.5X
reduction in file size of the Active layer.