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EVALUA BLE
IL
AVA A
Features
S 8.0V to 16.5V IN Supply-Voltage Range
S Selectable Frequency (500kHz/750kHz)
S Current-Mode Step-Up Regulator
Turn-On Delay
S High-Speed Operational Amplifier
Sequencing
S PGOOD Comparator
S Input Undervoltage Lockout and Thermal-
Overload Protection
S 48-Pin, 7mm x 7mm, Thin QFN Package
Ordering Information
PART
MAX17126ETM+
TEMP RANGE
-40NC to +85NC
PIN-PACKAGE
48 Thin QFN-EP*
MAX17126AETM+
-40NC to +85NC
48 Thin QFN-EP*
Applications
LCD TV Panels
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxims website at www.maxim-ic.com.
MAX17126/MAX17126A
General Description
MAX17126/MAX17126A
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VINVL= VIN2 = 12V, VVOP = VVREF_I = 15V, TA = 0C to +85C. Typical values are at TA = +25NC, unless otherwise noted.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
16.5
GENERAL
INVL, IN2 Input-Voltage Range
8.5
20
mA
24
mA
630
750
870
FSEL = GND
420
500
580
6.0
7.0
8.0
VL Output Voltage
4.85
5.15
VL Undervoltage-Lockout
Threshold
3.5
3.9
4.3
1.2375
1.250
1.2625
mV
kHz
VL REGULATOR
REFERENCE
REF Output Voltage
No external load
In regulation
REF Undervoltage-Lockout
Threshold
10
FA
1.0
2 _______________________________________________________________________________________
1.2
CONDITIONS
MIN
TYP
3.3
MAX
UNITS
STEP-DOWN REGULATOR
OUT Voltage in Fixed Mode
0C < TA = +85C
3.25
TA = +25C
3.267
0C < TA = +85C
TA = +25C
1.23
1.2375
1.25
1.27
1.2625
0.10
0.15
0.20
Falling edge
0.96
1.0
1.04
VFB2 = 1.25V
50
125
200
nA
3.35
3.333
1.5
DC Load Regulation
0.5
DC Line Regulation
0.1
%/V
100
200
mI
10
23
40
30
110
Low-Frequency Operation
OUT Threshold
Low-Frequency Operation
Switching Frequency
LX2 Positive Current Limit
Soft-Start Ramp Time
LX2 only
0.8
FSEL = INVL
125
FSEL = GND
83
V
kHz
MAX17126
2.50
3.20
3.90
MAX17126A
3.0
3.5
4.0
70
78
A
ms
85
10
STEP-UP REGULATOR
Output Voltage Range
VIN
20
70
78
85
1.2375
1.25
1.2625
0.96
1.0
1.04
Falling edge
0.5
0.08
%/V
30
125
200
FB1 Transconductance
150
320
560
FB1 to COMP
1400
10
nA
FS
V/V
40
FA
MAX17126/MAX17126A
MAX17126/MAX17126A
MIN
TYP
MAX
CONDITIONS
3.6
4.2
4.8
-20%
4.2 (68k/
RCLIM)
+20%
RCLIM = 60.5kI
0.56
0.625
0.69
0.19
0.21
0.25
V/A
100
185
mI
Current-Sense Transresistance
LX1 On-Resistance
Soft-Start Period
SS Charge Current
VSS = 1.2V
16
4
UNITS
A
ms
6
20
0.15
0.3
mA
V
FA
8.0
Positive Charge-Pump
Soft-Start Period
Falling edge
20.1
21
22
1.2375
1.25
1.2625
0.2
%/V
+50
nA
1.5
1.0
1.04
-50
0.96
ms
750kHz frequency
ms
VREF - VFBN
0.99
-50
1.00
1.01
+50
nA
0.2
%/V
1.5
800
880
mV
Rising edge
720
750kHz frequency
EN = GND
25
50
ms
EN = VL
10
15
FA
GD Done Threshold
20
OPERATIONAL AMPLIFIERS
VOP Supply Range
4 _______________________________________________________________________________________
CONDITIONS
VVOP = rising, hysteresis = 200mV (Note 2)
MIN
TYP
MAX
UNITS
20.1
21
22
mA
14
mV
-1
+1
FA
VOP
Input Common-Mode
Voltage Range
Input Common-Mode
Rejection Ratio
IOPO = 25mA
VOP 320
80
dB
VOP 150
mV
IOPO = -25mA
150
80
Slew Rate
45
V/Fs
-3dB Bandwidth
20
MHz
Short-Circuit Current
mA
200
35
150
300
FA
10
VGHM-to-VGH Switch
On-Resistance
VGHM-to-VGH Switch
Saturation Current
VGHM-to-DRN Switch
On-Resistance
VGHM-to-DRN Switch
Saturation Current
75
200
VGHM-to-GND Switch
On-Resistance
DLY1 = GND
1.0
2.5
150
mV
dB
200
390
20
300
mA
50
I
mA
4.0
kI
0.6
+1
FA
1.6
GVOFF-to-VGHM Rising
Propagation Delay
100
ns
GVOFF-to-VGHM Falling
Propagation Delay
200
ns
-1
9.4
10
10.6
V/V
_______________________________________________________________________________________ 5
MAX17126/MAX17126A
MAX17126/MAX17126A
CONDITIONS
MIN
TYP
MAX
UNITS
SEQUENCE CONTROL
EN Pulldown Resistance
DLY1 Charge Current
1
VDLY1 = 1V; when DLY1 cap is not used, there is no
delay
MI
10
FA
1.19
1.25
1.31
10
kI
GAMMA REFERENCE
VREF_I Input-Voltage Range
10
18.0
No load
125
250
FA
IVREF_O = 60mA
0.25
0.5
1.250
1.256
P 0.9
mV/V
1.243
60
mA
PGOOD FUNCTION
VDET Threshold
VDET rising
1.274
1.3
50
175
VDET Hysteresis
50
1.326
V
mV
300
nA
0.4
FAULT DETECTION
Duration-to-Trigger Fault
50
ms
0.36 x
VREF
0.4 x
VREF
0.44 x
VREF
0.18 x
VREF
0.2 x
VREF
0.22 x
VREF
0.18 x
VREF
0.2 x
VREF
0.22 x
VREF
Positive Charge-Pump
Short-Circuit Protection
0.36 x
VREF
0.4 x
VREF
0.44 x
VREF
Negative Charge-Pump
Short-Circuit Protection
VREF - VFBN
0.4
0.45
0.5
Thermal-Shutdown Threshold
Latch protection
Step-Down Short-Circuit
Protection
+160
6 _______________________________________________________________________________________
NC
CONDITIONS
MIN
TYP
MAX
UNITS
0.6
500kHz
750kHz
1.6
V
1
MI
ELECTRICAL CHARACTERISTICS
(VINVL = VIN2 = 12V, VVOP = VVREF_I = 15V, TA = -40NC to +85NC.) (Note 3)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
GENERAL
INVL, IN2 Input-Voltage Range
16.5
630
870
FSEL = GND
420
580
6.0
8.0
VL Output Voltage
4.85
5.15
VL Undervoltage-Lockout
Threshold
3.5
4.3
1.235
1.265
1.2
kHz
VL REGULATOR
REFERENCE
REF Output Voltage
No external load
REF Undervoltage-Lockout
Threshold
STEP-DOWN REGULATOR
OUT Voltage in Fixed Mode
3.267
3.333
1.2375
1.2625
Dual-mode comparator
0.10
0.20
1.5
0.96
1.04
200
mI
Falling edge
23
40
110
MAX17126
2.50
3.90
MAX17126A
3.0
4.0
70
85
A
%
_______________________________________________________________________________________ 7
MAX17126/MAX17126A
MAX17126/MAX17126A
CONDITIONS
MIN
TYP
MAX
UNITS
STEP-UP REGULATOR
Output-Voltage Range
VIN
20
70
85
1.2375
1.2625
0.96
1.04
150
560
FS
40
FA
3.6
4.8
-20%
+20%
FB1 Transconductance
CLIM Voltage
RCLIM = 60.5kI
Current-Sense Transresistance
0.56
0.69
0.19
0.25
V/A
185
mI
FA
LX1 On-Resistance
SS Charge Current
VSS = 1.2V
8.0
20
0.2
mA
20.1
22
1.243
1.256
0.2
%/V
0.96
1.04
0.99
1.01
0.2
%/V
I
Falling edge
VREF - VFBN
Rising edge
720
880
mV
EN = VL
15
FA
GD Done Threshold
8 _______________________________________________________________________________________
CONDITIONS
MIN
TYP
MAX
UNITS
OPERATIONAL AMPLIFIERS
VOP Supply Range
20
20.1
22
mA
14
mV
OVIN
IOPO = 25mA
IOPO = -25mA
Short-Circuit Current
VOP 320
mV
300
200
200
mV
mA
35
300
FA
10
VGHM-to-VGH Switch
On-Resistance
VGHM-to-VGH Switch
Saturation Current
VGHM-to-DRN Switch
On-Resistance
VGHM-to-DRN Switch
Saturation Current
75
VGHM-to-GND Switch
On-Resistance
DLY1 = GND
1.0
150
mA
50
1.6
9.4
I
mA
4.0
kI
0.6
10.6
V/V
0.6
SEQUENCE CONTROL
EN Input Low Voltage
EN Input High Voltage
DLY1 Charge Current
DLY1 Turn-On Threshold
1.6
VDLY1 = 1V; when DLY1 cap is not used,
there is no delay
10
FA
1.19
1.31
_______________________________________________________________________________________ 9
MAX17126/MAX17126A
MAX17126/MAX17126A
CONDITIONS
MIN
TYP
MAX
UNITS
GAMMA REFERENCE
18.0
5.2
No load
250
FA
IVREF_O = 60mA
10
1.2375
VREF_O Maximum
Output Current
0.5
1.2625
P 0.9
mV/V
60
mA
PGOOD FUNCTION
VDET Threshold
VDET rising
1.274
1.326
0.4
FAULT DETECTION
FB1 falling edge
0.36 x
VREF
0.44 x
VREF
0.18 x
VREF
0.22 x
VREF
0.18 x
VREF
0.22 x
VREF
Positive Charge-Pump
Short-Circuit Protection
0.36 x
VREF
0.44 x
VREF
Negative Charge-Pump
Short-Circuit Protection
VREF - VFBN
0.4
0.5
0.6
Step-Up Short-Circuit
Protection
Step-Down Short-Circuit
Protection
500kHz
750kHz
1.6
Note 1: When the step-down inductor is in continuous conduction (EN = VL or heavy load), the output voltage has a DC regulation
level lower than the error comparator threshold by 50% of the output voltage ripple. In discontinuous conduction (EN = GND
with light load), the output voltage has a DC regulation level higher than the error comparator threshold by 50% of the output
voltage ripple.
Note 2: Disables boost switching if either GD_I or VOP exceeds the threshold. Switching resumes when no threshold is exceeded.
Note 3: Specifications to TA = -40NC are guaranteed by design, not production tested.
10
70
500kHz
65
60
MAX17126 toc02
750kHz
750kHz
OUTPUT VOLTAGE (V)
EFFICIENCY (%)
80
75
3.350
MAX17126 toc01
85
3.325
3.300
500kHz
55
50
0.10
3.275
10.00
1.00
LOAD CURRENT (A)
2.00
2.40
MAX17126 toc03
MAX17126 toc04
VOUT
(AC-COUPLED)
200mV/div
0V
0.42
VIN
5V/div
VOUT
1V/div
0V
0V
IL2
1A/div
0A
IL2
1A/div
0A
0A
ILOAD
1A/div
0A
LX2
10V/div
20Fs/div
4ms/div
L = 4.7FH
80
500kHz
75
70
750kHz
65
16.440
OUTPUT VOLTAGE (V)
EFFICIENCY (%)
90
60
MAX17126 toc06
95
85
16.445
MAX17126 toc05
100
16.435
16.430
750kHz
16.425
500kHz
16.420
16.415
55
16.410
50
0.01
0.10
1.00
LOAD CURRENT (A)
10.00
0.5
1.0
1.5
LOAD CURRENT (A)
2.0
2.5
______________________________________________________________________________________ 11
MAX17126/MAX17126A
MAX17126 toc08
MAX17126 toc07
ILOAD
1A/div
0V
ILOAD
1A/div
0A
VAVDD
(AC-COUPLED)
200mV/div
0A
VAVDD
(AC-COUPLED)
200mV/div
0A
IL1
1A/div
0A
IL1
1A/div
0V
10Fs/div
20Fs/div
L = 10FH
L = 10FH
SWITCHING FREQUENCY
vs. INPUT VOLTAGE
497
SWITCHING FREQUENCY (kHz)
0V
VAVDD
5V/div
VGD
5V/div
0V
0V
IL1
1A/div
0A
495
494
493
492
491
490
488
8
SWITCHING
NO SWITCHING
1.2470
1.2465
50
100
150
LOAD CURRENT (FA)
12
VIN (V)
200
15.04
14.99
14.94
14.89
15.2
MAX17126 toc13
MAX17126 toc12
15.09
16
14
1.2480
15.14
GAMMA REFERENCE VOLTAGE (V)
1.2485
10
1.2490
496
489
1ms/div
1.2475
MAX17126 toc10
498
EN
5V/div
MAX17126/MAX17126A
15.1
15.0
14.9
14.8
14.7
14.6
14.5
14.84
15.0
15.5
17.5
18.0
50
100
150
200
LOAD CURRENT (mA)
12
250
-4
IGON = 25mA
-6
-8
-10
MAX17126 toc15
IGON = 0A
-2
0.5
OUTPUT CURRENT ERROR (%)
0
-0.5
-1.0
-1.5
-2.0
-12
10
11
12
13 14 15 16
SUPP VOLTAGE (V)
18
17
0.01
MAX17126 toc16
VGON
0V
(AC-COUPLED)
200mV/div
60mA
ILOAD
20mA/div
0A
10mA
IGON = 0mA
-0.02
-0.03
-0.04
8
10
11 12 13 14
SUPN VOLTAGE (V)
15
16
MAX17126 toc17
IGON = 25mA
-0.01
40Fs/div
0.2
150
50
100
LOAD CURRENT (mA)
MAX17126 toc17
MAX17126 toc14
-0.2
VGOFF
0V
-0.4
(AC-COUPLED)
200mV/div
-0.6
60mA
-0.8
ILOAD
20mA/div
-1.0
0A
10mA
-1.2
0
50
100
150
200
LOAD CURRENT (mA)
250
300
20Fs/div
______________________________________________________________________________________ 13
MAX17126/MAX17126A
0V
VOUT
0V
0V
VGOFF
VAVDD
VGON
0V
0V
VCOM
VDLY1
0V
0V
0V
VGHM
0V
MAX17126 toc20
2.65
VIN
2.60
VOP SUPPLY CURRENT (mA)
MAX17126/MAX17126A
2.55
2.50
2.45
2.40
2.35
2.30
VIN = 10V/div
VOUT = 5V/div
VGOFF = 10V/div
VAVDD =10V/div
10ms/div
VGON = 20V/div
VCOM = 10V/div
VDLY1 = 5V/div
VGHM = 50V/div
9 10 11 12 13 14 15 16 17 18 19 20
VOP VOLTAGE (V)
MAX17126 toc21
MAX17126 toc22
VOPP
5V/div
VCOM
0V
(AC-COUPLED)
500mV/div
0V
VCOM
5V/div
IVCOM
100mA/div
0A
0V
4Fs/div
1Fs/div
14
OPERATIONAL AMPLIFIER
SMALL-SIGNAL STEP RESPONSE
MAX17126 toc25
0V
VCOM
(AC-COUPLED)
200mV/div
0V
VOPP
(AC-COUPLED)
200mV/div
MAX17126 toc26
NO OUTPUT SWITCHING
3
2
1
0
100ns/div
10
12
14
16
OPERATIONAL AMPLIFIER
LARGE-SIGNAL STEP RESPONSE
MAX17126 toc23
MAX17126 toc27
VGVOFF
5V/div
0V
VGHM
10V/div
VOPP
5V/div
0V
0V
VCOM
5V/div
0V
1Fs/div
4Fs/div
______________________________________________________________________________________ 15
MAX17126/MAX17126A
MAX17126/MAX17126A
NAME
VREF_I
FUNCTION
Gamma Reference Input
VOP
OGND
OPP
OPN
OPO
PGOOD
Input voltage power-good open-drain output pulled high to VL or 3.3V through 10kI resistor.
GVOFF
High-Voltage Switch-Control Block Timing Control Input. See the High-Voltage Switch Control
section for details.
EN
Enable Input. Enable is high, turns on step-up converter and positive charge pump.
10
FB2
Step-Down Regulator Feedback Input. Connect FB2 to GND to select the step-down converters 3.3V
fixed mode. For adjustable mode, connect FB2 to the center of a resistive voltage-divider between the
step-down regulator output (OUT) and GND to set the step-down regulator output voltage. Place the
resistive voltage-divider within 5mm of FB2.
11
OUT
Step-Down Regulator Output Voltage Sense. Connect OUT to step-down regulator output.
12
N.C.
13, 14
LX2
Not Connected
Step-Down Regulator Switching Node. LX2 is the source of the internal n-channel MOSFET connected
between IN2 and LX2. Connect the inductor and Schottky catch diode to both LX2 pins and minimize
the trace area for lowest EMI.
15
BST
Step-Down Regulator Bootstrap Capacitor Connection. Power supply for high-side gate driver. Connect
a 0.1FF ceramic capacitor from BST to LX2.
16, 17
IN2
Step-Down Regulator Power Input. Drain of the internal n-channel MOSFET connected between IN2
and LX2.
18, 44
GND
Analog Ground
19
VDET
Voltage-Detector Input. Connects VDET to the center of a resistor voltage-divider between input voltage
and GND to set the trigger point of PGOOD.
20
INVL
Internal 5V Linear Regulator and the Startup Circuitry Power Supply. Bypass VINVL to GND with 0.22FF
close to the IC.
21
VL
5V Internal Linear Regulator Output. Bypass VL to GND with 1FF minimum. Provides power for the
internal MOSFET driving circuit, the PWM controllers, charge-pump regulators, logic, and reference
and other analog circuitry. Provides 25mA load current when all switching regulators are enabled. VL is
active whenever input voltage is high enough.
22
FSEL
Frequency Select Pin. Connect FSEL to VL or INVL or float FSEL pin for 750kHz operation. Connect to
GND for 500kHz operation.
23
CLIM
Boost Current-Limit Setting Input. Connects a resistor from CLIM to GND to set current limit for boost
converter.
24
SS
Soft-Start Input. Connects a capacitor from SS to GND to set the soft-start time for the step-up converter. A 5FA current source starts to charge CSS when GD is done. See the Step-Up Regulator External
pMOS Pass Switch section for description. SS is internally pulled to GND through 1kI resistance when
EN is low OR when VL is below its UVLO threshold.
25, 26
LX1
Step-Up Regulator Power-MOSFET n-Channel Drain and Switching Node. Connects the inductor and
Schottky catch diode to both LX1 pins and minimizes the trace area for lowest EMI.
27, 28
PGND
29
GD_I
Step-Up Regulator External pMOS Pass Switch Source Input. Connects to the cathode of the step-up
regulator Schottky catch diode.
16
NAME
FUNCTION
30
GD
Step-Up Regulator External pMOS Pass Switch Gate Input. A 10FA P 20% current source pulls down
on the gate of the external pFET when EN is high.
31
FB1
Boost Regulator Feedback Input. Connects FB1 to the center of a resistive voltage-divider between the
boost regulator output and GND to set the boost regulator output voltage. Place the resistive voltagedivider within 5mm of FB1.
32
COMP
33
THR
VGHM Low-Level Regulation Set-Point Input. Connects THR to the center of a resistive voltage-divider
between AVDD and GND to set the VGHM falling regulation level. The actual level is 10 x VTHR. See the
Switch Control section for details.
34
SUPP
Positive Charge-Pump Drivers Power Supply. Connects to the output of the boost regulator (AVDD) and
bypasses to CPGND with a 0.1FF capacitor. SUPP is internally connected to GD_I.
35
CPGND
36
DRVP
Positive Charge-Pump Driver Output. Connects DRVP to the positive charge-pump flying capacitor(s).
37
DLY1
High-Voltage Switch Array Delay Input. Connects a capacitor from DLY1 to GND to set the delay time
between when the positive charge pump finishes its soft-start and the startup of this high-voltage switch
array. A 10FA current source charges CDLY1. DLY1 is internally pulled to GND through 50I resistance
when EN is low or when VL is below its UVLO threshold.
38
FBP
Positive Charge-Pump Regulator Feedback Input. Connects FBP to the center of a resistive voltagedivider between the positive charge-pump regulator output and GND to set the positive charge-pump
regulator output voltage. Place the resistive voltage-divider within 5mm of FBP.
39
VGH
Switch Input. Source of the internal high-voltage p-channel MOSFET between VGH and VGHM.
40
VGHM
41
DRN
Switch Output. Drain of the internal high-voltage p-channel MOSFET connected to VGHM.
42
SUPN
Negative Charge-Pump Drivers Power Supply. Bypass to CPGND with a 0.1FF capacitor. SUPN is internally connected to IN2.
43
DRVN
Negative Charge-Pump Driver Output. Connects DRVN to the negative charge-pump flying
capacitor(s).
45
FBN
Negative Charge-Pump Regulator Feedback Input. Connect FBN to the center of a resistive voltagedivider between the negative output and REF to set the negative charge-pump regulator output voltage.
Place the resistive voltage-divider within 5mm of FBN.
46
REF
Reference Output. Connects a 0.22FF capacitor from REF to GND. All power outputs are disabled until
REF exceeds its UVLO threshold.
47
VREF_FB
Gamma Reference Feedback Input. Connect VREF_FB to the center of a resistive voltage-divider
between VREF_O and GND to set the gamma reference output voltage. Place the resistive voltagedivider within 5mm of VREF_FB.
48
VREF_O
EP
Compensation Pin for the Step-Up Regulator Error Amplifier. Connects a series resistor and capacitor
from COMP to ground.
Internal High-Voltage MOSFET Switch Common Terminal. VGHM is the output of the high-voltage
switch-control block.
Exposed Pad. Connects EP to GND, and ties EP to a copper plane or island. Maximizes the area of this
copper plane or island to improve thermal performance.
______________________________________________________________________________________ 17
MAX17126/MAX17126A
MAX17126/MAX17126A
C1
L1
10H
0.1F
D1
BST
LX1
IN2
C4
LX1
IN2
C2
PGND
PGND
FB1
COMP
L2
OUT
3.3V, 1.5A
D2
C5
LX2
FSEL
LX2
CLIM
RCOMP
25kI
R2
CCOMP
1nF
R1
OUT
GD_I
Q1
GD
VL (OR 3.3V)
FB2
R7
68.1kI
PGOOD
VIN
VIN
10kI
MAX17126
MAX17126A
INVL
AVDD
16V, 1A
VDET
C3
0.1F
R8
422kI
VL
VL
VOP
REF
OPN
GND
OGND
1F
REF
OPP
0.22F
ON/OFF
OPO
2.2kI
1kI
EN
DRN
13.3kI
DLY1
0.1uF
GVOFF
VREF_I
GREF
VCOM
THR
SS
UNCONNECTED OR 150nF
AVDD
13.3kI
0.1F
3
2.2kI
FROM
TCON
150F
VGHM
VGHM
VREF_O
VGH
SUPP
R9
1.61kI
0.1F
VREF_FB
SUPN
R10
1.3nF
D3
VGH
35V, 50mA
0.1F
DRVP
D4
VGOFF
-6V, 50mA
C11
1F
1F
C12
DRVN
C14
0.1F
R5
R6
C10
0.1F
FBN
FBP
CPGND
R3
AVDD
C13
D5
C15
33pF
R4
REF
C5
D1, D2
D3, D4, D5
DESCRIPTION
10FF P Q10%, 25V X5R ceramic
capacitors (1206)
Murata GRM31CR61E106K
TDK C3216X5R1E106M
22FF Q10%, 6.3V X5R ceramic capacitor
(0805)
Murata GRM21BR60J226K
TDK C2012X5R0J226K
Schottky diodes 30V, 3A (M-flat)
Toshiba CMS02
Dual diodes 30V, 200mA (3 SOT23)
Zetex BAT54S
Fairchild BAT54S
L1
L2
FAX
Fairchild Semiconductor
SUPPLIER
408-822-2000
408-822-2102
www.fairchildsemi.com
WEBSITE
Sumida Corp.
847-545-6700
847-545-6720
www.sumida.com
TDK Corp.
847-803-6100
847-390-4405
www.component.tdk.com
949-455-2000
949-859-3963
www.toshiba.com/taec
______________________________________________________________________________________ 19
MAX17126/MAX17126A
VIN
L1
BST
IN2
OUT
LX1
VL
LX2
STEP-DOWN
REG
STEP-UP
REG
OSC
PGND
FB1
COMP
OUT
FSEL
CLIM
GD_I
GD
FB2
VIN
VL (OR 3.3V)
150mV
INVL
VL
VL
REF
PGOOD
VL
REF
VDET
REF
VOP
GND
ON/OFF
VCOM
AMP
EN
DLY1
SS
AVDD
GREF
AVDD
VIN
REF
SEQUENCE
MAX17126/MAX17126A
OPP
OPN
OPO
VCOM
OGND
VREF_I
DRN
VREF_O
GAMMA
REF
THR
HIGHVOLTAGE
SWITCH
BLOCK
VREF_FB
GVOFF
FROM
TCON
VGHM
VGHM
VGH
IN2
GD_I
50%
OSC
SUPN
SUPP
VGH
DRVP
VGOFF
DRVN
CPGND
NEGATIVE
CHARGE
PUMP
FBN
POSITIVE
CHARGE
PUMP
FBP
CPGND
AVDD
REF
Dual-Mode Feedback
The step-down regulator of the MAX17126/MAX17126A
support both fixed output and adjustable output. Connect
FB2 to GND to enable the 3.3V fixed-output voltage.
Connect a resistive voltage-divider between OUT and
GND with the center tap connected to FB2 to adjust the
output voltage. Choose RB (resistance from FB2 to GND)
to be between 5kI and 50kI, and solve for RA (resistance from OUT to FB2) using the equation:
V
RA = RB OUT - 1
V
FB2
where VFB2 = 1.25V, and VOUT may vary from 1.5V to 5V.
Because FB2 is a very sensitive pin, a noise filter is generally required for FB2 in adjustable-mode operation.
Place an 82pF capacitor from FB2 to GND to prevent
unstable operation. No filter is required for 3.3V fixedmode operation.
Soft-Start
The step-down regulator includes a 7-bit soft-start DAC
that steps its internal reference voltage from zero to
1.25V in 128 steps. The soft-start period is 3ms (typ)
and FB2 fault detection is disabled during this period.
The soft-start feature effectively limits the inrush current
during startup (see the Step-Down Regulator Soft-Start
Waveforms in the Typical Operating Characteristics).
Step-Up Regulator
The step-up regulator employs a current-mode, fixed-frequency PWM architecture to maximize loop bandwidth
and provide fast-transient response to pulsed loads
typical of TFT LCD panel source drivers. The integrated
MOSFET and the built-in digital soft-start function reduce
the number of external components required while
controlling inrush currents. The output voltage can be
set from VIN to 16.5V with an external resistive voltagedivider. The regulator controls the output voltage and the
power delivered to the output by modulating duty cycle
D of the internal power MOSFET in each switching cycle.
The duty cycle of the MOSFET is approximated by:
where VAVDD is the output voltage of the step-up regulator, VDIODE is the voltage drop across the diode, and
VLX1 is the voltage drop across the internal MOSFET.
______________________________________________________________________________________ 21
MAX17126/MAX17126A
Step-Down Regulator
The step-down regulator consists of an internal n-channel MOSFET with gate driver, a lossless current-sense
network, a current-limit comparator, and a PWM controller block. The external power stage consists of a
Schottky diode rectifier, an inductor, and output capacitors. The output voltage is regulated by changing the
duty cycle of the high-side MOSFET. A bootstrap circuit
that uses a 0.1FF flying capacitor between LX2 and BST
provides the supply voltage for the high-side gate driver.
Although the MAX17126/MAX17126A also include a 10I
(typ) low-side MOSFET, this switch is used to charge the
bootstrap capacitor during startup and maintains fixedfrequency operation at light load and cannot be used as
a synchronous rectifier. An external Schottky diode (D2
in Figure 1) is always required.
MAX17126/MAX17126A
GD_I
ERROR
AMPLIFIER
OSC
SUPP
C12
P1
D5
C14
REF
1.25V
DRVP
C13
MAX17126
MAX17126A
POSITIVE CHARGE-PUMP REGULATOR
N1
D3
CPGND
VGH
C15
FBP
MAX17126
MAX17126A
ERROR
AMPLIFIER
SUPN
IN2
OSC
P2
REF
0.25V
DRVN
C10
D4
N2
VGOFF
CPGND
C11
R5
FBN
REF
R6
______________________________________________________________________________________ 23
MAX17126/MAX17126A
the output voltage of the positive charge-pump regulator. The charge pump includes a high-side p-channel
MOSFET (P1) and a low-side n-channel MOSFET (N1) to
control the power transfer as shown in Figure 3.
MAX17126/MAX17126A
10A
DLY1
Q4
FAULT
SHDN
EN
GD DONE
VGH
VREF
Q1
VGHM
9R
1kI
GVOFF
Q2
DRN
THR
Operational Amplifier
24
OPP
4V 500
High-Accuracy,
High-Voltage Gamma Reference
OPN
OPO
PGOOD Function
OGND
SWITCHING FREQUENCY
(kHz)
750
GND
500
______________________________________________________________________________________ 25
MAX17126/MAX17126A
MAX17126/MAX17126A
VL
UVLO
INVL UVLO
REF
UVLO
tSS
TIME
tSS
BUCK FAULT BLANK
NEGATIVE CHARGE-PUMP FAULT BLANK
NEGATIVE
CHARGE-PUMP
REGULATOR
OUTPUT
PGOOD
TIME
POSITIVE CHARGE -PUMP FAULT BLANK
BOOST FAULT BLANK
POSITIVE
CHARGE-PUMP
REGULATOR
OUTPUT
AVDD
GREF
GD
SS
GD
DONE
REF
tSS
TIME
tSS
DLY1
REF
TIME
VGHM UNCONNECTED
VGHM
VGHM DEPENDS
ON GVOFF
TIME
Fault Protection
Thermal-Overload Protection
INVL UVLO
INVL
VL UVLO
VL
REF
TIME
NEGATIVE
CHARGE-PUMP
REGULATOR
OUTPUT
POSITIVE
CHARGE-PUMP
REGULATOR
OUTPUT
AVDD
TIME
Design Procedure
Step-Down Regulator
GREF
TIME
BUCK
OUTPUT
PGOOD
TIME
VGHM
VGHM DEPENDS
ON GVOFF
VGHM UNCONNECTED
TIME
Inductor Selection
Three key inductor parameters must be specified:
inductance value (L), peak current (IPEAK), and DC
resistance (RDC). The following equation includes a
constant, LIR, which is the ratio of peak-to-peak inductor
ripple current to DC load current. A higher LIR value
allows smaller inductance, but results in higher losses
and higher ripple. A good compromise between size
and losses is typically found at a 30% ripple current-toload current ratio (LIR = 0.3) that corresponds to a peak
inductor current 1.15 times the DC load current:
L2 =
______________________________________________________________________________________ 27
MAX17126/MAX17126A
Power-Down Sequence
MAX17126/MAX17126A
IOUT_PEAK = 1.5A +
= 0.68A
0.68A
= 1.84A
2
Input Capacitors
The input filter capacitors reduce peak currents drawn
from the power source and reduce noise and voltage
ripple on the input caused by the regulators switching.
They are usually selected according to input ripple
current requirements and voltage rating, rather than
capacitance value. The input voltage and load current
determine the RMS input ripple current (IRMS):
IRMS = IOUT
VOUT_RIPPLE(C) =
IOUT_RIPPLE
8 C OUT fSW
28
L 2 (DIOUT ) 2
L 2 (DIOUT ) 2
2 C OUT VOUT
Step-Up Regulator
Inductor Selection
The inductance value, peak current rating, and series
resistance are factors to consider when selecting the
inductor. These factors influence the converters efficiency,
maximum output load capability, transient response time,
and output voltage ripple. Physical size and cost are also
important factors to be considered.
VAVDD
I AVDD(MAX) VAVDD
VIN(MIN) MIN
______________________________________________________________________________________ 29
MAX17126/MAX17126A
MAX17126/MAX17126A
I
I AVDD_PEAK = IIN(DC,MAX) + AVDD_RIPPLE
2
The inductors saturation current rating and the MAX17126/
MAX17126As LX1 current limit should exceed IAVDD_
PEAK and the inductors DC current rating should exceed
IIN(DC,MAX). For good efficiency, choose an inductor with
less than 0.1I series resistance.
Considering the typical operating circuit (Figure 1), the
maximum load current (IAVDD(MAX)) is 1A with a 16V
output and a typical input voltage of 12V. Choosing
an LIR of 0.3 and estimating efficiency of 90% at this
operating point:
2
= 9FH
16V 1A 750kHz 0.3
Using the circuits minimum input voltage (8V) and
estimating efficiency of 85% at that operating point:
IIN(DC,MAX) =
1A 16V
2.35A
8V 85%
8V (16V - 8V)
10FH 16V 750kHz
I AVDD_PEAK = 2.35A +
0.53A
0.53A
2.62A
2
V
I
-V
VAVDD_RIPPLE(C) AVDD AVDD IN
C AVDD VAVDDfSW
and:
VAVDD_RIPPLE(ESR) I AVDD_PEAKR ESR_AVDD
where IAVDD_PEAK is the peak inductor current (see
the Inductor Selection section). For ceramic capacitors,
R1 = R2 AVDD - 1
V
FB1
VAVDD C AVDD
10 I AVDD(MAX) R COMP
30
V
+ VDROPOUT - VAVDD
n POS = GH
VSUPP - 2 VD
where nPOS is the number of positive charge-pump
stages, VGH is the output of the positive charge-pump
regulator, VSUPP is the supply voltage of the chargepump regulators, VD is the forward voltage drop of the
charge-pump diode, and VDROPOUT is the dropout
margin for the regulator. Use VDROPOUT = 300mV.
The number of negative charge-pump stages is given by:
n NEG =
-VGOFF + VDROPOUT
VSUPN - 2 VD
V
+ VDROPOUT - VOUT
n POS = GH
VSUPP - 2 VD
nNEG =
Flying Capacitors
Increasing the flying capacitor CX (connected to DRVP
and DRVN) value lowers the effective source impedance
and increases the output current capability. Increasing
the capacitance indefinitely has a negligible effect on
output current capability because the internal switch
resistance and the diode impedance place a lower limit
ILOAD_CP
2 fSW VRIPPLE_CP
R3 = R4 VGH - 1
VFBP
where VFBP = 1.25V (typ).
Adjust the negative charge-pump regulators output
voltage by connecting a resistive voltage-divider from
VGOFF to REF with the center tap connected to FBN
(Figure 1). Select R6 in the 20kI to 68kI range. Calculate
R5 with the following equation:
V
-V
R5 = R6 FBN GOFF
VREF - VFBN
where VFBN = 250mV, VREF = 1.25V. Note that REF
can only source up to 50FA, using a resistor less than
20kI, for R6 results in a higher bias current than REF
can supply.
______________________________________________________________________________________ 31
MAX17126/MAX17126A
MAX17126/MAX17126A
R9 = R10 REF_O -1
V
REF_FB
where VREF_FB, the LDOs feedback set point, is 1.25V.
Place R9 and R10 close to the IC.
Input and Output Capacitor Selection
To ensure stability of the LDO, use a minimum of 1FF
on the regulators input (VREF_I) and a minimum of 2.2FF
on the regulators output (VREF_O). Place the capacitors
near the pins and connect their ground connections
directly together.
R7 = R8 IN_PGOOD -1
V
DET
32
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
No.
LAND PATTERN
No.
48 TQFN
T4877-3
21-0144
90-0129
LX1
PGND
PGND
GD_I
GD
FB1
COMP
THR
CPGND
SUPP
DRVP
LX1
SS
FBP
38
23
CLIM
VGH
39
22
FSEL
VGHM
40
21
VL
DRN
41
20
INVL
SUPN
42
19
VDET
DRVN
43
18
GND
GND
44
17
IN2
FBN
45
16
IN2
46
15
BST
REF
MAX17126
MAX17126A
LX2
10 11 12
N.C.
FB2
OUT
LX2
13
EN
14
48
GVOFF
47
VREF_O
PGOOD
VREF_FB
OPO
24
OPN
Package Information
37
OPP
PROCESS: BiCMOS
DLY1
OGND
Chip Information
36 35 34 33 32 31 30 29 28 27 26 25
VOP
TOP VIEW
VREF_I
Pin Configuration
THIN QFN
______________________________________________________________________________________ 33
MAX17126/MAX17126A
MAX17126/MAX17126A
REVISION
DATE
6/09
Initial release
3/10
DESCRIPTION
PAGES
CHANGED
1-33
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.
34
2010
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
Maxim Integrated Products