Switching Circuits & Logic Design

Reduction of State Table and State

Assignment
Professor Chien-Mo James Li
Graduate Institute of Electronics Engineering
National Taiwan University
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Objective of this Chapter

Learn how to reduce state table
Learn how to assign states

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Flow of Design a Sequential Ckt.

specification
Ch 14
State graph
State Table

Ch 15
Ch 12

Ch 13

Ch 16

K-map
FF, Comb Logic
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Outline

15.1 Elimination of Redundant States

15.2 Equivalent State
15.3 Determination if State Eq. Using Implication Table
15.4 Equivalent Sequential Circuits
15.5 Incompletely Specified State Tables
15.6 Derivation of Flip-Flop Input Equations
15.8 State Assignment (not in exam)

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Old Example (14.3)

Specification:

Design a Sequence detector with one input and one output

Inputs sequence is grouped in 4
Output = 1 if input = 0101 or 1001
Partial graph

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Complete graph

Present Next State

State
X=0 X=1

Present
Output
X=0 X=1

S0
S1
S2
S5
S3
S6
S4

0
0
0
0
0
0
0

B
D
E
H
J
A
A

Fig. 15-1 (a)

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C
E
D
H
H
A
A

0
0
0
0
0
0
1
Fig. 15-1 (b)

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Question!
I am not very smart .

What if I create more states than needed?

A
0

C
0

D
0

F
1

K L

M N

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Before
State table

Table 15-1
Input
Present
Sequence
State
reset
0
1
00
01
10
11
000
001
010
011
100
101
110
111

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A
B
C
D
E
F
G
H
I
J
K
L
M
N
P

Next State
X=0
B
D
F
H
J
L
N
A
A
A
A
A
A
A
A

X=1
C
E
G
I
K
M
P
A
A
A
A
A
A
A
A

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Present Output
X=0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

X=1
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0

After
State table

Table 15-2
Input
Present
Sequence
State
reset
0
1
00
01
10
11
000
001
010
011
100
101
110
111

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A
B
C
D
E
F
G
H
I
J
K
L
M
N
P

Next State
X=0
B
D
F
H
J
L
N
A
A
A
A
A
A
A
A

X=1
C
E
G
I
K
M
P
A
A
A
A
A
A
A
A

Present Output
X=0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

X=1
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0

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Outline

15.1 Elimination of Redundant States

15.2 Equivalent State
15.3 Determination if State Eq. Using Implication Table
15.4 Equivalent Sequential Circuits
15.5 Incompletely Specified State Tables
15.6 Derivation of Flip-Flop Input Equations
15.8 State Assignment (not in exam)

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Equivalent State
Definition 15.1 pq

Let N1 and N2 be sequential circuits (not necessarily different).

Let X represent an input sequence of arbitrary length. Then state
p in N1 is equivalent to state q in N2 iff Output1(p, X) = output2
(q, X) for EVERY possible input sequence X.
Problem
X can be very long

10101110101110.

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Theorem 15.1
Two states p and q of a sequential circuit are equivalent iff for every
SINGLE input X,
the outputs are the same ; (p,X) = (q, X)
and the next states are equivalent. (p, X) (q, X)

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12

Row Matching Technique

One way to delete unneeded states
Procedures
1. find states with same NS and same output equivalent states
2. leave one state from a group of equivalent states,
delete all the others
3. update the next state portion of the state table
4. repeat step 1 to 3 until no more equivalent states found
Table 15-2 Example

Problem: Row matching technique helps to find some equivalent

states
But not ALL equivalent states

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Outline

15.1 Elimination of Redundant States

15.2 Equivalent State
15.3 Determination if State Eq. Using Implication Table
15.4 Equivalent Sequential Circuits
15.5 Incompletely Specified State Tables
15.6 Derivation of Flip-Flop Input Equations
15.8 State Assignment (not in exam)

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14

Implication Table (Aka. Pair Chart)

Table 15-3 Fig 15-3
ab iff
d f and c h
States d-f and c-h are
Implied pairs of a-b

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First Pass
Fig 15-4
Square can be cross out if
ANY ONE implied pair NOT
equivalent

a-b is crossed out because

f-d NOT equivalent

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Second Pass
Fig 15-4
a-g is crossed out because
b-d NOT equivalent

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Final Result
After third pass, nothing change

stop
Results
ad
ce

Reduced 2 states out of 8

final results Table 15-4

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Outline

15.1 Elimination of Redundant States

15.2 Equivalent State
15.3 Determination if State Eq. Using Implication Table
15.4 Equivalent Sequential Circuits
15.5 Incompletely Specified State Tables
15.6 Derivation of Flip-Flop Input Equations
15.8 State Assignment (not in exam)

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Equivalent Sequential Circuits

Def 15.2:
Two sequential circuits are equivalent N1N2

If for each state p in N1, there is a state q in N2

Such that p q
And conversely, for each state s in N2, there is a state t in N1
Such that s t

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Check Equivalence by Inspection

Fig 15-6 compare two state graphs by inspection
A! S3 because outputs do not match
A S2, B S0, D S1, C S3
N1 N2
Not easy for large design

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Check Equivalence by Table (1)

Fig 15-7 Implication table
Compare every row of N1 with every row of N2
X represents mismatch in outputs

A ! S0, A ! S3
A S1 if B S3, A S0

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X=0 X=1

X=0 X=1

X=0 X=1

X=0 X=1

S0

S3

S1

S1

S3

S0

S2

S0

S2

S3

S2

S3

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22

Check Equivalence by Table (2)

Cross out impossible cells
Because A ! S0

AS1 is crossed out

Results
A S2, B S0,
D S1, C S3
N1 N2

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FFT
Why is checking equivalent states so important?

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Outline

15.1 Elimination of Redundant States

15.2 Equivalent State
15.3 Determination if State Eq. Using Implication Table
15.4 Equivalent Sequential Circuits
15.5 Incompletely Specified State Tables
15.6 Derivation of Flip-Flop Input Equations
15.8 State Assignment (not in exam)

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Incompletely Specified State Table

Certain sequence will never occur as input
Output of circuits will be observed at certain time
Example Fig 15-8

Input to B has only two sequence

Output of B observed only at t2

t0 t1 t2
X=1 0 0
X=1 1 0

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t0 t1 t2
Z= - Z= - -

0
1

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How to Reduce?
Fill the dont cares in appropriate manner and reduce the table
Example Table 15-5
t0 t1 t2

t0 t1 t2

X=1 0 0
X=1 1 0

Z= - Z= - -

0
1

Merge S0 S2
Merge S1 S3

X=0 X=1

X=0 X=1

X=0 X=1

X=0 X=1

X=0 X=1

X=0 X=1

S0 -

S1

S0 (S0) S1

(0)

S0 S0

S1

S1 S2

S3

S1 S0

S3

(1)

S1 S0

S1

S2 S0

S2 S0

(S1)

S3 S0

S3 S0

(S3)

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Unfortunately, determining the best way to fill in the dont cares

requires trial and error

Large design difficult to solve by hand
Minimization of state table will be covered in other classes
Such as Algorithm or Introduction to EDA

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Outline

15.1 Elimination of Redundant States

15.2 Equivalent State
15.3 Determination if State Eq. Using Implication Table
15.4 Equivalent Sequential Circuits
15.5 Incompletely Specified State Tables
15.6 Derivation of Flip-Flop Input Equations
15.8 State Assignment (not in exam)

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How many FFs Do we need?

Number of FF = n
Must satisfy

2n number of states > 2n-1

so that we have enough FF to represents all different states

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Derive FF Input Equations

1. Assign flip-flop state values to correspond to the states in the

reduced table
See 15.8 for more
2. Construct a transition table which gives the next states of FF as a
function of present states and inputs
3. Derive the next-state map for the transition table
4. Find FF input map from the next-state map
See Ch 12
5. Find FF input equations

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Example
Table 15-6
Assign states

S0=000, S1=110, S2=001, S3=111, S4=011, S5=101, S6=010

Why? See 15.8

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Another Example
Table 15-7

Two inputs, two outputs

Use D-FF

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 Use SR FF

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Outline

15.1 Elimination of Redundant States

15.2 Equivalent State
15.3 Determination if State Eq. Using Implication Table
15.4 Equivalent Sequential Circuits
15.5 Incompletely Specified State Tables
15.6 Derivation of Flip-Flop Input Equations
15.8 State Assignment (not in exam)

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State Assignment
What is it?

Assign binary numbers to every state

A good state assignment helps to reduce combinational logic
complexity
Straight state assignment is not always good
00 S0, 01 S1, 10 S2
Some guideline is needed for a good assignment

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Adjacent States
Two states are adjacent if their code differ in only one variable

E.g. 000, 001 are adjacent

On Kmap, adjacent states are map to neighboring cells

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Guidelines for State Assignment

The following states should be assign to adjacent states:
1. same next state for a given input
2. next states of the same state
3. same output for a given input

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Example
State Table Fig 15-14

Rule 1 (S0, S1, S3, S5) (S3, S5), (S4, S6), (S0, S2, S4, S6)
Rule 2 (S1, S2) (S2, S3) (S1, S4)
(S2, S5) x2
(S1, S6) x2

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Two possible Assignments

Either one is fine

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Next-state map
Adjacent states help to simplify K map

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Next-state Map (contd)

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Final Notice
Not possible to satisfy all guidelines

Give priority to more frequent states groups

There are many possible assignments

Not possible to try all

Stop as long as assignment is good enough

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Next Time

ch 9 Multiplexers Decoders and PLD

ch 11 Latches and FF
ch 12 Registers and Counters
ch 13 Analysis of Clock Sequential Ckts
ch 14 Derivation of State Graphs and
Tables
ch 16 Sequential Ckt Design
ch 18 Ckts for Arith. Operations
final exam

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