ECE 4141 VLSI Design

Created by Ahmad Anwar Zainuddin and Dr. Anis Nurashikin Nordin

Experiment 3:
1. Introduction to Microwind Analysis of CMOS 0.35 micron Technology MOSFET
2. CMOS 0.35 micron Technology Inverter Characteristic and layout in Microwind
3. To extract netlist from the inverter layout for SPICE.
Overview
The main goal of this tutorial is to walk through using Layout based EDA tool MIcrowind and the
introduction will be accompanied with analysis of MOS transistor.
You can direct download the software at this link: MICROWIND2
If the link not working, please try this link:
http://www.mediafire.com/download/p5ygrkkhuch0cqg/Microwind2.zip
The tasks given in the lab include:

Familiarity and Hands on Example using tool

Layout Design using tool
Study of MOSFET characteristics
Analog simulation of MOSFETs
Design of CMOS Inverter and transistor sizing
Gate delay, area and the effects of transistor sizing on these parameters.

CMOS Technology : 0.35um

Introduction:
1. MOSFET
The Metal Oxide Semiconductor Field Effect Transistor is very important part of Digital Integrated Circuits. It is
mostly used as switch in digital design. MOSFET is a four terminal device. The voltage applied to the gate terminal
determine the current flow between drain and source terminals. The body/substrate of the transistor is the fourth
terminal. Mostly the fourth terminal (body/substrate) of the device is connected to dc supply that is identical for all
devices of the same type (GND for nMOS and Vdd for pMOS). Usually this terminal is not shown on the
schematics.

2. nMOS
The nMOS transistor consists of n+ drain and source diffusion regions, which are embedded in a p-type substrate.
The electrons in the channel beneath the gate between source and drain terminal are responsible for the current flow.

3. pMOS
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The pMOS transistor consists of p+ drain and source diffusion regions, which are embedded in an n-type substrate.
The holes in the channel beneath the gate between source and drain terminal are responsible for the current flow.

4. CMOS
The CMOS (Complementary MOS) consist of both p-type and n-type MOS. The advantage of CMOS is its low
power design due its Static behavior.

5. CMOS Inverter
CMOS Inverter/NOT gate is considered to be the heart of VLSI circuits, based on the understanding of NOT gate
we can extend it easily to NAND and NOR gates which are the basic building blocks of more complex circuits e.g.
multipliers and microprocessors. As per discussion and design on white board in the Lab, a NOT gate can be
implemented using two FETs i.e. a pFET and an nFET both connected in series, in which Vdd is supplied to pFET
and nFET is grounded, input x is applied to the gate terminals of both and the output is obtained at node y.

Design/ Diagram/Circuit

As covered in the lectures we know that the mobility of the holes is less than that of electrons, and in CMOS inverter
pFET is responsible for the conduction of current leading a logic 1 at the output, while nFET is responsible for the
conduction of current leading a logic 0 at the output. This means that the gate delay form low to high will be
greater than the gate delay for low to high voltage.

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Tutorial : CMOS 0.35 micron Technology Inverter

a) Open the Microwind2 by double clicking it located in the installed directory of
microwind2.

Microwind2
The following Microwind Interface will be appeared as below.

On the right side of the window, you can see a pallet. This is your basic tool. Using palette,
you can lay different layers, for example, Polysilicon, Diffusion Layer, N-Well etc. At the
top of the screen you can see various icons. Let us explore each of them one by one.

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To make use of any of the following palette

tools, click on it, and then click on the layer to
which you want to apply:
1. Vdd Supply. This is used to supply the
necessary voltage required for the layout. We
usually apply this to N Well (to avoid floating)
and to pMOS.
2. Ground. As simple as ground. It grounds the
region over which it is placed.
3. Ads Clock to the clicked region. You can
specify the period, low time, high times and
many other specifications. If you are a beginner,
do not change the default values. Simply click
and click on the region to be applied.
Important note: Once you have applied clock to
any node (point or region), the next time when
you click on it to apply it to other region, it takes
a period twice that of last click automatically.
This happens to maintain binary counting.
4. If you want to see voltage, current or few other parameters of the node, then this is used.
Usually it is used to see the output during simulation. It can also be used in debugging the
layout by checking behavior of a particular node. You can see few other buttons too. We shall
come to them as and when we use them. The next set of palette tools are to be used in a bit
different way. For example, if you need a polysilicon layer, then click on Red Icon with
Polysilicon written on it (They were a bit considerate to do that favor to us J ). Come to the
main area (Black: Substrate) hold the left mouse button, move the mouse holdingthe left button.
5. The metal 1 Layer. When you need to give metallic connection between two different parts
of the layout, use this option. Please note that when you draw the metal layer over say a
polysilicon, it doesnt get connected (attached) automatically. You need to use an appropriate
contact to do this. The following diagram illustrates various contacts.

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6. Polysilicon.
7. P+ Diffusion. The substrate which we use here is P-substrate(Black Colour). We are
supposed to lay it under N-well. You can draw P+ diffusion first, but make sure that you
cover it with N-well. The + sign indicates that it is doped higher than the P substrate. I
recommend drawing it on the top. It wont make any difference wherever you draw, but it
increases understand-ability of the circuit. Follow the convention everywhere.
8. N+ Diffusion. I suggest drawing it in the bottom. Its same as P+. But it doesnt need any
well. You can simply place it over P-substrate.
9. The much discussed N well is ready to be drawn now! (Finally). You can lay it over P+
Diffusion. Make sure that it surrounds it completely. Various layers in the following figure.

b) Lets have a look at the tools which are there in the top menu bar. See the related definition
based on the number indication.

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1. Opens already existing layout. If you have saved your layout somewhere, browse to that folder and
you can open it.
2. Save the current layout. The layouts are stored with .MSK extension. If you want to store to a
specific location go to File>Save As.
3. Its called draw box. When you click on this, then you can draw the last layer you selected from
palette.
4. To erase, delete or remove a particular area.
5. Why to draw the same device again which you have already drawn? We have a copy tool. Click on
this, then again highlight the area by holding the left mouse key and covering that area, release the
mouse button. Safely place the area where you want to.
6. Stretch (Resize)/Move tool. Yet another important tool. It is used if you want to move a certain
layout from on place to another.
7. Zoom In (Maximize) the layout. If you want to view the layout in detail, use this tool.
8. Zoom out. I suggest using this when you are drawing a large layout. Zoom out to connect the
devices in proper alignment.
9. See All. As it says, it fits your layout to the screen.
10. It shows the electrical properties. (You will not be using it initially, so dont worry)
11. Run Simulation: Click this when you are done. It shows the various input and output waveform.
(We will come to this in the next part)
12. Measures the distance of various layers, devices. If you know the design rule, use it repeatedly to
verify you adhere to them
13. 2-D cross section. As the name indicates, it shows the 2-Dimensional view of the selected area.
This gives 3-D view of the layout. Try this out, looks good!
14. DRC: Design Rule Check. It check various design rules and suggest corrections if the rules are
violated. Hint: It is recommended to perform the DRC after laying each and every layer. This helps
you to debug the circuit easily. Also try to use as less amount of diffusion or silicon as possible.
Remember: In silicon real estate, every nano meter is precious. Not only that, it prevents unwanted
capacitance and resistance.
15. Add text. This is like commenting code in programming language. It helps to make your layout
readable. Click on this tool and click where you want to add the text.
16. Connect Layers: Suppose you have drawn two layers, and want to interconnect (they are not
connected by default) click on this and then on the layers.
17. This simulates MOS characteristics.
18. Show Palette. It happens. Sometimes, the palette disappears. To get it back, click on this.
19. To scroll around the layout, to see various areas, use these arrows.
20. To move layout, up, down, left, right

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c) Select the foundry using the command File > Select Foundry

Thing to remember:
Since we are dealing with the model of 0.35 um CMOS technology, make sure the design
rule process is correct. Select 0.35-micron process by selecting cmos035.rul file. You can
get the rule from the same given folder. Or,
File >Select Foundry>MIcrowind2>Design Rule Technology>cmos035.rul .

d) Save the design as inverter01 using the command File > Save as.
e) Create an nMOS by using the nMOS generator button in the Palette. Then do the same
for pMOS transistor.
For nMOS device, make it (W/L) to (1.4um/0.4um), whilst pMOS device turn (W/L)
to 2.2um/0.4um).
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You can set the width and length of MOS by typing in the fields Width MOS and Length MOS
either in micron or in lambda units as indicated in the above figure. Click on Generate Device
Tab to generate the device.

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f) Well tap and Substrate tap.

Based on figure below, for pMOS , we are going to draw the well tap. This consists of an ntype diffusion region (nactive and nselect) and a contact. In the case of the nMOS we don't
need to draw a well because the substrate is already p-type so the device is already isolated
by a pn junction as long as this junction remains reverse-biased. We can ensure this by
drawing a substrate tap to tie the substrate to ground.

Based on the figure, follow these steps

accordingly:
1. Select Contact N+ and place
beside the pMOS device. For
pMOS, Select N+ Diffusion layer
and cover the Contact N+.

2. For nMOS, do the same like (3)

but substitute contact N+ to
Contact P+ and covered by P+
diffusion layer.

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g) Connect the two transistors, Vdd , Ground, Drain of pMOS/nMOS, Well-tap and Substratetap using Metal 1 as per design below.

Select Metal 1 and do the following steps:

1. Draw a rectangular Metal1 as Vdd.
2. Draw a rectangular Metal1 as Ground/Vss.
3. Connect
pMOSand
to Vdd.
h)
Connectsource
Gate pMOS
nMOS using Polysilicon.
4. Connect source nMOS to Ground/Vss.
5. Connect drain pMOS and nMOS together.

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Select Polysilicon and do the following steps:

1. Gate pMOS and nMOS are connected.
2. Apply the voltages and output node using the symbol buttons Vdd, Gnd, Add a
VClock, and Visible node in the Palette menu, as indicated in the following
figure.
3. You can use the Stretch/Move command button for these actions
1. Vdd+ on Metal 1 (top) = 3.5V
2. Connect the nWell to Vdd+ = 3.5V
3. Vout at drain of pMOS and nMOS

4. Vin(Clock) on Polysilicon

5. Vss- (ground)
metal
1 (bottom)
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Ahmad
Anwar Zainuddin

i) Check the design using DRC for any design rule violation and correct the design in case
of error, again run the DRC and check for errors. Or run the DRC after each change in the
layout.

j) Check for Electrical connections to be valid.

k) Analog Simulation execution. Go to Menu bar and select Run Simulation. Observe the
values of configuration delay, gate delay and VTC.

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1. Transient Analysis:
Click on Voltage vs. time to see the transient characteristics of the inverter

Analog simulation of the CMOS inverter.

The output has the opposite value of the clock input.

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2. DC Analysis (VTC):
Click on Voltage vs. Voltage to see the DC transfer characteristics of the inverter

From VTC result above, noting that the X-coordinate Y-Coordinate.

Homework 1: Dateline 25 November 2015

1. Based on your optimization transistor pMOS size in previous lab (Experiment 2).
Re-simulate the layout and discuss the VTC result and its transient waveform.

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Extract SPICE netlist

The SPICE netlist for the inverter layout can be extracted using the relevant menu command.
The extracted netlist can then be simulated using SPICE for performance.

1. Based on Procedur (g) as discussed previously, use the current layout and click save
layout or press F2.

2. Move to Menu bar, select File > Convert Into > SPICE netlist

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3. In Simulation Parameter, after properly checking the condition, click on Extract button.

4. Open PSPICE A/D Lite. Go to File > Open > inverter01.cir

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5. Run the simulation and obtain the transient waveform result (Voltage Vs Time).

6. Transient waveform result obtained like this :

Homework 2: Dateline 25 November 2015

1. Based on your optimization transistor pMOS size in previous lab (Experiment 2).

Re-simulate and compare the waveform results between layout and schematic in a single
graph (using Microsoft Excel). Discuss the result and justify the issue.
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