PPG INSTITUTE OF TECHNOLOGY

DEPARTMENT OF INFORMATION TECHNOLOGY

QUESTION BANK
CS2253-Computer Organization and Architecture
Common to IV Semester CSE and IT
UNIT-1
Basic Structure of Computers
Part -A
1. Draw the basic functional units of a computer.
2. Explain the single line bus structure.
3. Briefly explain Primary storage and secondary storage.
4. What is register?
5. Define RAM.
6. Write down the operation of control unit.
7. Define Memory address register.
8. Define Addressing modes.
9. Write the basic performance equation.
10. Define clock rate.
11. Mention the types of Opcode.
12. List out the various addressing techniques.
13. Draw the flow of Instruction Cycle
14. Define program counter (PC).
15. Define Absolute Addressing.
16. What is meant by stack addressing?
17. What is meant by response time and Execution time ?

18. Draw the diagram for processor cache.

19. Discuss the principle behind the Booths algorithm?
20. What is pipelining? How does it improve the performance?
21. Define MIPS rate & throughput rate
22. What is a carry look-ahead adder?
23. Draw the full adder circuit with two half adders
24. Define IEEE floating point single and double Precision standard?
25. What is Ripple carry adder?
26. What is Excess-127 format?
Part -B
Explain with suitable block diagram about the basic functional units system.
Explain various addressing modes with examples.
Explain instruction set Architecture with Examples.
Describe how floating point numbers are represented and used in digital Arithmetic operations
with Example.
Give the block diagram of the hardware implementation of addition and subtr action of signed
number and explain its operations

UNIT-II
Basic Processing Unit
PART-A
1. What are the differences between the hardwired control organization and micro programmed
Control organization.
2. What is a control word?
3. What is micro programmed control unit?

4. What is the WMFC step needed when reading from or writing to the main memory?
5. What is micro instruction?
6. What is micro program?
7. What are the differences between the main memory and control memory?
8. What is micro program sequencer?
9. What is meant by mapping process?
10. Give the micro instruction format.
11. What is hard wired logic?
12. What is micro programming?
13. What are the advantages and disadvantages of micro programming?
14. What is a processor clock?
15. Write down the control sequence for Move (R1), R2
16. What is the necessity of grouping of Signals?
17. What are the basic operations performed by a processor?
18. What is a Data path?
19. What is Nano Programming?
20. What is a register File?
21. Differentiate horizontal microinstruction from vertical microinstruction
PART-B (8 to 12 MARKS)
1. Draw and Explain Hardware control unit.
2. Write in detail about Micro programmed control unit organization.
3. What are the various operations performed to execute an instruction in the processor with
diagram?
4. Draw and Explain the Multiple Bus Organization.
UNIT-III

Pipelining
PART-A
1. What is the role of cache memory in pipeline?
2. What is data hazard?
3. What is instruction or control hazard?
4. Define structural hazards?
5. What is a side effect in data hazard?
6. What do you mean by branch penalty?
7. What is branch folding?
8. What do you mean by delayed branching?
9. What are the two types of branch prediction techniques available?
10. What is the ideal speedup expected in a pipelined architecture with n stages. Justify your
answer.
11. Draw the structure of two stage instruction pipeline
12. How data hazards can be minimized in the pipelining?
13. What do you mean by out-of order execution?
14. What is Operand Forward technique?

PART-B (8 to 12 MARKS)

1. Discuss the various hazards that might arise in a pipeline. What are the remedies adopted
to overcome/minimize these hazards?
2. Explain in detail Data Hazards with suitable diagrams and the remedies adopted to
minimize data hazards?
3. Explain in detail Instruction Hazards with suitable diagrams and the remedies adopted to
minimize Instruction hazards?
4. How addressing modes affect the instruction pipelining?

5. Explain the various approaches used to deal with conditional branching?

UNIT IV
MEMORY SYS TEM
Part A
1. Define Memory Access time for a computer system with two levels of caches.
2. Define latency time.
3. Write two advantages of MOS device.
4. List the factors that determine the storage device performance.
5. What is the significance of TLB?
6. Define memory cycle time.
7. What is RAM?
8. What is cache memory?
9. Explain virtual memory.
10. List the various semiconductors RAMs?
11. What do you mean by static memories?
12. Define DRAMs.
13. Define DDR SDRAM.
14. What is ROM?
15. What is the mapping procedures adopted in the organization of a cache Memory?
19. Define Hit and Miss rate?
20. What are the enhancements used in the memory management?
21. What is meant by memory management unit?
22. What is meant by memory interleaving?
23. What do you mean by seek time?

24. What is disk controller?

25. What is RAID?
26. Define data stripping?
27. How the data is organized in the disk?
Part B
1. Discuss the various mapping techniques used in cache memories.
2. Explain the concept of virtual memory with any one virtual memory management
technique.
3. Give the basic cell of an associative memory and explain its operation.
4. Explain the structure of semiconductor RAM memories. Explain read and write
5. Give the structure of semiconductor RAM memories. Explain the read and write operations in
detail.
6. Explain the organization of magnetic disks in detail
7. Explain the concept of memory hierarchy.

UNIT V
I/O ORGANIZATION
Part A
1. What are the functions of I/O interface?
2. How does the processor handle an interrupt request?
3. What are the necessary operations needed to start an I/O operation using DMA?
4. What are the three types of channel usually found in large computers?
5. Why does a DMA have priority over the CPU when both request a memory transfer?
6. What is the advantage of using interrupt initiated data transfer?
7. What is the difference between subroutine and interrupt service routine?

8. What is the need for interrupt masks?

9. How does bus arbitration typically works?
10. How does a processor handle an interrupt?
11. Distinguish synchronous bus and asynchronous bus.
12. Why I/O devices cannot be directly be connected to the system bus?
13. What are the major functions of I/O system?
14. What is an I/O interface?
15. Write the factors considered in designing an I/O subsystem?
16. Explain Direct Memory Access.
17. Define DMA controller.
18. What is polling?
19. What is the need of Interrupt controller?
20. What is a priority interrupt?
21. Define synchronous bus.
22. Define asynchronous bus.
23. Define interrupt.
24. What are the different methods used for handling the situation when multiple interrupts
occurs?
25. What is a privileged instruction?
26. What is bus arbitration?
27. What is a parallel port?
28. What is a serial port?
29. What is PCI bus?
30. What is SCSI?
31. Define USB.

Part B
1. Explain the functions to be performed by a typical I/O interface with a typical input output
Interface.
2. Discuss the DMA driven data transfer technique.
3. Discuss the operation of any two input devices
4. Explain in detail about interrupt handling.
5. Explain in detail about standard I/O interface.
6. Describe the functions of SCSI with a neat diagram.
7. What is the importance of I/O interface? Compare the features of SCSI and PCI
Interfaces.