Professional Documents
Culture Documents
1/3
Chapter 5 Impedance
Matching and Tuning
One of the most important and fundamental two-port
networks that microwave engineers design is a lossless
matching network (otherwise known as an impedance
transformer).
HO: MATCHING NETWORKS
Q: In microwave circuits, a source and load are connected by
Jim Stiles
Dept. of EECS
3/25/2009
2/3
Bandwidth
2. Complexity
3. Implementation
4. Adjustability
Dept. of EECS
3/25/2009
3/3
Jim Stiles
Dept. of EECS
3/12/2007
Matching Networks
1/9
Matching Networks
Consider again the problem where a passive load is attached
to an active source:
Zg
Vg
Z L = RL + jX L
ZL
1
= Re Vg
2
Z g + Z L
PL =
1
= Vg
2
=
1
Vg
2
Re {Z L
Z g + ZL
2
RL
Z g + ZL
Vg
Z g + ZL
Jim Stiles
Dept. of EECS
3/12/2007
Matching Networks
2/9
PLmax Pavl
=
1
Vg
2
1
Vg
2
Vg
Rg
Z g + Z g
2
Rg
2Rg
8 Rg
PL Pavl
Jim Stiles
Dept. of EECS
3/12/2007
Matching Networks
3/9
Iin
Z g = Rg + jX g
Vg
Iin
Vin
Matching
Network
VL
Z L = RL + jX L
Jim Stiles
Dept. of EECS
3/12/2007
Matching Networks
Zin =
Zin = Z
*
g
4/9
Vin
= Z g*
Iin
Matching
Network
Z L = RL + jX L
Pin = Pavl
Q: Wait just one second! The
Jim Stiles
Dept. of EECS
3/12/2007
Matching Networks
5/9
PL = Pin = Pavl
* Note that the design and construction of this lossless
network will depend on both the value of source
impedance Z g and load impedance Z L .
* However, the matching network does not physically alter
the values of either of these two quantitiesthe source
and load are left physically unchanged!
Now, lets consider the matching network from a different
perspective. Instead of defining it in terms of its input
impedance when attached the load, lets describe it in terms
of its output impedance when attached to the source:
Jim Stiles
Dept. of EECS
3/12/2007
Matching Networks
6/9
Iout
Z g = Rg + jX g
Matching
Network
Vg
Vout
This new source (i.e., the original source with the matching
network attached) can be expressed in terms of its
Thevenins equivalent circuit:
Z out = Rout + jXout
Vs
Iout = 0
Z g = Rg + jX g
Vg
Matching
Network
+
oc
Vout
Jim Stiles
Dept. of EECS
3/12/2007
Matching Networks
7/9
Z g = Rg + jX g
Matching
Network
Vg
Vout = 0
oc
sc
and Iout
) we can determine the
From these two values (Vout
Vs =V
oc
out
Zout
oc
Vout
= oc
Iout
Jim Stiles
Dept. of EECS
3/12/2007
Matching Networks
8/9
Zout = Z L
Vg
Matching
Network
Z L = RL + jX L
Jim Stiles
Dept. of EECS
3/12/2007
Matching Networks
9/9
Zg
Vg
Zin = Z g
ZL
Zg
Vg
Z out = Z L
Vs
ZL
Jim Stiles
Dept. of EECS
3/12/2007
1/7
Vg
Z0
Zin
ZL
Dept. of EECS
3/12/2007
2/7
Jim Stiles
Dept. of EECS
3/12/2007
3/7
Zg
Zg
Vg
Matching
Network
ZL
Z0
Vg
Zg
Z0
Matching
Network
ZL
In either case, we find that at any and all points along this
matched circuit, the output impedance of the equivalent
source (i.e., looking left) will be equal to the complex
conjugate of the input impedance (i.e., looking right).
Jim Stiles
Dept. of EECS
3/12/2007
Zg
Vg
4/7
Z out = Z in
Vs
Z in = Z out
ZL
Matching
Network
Vg
Z0
Matching
Network
ZL
Jim Stiles
Dept. of EECS
3/12/2007
5/7
Zg
Vg
Z out = Z 0
Z0
Vs
Z0
Z in = Z 0
ZL
Jim Stiles
Dept. of EECS
3/12/2007
6/7
Dept. of EECS
3/12/2007
7/7
Vs
Z0
Z0
Jim Stiles
Dept. of EECS
3/25/2009
L Network Analysis
1/10
L-Network Analysis
Consider the first matching L-network, which we shall denote as
matching network (A):
Z = jX
Z0 ,
( 0 ) = in
Z ( 0 ) = Zin
Y = jB
ZL
z =0
Zin = Z 0
Note that using basic circuit analysis we find that this input
impedance is:
1 Z
jB L
Zin = jX +
1
+ ZL
jB
ZL
= jX +
1 + jBZ L
Jim Stiles
Dept. of EECS
3/25/2009
L Network Analysis
2/10
AND
Im{Zin } = 0
Y1 Y +
ZL
= jB + YL
Z1 =
Z0,
Y1
ZL
1
=
jB + YL Z L + j B Z L
( 0 ) = in
Z = jX
Z ( 0 ) = Zin
Z1 =
ZL
ZL + j B ZL
z =0
Jim Stiles
Dept. of EECS
3/25/2009
L Network Analysis
3/10
ZL
= Z0
Z
j
B
Z
+
L
L
Re {Z 1 } = Re
Z0,
Z = jX
( 0 ) = in
Z 1 = Z 0 + j X1
Z ( 0 ) = Zin
z =0
jB
ZL
Z
j
B
Z
+
L
L
X1 = Im {Z 1 } = Im
Dept. of EECS
3/25/2009
L Network Analysis
4/10
ZL
ZL + j B ZL
X = X1 = Im
Z = jX1
( 0 ) = in
Z0 ,
Z ( 0 ) = Zin
Z 1 = Z 0 + j X1
z =0
Zin = Z + Z 1
= jX1 + Z 0 + jX1
= Z0
We have created a perfect match!
Going through this complex algebra, we can solve for the
required values X and B to satisfy these two equationsto
create a matched network!
and,
X L RL Z 0 RL2 + X L2 Z 0RL
B=
RL2 + X L2
X =
Jim Stiles
XL Z 0
Z
0
RL
B RL
Dept. of EECS
3/25/2009
L Network Analysis
5/10
where Z L = RL + jX L .
Note:
1) Because of the , there are two solutions for B (and
thus X).
2) For jB to be purely imaginary (i.e., reactive), B must be
real. From the term:
Z0 ,
( 0 ) = in
Z ( 0 ) = Zin
Y = jB
ZL
z =0
Jim Stiles
Dept. of EECS
3/25/2009
L Network Analysis
6/10
Yin = Y0
Note from circuit theory that the input admittance for this
network is:
1
Yin = jB +
jX + Z L
Therefore a matched network, with Yin = Y0 , is described as:
Re{Yin } = Y0
AND
Im{Yin } = 0
Y1
1
1
=
Z + Z L jX + Z L
jX + Z L
Y0 = Re {Y }1 = Re
Z0 ,
( 0 ) = in
Z ( 0 ) = Zin
Y = jB
Y1 = Y0 + jB1
z =0
Jim Stiles
Dept. of EECS
3/25/2009
L Network Analysis
7/10
jX
Z
+
L
B = Im {Y }1 = Im
So that we find:
Z0,
( 0 ) = in
Yin = Y0
Z ( 0 ) = Zin
z =0
X = RL ( Z 0 RL ) X L
and,
B =
where Z L = RL + jX L .
Jim Stiles
( Z 0 RL )
RL
Z0
Dept. of EECS
3/25/2009
L Network Analysis
8/10
Note:
1) Because of the , there are two solutions for B (and
thus X).
2) For jB and jX to be purely imaginary (i.e., reactive), B
and X must be real. We note from the term:
( Z 0 RL )
that RL must be less than Z 0 ( RL < Z 0 ) to insure that B and
thus X are real.
(B)
Jim Stiles
(A)
Dept. of EECS
3/25/2009
L Network Analysis
9/10
L
0
X =
1
0 C
if
X >0
if
X <0
if
B >0
if
B <0
and that:
C
0
B =
1
0 L
Make sure that you see and know why these equations are true.
As a result, we see that the reactance or susceptance of the
elements of our L-network will have the proper values for
matching at precisely one and only one frequency!
And this frequency better be the signal frequency 0 !
If the signal frequency changes from this design frequency, the
reactance and susceptance of the matching network inductors
and capacitors will likewise change. The circuit will no longer
be matched.
Jim Stiles
Dept. of EECS
3/25/2009
L Network Analysis
10/10
An L-Network
Design Example
Jim Stiles
Dept. of EECS