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Data sheet acquired from Harris Semiconductor

SCHS043
IMPORTANT NOTICE
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pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TIs standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
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Copyright 1998, Texas Instruments Incorporated
Philips Semiconductors Linear Products
Product specification
Sample-and-hold amplifiers
LF198/LF298/LF398
DESCRIPTION
PIN CONFIGURATIONS
The LF198/LF298/LF398 are monolithic sample-and-hold circuits

which utilize high-voltage ion-implant JFET technology to obtain
ultra-high DC accuracy with fast acquisition of signal and low droop
rate. Operating as a unity gain follower, DC gain accuracy is 0.002%
typical and acquisition time is as low as 6s to 0.01%. A bipolar
input stage is used to achieve low offset voltage and wide
bandwidth. Input offset adjust is accomplished with a single pin and
does not degrade input offset drift. The wide bandwidth allows the
LF198 to be included inside the feedback loop of 1MHz op amps
without having stability problems. Input impedance of 1010 allows
high source impedances to be used without degrading accuracy.
FE, N Packages
V+
LOGIC
OFFSET VOLTAGE
LOGIC REFERENCE
INPUT
Ch
OUTPUT
TOP VIEW
P-channel junction FETs are combined with bipolar devices in the

output amplifier to give droop rates as low as 5mV/min with a 1F
hold capacitor. The JFETs have much lower noise than MOS
devices used in previous designs and do not exhibit high
temperature instabilities. The overall design guarantees no
feedthrough from input to output in the hold mode even for input
signals equal to the supply voltages.
D1 Package
INPUT 1
Logic inputs are fully differential with low input current, allowing
direct connection to TTL, PMOS, and CMOS; differential threshold is
1.4V. The LF198/LF298/LF398 will operate from 5V to 18V
supplies. They are available in 8-pin plastic DIP, 8-pin Cerdip, and
14-pin plastic SO packages.
14 V
OS Adj
NC 2
13 NC
V 3
12 V+
NC 4
11 LOGIC
NC 5
10 LOGIC REF
NC 6
NC
Ch
OUTPUT
TOP VIEW
FEATURES
NOTE:
1. SO and non-standard pinouts.
Operates from 5V to 18V supplies

Less than 10s acquisition time
TTL, PMOS, CMOS compatible logic input
0.5mV typical hold step at CH=0.01F
Low input offset
0.002% gain accuracy
Low output noise in hold mode
Input characteristics do not change during hold mode
High supply rejection ratio in sample or hold
Wide bandwidth
APPLICATION
The LF198/LF298/LF398 are ideally suited for a wide variety of

sample-and-hold applications, including data acquisition,
analog-to-digital conversion, synchronous demodulation, and
automatic test setup
ORDERING INFORMATION
TEMPERATURE RANGE
ORDER CODE
-55C to +125C
LF198FE
0580A
14-Pin Plastic Small Outline (SO) Package
0 to +70C
LF398D
0175D
8-Pin Ceramic Dual In-Line Package (CERDIP)
0 to +70C
LF398FE
0580A
8-Pin Plastic Dual In-Line Package (DIP)
0 to +70C
LF398N
0404B
-25C to +85C
LF298FE
0580A
8-Pin Plastic Dual In-Line Package (DIP)
-25C to +85C
LF298N
0404B
DESCRIPTION
August 31, 1994
879
DWG #
853-0135 13721
LF198/LF298/LF398
FUNCTIONAL DIAGRAM
TYPICAL APPLICATIONS
OFFSET
V+
30k
OUTPUT
+
INPUT
S/H
ANALOG INPUT
LOGIC
300
HOLD 0V
Ch
SAMPLE 5V
LOGIC 7
REFERENCE
OUTPUT
LOGIC
INPUT
6
HOLD
CAPACITOR
ABSOLUTE MAXIMUM RATINGS

SYMBOL
VS
PARAMETER
RATING
UNIT
18
F package
780
mW
N package
1160
mW
D package
1040
mW
LF198
-55 to +125
LF298
-25 to +85
LF398
0 to +70
-65 to +150
Supply voltage
Maximum power dissipation
TA=25C (still-air)3
TA
TSTG
VIN
Operating ambient temperature range
Storage temperature range
Equal to
supply voltage
Input voltage
Logic-to-logic reference differential
voltage2
+7, -30
Output short-circuit duration

TSOLD
Indefinite
Hold capacitor short-circuit duration
10
sec
Lead soldering temperature (10sec max)
300
NOTES:
1. The maximum junction temperature of the LF398 is 150C. When operating at elevated ambient temperature, the packages must be derated
based on the thermal resistance specified.
2. Although the differential voltage may not exceed the limits given, the common-mode voltage on the logic pins must always be at least 2V
below the positive supply and 3V above the negative supply.
3. Derate above 25C, at the following rates:
F package at 6.2mW/C
N package at 9.3mW/C
D package at 8.3mW/C
August 31, 1994
880
LF198/LF298/LF398
DC ELECTRICAL CHARACTERISTICS
Unless otherwise specified, the following conditions apply: unit is in sample mode; VS = 15V; TJ = 25C; -11.5V3 VIN +11.5V; CH=0.01F;
and RL = 10k. Logic reference voltage = 0V and logic voltage = 2.5V.
SYMBOL
PARAMETER
VOS
Input offset voltage4
IBIAS
Input bias current4

Input impedance
Gain error
Feedthrough attenuation
ratio at 1kHz
Output impedance
HOLD step2
ICC
tAC
TEST CONDITIONS
LF198/LF298
Min
TJ=25C
Max
Full temperature range
Min
TJ=25C
25
10
0.002
0.005
96
0.5
TJ=25C, HOLD mode

50
0.004
0.01
0.02
80
2
90
0.5
UNIT
mV
nA
1010
0.02
86
100
1010
RL=10k
Max
10
75
TJ=25C
TJ=25C, Ch=0.01F
Typ

TJ=25C,
LF398
Typ
%
dB
4
6
TJ=25C, Ch=0.01F, VOUT=0
0.5
2.0
1.0
2.5
mV
Supply current4
TJ 25C
4.5
5.5
4.5
6.5
mA
Logic and logic reference

input current
TJ = 25C
10
10
Leakage current into hold

capacitor4
TJ=25C, HOLD mode
30
100
30
200
pA
VOUT=10V, Ch=1000pF
Ch=0.01F
20
20
Hold capacitor charging

current
VIN-VOUT=2V
mA
Supply voltage rejection

ratio
VOUT=0
80
110
80
110
dB
Differential logic threshold
TJ=25C
0.8
1.4
0.8
1.4
Acquisition time to 0.1%
2.4
2.4
NOTES:
1. Unless otherwise specified, the following conditions apply. Unit is in sample mode, VS=15V, TJ=25C, -11.5V VIN +11.5V, Ch = 0.01F,
and RL = 10k. Logic reference voltage = 0V and logic voltage = 2.5V.
2. Hold step is sensitive to stray capacitive coupling between input logic signals and the hold capacitor. 1pF, for instance, will create an
additional 0.5mV step with a 5V logic swing and a 0.01F hold capacitor. Magnitude of the hold step is inversely proportional to hold
capacitor value.
3. Leakage current is measured at a junction temperature of 25C. The effects of junction temperature rise due to power dissipation or elevated
ambient can be calculated by doubling the 25C value for each 11C increase in chip temperature. Leakage is guaranteed over full input
signal range.
4. The parameters are guaranteed over a supply voltage of 5 to 18V.
August 31, 1994
881
LF198/LF298/LF398
TYPICAL DC PERFORMANCE CHARACTERISTICS

Output Short Circuit Current
20
20
18
16
CURRENT (mA)
CURRENT (mA)
15
10
5
0
14
SOURCING
12
10
8
SINKING
4
10
15
25
25
50
75
100
0
50
125 150
JUNCTION TEMPERATURE (C)
25
50
75
100
0.8
TJ = 25C
RL = 10k
0.6
SAMPLE MODE
0.4
0.2
0
0.2
0.4
0.6
0.8
1
15
125 150
TJ = 25C
VOUT = 0
HOLD MODE
CURRENT (nA)
10
101
0.1
0.01F
0.1F
1F
10
15
2
VS = 15V
10
Hold Step Input Voltage
100
V+ = V = 15V
1000pF
10
INPUT VOLTAGE (V)
Leakage Current Into

Hold Capacitor
100
HOLD STEP (mV)
Hold Step
0.01
100pF
25
NORMALIZED HOLD STEP AMPLITUDE
50
Gain Error
INPUT VOLTAGE OUTPUT VOLTAGE (mV)
Input Bias Current

25
102
50
1.8
1.6
1.4
TJ = 100C
1.2
1
TJ = 25C
0.8
0.6
0.4
TJ = 55C
0.2
0
25
25
50
75
100
125 150
15
HOLD CAPACITOR
10
10
15
INPUT VOLTAGE (V)
TYPICAL AC PERFORMANCE CHARACTERISTICS

Acquisition Time
1
1%
Aperture Time
VIN = 0 TO 10V
250
TJ = 25C
225
10
VOUT 1mV
175
TIME (ns)
0.1%
TIME ( s)
100
V+ = V = 15V
200
0.01%
150
125
VIN = 10V
NEGATIVE
INPUT
STEP
75
50
POSITIVE
INPUT
STEP
25
0.01
HOLD CAPACITOR (F)
0.1
0
50
0.1
25
25
50
75 100 125 150
August 31, 1994
10
100
100
1000
0.001
Capacitor Hysteresis
882
0.1
10
SAMPLE TIME (ms)
100
LF198/LF298/LF398
TYPICAL AC PERFORMANCE CHARACTERISTICS (Continued)

Dynamic Sampling Error
100
Output Droop Rate
Hold Sampling Time
10 0
330pF
V+ = V = 15V
SETTLING TIME
1.8
TIME ( s)
330pF
1.4
TJ =85C
V/ T (V/SEC)
ERROR (mV)
1.6
101
10
102
TJ =25C
1
0.8
0.6
103
10
1.2
0.4
1000pF
0.2
104
100
1
10
100
1000
100pF
1000pF
INPUT SLEW RATE (V/ms)
70
Ch = 1000pF
60
Ch 0.01F
50
Ch = 1000pF
40
Ch = 0.01F
30
20
Ch 0.01F
10
Ch = 0
100k
1M
120
140
VOUT = 0C
120
100
POSITIVE
MODE
80
NEGATIVE
MODE
60
100 125
150
HOLD MODE
80
60
40
20
20
10k
100k
1M
130
V+ = V = 15V
120
TJ =25C
VIN = 10Vp-p
110
V7.8 = 0
Ch = 0.1F
100
Ch = 0.01F
90
80
Ch = 1000pF
70
60
50
100
100
1k
10k 100k
FREQUENCY (Hz)
883
10
100
1k
10k
FREQUENCY (Hz)
Feedthrough Rejection Ratio

(Hold Mode)
10
SAMPLE
MODE
0
1k
FREQUENCY (Hz)
RATIO (dB)
75
100
40
FREQUENCY (Hz)
August 31, 1994
50
Output Noise
TJ =25C
V+ = V = 15V
0
100
10M
25
160
140
0
10k
160
REJECTION RATIO (dB)
GAIN INPUT TO OUTPUT (dB)
INPUT TO OUTPUT PHASE DELAY ( o )
80
Ch = 0
1k
50 25
1F
Power Supply Rejection
10
0.1F
HOLD CAPACITOR
Phase And Gain

(Input to Output, Small-Signal)
0.01F
NOISE (nV/ Hz)
0.1
1M
100k
NE555
SA555 - SE555
General-purpose single bipolar timers
Features
Low turn-off time
Maximum operating frequency greater than

500 kHz
Timing from microseconds to hours
Operates in both astable and monostable

modes
Output can source or sink up to 200 mA
Adjustable duty cycle
TTL compatible
Temperature stability of 0.005% per C
N
DIP8
(Plastic package)
D
SO8
(Plastic micropackage)
Description
The NE555, SA555, and SE555 monolithic timing
circuits are highly stable controllers capable of
producing accurate time delays or oscillation. In
the time delay mode of operation, the time is
precisely controlled by one external resistor and
capacitor. For a stable operation as an oscillator,
the free running frequency and the duty cycle are
both accurately controlled with two external
resistors and one capacitor.
The circuit may be triggered and reset on falling
waveforms, and the output structure can source
or sink up to 200 mA.
Pin connections
(top view)
1 - GND
2 - Trigger
3 - Output
4 - Reset
January 2012
Doc ID 2182 Rev 6
5 - Control voltage
6 - Threshold
7 - Discharge
8 - VCC
1/20
www.st.com
20
Schematic diagrams
NE555 - SA555 - SE555
Schematic diagrams
Figure 1.
Block diagram
VCC+
5k
COMP
THRESHOLD
CONTROL VOLTAGE
DISCHARGE
R
FLIP-FLOP
5k
COMP
OUT
TRIGGER
S
INHIBIT/
RESET
5k
RESET
Figure 2.
2/20
Schematic diagram
Doc ID 2182 Rev 6
NE555 - SA555 - SE555
Absolute maximum ratings and operating conditions
Absolute maximum ratings and operating conditions

Table 1.
Absolute maximum ratings
Symbol
Parameter
VCC
Supply voltage
IOUT
Output current (sink & source)
Rthja
Thermal resistance junction to ambient

DIP8
SO-8
Rthjc
Thermal resistance junction to case(1)

DIP8
SO-8
Machine model
(MM)(3)
Charged device model
TLEAD
Tj
(CDM)(4)
18
225
mA
85
125
C/W
41
40
C/W
1000
100
1500
Latch-up immunity
200
mA
Lead temperature (soldering 10 seconds)
260
Junction temperature
150
-65 to 150
Storage temperature range
Tstg
Unit
(1)
Human body model (HBM)(2)

ESD
Value
1. Short-circuits can cause excessive heating. These values are typical.

2. Human body model: a 100 pF capacitor is charged to the specified voltage, then discharged through a
1.5 k resistor between two pins of the device. This is done for all couples of connected pin combinations
while the other pins are floating.
3. Machine model: a 200 pF capacitor is charged to the specified voltage, then discharged directly between
two pins of the device with no external series resistor (internal resistor < 5 ). This is done for all couples of
connected pin combinations while the other pins are floating.
4. Charged device model: all pins and the package are charged together to the specified voltage and then
discharged directly to the ground through only one pin. This is done for all pins.
Table 2.
Operating conditions
Symbol
Value
Unit
4.5 to 16
4.5 to 16
4.5 to 18
Maximum input voltage
VCC
IOUT
Output current (sink and source)
200
mA
Toper
Operating free air temperature range

NE555
SA555
SE555
VCC
Vth, Vtrig,
Vcl, Vreset
Parameter
Supply voltage
NE555
SA555
SE555
Doc ID 2182 Rev 6
0 to 70
-40 to 105
-55 to 125
3/20
Electrical characteristics
NE555 - SA555 - SE555
Table 3.
Tamb = +25 C, VCC = +5 V to +15 V (unless otherwise specified)

SE555
Symbol
Unit
Min.
ICC
NE555 - SA555
Parameter
Typ.
Max.
3
10
2
Timing error (monostable)

(RA = 2 k to 100 k, C = 0.1 F)
Initial accuracy (1)
Drift with temperature
Drift with supply voltage
0.5
30
0.05
Timing error (astable)

(RA, RB = 1 k to 100 k, C = 0.1 F, VCC= +15 V)
Initial accuracy (1)
Drift with temperature
Drift with supply voltage
1.5
90
0.15
Supply current (RL = )

Low state
VCC = +5 V
VCC = +15 V
High state
VCC = +5 V
Min.
Typ.
Max.
5
12
3
10
2
6
15
2
100
0.2
1
50
0.1
3
0.5
2.25
150
0.3
mA
%
ppm/C
%/V
%
ppm/C
%/V
VCL
Control voltage level

VCC = +15 V
VCC = +5 V
9.6
2.9
10
3.33
10.4
3.8
9
2.6
10
3.33
11
4
Vth
Threshold voltage
VCC = +15 V
VCC = +5 V
9.4
2.7
10
3.33
10.6
4
8.8
2.4
10
3.33
11.2
4.2
Ith
Threshold current (2)
0.1
0.25
0.1
0.25
5
1.67
5.2
1.9
5
1.67
5.6
2.2
0.5
0.9
0.5
2.0
0.7
0.7
V
mA
Vtrig
Trigger voltage
VCC = +15 V
VCC = +5 V
Itrig
Trigger current (Vtrig = 0 V)

(3)
4.8
1.45
Vreset
Reset voltage
Ireset
Reset current
Vreset = +0.4 V
Vreset = 0 V
0.1
0.4
0.4
1
0.1
0.4
0.4
1.5
VOL
Low level output voltage

VCC = +15 VIO(sink) = 10 mA
IO(sink) = 50 mA
IO(sink) = 100 mA
IO(sink) = 200 mA
VCC = +5 V IO(sink) = 8 mA
IO(sink) = 5 mA
0.1
0.4
2
2.5
0.1
0.05
0.15
0.5
2.2
0.1
0.4
2
2.5
0.3
0.25
0.25
0.75
2.5
4/20
0.4
4.5
1.1
Doc ID 2182 Rev 6
0.25
0.2
0.4
0.4
0.35
NE555 - SA555 - SE555

Table 3.
Tamb = +25 C, VCC = +5 V to +15 V (unless otherwise specified) (continued)

SE555
Symbol
VOH
Idis(off)
High level output voltage

VCC = +15 VIO(sink) = 200 mA
IO(sink) = 100 mA
VCC = +5 V IO(sink) = 100 mA
Unit
Min.
Typ.
13
3
12.5
13.3
3.3
Discharge pin leakage current

(output high) Vdis = 10 V
toff
Max.
Min.
12.7
5
2.75
Typ.
Max.
12.5
13.3
3.3
20
100
20
100
180
80
480
200
180
80
480
200
Output rise time

Output fall time
100
100
200
200
100
100
300
300
Turn off time (5) (Vreset = VCC)
0.5
Discharge pin saturation voltage

(output low) (4)
Vdis(sat)
VCC = +15V, Idis = 15 mA
VCC = +5V, Idis = 4.5 mA
tr
tf
NE555 - SA555
Parameter
nA
mV
0.5
ns
s
1. Tested at VCC = +5 V and VCC = +15 V.

2. This will determine the maximum value of RA + RB for 15 V operation. The maximum total (RA + RB) is 20 M for +15 V
operation and 3.5 M for +5 V operation.
3. Specified with trigger input high.
4. No protection against excessive pin 7 current is necessary, providing the package dissipation rating is not exceeded.
5. Time measured from a positive pulse (from 0 V to 0.8 x VCC) on the threshold pin to the transition from high to low on the
output pin. Trigger is tied to threshold.
Doc ID 2182 Rev 6
5/20
NE555 - SA555 - SE555
Figure 3.
Minimum pulse width required for

triggering
Figure 4.
Supply current versus supply

voltage
Figure 5.
Delay time versus temperature
Figure 6.
Low output voltage versus output

sink current
Figure 7.

sink current
Figure 8.

sink current
6/20
Doc ID 2182 Rev 6
NE555 - SA555 - SE555
Figure 9.
High output voltage drop versus

output
Figure 10. Delay time versus supply voltage
Figure 11. Propagation delay versus voltage

level of trigger value
Doc ID 2182 Rev 6
7/20
Application information
NE555 - SA555 - SE555
4.1
Monostable operation
In the monostable mode, the timer generates a single pulse. As shown in Figure 12, the
external capacitor is initially held discharged by a transistor inside the timer.
Figure 12. Typical schematics in monostable operation
VCC = 5 to 15V
Reset
R1
4
Trigger
NE555
Output
3
1
C1
Control Voltage
0.01F
The circuit triggers on a negative-going input signal when the level reaches 1/3 VCC. Once
triggered, the circuit remains in this state until the set time has elapsed, even if it is triggered
again during this interval. The duration of the output HIGH state is given by t = 1.1 R1C1 and
is easily determined by Figure 14.
Note that because the charge rate and the threshold level of the comparator are both
directly proportional to supply voltage, the timing interval is independent of supply. Applying
a negative pulse simultaneously to the reset terminal (pin 4) and the trigger terminal (pin 2)
during the timing cycle discharges the external capacitor and causes the cycle to start over.
The timing cycle now starts on the positive edge of the reset pulse. During the time the reset
pulse is applied, the output is driven to its LOW state.
When a negative trigger pulse is applied to pin 2, the flip-flop is set, releasing the shortcircuit across the external capacitor and driving the output HIGH. The voltage across the
capacitor increases exponentially with the time constant t = R1C1. When the voltage across
the capacitor equals 2/3 VCC, the comparator resets the flip-flop which then discharges the
capacitor rapidly and drives the output to its LOW state.
Figure 13 shows the actual waveforms generated in this mode of operation.
When Reset is not used, it should be tied high to avoid any possibility of unwanted
triggering.
8/20
Doc ID 2182 Rev 6
NE555 - SA555 - SE555
Figure 13. Waveforms in monostable operation

t = 0.1 ms / div
INPUT = 2.0V/div
OUTPUT VOLTAGE = 5.0V/div
CAPACITOR VOLTAGE = 2.0V/div
R1 = 9.1k, C1 = 0.01F, RL = 1k
Figure 14. Pulse duration versus R1C1
0.01
0.001
10
s
4.2
10
M
0.1
10
k
1=
1.0
10
0k
1M
1k
C
(F)
10
100
s
1.0
ms
10
ms
100
ms
10
s
(t d )
Astable operation
When the circuit is connected as shown in Figure 15 (pins 2 and 6 connected) it triggers
itself and free runs as a multi-vibrator. The external capacitor charges through R1 and R2
and discharges through R2 only. Thus the duty cycle can be set accurately by adjusting the
ratio of these two resistors.
In the astable mode of operation, C1 charges and discharges between 1/3 VCC and 2/3 VCC.
As in the triggered mode, the charge and discharge times and, therefore, frequency are
independent of the supply voltage.
Doc ID 2182 Rev 6
9/20
NE555 - SA555 - SE555
Figure 15. Typical schematics in astable operation

VCC = 5 to 15V
R1
8
4
Output
NE555
Control
Voltage
R2
0.01F
C1
Figure 16 shows the actual waveforms generated in this mode of operation.

The charge time (output HIGH) is given by:
t1 = 0.693 (R1 + R2) C1
and the discharge time (output LOW) by:
t2 = 0.693 (R2) C1
Thus the total period T is given by:
T = t1 + t2 = 0.693 (R1 + 2R2) C1
The frequency of oscillation is then:
1
1.44
f = --- = --------------------------------------T
( R1 + 2R2 )C1
It can easily be found from Figure 17.

The duty cycle is given by:
R2
( R1 + R2 ) - = 1 -------------------------t1
= ------------------------------------------------------( R1 + R2 )
( R1 + 2 R2 )
( t1 + t2 )
10/20
Doc ID 2182 Rev 6
NE555 - SA555 - SE555
Figure 16. Waveforms in astable operation

t = 0.5 ms / div
OUTPUT VOLTAGE = 5.0V/div
CAPACITOR VOLTAGE = 1.0V/div
R1 = R2 = 4.8k, C1= 0.1F, RL = 1k
Figure 17. Free running frequency versus R1, R2 and C1

C
(F)
10
1.0
1k
10
k
0.1
0.01
0.001
0.1
R2
1M
10
M
10
10
0k
100
Doc ID 2182 Rev 6
1k
10k
f o (Hz)
11/20
4.3
NE555 - SA555 - SE555
Pulse width modulator

When the timer is connected in the monostable mode and triggered with a continuous pulse
train, the output pulse width can be modulated by a signal applied to pin 5. Figure 18 shows
the circuit.
Figure 18. Pulse width modulator
VCC
RA
8
4
Trigger
NE555
6
Modulation
Input
5
Output
4.4
Linear ramp
When the pull-up resistor, RA, in the monostable circuit is replaced by a constant current
source, a linear ramp is generated. Figure 19 shows a circuit configuration that will perform
this function.
Figure 19. Linear ramp
VCC
RE
Trigger
R1
NE555
2N4250
or equiv.
C
Output
3
1
12/20
Doc ID 2182 Rev 6
R2
0.01F
NE555 - SA555 - SE555
Figure 20 shows the waveforms generator by the linear ramp.

The time interval is given by:
(2/3 Vcc RE (R1+R2) C
T = ---------------------------------------------------------------- VBE = 0.6V
R1 Vcc - VBE (R1+R2)
Figure 20. Linear ramp
VCC = 5 V
Time:
20 s/DIV
R1 + 47 k
R2 = 100 k
RE = 2.7 k
C = 0.01 F
4.5
Top trace: input 3 V/DIV

Middle trace: output 5 V/DIV
Bottom trace: output 5 V/DIV
Bottom trace: capacitor voltage 1 V/DIV
50% duty cycle oscillator

For a 50% duty cycle, the resistors RA and RB can be connected as in Figure 21. The time
period for the output high is the same as for astable operation (see Section 4.2 on page 9):
t1 = 0.693 RA C
For the output low it is
RB 2RA
t 2 = [(R. RB)/(RA+RB)].C.Ln --------------------------2RB RA
Thus the frequency of oscillation is:

1
f = ---------------t1 + t2
Doc ID 2182 Rev 6
13/20
Figure 21.
NE555 - SA555 - SE555

50% duty cycle oscillator
VCC
VCC
RA
51k
8
RB
7
22k
NE555
Out
3
1
0.01F
C
0.01F
Note that this circuit will not oscillate if RB is greater than 1/2 RA because the junction of RA
and RB cannot bring pin 2 down to 1/3 VCC and trigger the lower comparator.
4.6
Additional information
Adequate power supply bypassing is necessary to protect associated circuitry. The
minimum recommended is 0.1 F in parallel with 1 F electrolytic.
14/20
Doc ID 2182 Rev 6
NE555 - SA555 - SE555
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
Doc ID 2182 Rev 6
15/20
Package information
5.1
NE555 - SA555 - SE555
DIP8 package information

Figure 22. DIP8 package mechanical drawing
Table 4.
DIP8 package mechanical data

Dimensions
Ref.
Millimeters
Min.
Typ.
Max.
Min.
Typ.
5.33
Max.
0.210
A1
0.38
0.015
A2
2.92
3.30
4.95
0.115
0.130
0.195
0.36
0.46
0.56
0.014
0.018
0.022
b2
1.14
1.52
1.78
0.045
0.060
0.070
0.20
0.25
0.36
0.008
0.010
0.014
9.02
9.27
10.16
0.355
0.365
0.400
7.62
7.87
8.26
0.300
0.310
0.325
E1
6.10
6.35
7.11
0.240
0.250
0.280
2.54
0.100
eA
7.62
0.300
eB
L
16/20
Inches
10.92
2.92
3.30
3.81
Doc ID 2182 Rev 6
0.430
0.115
0.130
0.150
NE555 - SA555 - SE555
5.2
Package information
SO-8 package information

Figure 23. SO-8 package mechanical drawing
Table 5.
SO-8 package mechanical data

Dimensions
Ref.
Millimeters
Min.
Typ.
Inches
Max.
Min.
Typ.
1.75
0.069
A1
0.10
A2
1.25
0.28
0.48
0.011
0.019
0.17
0.23
0.007
0.010
4.80
4.90
5.00
0.189
0.193
0.197
5.80
6.00
6.20
0.228
0.236
0.244
E1
3.80
3.90
4.00
0.150
0.154
0.157
0.25
Max.
0.004
0.010
0.049
1.27
0.050
0.25
0.50
0.010
0.020
0.40
1.27
0.016
0.050
L1
k
ccc
1.04
0
0.040
8
0.10
Doc ID 2182 Rev 6
8
0.004
17/20
Ordering information
NE555 - SA555 - SE555
Ordering information
Table 6.
Order codes
Part number
NE555N
NE555D(1)/DT
SA555N
SA555D(1)/DT
SE555N
SE555D(1)/DT
Temperature range
0 C, +70 C
-40 C, +105 C
-55 C, + 125 C
Package
Packing
Marking
Tube
NE555N
DIP8
SO-8
Tube(1)
NE555
DIP8
Tube
SA555N
SO-8
Tube(1) or tape & reel
SA555
Tube
SE555N
DIP8
SO-8
Tube(1)
1. Not recommended for new design. Contact local ST sales office for availability.
18/20
or tape & reel
Doc ID 2182 Rev 6
or tape & reel
SE555
NE555 - SA555 - SE555
Revision history
Revision history
Table 7.
Document revision history
Date
Revision
01-Jun-2003
2004-2006
2-3
15-Mar-2007
Expanded order code table.

Template update.
Added IOUT value in Table 1: Absolute maximum ratings and

Table 2: Operating conditions.
Added ESD tolerance, latch-up tolerance, Rthja and Rthjcin
Table 1: Absolute maximum ratings.
Modified duty cycle equation in Section 4.2: Astable operation.

Updated ECOPACK text in Section 5: Package information.
Added footnote 1 to Table 6: Order codes as shipping method in
tubes is not recommended for new design.
06-Nov-2008
04-Jan-2012
Changes
Initial release.
Internal revisions
Doc ID 2182 Rev 6
19/20
NE555 - SA555 - SE555
Please Read Carefully:
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Data sheet acquired from Harris Semiconductor

Copyright 1998, Texas Instruments Incorporated

Philips Semiconductors Linear Products

The LF198/LF298/LF398 are monolithic sample-and-hold circuits

P-channel junction FETs are combined with bipolar devices in the

Operates from 5V to 18V supplies

The LF198/LF298/LF398 are ideally suited for a wide variety of

14-Pin Plastic Small Outline (SO) Package

8-Pin Ceramic Dual In-Line Package (CERDIP)

8-Pin Plastic Dual In-Line Package (DIP)

8-Pin Ceramic Dual In-Line Package (CERDIP)

8-Pin Plastic Dual In-Line Package (DIP)

August 31, 1994

Philips Semiconductors Linear Products

ABSOLUTE MAXIMUM RATINGS

Operating ambient temperature range

Storage temperature range

Output short-circuit duration

Hold capacitor short-circuit duration

Lead soldering temperature (10sec max)

August 31, 1994

Philips Semiconductors Linear Products

Input offset voltage4

Input bias current4

Full temperature range

Full temperature range

TJ=25C, HOLD mode

Full temperature range

TJ=25C, Ch=0.01F, VOUT=0

Logic and logic reference

Leakage current into hold

TJ=25C, HOLD mode

Hold capacitor charging

Supply voltage rejection

Differential logic threshold

Acquisition time to 0.1%

August 31, 1994

Philips Semiconductors Linear Products

TYPICAL DC PERFORMANCE CHARACTERISTICS

JUNCTION TEMPERATURE (C)

Hold Step Input Voltage

INPUT VOLTAGE (V)

Leakage Current Into

HOLD STEP (mV)

JUNCTION TEMPERATURE (C)

NORMALIZED HOLD STEP AMPLITUDE

Input Bias Current

JUNCTION TEMPERATURE (C)

INPUT VOLTAGE (V)

TYPICAL AC PERFORMANCE CHARACTERISTICS

75 100 125 150

JUNCTION TEMPERATURE (C)

August 31, 1994

SAMPLE TIME (ms)

Philips Semiconductors Linear Products

TYPICAL AC PERFORMANCE CHARACTERISTICS (Continued)

Output Droop Rate

Hold Sampling Time

INPUT SLEW RATE (V/ms)

Feedthrough Rejection Ratio

August 31, 1994

JUNCTION TEMPERATURE (C)

REJECTION RATIO (dB)