Preliminary

Revised August 2001

74LCX32373
Low Voltage 32-Bit Transparent Latch
with 5V Tolerant Inputs and Outputs (Preliminary)
General Description

Features

The LCX32373 contains thirty-two non-inverting latches

with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. The flip-flops
appear transparent to the data when the Latch Enable (LE)
is HIGH. When LE is LOW, the data that meets the setup
time is latched. Data appears on the bus when the Output
Enable (OE) is LOW. When OE is HIGH, the outputs are in
a high impedance state.

5V tolerant inputs and outputs

The LCX32373 is designed for low voltage (2.5V or 3.3V)

VCC applications with capability of interfacing to a 5V signal
environment.
The LCX32373 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining
CMOS low power dissipation.

2.3V3.6V VCC specifications provided

5.4 ns tPD max (VCC = 3.3V), 20 A ICC max
Power down high impedance inputs and outputs
Supports live insertion/withdrawal (Note 1)
24 mA output drive (VCC = 3.0V)
Uses patented noise/EMI reduction circuitry
Latch-up performance exceeds 500 mA
ESD performance:
Human body model > 2000V
Machine model > 200V
Packaged in plastic Fine-Pitch Ball Grid Array (FBGA)
(Preliminary)
Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to VCC through a pull-up resistor: the minimum value or the
resistor is determined by the current-sourcing capability of the driver.

Ordering Code:
Order Number
74LCX32373GX
(Note 2)

Package Number
BGA96A
(Preliminary)

Package Description
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[TAPE and REEL]

Note 2: BGA package available in Tape and Reel only.

Logic Symbol

2001 Fairchild Semiconductor Corporation

DS500547

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74LCX32373 Low Voltage 32-Bit Transparent Latch with 5V Tolerant Inputs and Outputs (Preliminary)

January 2001

74LCX32373

Preliminary
Connection Diagram

Pin Descriptions
Pin Names

Description

OEn

Output Enable Input (Active LOW)

LEn

Latch Enable Input

I0 - I31

Inputs

O0 - O31

Outputs

FBGA Pin Assignments

(Top Thru View)

O1

O0

OE1

LE1

I0

I1

O3

O2

GND

GND

I2

I3

O5

O4

VCC

VCC

I4

I5

O7

O6

GND

GND

I6

I7

O9

O8

GND

GND

I8

I9

O11

O10

VCC

VCC

I10

I11

O13

O12

GND

GND

I12

I13

O14

O15

OE2

LE2

I15

I14

O17

O16

OE3

LE3

I16

I17

O19

O18

GND

GND

I18

I19

O21

O20

VCC

VCC

I20

I21

O23

O22

GND

GND

I22

I23

O25

O24

GND

GND

I24

I25

O27

O26

VCC

VCC

I26

I27

O29

O28

GND

GND

I28

I29

O30

O31

OE4

LE4

I31

I30

Truth Table
Inputs

Outputs

LEn

OEn

In

On

O0

H = HIGH Voltage Level

L = LOW Voltage Level
X = Immaterial
Z = High Impedance
O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable

Functional Description
The LCX32373 contains thirty-two D-type latches with
3-STATE standard outputs. The device is byte controlled
with each byte functioning identically, but independent of
the other. Control pins can be shorted together to obtain full
32-bit operation. The following description applies to each
byte. When the Latch Enable (LEn) input is HIGH, data on
the In enters the latches. In this condition the latches are
transparent, i.e. a latch output will change state each time

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its I input changes. When LEn is LOW, the latches store

information that was present on the I inputs a setup time
preceding the HIGH-to-LOW transition of LEn. The
3-STATE standard outputs are controlled by the Output
Enable (OEn) input. When OEn is LOW, the standard outputs are in the 2-state mode. When OEn is HIGH, the standard outputs are in the high impedance mode but this does
not interfere with entering new data into the latches.

Preliminary

74LCX32373

Logic Diagrams

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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74LCX32373

Preliminary
Absolute Maximum Ratings(Note 3)
Symbol

Parameter

Value

VCC

Supply Voltage

0.5 to +7.0

VI

DC Input Voltage

0.5 to +7.0

VO

DC Output Voltage

0.5 to +7.0

Conditions

Units
V
V

Output in 3-STATE

0.5 to VCC + 0.5

Output in HIGH or LOW State (Note 4)

IIK

DC Input Diode Current

50

VI < GND

IOK

DC Output Diode Current

50

VO < GND

+50

VO > VCC

V
mA
mA

IO

DC Output Source/Sink Current

50

mA

ICC

DC Supply Current per Supply Pin

100

mA

IGND

DC Ground Current per Ground Pin

100

mA

TSTG

Storage Temperature

65 to +150

Recommended Operating Conditions (Note 5)

Symbol
VCC

Parameter
Supply Voltage

VI

Input Voltage

VO

Output Voltage

IOH/IOL

Output Current

TA

Free-Air Operating Temperature

t/V

Input Edge Rate, VIN = 0.8V2.0V, VCC = 3.0V

Min

Max

Operating

2.0

3.6

Data Retention

1.5

3.6

5.5

HIGH or LOW State

VCC

3-STATE

5.5

VCC = 3.0V 3.6V

24

VCC = 2.7V 3.0V

12

VCC = 2.3V 2.7V

Units
V
V
V

mA

40

85

10

ns/V

Note 3: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated
at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The Recommended Operating Conditions table will define the conditions for actual device operation.
Note 4: IO Absolute Maximum Rating must be observed.
Note 5: Unused inputs must be held HIGH or LOW. They may not float.

DC Electrical Characteristics
Symbol
VIH
VIL
VOH

VOL

Parameter

Conditions

HIGH Level Input Voltage

LOW Level Input Voltage
HIGH Level Output Voltage

LOW Level Output Voltage

IOH = 100 A

VCC

TA = 40C to +85C

(V)

Min

2.3 2.7

1.7

2.7 3.6

2.0

Max

Units
V

2.3 2.7

0.7

2.7 3.6

0.8

2.3 3.6

VCC 0.2

IOH = 8 mA

2.3

1.8

IOH = 12 mA

2.7

2.2

IOH = 18 mA

3.0

2.4

IOH = 24 mA

3.0

2.2

IOL = 100 A

2.3 3.6

0.2

IOL = 8 mA

2.3

0.6

IOL = 12 mA

2.7

0.4

IOL = 16 mA

3.0

0.4

IOL = 24 mA

3.0

0.55

II

Input Leakage Current

0 VI 5.5V

2.3 3.6

5.0

IOZ

3-STATE Output Leakage

0 VO 5.5V

2.3 3.6

5.0

10

VI = VIH or VIL
IOFF

Power-Off Leakage Current

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VI or VO = 5.5V

Preliminary

Symbol

(Continued)

Parameter

VCC

Conditions

(V)
ICC
ICC

Quiescent Supply Current

Increase in ICC per Input

TA = 40C to +85C
Min

Units

Max

VI = V CC or GND

2.3 3.6

20

3.6V VI, VO 5.5V (Note 6)

2.3 3.6

20

VIH = VCC 0.6V

2.3 3.6

500

A
A

Note 6: Outputs disabled or 3-STATE only.

AC Electrical Characteristics
TA = 40C to +85C, RL = 500
Symbol

Parameter

VCC = 3.3V 0.3V

VCC = 2.7V

VCC = 2.5V 0.2V

CL = 50 pF

CL = 50 pF

CL = 30 pF

Min

Max

Min

Max

Min

tPHL

Propagation Delay

1.5

5.4

1.5

5.9

1.5

6.5

tPLH

In to On

1.5

5.4

1.5

5.9

1.5

6.5

tPHL

Propagation Delay

1.5

5.5

1.5

6.4

1.5

6.6

tPLH

LE to On

1.5

5.5

1.5

6.4

1.5

6.6

tPZL

Output Enable Time

1.5

6.1

1.5

6.5

1.5

7.9

1.5

6.1

1.5

6.5

1.5

7.9

1.5

6.0

1.5

6.3

1.5

7.2

1.5

6.0

1.5

6.3

1.5

7.2

tPZH
tPLZ

Output Disable Time

tPHZ

Units

Max
ns
ns
ns
ns

tS

Setup Time, In to LE

2.5

2.5

3.0

ns

tH

Hold Time, In to LE

1.5

1.5

2.0

ns

tW

LE Pulse Width

3.0

3.0

3.5

ns

Dynamic Switching Characteristics

Symbol
VOLP
VOLV

VCC

TA = 25C

(V)

Typical

CL = 50 pF, VIH = 3.3V, VIL = 0V

3.3

0.8

CL = 30 pF, VIH = 2.5V, VIL = 0V

2.5

0.6

CL = 50 pF, VIH = 3.3V, VIL = 0V

3.3

0.8

CL = 30 pF, VIH = 2.5V, VIL = 0V

2.5

0.6

Parameter
Quiet Output Dynamic Peak VOL
Quiet Output Dynamic Valley VOL

Conditions

Units

V
V

Capacitance
Typical

Units

CIN

Symbol
Input Capacitance

Parameter

VCC = Open, VI = 0V or VCC

Conditions

pF

COUT

Output Capacitance

VCC = 3.3V, VI = 0V or VCC

pF

CPD

Power Dissipation Capacitance

VCC = 3.3V, VI = 0V or VCC, f = 10 MHz

20

pF

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74LCX32373

DC Electrical Characteristics

74LCX32373

Preliminary
AC LOADING and WAVEFORMS Generic for LCX Family

FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance)

Test

Switch

tPLH, tPHL

Open

tPZL, tPLZ

6V at VCC = 3.3 0.3V, and 2.7V

VCC x 2 at VCC = 2.5 0.2V

tPZH, tPHZ

GND

Waveform for Inverting and Non-Inverting Functions

3-STATE Output High Enable and

Disable Times for Logic

Propagation Delay. Pulse Width and trec Waveforms

Setup Time, Hold Time and Recovery Time for Logic

trise and tfall

3-STATE Output Low Enable and

Disable Times for Logic
FIGURE 2. Waveforms
(Input Characteristics; f = 1MHz, tr = tf = 3ns)
Symbol

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VCC
3.3V 0.3V

2.7V

2.5V 0.2V

Vmi

1.5V

1.5V

VCC/2

Vmo

1.5V

1.5V

VCC/2

Vx

VOL + 0.3V

VOL + 0.3V

VOL + 0.15V

Vy

VOH 0.3V

VOH 0.3V

VOH 0.15V

Preliminary

74LCX32373

Schematic Diagram Generic for LCX Family

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74LCX32373 Low Voltage 32-Bit Transparent Latch with 5V Tolerant Inputs and Outputs (Preliminary)

Preliminary
Physical Dimensions inches (millimeters) unless otherwise noted

96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Package Number BGA96A
Preliminary

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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