An Ultra-Low-Power CMOS OTA For Low-Frequency GM-C Applications

International Journal of Scientific Research Engineering & Technology (IJSRET)
Volume 2 Issue 11 pp 792-797 February 2014
www.ijsret.org
ISSN 2278 0882
An ultra-low-power CMOS OTA for low-frequency

Gm-C applications
1
Sareh Rigi, 2Sahar Chahkandi

Department of Electrical Engineering, University of Sistan and Baluchestan,
Iran.Sistan and Baluchestan, Iran.
Abstract
In this paper, we have designed and simulated an ultralow-power CMOS OTA in weak inversion for lowfrequency Gm-C applications. In this OTA using DC
shifting and bulk-driven differential pair configuration
can be made large common mode input range and linear
input range without using complex approaches. The
symmetricalOTA was successfully verified in a standard
0.35-m CMOS process. This OTA is optimized for
800mV supply voltage. The simulated OTA consumes
45A, performing 46 dB open loop gain, 187 Hz unity
gain frequency. The simulated transconductance of this
OTA is 66nS, which is suitable for low-frequency Gm-C
applications. This OTA can be used in band-gap,
physical transducers, process controllers and mainly on
small battery operated devices.
Keywords: Low-voltage, Low-power,bulk-driven, lowfrequency Gm-C applications, symmetricalOTA.
1. INTRODUCTION
One of the most widespread analog building blocks with
very large number of applications is the operational
transconductance amplifier (OTA). The symmetrical
OTA especially, with its
low-transconductance,
makes it possible to implement fully integrated Gm-C
filters for low-frequency applications, which are
important for the acquisition of bioelectric signals where
chip realization of large time constants are needed [1].
Nowadays, a high performance analog and mixed signal
circuit using low-voltage becomes mandatory mainly
due to the advance of the VLSI with complicated circuit
systems, and the demand for battery-operated portable
equipments. Low-voltage operation helps reducing
power consumption of the digital circuitry, and also
preventing oxide breakdown due to decreased gate oxide
thickness. However, supply voltage reduction in analog
circuit causes several performance degradations and,
therefore, new approaches in the design are needed to
achieve analog circuits with enough bandwidth, gain,

and linearity. The weak inversion operation is an
interesting choice when considering the market trend
towards low-voltage and low-power applications. One of
the best approaches for low-voltage CMOS circuits is
the bulk-driven differential pair, improving the common
mode input range, since it allows a large signal swing
without cutting off the transistor [2].
The use of complex symmetrical OTA architectures to
increase the linear input range shows some drawbacks
since it also increases noise, mismatch offset and
transistor area, which degrades results in design tradeoffs [3]. Moreover, a rail-to-rail common mode input
range may be desirable in many applications and a linear
input range of a few ten millivolts can be sufficient for
biomedical applications [2]. Several modified
symmetrical OTAs have been developed to achieve
transconductances in the order of a few nA/V with a
linear input range up to 1 V or more, where the natural
attenuating properties of the floating-gate and bulkdriven transistors have been advantageously utilized for
realizing small transconductance values [1, 2, 5].
In general, filters employed in biomedical systems are
used for sensing bioelectrical signals, which are typically
in the range of 1 V to 100 mV with frequencies below
100 Hz [1].Therefore, in this paper, we use the
symmetrical OTA in weak inversion operation since a
circuit working on low-voltage and low-power is desired
for low-frequency applications. Using DC shifting and
bulk-driven differential pair configuration can be made
large common mode input range and linear input range.
The bulk transconductance is smallerthan the gate
transconductance and, therefore, the linear input range
and input-referred noise are naturally higher, and the unit
gain bandwidth is smaller considering the same
conditions [2]. Thus, in designing a lowtransconductance symmetrical OTA using MOS
IJSRET @ 2014

www.ijsret.org
ISSN 2278 0882
transistor operating in weak inversion some trade-offs

are considered.
This report is organized as follows: in Sect. 2, the
operation of the simulated OTA is presented. Detailed
simulation results that verify the proper operation of the
simulated OTA are provided in Sect. 3. Finally,
conclusions is provided in Sect. 4 .
REVIEW
OF
SYMMETRICAL OTA
2.
THE
SIMULATED
The MOS transistor will be saturated in weak inversion

when
3 / [6, 7]. The drain current IDS of a
long channel MOS transistor operating in weak
inversion is based on the channel diffusion current and
can be given by
=
( )
(2)
The gate transconductancegm

transconductancegmb are given by
=
The current and voltage expressions of the composite

MOS transistor can be derived directly from Fig. 1 and
are given by
(1)
Where ISis the characteristic current and n the slope

factor in weak inversion. All the other symbols have
their usual meanings. The threshold voltage VTH can be
linearly expanded by
=
Fig. 1 Composite transistor: (a) schematic;

(b) Symbol[2]
and
the
bulk
(4)
where is the body effect coefficient and

is the
Fermi potential. The bulk transconductance varies from
20 to 30% of gate one for the same transistor in a CMOS
process [6, 7]. All the other symbols have their usual
meanings.
An important configuration in weak inversion is the
composite MOS transistor [2]. Considering that the
transistors are implemented in the same well, since the
substrate is common to all nMOS transistors in the
CMOS process utilized, the structure of a composite
nMOS transistor is shown in Fig. 1.
(5)
The drain-source voltage for saturation of transistor Qa

is a function of the transistor sizes and the CMOS
process parameters and does not depend on the gatesource voltage [2]. This is the basis of the composite
MOS transistor, which is valid only for weak inversion
operation and not for strong inversion. According to (1)
and the conclusions given by [2], and considering that
the drain-source voltage applied to the composite MOS
transistor is enough to saturate transistor Qb, then the
voltage VDSa is given by
(3)
=( )
(6)
An improved symmetrical OTA circuit is shown in Fig.

2. A bulk-driven differential pair allows low-voltage
operation of symmetrical OTA. This is valid since a
transistor biased by the bulk and having maximum gate
voltage is always active[8].
For analysis, the input signals are split in two parts: the
common mode voltage Vcm added to differential mode
voltage Vdm, which are given by
=
(7)
If the common mode voltage is close to the positive rail,

the circuit is highly linear. On the other hand, if the
common mode voltage is close to the negative rail, the
differential pair causes distortion to the signal, since the
active load starts switching off. In order to solve this
problem, two level shifters are placed in series with the
IJSRET @ 2014

active load (implemented by transistors Q3b and Q4b in

diode configuration), as indicated in Fig. 2. As such, the
active load remains operational with constant voltage for
lower values of the input signal, thus avoiding
nonlinearity conditions. However, the pn junction of
well-source transistors Q1 and Q2 could be forwarded
biased.
The statements above allow an almost rail-to-rail
common mode input voltage swing. Note also that
transistor pairs Q3a-Q3b;Q4a-Q4b;Q5a-Q5b and Q6a-Q6b
form composite MOS transistors. They allow the
differential pair active load and the common gate
amplifier to be biased by the same potential, without the
use of additional biasing sources, simplifying our
topology[8].
The transconductanceGm of the improved symmetrical
OTA is given by
=
www.ijsret.org
The symmetrical OTA was designed and simulated to

operate for a supply voltage equal to 800mV using a
standard 0.35-m n-well CMOS process [9]. Weak
inversion operation implies large transistor dimensions,
which in turn minimizes the influence of noise; mainly
the flicker noise that is dominant in an MOS transistor at
low frequency [7].Table 1 presents the transistors aspect
ratios for the simulated OTA. These values simplify the
transistor matching, especially in differential pair
matching.
Table 1 Transistors aspect ratios and currents
Transistor Type Id (nA) W/L (m) m
(8)
The third-order harmonic distortion (HD3) as a function

of the peak input sinusoidal signal VDM is given by
(9)
Where IB and np are the biasing current and the pMOS

slope factor, respectively.
The slew-rate can be obtained using a complex
approach. Since neither of the differential pair transistors
is ever cut off, the drain current never flows in just one
of them. Therefore, the slew-rate SR is given by the
difference of the currents at these transistors after a sharp
transition at
the input [2]:
=
(10)
The open loop gain Ao is independent of the frequency;

it can be obtained directly equating the circuit without
the capacitances, and is given by[9]
=
3.
(11)
RESULTS AND DISCUSSION
ISSN 2278 0882
M1/M2
PMOS
20/2
50
M3a
NMOS
10
20/10
10
M3b
NMOS
20/10
M4a
NMOS
10
20/10
10
M4b
NMOS
20/10
M5a/M5b
NMOS
10
20/10
10
M6a/M6b
NMOS
10
20/10
10
M7a/M7b
PMOS
10
20/10
40
M8a/M8b
PMOS
10
20/10
40
M9
PMOS
20/10
50
M10
PMOS
10
20/10
50
M11
PMOS
20/10
101
M12
PMOS
20/10
50
For this simulation a 5nA biasing current and a 25 pF

load capacitor were considered, which is compatible
with weak inversion operation[8]. The main results of
the corner simulations are shown in Table 2, where the
values of several critical factors such as DC gain, unity
gain frequency, THD etc. are included. The corner
simulations show the simulated symmetrical OTA
capability of operating in low-voltage with an almost
rail-to-rail common mode input voltage swing, due to its
DC shifting and its bulk-driven differential pair
configuration.
IJSRET @ 2014

www.ijsret.org
ISSN 2278 0882
The input-referred noise as function of frequency for the

simulated bulk-driven OTA in three corners is illustrated
in Fig. 3. The total harmonicdistortion (THD) was
calculated for the linear signal swing scenario. Fig. 4
shows total harmonic distortion (THD) versus the
frequency of the input voltage. As seen, THD of the
circuit remains lower than -40 dB for the input
amplitude up to 0.6 Vpp. Fig. 5 shows output voltage
swing of the simulated OTA.As seen; the simulated
OTA allows a large signal swing without cutting off the
transistor.
Fig. 6 shows the frequency response of the simulated
OTA for differential-mode input signals.
Fig. 2 Improved symmetrical OTA circuit using

composite MOS transistor as DC shifting[8]
Table 2 Performance summary of the simulated OTA for
corner simulations
Parameter
Typical Best
Worst
case
case
Technology
0.35 m 0.35
0.35 m
m
MOS Model
Nominal Fast
Slow
Temperature (0C)
27
80
Supply Voltage (V)
0.8
0.8
0.8
Open Loop Gain (dB)
46.21
45.63
46.70
Unity Gain Frequency 187.73

(Hz)
Phase Margin (deg.)
75
191.28
164.45
75.88
74.60
Output Swing (Vp-p)
0.7
0.7
0.7
-3dB frequency (Hz)
0.92
0.77
THD @ f=1 Hz (Vop- 0.696

p=600m V) (%)
Input Referred Noise 59
(Vrms)
Slew Rate (V/ms)
0.13
0.625
0.907
61
60
0.14
0.12
CL (pF)
25
25
25
Power Consumption (nW)
36
36
36
For typical corner, we have:

- DC gain: 46.21 dB
- Unity gain frequency : 187.73 Hz
- Phase Margin: 75oC
- 3-dB frequency: 0.92 Hz
For fast corner, we have:
- DC gain: 45.63 dB
- Phase Margin: 75.88oC
- 3-dB cut-off frequency: 1 Hz
Also, for fast corner, we have:
- DC gain: 46.70 dB
- Phase Margin: 74.60oC
- 3-dB cut-off frequency: 0.77 Hz
4.
CONCLUSION
In this paper, we designed and simulated an ultra-lowpower CMOS symmetrical OTA using DC shifting and
bulk-driven differential pair configuration in weak
inversion. The symmetrical OTA was designed using a
standard 0.35-m n-well CMOS process with 800 mV
supply voltage and just a 36nW power consumption. The
simulated OTA presents 46dB DC gain and about 187Hz
unity gain bandwidth at 75o phase margin .The input
referred voltage noise was about 60Vrms at low
frequencies. The designed OTA can be used in lowfrequency Gm-C applications and high time constant
applications.
IJSRET @ 2014

www.ijsret.org
ISSN 2278 0882
Fig. 5: Transient response of simulated OTA for three

corners (typical, fast and slow)
Fig. 3 Input-referred noise as a function of frequency for
three corners (typical, fast and slow)
(a)
Fig. 4: THD of the simulated OTA for three corners

(typical, fast and slow)
IJSRET @ 2014
(b)

(c)
Fig.6: Frequency response of OTA for three corners; (a)
typical, (b) fast and (c) slow
www.ijsret.org
ISSN 2278 0882
Transactions on Circuits and Systems-I, Regular Papers,

52(8), 14811488.
6. Allen, P. E., &Holberg, D. R. (2002). CMOS analog
circuits design (2nd ed.). New York, USA: Oxford
University Press, Inc.
7. Tsividis, Y. P. (1999). Operation and modeling of the
MOS transistor (2nd ed.). New York, USA: Oxford
University Press,Inc.
8. Daniel CalderaroCotrim,E. & Henrique de
CarvalhoFerreira,F. (2012) . An ultra-low-power CMOS
symmetrical
OTA
for
low-frequency
Gm-C
applications.Analog Integrated Circuits and Signal
Processing, 71(2), 275-282.
9. MOSIS Technical Documents. The MOSIS Service,
Marina DelRay, CA, Nov. 2010 [Online]. Available:
www.mosis.org.
ACKNOWLEDGEMENTS
The authors would like to express their sincere thanks to
Dr.Amiri for his valuable comments.
REFERENCES
1. Sols-Bustos, S., Silva-Martnez, J., Maloberti, F.,
&Sanchez-Sinencio, E. (2000). A 60-dB dynamic-range
CMOS sixth-order 2.4-Hz low-pass filter for medical
applications. IEEE Transactions on Circuits and
Systems-II,
Analog
and
Digital
Signal
Processing,47(12), 13911398.
2. Ferreira, L. H. C., Pimenta, T. C., & Moreno, R. L.
(2007). An ultra-low-voltage ultra-low-power CMOS
miller OTA with rail-to-rail input/output swing. IEEE
Transactions on Circuits and Systems-II, Express Briefs,
54(10), 843847.
3. Veeravalli, A., Sanchez-Sinencio, E., & SilvaMartnez, J. (2002). Transconductance amplifier
structures with very small transconductances:
Acomparative design approach. IEEE Journal of SolidState Circuits, 37(6), 770775.
4. Harrison, R., & Charles, C. (2003). A low-power lownoise CMOS amplifier for neural recording applications.
IEEE Journal of Solid-State Circuits, 38(6), 958965.
5. El Mourabit, A., Lu, G., &Pittet, P. (2005).Widelinear-range subthreshold OTA for low-power, lowvoltage, and low-frequency applications. IEEE
IJSRET @ 2014

An Ultra-Low-Power CMOS OTA For Low-Frequency GM-C Applications

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

An Ultra-Low-Power CMOS OTA For Low-Frequency GM-C Applications

Uploaded by

Copyright:

Available Formats

International Journal of Scientific Research Engineering & Technology (IJSRET)

Volume 2 Issue 11 pp 792-797 February 2014

ISSN 2278 0882