EMBEDDED SOFTWARE

MEMORY DEVICE DRIVERS

G.MANASA
(14021D3614)
DEFINITION OF DEVICE DRIVERS:Most
hardware requires some type of software initialization and

embedded
management

The software that directly interfaces to hardware resources in the kernal is called a
DeviceDrivers

INTERFACE OF DEVICE DRIVERS:

The main goal of device driver is to allow communication between

the operating system and the peripheral devices

It also provides a link between the kernel software and the user
software. It's important to achieve a sort of systematic way to do this.

This makes the interface more recognizable for the user.

The driver has the responsibility of hiding the details of the hardware
from the operating system and, ultimately, from the user.

CONCEPT OF DEVICE-DRIVERS:Device drivers are the software libraries that initialize the
hardware,and manage access to the hardware by higher layers of software.

Device drivers are the liaison between the hardware and the operating

system, middleware, and application layers

Device drivers are typically considered either architecture specific or generic.
A Device driver that is architecture specific manages the hardware that is
integrated into the master processor
Example :Architecture-specific drivers that initialize and enable components within a
master

processor

include

on-chip

memory,

integrated

memory

managers(MMUs), and floating point hardware.

A device driver that is Generic manages hardware that is located on the board

and not integrated onto the master processor

Generic drivers include code that initializes and manages access to the
remaining major components of the board, including board buses (I2C, PCI,
PCMCIA, etc.), off-chip memory (controllers, level-2+ cache, Flash, etc.),
and off-chip I/O (Ethernet, RS-232, Display ,Mouse, etc.)

Figure a shows a hardware block diagram of a MPC860-based board, and

shows a systems diagram that includes examples of both MPC860 processorspecific device drivers, as well as generic device drivers

MEMORY DEVICE DRIVERS:

All types of physical memory are two-dimensional arrays (matrices) made

up of cells addressed by a unique row and column, the master processor and
programmers view memory as a large one-dimensional array, commonly

referred to as the Memory Map

In the memory map, each cell of the array is a row of bytes (8 bits) and the
number of bytes per row depends on the width of the data bus (8-bit, 16-bit,

32-bit, 64-bit,etc)
When physical memory is referenced from the softwares point-of-view, it is
commonly referred to
as ,logical memory and its most basic unit is the byte.

Logical memory is made up of all the physical memory (registers, ROM, and
RAM) in the entire
Embedded system.

ADDRESS RANGE
0x00000000 - 0x003FFFFF
0x00400000 - 0x007FFFFF
0x04000000 - 0x043FFFFF
0x09000000 - 0x09003FFF
0x09100000 - 0x09100003
0x10000000 - 0x17FFFFFF
.

Accessed Device
Flash PROM Bank 1 32
Flash PROM Bank 2
DRAM 4 Mbyte (1Meg 32-bit)
MPC Internal Memory Map
BCSR - Board Control & Status
Register
PCMCIA Channel
Table :-SAMPLE MEMORY MAP

PORT WIDTH
32
32
32
32
32
16

The software must provide the processors in the system with the ability to
access various
portions of the memory map.

The software involved in managing the memory on the masteprocessor and

on the board, as well as managing memory hardware mechanisms,
consistsof the device drivers for the management of the overall memory

subsystem.
The memorysubsystem includes all types of memory management
components, such as memory controllersand MMU, as well as the types of
memory in the memory map, such as registers, cache,
ROM, DRAM, and so on.
Regardless of what type of data is being read or written, all data within

memory is managed
as a sequence of bytes.

While one memory access is limited to the size of the data bus,
certain architect ures manage access to larger blocks of data,
called segments thus implement a more complex address
translation scheme in which the logical address provided via
software is made up of a segment number and offset which is
used to determine the physical address of thememory location.

The order in which bytes are retrieved or stored in memory

depends on the byte ordering
scheme of an architecture

The two possible byte ordering schemes are little endian and big endian
In little endian mode, bytes (or bits with 1 byte (8-bit)
schemes) are retrieved and
stored in the order of the lowest byte first, meaning the lowest
byte is furthest to the left.

In big endian mode bytes are accessed in the order of the highest
byte first, meaning that the
lowest byte is furthest to the right

The following pseudocode demonstrates implementation of various memory

management
routines on the MPC860, specifically startup, disable, enable, and
writing/erasing functions in
reference to the architecture.
These examples demonstrate how memory management can be implemented
on a more complex architecture, and this in turn can serve as a guide to
understanding how to write memory management drivers on other processors
that are as complexor less complex than the MPC860 architecture.
configuring the MMU.

INITIALIZING THE MEMORY CONTROLLER AND CONNECTED

ROM/RAM :

The MPC860 memory controller (shown in Figure 8-19) is

responsibl

for

the

control

of

up

to

eight

memory

banks,interfacing to SRAM, EPROM, flash EPROM various

DRAM devices, and other peripherals (i.e.,PCMCIA).

Thus, in this example of theMPC860, on-board memory (Flash,
SRAM, DRAM, etc.) is initialized by initializing the memory

controller
.The memory controller has two different types of subunits, the
general-purpose

chip-select

machine

(GPCM)

and

the

userprogrammable machines (UPMs), that exist to connect to

certain types of memory.

The GPCM is designed to interface to SRAM,EPROM, Flash
EPROM, and other peripherals(such as PCMCIA), whereas the
UPMs are designed to interface to a wide variety of memory,

including DRAMs.
The pinouts of the MPC860s memory controller reflect the
different signals that connect these subunits to the various types
of memory . For every chip select (CS), there is an associated
memory bank

INTIALIZING THE INTERNAL MEMORY MAP ON THE MPC860:

The MPC860s internal memory map contains the architectures special purpose
registers(SPRs), as well as dual-port RAM, also referred to as parameter RAM, that
contain the buffers of the various integrated components, such as Ethernet or I2C, for
example. On the MPC860, it is simply a matter of configuring one of these SPRs, the
Internal Memory MapRegister (IMMR) to contain the base address of the internal
memory map.

INITIALIZING THE MMU ON THE MPC860 :

The MPC860 uses the MMUs to manage the boards virtual memory
management scheme,
providing logical/effective to physical/real address translations, cache control
(instruction
MMU and instruction cache, data MMU and data cache), and memory access

protections.
The MPC860 MMU (shown in Figure 8-23a) allows support for a 4 GB
uniform (user) address
space that can be divided into pages of a variety of sizes, specifically 4 kB,
16 kB, 512 kB, o8 MB, that can be individually protected and mapped to
physical memory.