21: ON BOARD BUS DEVICE DRIVERS

Every bus is some type of protocol that defines how devices gain access to the
bus (arbitration), the rules attached devices must follow to communicate over the

bus (handshaking), and the signals associated with the various bus lines.
Board devices obtain access to a bus using a bus arbitration scheme.
Bus arbitration is based upon devices being classified as either master devices or

slave devices.
When there is one master no arbitration is necessary.

21.1: ON-BOARD BUS DEVICE DRIVER PSEUDOCODE EXAMPLES

The following pseudo code gives an example of implementing a
bus initialization routine on the

MPC860, specifically the

startup function in reference to the architecture.

The I2C (inter-integrated circuit) protocol is a serial bus with one serial data line

(SDA) and one serial clock line (SCL).

With the I2C protocol, all devices attached to the bus have a unique address
(identifier)and this identifier is part of the data stream transmitted over the SDL

line.
In the case of the MPC860, there is an integrated I2C controller on the master

processor (see Figure 2.1.1a).

The I2C controller is made up transmitter registers, receiver registers, a baud rate

generator and a control unit.

The baud rate generator generates the clock signals when the I2C controller acts
as the I2C bus masterif in slave mode, the controller uses the clock signal

received from the master.

In reception mode, data is transmitted from the SDA line into the control unit,
through the shift register, which in turn transmits the data to the receive data

register.
Initializing the I2C bus on the MPC860 means initializing the I2C SDA and SCL
pins, many of the I2C registers, some of the parameter RAM and the associated
buffer descriptors.

The MPC860 I2C SDA and SCL pins are configured via the Port B general
purpose I/O port (Figure 2.1.1b and 2.1.1c).

Fig 21.1a: I2C controller on MPC860

Fig 21.1b: SDA and SCL pins on MPC860

Fig 21.1c: MPC860 port B

21.2: BOARD I/O DRIVER EXAMPLES

The board I/O subsystem components that require some form of software
management include the components integrated on the master processor, as well

as an I/O slave controller, if one exists.

The I/O controllers have a set of status and control registers used to control the
processor and check on its status.

The Ethernet and RS232 I/O initialization routines for the Power PC and ARM
architectures are provided as examples of I/O startup (initialization) device drivers.
EXAMPLE 21.2.1 : INITIALIZING AN ETHERNET DRIVER

The example used here will be the widely implemented LAN protocol Ethernet,

which is primarily based upon the IEEE 802.3 family of standards.

The software required to enable Ethernet functionality maps to the lower section

of the OSI data-link layer.

The Ethernet component that can be integrated onto the master processor is

called the Ethernet Interface.

The only firmware (software) that is implemented is in the Ethernet interface.
The software is dependent on how the hardware supports two main components
of the IEEE802.3 Ethernet protocol: the media access management and data

encapsulation.
Ethernet devices encapsulate data they want to transmit or receive into what are

called Ethernet frames.

The Ethernet frame (as defined by IEEE 802.3) is made of up a series of bits,
each grouped into fields. Multiple Ethernet frame formats are available,
depending on the features of the LAN.

Let us consider Motorola/ Free scale MPC823 Ethernet example.

The MPC823 has two serial communication controllers (SCC2 and SCC3) that

can be configured independently to implement different protocols.

They can be used to implement bridging functions, routers, gateways, and
interface with a wide variety of standard WANs, LANs, and proprietary

networks.
It determines how Ethernet on the MPC823 is configured to be interrupt driven .
The actual initialization sequence can be divided into seven major functions:
disabling SCC2, configuring ports for Ethernet transmission and reception,
initializing buffers, initializing parameter RAM, initializing interrupts and
initializing registers.

Fig 21.2.1a: MPC823 ETHERNET Block Diagram

Fig 21.2.1b: OSI MODEL

EXAMPLE 21.2.2: INITIALIZING AN RS-232 DRIVER

One of the most widely implemented asynchronous serial I/O protocols is the

RS-232 or EIA-232 (Electronic Industries Association-232).

The firmware (software) required to enable RS-232 functionality maps to the

lower section of the OSI data-link layer.

The RS-232 component that can be integrated on the master processor is called
the RS-232 Interface which can be configured for synchronous or asynchronous

transmission.
Data is transmitted asynchronously over RS-232 in a stream of bits that are
traveling at a constant rate.

Fig 21.2.2: RS232 Hardware Diagram

SPECIFICATIONS OF RS232:
SPECIFICATIONS

RS232

Cabling

Single ended

Number of devices

1 transmit
1 receive

Communication mode

Full duplex

Maximum cable length

50 feet

Max data rate

20kbps

Signalling

unbalanced

Skew rate(Max)

30V/us

Drive load impedance(ohms)

3k to 7k

Input Level Min

+/- 3V

Output Current

500mA

Table 21.2.2: RS-232 Specifications