International Journal of Advanced Engineering Research and Technology (IJAERT) 217

Volume 2 Issue 7, October 2014, ISSN No.: 2348 8190

DESIGN ANALYSIS AND IMPLEMENTATION COST FOR

FRACTIONAL RATE CONVERTER
1

Anjana S, 2Rajesh Mehra

ME Scholar, 2Associate Professor
1,2
Department of Electronics & Communication Engineering
National Institute of Technical Teachers Training & Research Chandigarh, India
1

Abstract
This paper deals with the design analysis and
implementation cost for Fractional Rate Sample
Converters(FSRC).Fractional Sample Rate Converters
are extensively used for constructing sample rate
converters which require incommensurate sample
rates. The fractional rate conversion by L/M is
achieved by cascading L interpolators and M
decimators where L and M are positive prime
numbers. It finds applications in highly configurable
digital front end multimode/multisystem receivers for
cellular terminals, PWM DC/AC converters etc. It may
observe from the result that the cost of the system
increases by 66 % in terms of multiplier and 66 % in
terms of adders when using L/M ratio of 1.5 to 3.5
respectively.
Keywords: Decimator, FSRC, Interpolator, PWM
DC/AC converters, Sample rate converters.

compression. The main signal processing applications

[1] of DSP includes sound recording, echo cancelation
in telephone networks, FM stereo etc.. Obviously DSP
has some disadvantages also, like increased system
complexity and limited range of frequencies available
for processing.
DSP applications also include sonar and radar signal
processing biomedical signal processing, spectral
estimation statical signal processing etc. JPEG images,
MP3 songs, MPEG-2 videos and ZIP files are all
processed using digital processing techniques. We
need a non-integer sampling rate conversion in
applications such as in telecommunications, digital
audio, multi media where the two systems operating at
different sampling rates have to be connected. In this
paper, we consider the sampling rate conversion by a
rational factor, called sometimes a fractional sampling
rate conversion which is based on FIR filters and
polyphase decomposition.

1. Introduction
Digital Signal Processing (DSP) is the mathematical
manipulation of an information signal to modify or
improve it in any way. It is characterised by the
representation of discrete time, discrete frequency or
other discrete domain signals by a sequence of
numbers or symbols and processing of these signals.
The goal of DSP is to measure, filter and/or compress
continuous real world analog signal. The first step is to
convert analog signal to digital form by sampling and
digitising it by using Analog to Digital converters.DSP
algorithm have long been run on standard computers as
well as on specialised processors called Digital Signal
Processors and on purpose built in hardware such as
Application Specific Integrated Circuits (ASIC).
Today there are additional technologies are used for
DSP, microprocessors, FPGAs, digital controllers and
stream processors. In almost all DSP chips common
functions performed by FFTs, FIR Filters, Interpolator,
Decimators. DSP can involve linear or nonlinear
applications. The application of computational power
to DSP allows for many advantages over analog
processing in many applications, such as error
detection and correction in transmission as well as data

The system theoretic approach to fractional sample

rate conversion is characterised by the cascade
connection of an interpolator L fold rate increase
followed by a decimator M fold rate reduction
according to Fig.1[3]
L

HI(Z)

X[n]
W[r]

HD(Z
)

M
M
Y[n]

L
X(Zi)= L
X(ZL)

H(z)

Y(Z0)=
Y(ZM)

Fig 1 System theoretic approach to fractional rate

converter
The original signal x[n] is up sampled by L and then
filtered by the low pass interpolation filter HI(z).The
interpolated signal (W[r]) is filtered with the low pass

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International Journal of Advanced Engineering Research and Technology (IJAERT) 218

Volume 2 Issue 7, October 2014, ISSN No.: 2348 8190

antialiasing filter HD(z) and then down sampled by M .

The sampling rate of the output signal {Y[m]} is L/M
times the sampling rate of the original signal {x[n]}.
Since the inter polator HI(z) and the decimator HD(z)
operate at the same sampling rate they can be replaced
by the single low pass filter H(z) .
The low pass filter H(z) should be designed to
eliminate imaging caused by the up-sampling, and to
avoid aliasing produced in down sampling. The role of
filter H(z) in the efficient fractional sampling-rate
converter of Fig. 1 is twofold: it acts as the anti
imaging filter HI(z), and also as the anti aliasing filter
HD(z). For the adequate removal of images, the stop
band edge frequency of the low-pass filter H(z) must
be below /L, and avoiding of aliasing requires the
stop band edge below /M. Therefore, the low-pass
filter H(z) in the implementation scheme of Fig.1 has
the stop band edge frequency at s. Choosing s in
such a way as to ensure the elimination of imaging
which appears in interpolation, and at the same time
ensures the suppression of aliasing that may be caused
by decimation. An optimum polyphase structure of a
fractional sample rate converter was discussed in a USpatent [2] and two conference papers [4,5],
respectively. This approach requires one input
commutator for M fold decimation and one output for
L fold sample interleaving. All operations (including
memory shift) are performed at a [3] sub nyquist rate
FS..

H(z) = z

Step 2: Systematic re arrangement of Sequential Order

of Polyphase components according to (2).
Then we get
(3)
Where the quantities
El (zL) = H(lM)L(zL)z-(PL-1-pi)L
Represent the recorded components of the L branch
poly phase decomposition of the FSRC filter H (z) as
depicted in Fig.1
Step 3: Application of noble Identities
Next ,by applying the noble identities to the branch
filters and the output delay chain of (3) being
composed of delays that are multiples Z M, the input
expander and the output decimator are shifted into the
decomposed FSRC polyphase filter until they are
directly cascaded at the output of each polyphase
branch filter.

X(zi )

2. An Optimum Poly phase realisation[1,6]

Starting from Fig.1 let
H(z) = z_ Hc(z),

(1)

Where H(z) represents a causal, possibly minimum

phase FIR or IIR filter. H(z) is causal, hence realisable.
The derivation of the optimum FSRC realisation is
subdivided in to five steps. In step 1, the low pass filter
H(Z) is decomposed into polyphase components ,
where subsequently always type 1 poly phase filter
decomposition [1]is applied. In step 2, the sequential
order of these polyphase components is systematically
rearranged, such that the noble identities can readily be
exploited in step 3. In step 4 each original poly phase
component is subjected to a second poly phase
decomposition. Finally the optimum poly phase
realisation with one input and one output commutator
each is presented in step5.

(2)

E0(zi
)

E0(zi
)

E0(zi
)

Y( z0 )
Z0-1

Step 4: Polypahase decomposition of Branch Filters

Each of the associated branch filters is subjected to
further polyphase reduction in to M polyphase
components. As a result ,we obtain L polyphase
decimators with identical decimal delay chain circuits.
Eventually, the L identical input block circuits are
replaced by one by means of elementary signal flow
graph identities. Thus the general block structure of
Fig.3 results ,where the MIMO block represents an
LTI system with an LXM transfer matrix S(zs).

Step 1: Polyphase Decomposition of Hc(z)

In the derivation procedure, for instance, with an Lbranch polyphase decomposition of the FSRC filter
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International Journal of Advanced Engineering Research and Technology (IJAERT) 219

Volume 2 Issue 7, October 2014, ISSN No.: 2348 8190

Step 5: Commutator Polyphase Structure

The 1- to M input blocking and L-to-1 unblocking
circuits of Fig.4 are replaced by commutators rotating
counter clockwise as appropriate.Furthermore a
detailed structures of the MIMO system S(zs ),
resulting from the described twofoldpolyphase
decomposition, is revealed

3. Result and Analysis

From the above table it is observed that the

implementation cost increases by 66% when using
L/M ratio of 1.5 to 3.5 respectively.

5. Conclusion
The Polyphase Fractional Rate Sample Converter with
different L/M is given, where L , M N. Its merits are
(1) All multiplications and additions with zero terms
are avoided. (2) all operations are performed at a clock
rate ranging both below the input and output rates of
the FRSC, and (3) parallel processing is achieved by
means of one input commutator for decimation by M
and one output commutator for interleaving of L
polyphase sequences. A comparison table for
implemention of FRSCs is useful for cost analysis.

Acknowledgement
The author would also like to thank to The Director of
National Institute of Technical Teachers Training And
Research Chandigarh and Rajesh Mehra Associate
Professor for their inspirations and support throughout
this research paper.

Fig.4 Magnitude Response of FSRC for L/M=1.5

References
[1] John G. Proakis, Dimitris G. Manolakis, Digital
signal Processing, PHI, pp.794-803,1993.
[2] H.Gockler , Method and Apparatus for the
Transmission of time discrete signals between systems
operating at different sample rates, US patent 4, pp.
725- 729, 1993.

Fig.5 Magnitude Response of FSRC for L/M=2.5

[3] Sanjith K. Mitra, Digital Signal Processing Tata

McGraw-Hill 2006, pp 21-39,year.
[4] Gockler H , A Unified State Space representation
of
Digital
Multirate
Filters
in
Proc.Europ.Conf.(EUSIPCO) Erlangen/ Germany,
pp.1-9, Sept.1983.
Fig.6 Magnitude Response of FSRC for L/M=3.5
[5] Hsio C.C, Polyphase Filter Matrix for Rational
Samplig Rate Convesion in Proc ICASSP-87
Dalas/TX pp.2173-2176. April 1987.

4. Implementation Cost Comparison

Table .1
Fractionl No.of
Factor
multipl
iers

L/M=1.5 48
L/M=2.5 96
L/M=3.5 144

Num
ber
of
adder
s
46
92
138

No
of
stat
e
23
23
23

Multipl
ication
per
input
sample
24
48
72

Additio
n per
input
sample

[6] Vaidya Nathan P.P, Multirate Systems and Filter

Banks, Prentice-Hall Englewood Cliff , pp.87-12,
1993.

23
46
69

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International Journal of Advanced Engineering Research and Technology (IJAERT) 220

Volume 2 Issue 7, October 2014, ISSN No.: 2348 8190

Authors
Anjana S received Bachelors of
Technology degree in Electronics and
Communication Engineering from The
Indian Engineerig College ,Vadakangulam
in 1994. She is pursuing Masters in Electronics and
Communication Engineering from National Institute of
Technical Teachers Training and Research, Punjab
University, Chandigarh, India. Her current research
interests are in Very Large Scale Integration Design
and Embedded System Design.
Rajesh Mehra received the Bachelors of
Technology degree in Electronics and
Communication
Engineering
from
National Institute of Technology Jalandhar,
India in 1994. Masters of Engineering degree in
Electronics and Communication Engineering from
National Institute of TechnicalTeachers Training &
Research, Panjab Univsrsity, Chandigarh, India in
2008. He is pursuing Doctor of Philosophy degree in
Electronics and Communication Engineering from
National Institute of Technical Teachers Training &
Research, Panjab University, Chandigarh, India. He is
an Associate Professor with the Department of
Electronics & Communication Engineering, National
Institute of Technical Teachers Training & Research,
Ministry of Human Resource Development,
Chandigarh, India. His current research and teaching
interests are in Signal G and Communications
Processing, Very Large Scale Integration Design. He
has authored more than 175 research publications
including more than 100 in Journals. Mr. Mehra is
member of IEEE and ISTE.

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