Implementing a stack on a Xilinx Spartan 3e

CW558 Nov 2013

As a first step to developing our calculator we will implement a stack on a Spartan 3e FPGA.
First we will have a look at stacks in general. A stack operates as a type of LIFO (Last In First
Out) data storage and retrieval system.

The top of the stack is pointed to by a stack pointer.

Placing a byte of date on the top of the stack is referred to as pushing data on to the stack.
Retrieving data form the stack is referred to as popping data off the stack.
When a push occurs the stack pointer is incremented and when a pop occurs the stack pointer is
decremented.
Many programming languages facilitate the implementation of a stack in software using arrays or
linked lists. In such instances the data memory of the computer is used to store the stack data.
Stacks can also be implemented in hardware using RAM memory, a register (used for the stack
pointer) and combinational logic.
Stacks may be realised in a number of ways - namely
Ascending or Descending and Empty or Full.
An Ascending stack grows upwards. It starts from a low memory address and as items are
pushed onto it, progresses to higher memory addresses.
A Descending stack grows downwards. It starts from a high memory address and as items are
pushed onto it, progresses to lower memory addresses.
In an Empty stack, the stack pointers points to the next free (empty) location on the stack, i.e. the
place where the next item to be pushed onto the stack will be stored.
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In a Full stack, the stack pointer points to the topmost item in the stack, i.e. the location of the
last item to be pushed onto the stack.

We will implement our stack as a Full ascending stack. We will create a design entity (entity
architecture pair) which we can initially test and subsequently use as a component in our calculator.
The stack consists of some RAM memory, a register which stores the current stack pointer (a
memory address) and logic which controls the updating of the stack pointer and asserts the full and
empty flags. Refer to the block diagram (attached).
The following is a description of the signals: (Blue = input, Green= output)
Din:

The byte of data to be pushed on to the stack in applied to this input .

Dout:

This is the byte of data which is at the top of the stack.

Enable:

When asserted data can be pushed or popped on the next rising edge of the clock.

Push_PopN:

When 1 a push occurs on the next clock edge if enable is asserted when 0 a pop
occurs on the next clock edge if enable is asserted.

Reset:

When reset occurs the current_sp is reset it then points to the bottom of the stack.

Clock:

Data is pushed or popped on rising edge of clock if Enable is asserted.

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Full:

Flag - asserted when the current_sp = the last address in memory. (top of stack)

Empty:

Flag - asserted when the current_sp = the first address in memory. (bottom of stack)

Memory and the Spartan 3e FPGA:

There are two types of memory in the FPGA. Distributed RAM and Block RAM. The former is
constructed from the logic cell of a look up table while the latter is a special dedicated block of
memory which is separate from the logic cells. More detail will be provided in subsequent notes.
In Xilinx ISE there are a number of ways of incorporating memory in our design
1) Memory is inferred from the VHDL design.
2) Creating an instance of a Xilinx memory module component.
3) Creating a memory module with the Core Generator (Coregen) utility in ISE
We will use Coregen to create a memory that has 16 Bytes of storage. (way more than we need!)
The follow instructions will guide you through the process:
1) Create a new project called stack and configure the project settings as in previous projects.
2) Add a new VHDL source file called stack. The signals in the port are as described above.
3) Add another new source this time select Core Generator as shown below. Call this source
Stack_RAM. Press Next.

4) Select Block memory generator from the RAMs and ROMs tab.

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5) Accept the default setting (native) for the interface type on the first page.

6) For memory type select single port RAM - for other options use defaults.

7) For Memory width select 8, depth 16, write first and use ENA pin.

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Implementing a stack on a Xilinx Spartan 3e

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8) For optional output registers accept default as shown below. No registers or init file.

9) For next option do not select RSTA

10)

Accept the default settings for the simulation model options.

11) Finally select generate. This will take a little while.

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12) The design hierarchy should now look like this

13) We now need to add Stack RAM as a component to the stack. First use file open in ISE to
open the file Stack_RAM.VHO which is in the ipcore_dir sub directory.
The file contains templates for the component and its instantiation
Copy the component template and past it into the architecture for the stack

Note: wea is a vector. This is asserted during a PUSH

14) Copy the instantiation template and past into the architecture. This time however it should be
edited to match the signal names used in our design.

15) The design hierarchy should now look like this.

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16) Now it is over to you add a process and concurrent statements that will implement the
register and logic required to implement the stack.
17) Write a testbench to test the stack.
Make sure nothing is pushed on when full and nothing is popped off when empty.

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