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FEATURES
V/F Conversion to 1 MHz
Reliable Monolithic Construction
Very Low Nonlinearity
0.002% typ at 10 kHz
0.005% typ at 100 kHz
0.07% typ at 1 MHz
Input Offset Trimmable to Zero
CMOS or TTL Compatible
Unipolar, Bipolar, or Differential V/F
V/F or F/V Conversion
Available in Surface Mount
MIL-STD-883 Compliant Versions Available
PRODUCT DESCRIPTION
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
Voltage-to-Frequency and
Frequency-to-Voltage Converter
AD650
PIN CONFIGURATION
Model
DYNAMIC PERFORMANCE
Full-Scale Frequency Range
Nonlinearity1 fMAX = 10 kHz
Nonlinearity1 fMAX = 100 kHz
Nonlinearity1 fMAX = 500 kHz
Nonlinearity1 fMAX = 1 MHz
Full-Scale Calibration Error2, 100 kHz
Full-Scale Calibration Error2, 1 MHz
vs. Supply3
vs. Temperaturc
A, B, and S Grades
at 10 kHz
at 100 kHz
J and K Grades
at 10 kHz
at 100 kHz
BIPOLAR OFFSET CURRENT
Activated by 1.24 k Between Pins 4 and 5
DYNAMIC RESPONSE
Maximum Settling Time for Full Scale
Step Input
Overload Recovery Time
Step Input
ANALOLG INPUT AMPLIFIER (V/F Conversion)
Current Input Range (Figure 1)
Voltage Input Range (Figure 5)
Differential Impedance
Common-Mode Impedance
Input Bias Current
Noninverting Input
Inverting Input
Input Offset Voltage
(Trimmable to Zero)
vs. Temperature (TMIN to TMAX)
Safe Input Voltage
COMPARATOR (F/V Conversion)
Logic 0 Level
Logic 1 Level
Pulse Width Range4
Input Impedance
OPEN COLLECTOR OUTPUT (V/F Conversion)
Output Voltage in Logic 0
ISINK 8 mA, TMIN to TMAX
Output Leakage Current in Logic 1
Voltage Range5
AD650J/AD650A
Min
Typ
Max
0.002
0.005
0.02
0.1
5
10
0.015
Min
AD650K/AD650B
Typ
Max
1
0.005
0.02
0.05
0.002
0.005
0.02
0.05
5
10
+0.015
0.015
0.5
0.015
Max
Units
1
0.005
0.02
0.05
0.1
+0.015
MHz
%
%
%
%
%
%
% of FSR/V
75
150
ppm/C
ppm/C
75
150
0.55
0.45
0.5
ppm/C
ppm/C
0.55
0.45
0.5
0.55
0
10
0
10
0
10
+0.6
0
2 M10 pF
1000 M10 pF
40
8
30
VS
VS
0
0.1
2 M10 pF
1000 M10 pF
100
20
40
8
4
VS
1
VS
+VS
0
(0.3 tOS) 0.1
250
+0.6
0
100
20
40
8
4
30
VS
1
VS
+VS
0
(0.3 tOS) 0.1
250
0.4
100
+36
250
0.4
100
+36
0
10
POWER SUPPLY
Voltage, Rated Performance
Quiescent Current
18
8
18
8
0
25
+70
+85
0
25
+70
+85
+10
0
10
100
mA
+0.6
0
mA
V
100
20
nA
nA
4
30
mV
V/C
C
2 M10 pF
1000 M10 pF
TEMPERATURE RANGE
Rated Performance N Package
Rated Performance
D Package
0.002
0.005
0.02
0.05
5
10
75
150
75
150
0.45
1
0.005
0.02
0.05
0.1
+0.015
75
150
AD650S
Typ
Min
+10
+1
V
+VS
V
(0.3 tOS) s
k
0.4
100
+36
V
nA
V
+10
100
V
mA
pF
18
8
V
mA
55
+125
C
C
0
0
10
100
NOTES
Nonlinearity is defined as deviation from a straight line from zero to full scale, expressed as a fraction of full scale.
Full-scale calibration error adjustable to zero.
3
Measured at full-scale output frequency of 100 kHz.
4
Refer to F/V conversion section of the text.
5
Referred to digital ground.
Specifications subject to change without notice.
Specifications shown in boldface are tested on all production units at final electrical test. Results from those test are used to calculate outgoing quality levels. All min and max
specifications are guaranteed, although only those shown in boldface are tested on all production units.
1
2
REV. C
AD650
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
PIN
NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
D-14
N-14
P-20A
VOUT
+IN
IN
BIPOLAR OFFSET
CURRENT
VS
ONE SHOT
CAPACITOR
NC
FOUTPUT
COMPARATOR
INPUT
DIGITAL GND
ANALOG GND
+VS
OFFSET NULL
VOUT
+IN
IN
BIPOLAR OFFSET
CURRENT
VS
ONE SHOT
CAPACITOR
NC
FOUTPUT
COMPARATOR
INPUT
DIGITAL GND
ANALOG GND
+VS
OFFSET NULL
NC
VOUT
+IN
IN
OFFSET NULL
OFFSET NULL
NC
BIPOLAR OFFSET
CURRENT
NC
VS
ONE SHOT
CAPACITOR
NC
NC
FOUTPUT
COMPARATOR
INPUT
DIGITAL GND
NC
ANALOG GND
NC
+VS
OFFSET NULL
OFFSET NULL
ORDERING GUIDE
Model
Gain
Tempco
ppm/ C
100 kHz
1 MHz
Linearity
Specified
Temperature
Range C
Package
Description
Package
Option
AD650JN
AD650KN
AD650JP
AD650AD
AD650BD
AD650SD
150 typ
150 typ
150 typ
150 max
150 max
150 max
0.1% typ
0.1% max
0.1% typ
0.1% typ
0.1% max
0.1% max
0 to +70
0 to +70
0 to +70
25 to +85
25 to +85
55 to +125
Plastic DIP
Plastic DIP
Plastic Leaded Chip Carrier (PLCC)
Ceramic DIP
Ceramic DIP
Ceramic DIP
N-14
N-14
P-20A
D-14
D-14
D-14
REV. C
AD650
CIRCUIT OPERATION
UNIPOLAR CONFIGURATION
(1)
dV
tOS
=
(1mA I N )
dt CINT
(2)
After the Reset Period has ended, the device starts another Integration Period, as shown in Figure 2, and starts ramping downward
again. The amount of time required to reach the comparator
threshold is given as:
Figure 1. Connection Diagram for V/F Conversion,
Positive Input Voltage
t /C (1 mA IIN )
1 mA
TI = V = OS INT
= tOS
1
dV
IIN
IN /CINT
dt
(3)
IIN
V IN /RIN
1
=
= 0.15 F Hz
tOS + T I tOS 1 mA
A COS + 4.4 1011F
(4)
A key part of the preceding analysis is the one shot time period
that was given in equation (1). This time period can be broken
down into approximately 300 ns of propagation delay, and a second time segment dependent linearly on timing capacitor COS.
When the one shot is triggered, a voltage switch that holds Pin 6
4
REV. C
AD650
at analog ground is opened allowing that voltage to change. An
internal 0.5 mA current source connected to Pin 6 then draws
its current out of COS, causing the voltage at Pin 6 to decrease
linearly. At approximately 3.4 V, the one shot resets itself,
thereby ending the timed period and starting the V/F conversion
cycle over again. The total one shot time period can be written
mathematically as:
tOS =
V COS
+ TGATE
IDISCHARGE
DELAY
(5)
3.4 V COS
+ 300 109 sec
0.5 103 A
(6)
Figure 3a. Full-Scale Frequency vs. COS
(7)
When the proper value for CINT is used, the charge balance
architecture of the AD650 provides continuous integration of
the input signal, hence large amounts of noise and interference
REV. C
CINT >
tOS 110 3 A
+V S 3V V NOISE
(8)
AD650
BIPOLAR V/F
As in the unipolar circuit, RIN and COS must have low temperature coefficients to minimize the overall gain drift. The 1.24 k
resistor used to activate the 0.5 mA offset current should also
have a low temperature coefficient. The bipolar offset current
has a temperature coefficient of approximately 200 ppm/C.
UNIPOLAR V/F, NEGATIVE INPUT VOLTAGE
REV. C
AD650
1 F to 10 F tantalum capacitor should be connected directly
to the supply side of the pull-up resistor and to the digital
groundPin 10. The pull-up resistor should be connected
directly to the frequency outputPin 8. The lead lengths on the
bypass capacitor and the pull up resistor should be as short as
possible. The capacitor will supply (or absorb) the current transients, and large ac signals will flow in a physically small loop
through the capacitor, pull up resistor, and frequency output
transistor. It is important that the loop be physically small for
two reasons: first, there is less self-inductance if the wires are
short, and second, the loop will not radiate RFI efficiently.
AD650
by either drift or tolerance of CINT. The net effect of a change in
the integrator capacitor is simply to change the peak to peak amplitude of the sawtooth waveform at the output of the integrator.
NONLINEARITY SPECIFICATION
It is not possible to achieve very much improvement in performance unless the expected ambient temperature range is known.
For example, in a constant low temperature application such as
gathering data in an Arctic climate (approximately 20C), a
COS with a drift of 310 ppm/C is called for in order to compensate the gain drift of the AD650. However, if that circuit should
see an ambient temperature of +75C, the COS cap would
change the gain TC from approximately 0 ppm to +310 ppm/C.
REV. C
AD650
scale, if the maximum frequency error is 5 Hz, the nonlinearity
would be specified as 50 ppm or 0.005%. Typically on the
100 kHz scale, the nonlinearity is positive and the maximum
value occurs at about midscale (Figure 9a). At higher full-scale frequencies, (500 kHz to 1 MHz), the nonlinearity becomes S
shaped and the maximum value may be either positive or negative. Typically, on the 1 MHz scale (RIN = 16.9k, COS = 51 pF)
the nonlinearity is positive below about 2/3 scale and is negative
above this point. This is shown graphically in Figure 9b.
PSRR
in the figure will never call for a negative voltage at the output
but one may imagine an arrangement calling for a bipolar output voltage (say 10 volts) by connecting an extra resistor from
Pin 3 to a positive voltage. This will not work.
Care should be taken under conditions where a high positive
input voltage exists at or before power up. These situations can
cause a latch up at the integrator output (Pin 1). This is a nondestructive latch and, as such, normal operation can be restored
by cycling the power supply. Latch up can be prevented by
connecting two diodes (e.g., 1N914 or 1N4148) as shown in
Figure 4, thereby, preventing Pin 1 from swinging below Pin 2.
A second major difference is that the output will only sink 1 mA
to the negative supply. There is no pulldown stage at the output
other than the 1 mA current source used for the V-to-F conversion. The op amp will source a great deal of current from the
positive supply, and it is internally protected by current limiting.
The output of the op amp may be driven to within 3 volts of the
positive supply when it is not sourcing external current. When
sourcing 10 mA the output voltage may be driven to within
6 volts of the positive supply.
A third difference between this op amp and a normal device is
that the inverting input, Pin 3, is bias current compensated and
the noninverting input is not bias current compensated. The
bias current at the inverting input is nominally zero, but may be
as much as 20 nA in either direction. The noninverting input
typically has a bias current of 40 nA that always flows into the
node (an npn input transistor). Therefore, it is not possible to
match input voltage drops due to bias currents by matching
input resistors.
The op amp has provisions for trimming the input offset voltage. A potentiometer of 20 k is connected to Pins 13 and 14
and the wiper is connected to the positive supply through a
250 k resistor. A potential of about 0.6 volt is established
across the 250 k resistor, and the 3 A current is injected into
the null pins. It is also possible to null the op amp offset voltage
by using only one of the null pins and use a bipolar current
either into or out of the null pin. The amount of current required
will be very smalltypically less than 3 A. This technique is
shown in the applications section of this data sheet: the autozero
circuit uses this technique.
The bipolar offset current is activated by connecting a 1.24 k
resistor between Pin 4 and the negative supply. The resultant
current delivered to the op amp noninverting input is nominally
0.5 mA and has a tolerance of 10%. This current is then used
to provide an offset voltage when Pin 2 is tied to ground through a
resistor. The 0.5 mA which appears at Pin 2 is also flowing through
the 1.24 k resistor and this current may be by observing the
voltage across the 1.24 k resistor. An external resistor is used
to activate the bipolar offset current source to provide the lowest
tolerance and temperature drift of the resultant offset voltage. It
is possible to use other values of resistance between Pin 4 and VS
to obtain a bipolar offset current different than 0.5 mA. Figure 11 is a graph of the relationship between the bipolar offset
current and the value of the resistor used to activate the source.
AD650
constant offset voltage will not affect dynamic range but simply
shift all of the frequency readings by a few hertz. However, if the
offset should change, then it will not be possible to distinguish
between a small change in a small input voltage and a drift of
the offset voltage. Hence, the usable dynamic range is less. The
circuit shown in Figure 13 provides automatic adjustment of the
op amp offset voltage. The circuit uses an AD582 sample and
hold amplifier to control the offset and the input voltage to the
VFC is switched between ground and the signal to be measured
via an AD7512DI analog switch. The offset of the AD650 is
adjusted by injecting a current into or drawing a current out of
Pin 13. Note that only one of the offset null pins is used. During
the VFC Norm mode, the SHA is in the hold mode and the
hold capacitor is very large, 0.1 F, to hold the AD650 offset
constant for a long period of time.
REV. C
AD650
output cannot change very rapidly due to the integrator time
constant formed by CINT and RIN. While it is possible to decrease
the integrator time constant to provide faster settling of the
F-to-V output voltage, the carrier feedthrough will then be
larger. For signal frequency response in excess of 2 kHz, a phase
locked F/V conversion technique such as the one shown in Figure 14 is recommended.
25 A
= 4 106
2
amperes/radian
(9)
Ko =
2 1 106 Hz
= 6.3 105 radians
10 V
volt sec
(10)
(11)
R C KoKd
2
(12)
2 FMAX
V MAX
(13)
2. Calculate a value for C based upon the desired loop bandwidth, fn. Note that this is the desired frequency range of the
output signal. The loop bandwidth (fn) is not the maximum
carrier frequency (fMAX): the signal may be very narrow even
though it is transmitted over a 1 MHz carrier.
C=
Ko
1 107 V F
f n2
Rad sec
C units FARADS
fn units HERTZ
(14)
Ko units RAD/VOLTSEC
fn
2.5 106 Rad
Ko
V
R units OHMS
fn units HERTZ
(15)
Ko units RAD/VOLTSEC
Phase lock Techniques, 2nd Edition, by F.M. Gardner, (John Wiley and
Sons, 1979)
REV. C
KoKd
C
n =
11
AD650
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
14
C0079707/00 (rev. C)
0.310 (7.87)
0.220 (5.59)
1
PIN 1
0.785 (19.94) MAX
0.200 (5.08)
MAX
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36)
0.320 (8.13)
0.290 (7.37)
0.060 (1.52)
0.015 (0.38)
0.150
(3.81)
MAX
0.015 (0.38)
0.008 (0.20)
0.280 (7.11)
0.240 (6.10)
PIN 1
0.100 (2.54)
BSC
0.060 (1.52)
0.015 (0.38)
0.325 (8.25)
0.300 (7.62)
0.210 (5.33)
MAX
0.130
(3.30)
0.160 (4.06)
MIN
0.115 (2.93)
0.022 (0.558) 0.070 (1.77) SEATING
PLANE
0.014 (0.356) 0.045 (1.15)
0.195 (4.95)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
20-Lead PLCC
(P-20A)
0.180 (4.57)
0.165 (4.19)
0.048 (1.21)
0.042 (1.07)
0.056 (1.42)
0.042 (1.07)
3
4
19
18
PIN 1
IDENTIFIER
TOP VIEW
(PINS DOWN)
8
0.020
(0.50)
R
0.025 (0.63)
0.015 (0.38)
0.021 (0.53)
0.013 (0.33) 0.330 (8.38)
0.050
(1.27)
BSC
14
13
0.040 (1.01)
0.025 (0.64)
0.356 (9.04)
SQ
0.350 (8.89)
0.395 (10.02)
SQ
0.385 (9.78)
PRINTED IN U.S.A.
0.048 (1.21)
0.042 (1.07)
0.110 (2.79)
0.085 (2.16)
12
REV. C