AIM:- Write a VHDL program to implement PISO.

entity andg is
port(a,b:in bit; c: out bit);
end andg;

-- entity declaration
-- declaration of input output port
-- end of entity

architecture a1 of andg is
begin
c<= a and b;
end a1;

-- architecture declaration
-- architecture body

entity org is
port(i,e:in bit; f: out bit);
end org;

-- entity declaration
-- declaration of input output port
-- end of entity

architecture a2 of org is
begin
f<= i or e;
end a2;

-- architecture declaration
-- architecture body

entity notg is
port(g:in bit;h:out bit);
end notg;

-- entity declaration
-- declaration of input output port
-- end of entity

architecture a3 of notg is
begin
h<=not g;
end a3;

-- architecture declaration
-- architecture body
-- end of architecture

entity dff is
port(d1,clk1:in bit; q1:out bit);
end dff;

-- entity declaration
-- declaration of input output port
-- end of entity

architecture dff1 of dff is

signal s:bit;
begin
process(clk1,d1)
begin
if(clk1 ='1'and clk1'event)
then
s<=d1;q1<=s;
end if;
end process;
end dff1;

-- architecture declaration
-- architecture body

entity main is
port(SL,clk:in bit;d: in bit_vector(0 to 3);

-- end of architecture

-- end of architecture

-- end of architecture
-- entity declaration
-- declaration of input output port

qout: out bit);

end main;

-- end of entity

architecture a5 of main is
component andg is
port(a,b:in bit; c: out bit);
end component;

-- architecture declaration
-- component declaration

component org is
port(i,e:in bit; f: out bit);
end component;

-- component declaration

component notg is
port(g:in bit;h:out bit);
end component ;

-- component declaration

component dff is
port(d1,clk1:in bit; q1:out bit);
end component ;

-- component declaration

signal a:bit_vector(0 to 8);

signal q:bit_vector(0 to 2);
signal SL1:bit;
begin
g10: notg port map (SL,SL1);
g1: andg port map (q(0),SL,a(0));
g2: andg port map (q(1),SL,a(1));
g3: andg port map (q(2),SL,a(2));
g4: andg port map (d(1),SL1,a(3));
g5: andg port map (d(2),SL1,a(4));
g6: andg port map (d(3),SL1,a(5));
g7: org port map (a(0),a(3),a(6));
g8: org port map (a(1),a(4),a(7));
g9: org port map (a(2),a(5),a(8));
dff0: dff port map (d(0),clk,q(0));
dff1: dff port map (a(6),clk,q(1));
dff2: dff port map (a(7),clk,q(2));
dff3: dff port map (a(8),clk,qout);
end a5;

-- end of architecture

AIM:- Write a VHDL program to implement PISO

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY PTS IS
PORT(X : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
CLOCK,RESET : IN STD_LOGIC;
Z : OUT STD_LOGIC);
END PTS;
ARCHITECTURE PTS_A OF PTS IS
SIGNAL I: STD_LOGIC ;
BEGIN
PROCESS(RESET,CLOCK)
VARIABLE I : INTEGER;
BEGIN
IF RESET = '0' THEN
Z <= '0';
I := 0;
ELSIF(CLOCK'EVENT AND CLOCK = '1') THEN
IF I < 4 THEN
z <= X(I);
ELSE Z <= '0';
END IF;
I := I + 1;
ELSE
NULL;
END IF;
END PROCESS;
END PTS_A;

AIM:- Write a VHDL program to implement PISO( For ECE students)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity PISO is
PORT(X : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
CLOCK,RESET : IN STD_LOGIC;
Z : OUT STD_LOGIC);
end PISO;

architecture Behavioral of PISO is

SIGNAL I: STD_LOGIC ;
BEGIN
PROCESS(RESET,CLOCK)
VARIABLE I : INTEGER;
BEGIN
IF RESET = '1' THEN
Z <= '0';

I := 0;

ELSIF(CLOCK'EVENT AND CLOCK = '1') THEN

IF I < 4 THEN
z <= X(I);
ELSE I := 0;
END IF;
I := I + 1;
ELSE
NULL;
END IF;
END PROCESS;
end Behavioral;