International Journal of Advanced Engineering Research and Technology (IJAERT)

Volume 3 Issue 6, June 2015, ISSN No.: 2348 8190

Analysis of Leakage Power Reduction in 6T SRAM Cell

Mr. Nagendra Sah1, Mr. Nitish Goyal2
Assistant Professer, ECE Department, PEC University of Technology, Chandigarh, India1
PG Scholar, Electronics (VLSI design), PEC University of Technology, chandigarh, India2

Abstract
On chip cache memories contributes a large fraction to
the total power consumption of microprocessor. As
technology scales down into d e e p -submicron,
leakage power is becoming a dominant source of
power consumption. As cache memory is an array
structure leakage reduction in just one memory cell
can on the whole reduce a large amount of leakage
power.
In this thesis leakage power of conventional 6T cell at
180nm technology has been evaluated and circuit level
leakage reduction techniques such as Sizing of the
transistor and Gated VDD has been discussed and
applied on conventional 6T cache memory cell. By the
sizing of the transistors in SRAM cell an optimized 6T
SRAM cell is obtained and evaluated and found to be
more efficient than the conventional SRAM Cell. After
that Gated-VDD is applied on the optimized 6T
SRAM Cell and it is found to be most efficient in
terms of leakage power.

Fig. 1(a): Leakage Power Percentage of Total Power [2]

Fig. 1(b): Cache Area Percentage of Total Chip Area [2]

Keyword: SRAM 6T Cell, Leakage Power Reduction,

Sizing of transistor, Gated-VDD, Cadence tool

I. INTRODUCTION
Todays mobile/multimedia applications, e.g., a
combination of text, audio, still images, graphics
(discrete media) and audio, animation, video, video on
demand, video recording, interactivity content forms
(continuous media), etc. need to be incorporated in one
digital system. So, there is a strong need to reduce the
standby current leakage while keeping the memory cell
data unchanged [1].
The MOS transistor miniaturization also introduces
many new challenges in Very Large Scale Integrated
(VLSI) circuit designs, such as sensitivity to process
variations and increasing transistor leakage. In Fig.1, the
leakage power from a high-performance microprocessor
has been shown. It increases steadily, as the technology
is scaled down [2].

So, Reduction in the leakage power of even a single cell

of cache can on the whole reduce a large fraction of the
total power dissipation of microprocessor due to large
sizes of on-chip caches. Thus, cache memory is a good
candidate for optimizing leakage energy consumption
and reduction in leakage of cache memory can
significantly improve the system power efficiency.

II. CONVENTIONAL 6T SRAM CELL

The conventional six-transistor (6T) SRAM is built up
of two cross-coupled inverters and two access
transistors, connecting the cell to the bit-lines as shown
in fig. 2. The inverters make up the storage element and
the access transistors are used to communicate with the
outside. The cell is symmetrical and has a relatively
large area. No special process steps are needed and it is
fully compatible with standard CMOS processes.

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International Journal of Advanced Engineering Research and Technology (IJAERT)

Volume 3 Issue 6, June 2015, ISSN No.: 2348 8190

Fig. 2: Six-Transistor (6T) SRAM Cell [3]

Operation of SRAM Cell:
There are mainly the following three states of
SRAM Cell, Standby/Hold, Read and Write.

Fig. 4: 6T SRAM Cell write operation (writing0to1)

[3]

III. LEAKAGE REDUCTION TECHNIQUES

1. Standby/Hold Operation
When WL = 0, M5 and M6 disconnect the cell from
Bit-Lines (BL and BL (bar)). The two cross-coupled
inverters formed by M1-M4 will continue to reinforce
each other as long as they are disconnected from the
outside world. The current drawn in this state from the
power supply is termed as standby current.
2. Read Operation
Read cycle starts with pre-charging BL and BL (bar) to
1, i.e., VDD (see fig.3) within the memory cell M1 and
M4 are ON. Asserting the word line, turns ON the M5
and M6 and the values of Q and Q(bar) is transferred to
Bit-Lines (BL and BL(bar)). No current flows through
M6, thus M4 and M6 pull BL (bar) up to VDD, i.e., BL
(bar) = 1 and BL discharges through M1 and M5. This
voltage difference is sensed and amplified to logic levels
by sense amplifiers.
3. Write Operation
The value to be written is applied to the Bit lines. Thus
to write data 0, assert BL=0, BL (bar) = 1 and to
write data 1, the BL = 1, BL (bar) = 0, asserted
when WL = 1. In the fig. 4, while writing the state Q is
changing from 0 to 1.

Among the emerging leakage reduction techniques

, some require modification of the process technology,
achieving
leakage
reduction
during
the
fabrication/design stage, while others are based on
circuit-level optimization schemes that
require
architectural support, and in some cases, technology
support as well, but are applied at run-time
(dynamically).
In this section various circuit level leakage reduction
techniques have been discussed that have been
proposed and are being used to reduce the static power
dissipation in the SRAM cell [4-10].
1. Sizing of SRAM Cell
The sub-threshold leakage is the drain-source current of
a transistor operating in the weak inversion region.
Unlike the strong inversion region in which the drift
current dominates, the sub-threshold conduction is due
to the diffusion current of the minority carriers in the
channel for a MOS device. The magnitude of the subthreshold current is a function of the temperature, supply
voltage, device size, and the process parameters out of
which the threshold voltage (VT) plays a dominant role.
In current CMOS technologies, the sub-threshold
leakage current, ISUB, is much larger than the other
leakage current components. This is mainly because of
the relatively low VT in modern CMOS devices. ISUB is
calculated by using the following formula:
Isub =

Fig.3: 6T SRAM Cell read operation (reading 0)

Vth 2 Csth

(1- )

where W and L denote the transistor width and length, carrier mobility, Vth= kT q is thermal voltage at
temperature T, Csth= Cdep + Cit is the summation of the
depletion region capacitance and the interface trap

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International Journal of Advanced Engineering Research and Technology (IJAERT)

Volume 3 Issue 6, June 2015, ISSN No.: 2348 8190

capacitance both per unit area of the MOS gate , and is

the drain-induced barrier lowering (DIBL) coefficient. n
is the slope shape factor.
Now as we can see that the sub-threshold leakage current,
Isub depends on the Width and Length of the transistors.
So by taking appropriate value for the threshold voltage
we will find a relation for width and length to achieve the
minimum leakage power.

1. Conventional 6T SRAM Cell

Fig. 6 shows the schematic of the Conventional 6T
SRAM Cell. Its design includes two cross-coupled
CMOS inverters and two access transistors, connecting
the cells to the bit-lines.

2. Gated- V DD
Gated-VDD enables a cache to turn off the supply
voltage and eliminate virtually all the leakage energy
dissipation in the caches unused sections. The key idea
is to introduce an extra transistor with high VT in the
supply voltage (VDD) or the ground path (gnd) of the
caches SRAM cells whereas rest all transistors of the
cell have low VT.(see fig. 5).
Fig. 6: Schematic of Conventional 6T SRAM Cell
Transient Analysis
Fig. 7 shows the transient analysis waveform of the
schematically designed Conventional 6T SRAM Cell.
For the simulation purpose, an input supply voltage of
1.8 V is used. The power is calculated for the given
input specification and results have been shown in table
1.
Fig. 5: SRAM cell with an NMOS Gated VDD
The extra transistor is turned on in the used sections and
turned off in the unused sections. Thus, the cells
supply voltage is gated. Gated-VDD maintains the
performance advantages of lower supply and threshold
voltages while reducing leakage and leakage energy
dissipation

IV. CIRCUIT SIMULATION AND RESULT

ANALYSIS
The standard 6T SRAM Cell at 180 nm technology is
analyzed in terms of leakage power dissipation and
performance. After that different circuit level leakage
reduction techniques have been applied and analyzed.
Leakage power in the cell has been evaluated by
keeping word-line low to disconnect cell from the bitlines. Two components of the leakage have been
considered, one the leakage inside the cell and other
leakage to bit-lines.
Cadence Virtuoso @ Analog Design Environment at
GPDK 180nm technology is used for schematic design
and simulation purpose. The waveforms of the transient
analysis have been added in this section. The results are
shown in the terms of leakage power.

Fig. 7: Leakage power in Conventional 6T SRAM Cell

Table 1: Results obtained from Transient analysis of
Conventional 6T SRAM Cell
GPDK 180nm
Technology
1.8 V
Power Supply
200ns
Run Time
W = 2um L=180n
Sizing PMOS
m
of
(inverter)
Trans NMOS
W = 2um L=180n
istors (inverter)
m
NMOS(access W = 2um L=180n
m
transistor)
59.10 pW
Leakage Power

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International Journal of Advanced Engineering Research and Technology (IJAERT)

Volume 3 Issue 6, June 2015, ISSN No.: 2348 8190

2. Gated VDD 6T SRAM Cell

Fig. 8 shows the schematic of the Gated-VDD 6T SRAM
Cell. Its design includes two cross-coupled CMOS
inverters, two access transistors, connecting the cells to
the bit-lines and a NMOS transistor in the ground path of
SRAM Cell.
Transient Analysis
Fig. 9 shows the transient analysis waveform of the
schematically designed Gated VDD 6T SRAM Cell. For
the simulation purpose, an input supply voltage of 1.8 V
is used. The power is calculated for the above given
input specification and results have been shown in table
2.

Table 2: Results obtained from Transient analysis of

Gated VDD 6T SRAM Cell
GPDK 180nm
Technology
1.8 V
Power Supply
200ns
Run Time
W = 2um L=180nm
Sizing PMOS
of
(inverter)
Trans NMOS
W = 2um L=180nm
istors (inverter)
NMOS(access W = 2um L=180nm
transistor)
NMOS(gated W = 2um L=180nm
transistor)
24.55 W
Leakage Power
3. Optimized 6T SRAM Cell
Fig. 10 shows the schematic of the optimized 6T SRAM
Cell. Its design includes two cross-coupled CMOS
inverters and two access transistors, connecting the cells
to the bit-lines.

Fig. 8: Schematic of Gated VDD 6T SRAM Cell

Fig. 10: Schematic of Optimized 6T SRAM Cell
Transient Analysis
Fig. 11 shows the transient analysis waveform of the
schematically designed optimized 6T SRAM Cell. The
power is calculated for the given input specification and
results have been shown in table 3.

Fig. 9: Leakage power in Gated VDD 6T SRAM Cell

Fig. 11: Leakage power in Optimized 6T SRAM Cell

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International Journal of Advanced Engineering Research and Technology (IJAERT)

Volume 3 Issue 6, June 2015, ISSN No.: 2348 8190

Table 3: Results obtained from Transient analysis of

Optimized 6T SRAM Cell
GPDK 180nm
Technology
1.8 V
Power Supply
200ns
Run Time
W=
L=360n
Sizing PMOS
1.44um
m
of
(inverter)
Trans NMOS
W=
L=960n
istors (inverter)
1.44um
m
W=
L=720n
NMOS(access
1.44um
m
transistor)
10.84 pW
Leakage Power
4. Optimized Gated VDD 6T SRAM Cell
Fig. 12 shows the schematic of the Optimized GatedVDD 6T SRAM Cell. Its design includes two crosscoupled CMOS inverters, two access transistors,
connecting the cells to the bit-lines and a NMOS
transistor in the ground path of SRAM Cell.

Fig. 12: Schematic of Optimized Gated-VDD 6T SRAM

Cell
Transient Analysis
Fig. 13 shows the transient analysis waveform of the
schematically designed Optimized Gated VDD 6T SRAM
Cell. For the simulation purpose, an input supply voltage
of 1.8 V is used. The power is calculated for the above
given input specification and results have been shown in
table 4.

Fig. 13: Leakage power in Optimized Gated-VDD 6T

SRAM Cell
Table 4: Results obtained from Transient analysis of
Optimized Gated VDD 6T SRAM Cell
GPDK 180nm
Technology
1.8 V
Power Supply
200ns
Run Time
W=
L=360n
Sizing PMOS
1.44um
m
of
(inverter)
Trans NMOS
W=
L=960n
istors (inverter)
1.44um
m
W=
L=720n
NMOS(access
1.44um
m
transistor)
W=
L=720n
NMOS(gated
1.44um
m
transistor)
3.76pW
Leakage Power

Summary of Results
After simulating the circuits, the results have been
summarized in table below. Table 5 shows the
comparison of different reduction techniques in SRAM
6T.
Table 5: Comparison of leakage Power Reduction
Techniques in 6T SRAM Cell
Leakage
Leakage
Percentage
Reduction
Power
Power
Techniques
Dissipation
Reduction
(in pW)
(%)
Conventional
59.10
Gated VDD
24.55
58.46
Optimized
10.84
81.65
Optimized
3.76
93.64
Gated VDD

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International Journal of Advanced Engineering Research and Technology (IJAERT)

Volume 3 Issue 6, June 2015, ISSN No.: 2348 8190

V. CONCLUSION
Various circuit level techniques have been applied to
6T SRAM cell for leakage power reduction and
compared. Out of all the techniques discussed
optimized Gated-VDD has found to be the best as it
reduces more leakage comparable to Gated VDD.It
has been found that in conventional 6T SRAM cell
up to 98% reduction in leakage power can be
achieved using these techniques..
One can choose any method to reduce leakage
depending upon requirements. Optimized Gated-VDD
leakage reduction technique shows large reduction but
due to some limitations in the Gated-VDD SRAM Cell
optimized circuit by considering the other parameters
also.

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First A. Prof. Nagendra Sah was born in
Jaynagar, India, on 05-01-1960. He is
Assistant Professor in PEC University of
Technolgy ( Formerly PEC-Deemed
University), Chandigarh, India. He has
done his B.Tech degree in Electronics
and Communication Engg. from
National
Institute of Technolgoy,
Warangal, Andhra Pradesh, India in 1986 and Master of
Engg. Degree in Electronics Engg. From Panjab
University, Chandigarh, India in 2005. He has teaching
experience of about 18 years. Presntly, he is working as
Assistant Professor. He has published about 40 papers in
national and international conferences and in
international journals. His research is focused on the
radio-system design, wireless communication and
networking and modeling of mobile radio propagation
and the development of simulation methods for a mobile
radio channels.

Second A. Nitish Goyal received

B.Tech.(Electronics & Communication)
degree from DAV institute of Engg. and
Technology, Jalandhar in 2011. He is
pursuing
M.E.
Electronics(VLSI
Design) from PEC University of
Technology, Chandigarh. His area of interest is Low
power VLSI design.

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