1980

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS, VOL. 58, NO. 8, AUGUST 2011

Design and Implementation of Fully Integrated

Digitally Controlled Current-Mode Buck Converter
Man Pun Chan, Student Member, IEEE, and Philip K. T. Mok, Senior Member, IEEE

AbstractDigital current-mode control is a dual-loop control

which potentially results in a better transient response and thus
is more favorable than voltage-mode control. There are only a few
publications on how to design and implement a fully integrated digital controller as the on-chip implementation is very challenging,
especially for current-mode control. This paper addresses those design challenges and considerations. One of the main challenges is
to efficiently sample and quantize both the output voltage and inductor current of the buck converter for control purposes. A timemultiplex scheme is used for the control-loop which enables the
converter to work with a single ADC. A modified delay-lock-loop
DPWM has been developed for minimizing the mismatch of the
delay-cells. This enhances the accuracy at high frequency to prevent limit-cycle. A new algorithm has also been proposed for implementing look-up-table digital compensators with 20% less chip
area. A converter with the fully integrated digitally controlled loop,
including the single ADC, digital compensators and DPWM, has
been fabricated in a CMOS 0.35 m process with a chip area of
1049 m 1533 m. Measurement results show that the buck converter has a load transient response of 20 s, which is one of the
fastest compared to other state-of-the-art digitally controlled buck
converter.
Index TermsAnalog-digital conversion, buck converter, current-mode, digitally controlled, integrated circuit.

I. INTRODUCTION

UCK converters are commonly used as efficient voltage

regulators in most miniature portable consumer electronics like mobile phones, PDAs, and multimedia players.
There is an increasing trend to use digital controllers over
analog ones to control the buck converter in those applications.
Because of the ever-decreasing sizes of those devices, it is
very desirable to integrate the buck converter controllers with
the digital system that is being regulated [1][3]. The digital
controllers make this possible and easier. A typical product
development cycle for consumer electronics devices is about
six months shorter than the IC suppliers cycle to deliver
the underlying circuitry for these products [4]. Therefore,
the reprogrammability of the digital controllers can shorten
the development time by programming the digital controllers
according to the specification for different products. The digital
Manuscript received July 14, 2010; revised December 20, 2010; accepted January 18, 2011. Date of publication March 10, 2011; date of current version July
27, 2011. This work was supported by the Research Grant Council of Hong
Kong SAR Government, China, under project No. 617308. This paper was recommended by Associate Editor E. Alarcon.
The authors are with the Department of Electronic and Computer Engineering, Hong Kong University of Science and Technology, Kowloon, Hong
Kong (e-mail:eecmp@ece.ust.hk; e-mail:eemok@ece.ust.hk).
Digital Object Identifier 10.1109/TCSI.2011.2112531

Fig. 1. Generic architecture of a digitally controlled current-mode buck converter.

controllers are also favorable because they are capable of

operating at an ultralow quiescent power [5], [6].
Several digital current-mode controllers (DCMCs) for buck
converters have been successfully demonstrated in recent research. In [7], a FPGA-based peak-current-mode digital controller is demonstrated to control a nonisolated point-of-load
(POL) converter with 20 A loading current. Similarly, [8] shows
a FPGA-based average-current-mode digital controller for controlling a 10 A synchronous buck converter. These two DCMCs
are designed for high-current applications with off-chip power
MOSFETs. In contrast, another paper [9] aims to demonstrate
a peak-current-mode digital controller for a 500 mA low-power
buck converter used in battery-powered products.
The digitally controlled current-mode buck converter is
more favorable for portable consumer electronics if it is highly
integrated as shown in Fig. 1. For example, the buck converter, including DCMC and power MOSFETs, should be
fully integrated into a single silicon chip. However, all the
aforementioned papers only verify their digitally controlled
current-mode converters design through FPGAs/CPLD implementation. There are different design considerations between
FPGAs and fully IC implementations. Therefore, this paper
addresses the challenges and design considerations of implementing a fully integrated digitally controlled current-mode
buck converter.
One of the main challenges to implementing the converter in
Fig. 1 is that two ADCs are required for quantizing the output
voltage and the inductor current . Compared to the digital
voltage-mode control, the extra ADC requires more chip area
and power to operate. The two-ADC architecture for DCMCs is
often used, as cited in [7], [8], [10]. Alternatively, other papers

1549-8328/$26.00 2011 IEEE

CHAN AND MOK: DESIGN AND IMPLEMENTATION OF FULLY INTEGRATED DIGITALLY CONTROLLED CURRENT-MODE BUCK CONVERTER

[9], [11] have used a different approach to obtain the inductor

current information, but that still required one ADC and one
DAC. Based on this observation, it would be interesting to investigate how to use only one ADC in the DCMC for quantizing
both the output voltage and the inductor current.
Another design challenge is to design a timing scheme such
that the single ADC knows when to sample and quantize the
output voltage and the inductor current. The timing scheme also
needs to make sure that the digitized signals can be sent to both
the current-loop and the voltage-loop compensators with the
least amount of delay to ensure the stability of the converter
shown in Fig. 1.
Motivated by the above discussions, a fully integrated digitally controlled current-mode buck converter with a single timemultiplex (TM) ADC is proposed. The proposed converter uses
a time-multiplex scheme (TMS) to demonstrate how the DCMC
controls the buck converter by using a single TM-ADC for quantizing both the output voltage and the inductor current. A lowpower and small chip area TM-ADC is designed for the TMS
and integration purposes. This not only saves one ADC static
power but also requires less chip area.
Since the proposed converter is designed with fully integrated
circuits, several design issues, which will not concerned the
implementation of FPGAs, will be addressed throughout this
paper. For example, the IC implementation of DPWM is very
different from that of the FPGAs. The former requires a full
custom IC design while the latter requires the coding of delaycells and time-constraints. The design consideration of those
two digital compensators shown in Fig. 1 is also different between integrated circuits and FPGAs. The former focuses on
reducing chip area while the latter focuses on reducing the gate
count. As a result, it is necessary to design area-efficient digital
compensators in IC implementation.
The organization of this paper is as follows. Section II describes the overall system architecture of the proposed converter
and how the TMS works with the whole system and a single
TM-ADC. Design details of the TM-ADC will also be presented
in this section. In Section III, the design of the DPWM will
be discussed. Then, the design of voltage-loop and current-loop
digital compensators will be shown in Section IV. Experimental
results of the proposed converter are shown in Section V. Finally, conclusions are made in Section VI.
II. OVERALL SYSTEM ARCHITECTURE WITH TIME-MULTIPLEX
SCHEME AND TM-ADC
The proposed digitally controlled current-mode buck converter is shown in Fig. 2. There is one TM-ADC instead of two
ADCs in the conventional approach as shown in Fig. 1. The
proposed buck converter is controlled by the DCMC, which includes the DPWM, voltage-loop and current-loop digital compensators (DCs), TM-ADC, and 500 mA power MOSFETs. The
converter requires no external component except for the LC
filter. The memory cells, which are used by the DCs with a
look-up-table approach, are also integrated on chip.
A. Design of Time-Multiplex Scheme
The time-multiplex scheme (TMS) for the DCMC is depicted
in Fig. 3. This scheme allows the DCMC to regulate the buck

1981

Fig. 2. Block diagram of the digitally controlled current-mode buck converter

with a single TM-ADC.

converter by using a single TM-ADC to quantize both the

output voltage and the inductor current through an on-chip
current sensor. To understand how the scheme works, consider
, the rising edge of
triggers
starting from the time at
) and the
the output voltage quantization
(error difference between the reference voltage and the output
. This
voltage) is available after some conversion time
is then fed to the voltage-loop compensator
for
calculating the current-command
at the rising edge
. At the same time, the falling edge of
triggers
of
and the inductor
the inductor current quantization
is available after some convercurrent information
sion time
. Before the rising edge of
at time , both
and
are available for calculating the duty
. Lastly, the
is obtained from the current-loop
ratio
and the DPWM drives the power MOSFETs
compensator
with the pulse width according to the
. By using half of the
switching period for the voltage quantization and the other half
for current quantization, a single ADC is shown to be possible
for current-mode control.
has to be done beIt is very important to note that
because the
must be available together
fore
for calculating the
. Otherwise, the compenwith
will be idle and wait for
to be calculated
sator
from the
by the compensator
. This increases the
control-loop delay by one switching period and thus affects the
stability of the converter.
Another design consideration of the TMS is to determine
what kind of inductor current information is needed to be sampled for the current-mode control. For the current-mode control
used in this paper, only the magnitude of the change of the in[8].
ductor current is needed to calculate the duty ratio
Fig. 4 shows the sampling instant at an arbitrary point before the current quantization. As long as the sampling instant for
every period is unchanged, the magnitude change of the inductor
current can be obtained. Therefore, the sampling instant can be

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS, VOL. 58, NO. 8, AUGUST 2011

Fig. 5. Schematic of 4-bit time-multiplex ADC with an on-demand clock.

Fig. 3. Time-multiplex scheme for the DCMC.

Fig. 4. Timing diagram of the inductor current sampling.

set at any time before the current quantization

. In
this design, in order to simplify the sampling control, the sample
point is taken at the beginning of each period as shown by the
in Fig. 4. Both the inductor current and the output
signal
. However, the time
voltage are sampled at the rising edge of
when they are quantized is different. The output voltage quantization begins right after the output voltage is sampled while the
inductor current quantization begins at the falling edge of
as explained before with Fig. 3.
The inductor current information is sensed by an on-chip current sensor used in [12], which is a high-side inductor current
sensor. In other words, only the input current through the p-type
power MOSFET is sensed. The sensed inductor current is then
held by the sample-and-hold (S/H) circuit discussed in [13] until
signal.
it is quantized at the falling edge of the
B. Design of TM-ADC
In order to ensure the TMS works properly, it is crucial that
the single TM-ADC can quantize both the output voltage and
the inductor current within a switching period. In FPGA implementation, the required ADCs may be built-in with the FPGA
board or external to it. Therefore, little or no function modification can be made to achieve time multiplexing. In contrast,

the TM-ADC, which is based on the successive approximation

(SA) ADC reported in [14], can be fully custom-made to fit this
specific application.
1) Operating Principle of TM-ADC: The schematic of the
4-bit TM-ADC with an on-demand clock is depicted in Fig. 5.
Although the TM-ADC is based on the same principle of successive approximation to do the analog-to-digital conversion, its
implementation is different from [14], [15]. Some modifications
have been made for the design of the controller in this paper.
One is that two set of reference voltages are needed for two different phases of quantization. One (vhigh, vlow) is for output
voltage quantization and the other (ihigh, ilow) is for inductor
current quantization. In this case, the successive approximation
register (SAR) needs to switch the references according to the
TMS mentioned in Fig. 3. Since the upper
and lower
bound
reference voltages are used, the TM-ADC is actually a window ADC [16], which means the ADC is only
linear within the window. This kind of window ADC provides a fine resolution while maintaining low power consumption.
Because of the bipolar supply used in [14], [15], [17], those
SA-ADCs can obtain the digital code by comparing the sampled voltage to the virtual ground. However, bipolar supply is
often unavailable in portable consumer electronics, which use
batteries as the only source of power. This leads to another modification of those SA-ADCs. The TM-ADC shown in Fig. 5 is
implemented using a single supply only. The generation of the
digital code is then done by comparing a predefined DC voltage
as shown in Fig. 5. To have a better underat the node
standing of how the TM-ADC works with the predefined DC
and the window imposed, Fig. 6(a)
voltage used at
shows the simplified version of a 4-bit time-multiplex ADC at
the beginning of the voltage quantization phase.
The following describes how to generate the MSB of the
sampled output voltage of the buck converter. When the
TM-ADC samples the output voltage (i.e.,
voltage of the buck converter), the switch
is closed and
the voltage across all capacitors is given by
(1)

CHAN AND MOK: DESIGN AND IMPLEMENTATION OF FULLY INTEGRATED DIGITALLY CONTROLLED CURRENT-MODE BUCK CONVERTER

1983

actually cancels out.

As we can see from (7), the
Therefore, the behavior of the TM-ADC will not be affected as
is within the input range of the comparator
long as the
(CMP) as shown in Fig. 5. The TM-ADC will continue to
switch the capacitors for comparison and generate the corresponding digital code of the sampled buck converter output
voltage. The detailed operating principles of a generic SA ADC
can be found in [17].
and
) of the TM-ADC in the
The window (
voltage quantization phase defines the quantization level
and the output voltage of the buck converter. This is shown in
the following:
(11)
(12)

Fig. 6. Simplified version of 4-bit time-multiplex ADC: (a) at the beginning

of the voltage quantization phase and (b) at the first comparison for generating
MSB.

Then, when the switch

is opened, the lower plates of
all capacitors will connect to the reference
and the voltage
is given by
(2)
Sub (1) into (2)
(3)
At this stage, the TM-ADC will undergo a first-comparison
and
in order to generate the MSB code of
between
the sampled voltage. This is done by connecting the largest caas shown in Fig. 6(b). The new voltage
pacitor (8C) to
will be given as
(4)
(5)
is logic 1,
Lastly, if the output of the comparator
which is the MSB code of the sampled voltage, this implies
is smaller than
, i.e.,
(6)
(7)
(8)
Similarly, if

is logic 0,
(9)
(10)

For example, if
mV and
V are required,
then we have
V and
V.
The above discussion and derivation are for the voltage quantization phase while the operation of the current quantization
phase is the same as the voltage quantization. The difference is
and
are used as references in the current
that the
quantization. The current quantization level is determined by
the same (11) as the voltage quantization. In particular, the upper
could be designed for the maximum voltage genwindow
erated by the on-chip current sensor when the inductor current
is maximum (e.g., maximum loading current).
However, if one wants to fix a different current quantization
, this can be done by designing the sensing scaling
level
factor of the on-chip current sensor to have the desired maximum voltage under the maximum loading current. The
value is constrained by the flipped voltage follower buffer. In
this case, the hardware-reuse makes the TM-ADC possible for
quantizing both the voltage and the current.
2) On-Demand Clock and Its Synchronization: In order to
start and carry out each step in the successive approximation,
the SAR requires an extra clock. However, the frequency of
this extra clock signal needs to be synchronized with the buck
converter switching frequency. The synchronization here does
not refer to the absolute frequency synchronization between
the extra clock frequency and the buck converter switching
frequency. It means that the extra clock should provide the
TM-ADC with a working-clock right after the rising/falling
signal as shown in Fig. 3. In this case, the
edge of the
TM-ADC can always start the first step of the successive
signal.
approximation after the rising/falling edge of the
The synchronization problem is resolved by incorporating an
on-demand clock. The SAR actively enables the on-demand
in Fig. 3) for successive approximation after the
clock (
rising/falling edge of the
signal. After finishing either the
output voltage or the inductor current quantization, the SAR
turns it off to save power as the clock is unnecessary when the
successive approximation has finished. In fact, the turning off of
the extra clock is also necessary to reset the on-demand clock.
The timing diagram is shown in the enlarged part of Fig. 3.
The
and
are the clock signal from the on-demand
clock and the enabling pin of the on-demand clock, respectively.

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS, VOL. 58, NO. 8, AUGUST 2011

Consider the period of

, at the rising edge of the
,
pin and enables the on-demand
the SAR pulls up the
clock. Then, it feeds a clock signal to the SAR. Once the clock is
available, the SAR starts and carries out the successive approximation, the steps of which are triggered by the falling edge of the
signal. Lastly, the e[n] is generated according to the output
voltage. After the successive approximation is completed, the
SAR pulls down the vosc en pin and disables the on-demand
clock. This is also the purpose of resetting the clock. A simbut the on-demand
ilar procedure is repeated for the
.
clock enabling time is at the falling edge of the
The requirements of the accuracy of the frequency of the
on-demand clock are not stringent. In theory, a 4-bit TM-ADC
requires five clock-cycles to complete either the voltage or
current phase of the analog-to-digital conversion. In practice,
the TM-ADC requires five clock-cycles plus one reset cycle
as illustrated in the enlarged part of Fig. 3. In other words, as
long as the on-demand clock feeds a 12 times or higher clock
frequency to the SAR, it should be sufficient. Therefore, the
on-demand clock is implemented by a simple chain-inverter.
Since the chain-inverter is an all-digital circuit, it consumes
little power. For having enough design margins, the on-demand
clock frequency is 21 times higher than the 3 MHz switching
frequency of the buck converter. From the simulation results,
the 63 MHz chain-inverter consumes 1.72 A/MHz at 3 V
supply with the 0.35 m CMOS process. Although higher
frequency of the on-demand clock can be used, this requires a
faster comparator for the TM-ADC. A faster comparator will
inevitably increase the power consumption.
The TM-ADC operates at the frequency of 3 MHz, which is
the switching frequency of the buck converter, while the on-demand clock operates at 63 MHz. The total current consumption of the TM-ADC in this case is 33 A which is about 33
A/3 MHz
A/MHz. The chip area of the TM-ADC
is about 0.428 mm in the 0.35 m CMOS process. Table I
shows the comparison between the TM-ADC and the self-strobe
delay-line (SS-DL) ADC [16] used in typical low-power digital
controller IC. From Table I, the TM-ADC has an advantage of
low current consumption (11 A/MHz). Although the chip area
of TM-ADC is larger, it can be justified that the technology used
in TM-ADC has a longer channel length. Improvement can be
made if a more advanced process is used.
The slower conversion time of TM-ADC can also be improved by using higher on-demand clock frequency fed to the
SAR. Because the on-demand clock is the simple chain-inverter,
a higher frequency can be easily obtained. However, a 100 ns
conversion time is sufficient for the converter operating up to
3 MHz. Given the same switching frequency of the buck converter, faster conversion time in TM-ADC is unnecessary and
will not help in reducing the control loop delay. This is because the TM-ADC will idle anyway and wait for the next rising/
signal for subsequent output voltage/infalling edge of the
ductor current quantization.
3) Flipped Voltage Follower Buffer for the TM-ADC: Another design consideration of the TM-ADC is that a buffer is
needed to drive its input from the S/H circuit, which does not
have a large capacitive load driving capability. From Fig. 2,
signal is passed to a flipped voltage follower (FVF)
the

TABLE I
COMPARISON OF THE TM-ADC AND THE SS-DL ADC

Fig. 7. Schematic of the FVF.

[18], [19] before feeding the inductor current information to the

TM-ADC. Fig. 7 shows the schematic of the FVF and there are
acts as a buffer
two identical branches. The left branch
of the TM-ADC. However, the
and connects to the input
voltage of the sensed inductor current will have a constant DC
shift (approximately equals to the source-gate voltage of the
) after passing through the FVF. In other words, there is
still constant DC output voltage shift even when the buffer input
is used to
voltage is zero. Therefore, the right branch
by connecting its gate to the
obtain the DC shift
ground. Then, the
is fed to the TM-ADC as a lower
of the inductor current quantization.
bound
C. Design of On-Chip Power MOSFETs
To ensure the high power efficiency of the buck converter, the
power MOSFETs sizing design is important. As a general guideline, it is assumed that the switch resistances of power MOSFETs are 1% of the load resistance. Since the power MOSFETs
are operating in the linear region for most of the time, we have
the following linear equations for the MOSFETs [20] to estimate

CHAN AND MOK: DESIGN AND IMPLEMENTATION OF FULLY INTEGRATED DIGITALLY CONTROLLED CURRENT-MODE BUCK CONVERTER

Fig. 8. Dead time circuit.

1985

Fig. 9. Architecture of the DPWM.

the switch resistance of the p-type power MOSFET

and the n-type power MOSFET
(13)

(14)

where
mobility of holes in (m /Vs),
of
oxide thickness in (F/m ),
electrons in (m /Vs),
to source voltage in (V),
voltage
of the PMOS transistor in (V), and
voltage of
the NMOS transistor in (V).
By simulations, both the sizing of the n-type and p-type power
MOSFETs are optimized for a heavy load condition, i.e., 500
mA loading current. After optimizing the switching resistance
of the power MOSFETs, a dead time circuit, that to preclude
any shoot-through current, is also important for ensuring high
power efficiency. The dead time circuit makes sure that both
n-type and p-type power MOSFETs are not turned on at the
same time, i.e., there is a time that the both MOSFETs are off
(dead time). Although some advanced dead time controls [21],
[22] are available, a simple SR latch implementation has been
chosen for the controller in this paper as shown in Fig. 8. Those
two capacitors Cd are used to adjust the dead time.
III. DESIGN OF DIGITAL PULSE WIDTH MODULATOR
The main function of the DPWM is to convert a digital word
to an analog pulse with different pulse widths
as shown
in Fig. 9 [23]. Conceptually, the DPWM is achieved by quan.
tizing time into a number of discrete time slots of length
Then a particular slot is selected by the digital control input
. The pulse width from the DPWM is then used to
word
drive the power MOSFETs of the switching converter.
In this section, the on-chip implementation of DPWM will be
presented. First, a commonly used DPWM implementation will
be highlighted. It focuses on low power and chip area efficiency.
Then, a modification of the DPWM will be discussed to improve
the conversion accuracy at higher operating frequency.
A. Common Low Power DPWM
Delay-line DPWM is commonly used in low-power digital
PWM controller [5], [6], [16], [24], [25] because of its low

Fig. 10. Common low power DPWM.

power and small chip area. For example, [16] shows one of the
8-bit delay-line DPWM implementations as shown in Fig. 10.
This DPWM has the advantage of not requiring an external
clock and can be implemented on less than one-eighth of the
area needed for the conventional ring implementation.
The operating principle of the DPWM is to use two branches
of delay-line to quantize time into a number of discrete time
slots. One branch consists of fast-delay-cells and the other consists of slow-delay-cells. The slow-delay-cells quantize the time
into coarse slots and then each coarse slot is further quantized by
fast-delay-cells into a fine slot. Then a particular fine time slot is
.
selected by the digital MUX according to the digital word
The main disadvantage of this DPWM is that it is difficult
to match two different types of delay cells, namely, those that
are fast and those that are slow. That is, for the 8-bit DPWM
of one fast-delay-cell has to be
in [16], the delay time
exactly equal to 1/16 of the delay time of one slow-delay-cell
, i.e.,
. Matching all 16 fast-delay-cells
to one slow-delay-cell is very difficult to achieve monolithically
by simply adjusting biasing current because of process variation
and the parasitic layout.
B. Modified 8-Bit Delay-Line DPWM
To solve the matching problem in the delay cells, a modified
architecture of the DPWM is developed as shown in Fig. 11.
The digital duty ratio
is from the current-loop digital com. Then
is split into two halves. One half
pensator
is from the MSB to the middle bit of
for controlling the MUX-A to select the slow-delay-cells. The other
is from the middle bit minus one bit to the LSB
half

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS, VOL. 58, NO. 8, AUGUST 2011

Fig. 13. Block diagram of LUT implementation of PID digital compensator.

A. Voltage-Loop Digital Compensator

Fig. 13 shows the look-up-table implementation of the PID
voltage-loop digital compensator as described in [27]. The PID
compensator block diagram is drawn according to the equation
below:
(15)

Fig. 11. Modified 8-bit delay-line DPWM.

are well docuThe designs of the gain constant

mented in papers [28][31]. The
corresponds to the
duty ratio of the next switching cycle. However, the
is actually the next current command signal
as shown
in Fig. 2. Therefore, can be rewritten as follows:
(15)

Fig. 12. Operation of the DLL.

of the d[n] for controlling the MUX-B to select the fast-delaycells.

, a delay
For ensuring the requirement of
lock loop (DLL) is added to lock the delay of one ref-delaycell equal to that of 16 fast-delay-cells. The ref-delay-cell is
actually the exact replica of one slow-delay-cell. A similar DLL
technique in DPWM has been reported in [26]. However, as the
implementation of the DPWM is different from that in [26], so
is the design of the DLL in this paper.
The operation details of operation of the DLL are summarized in Fig. 12. It is a standard DLL operation including phase
frequency detector (PFD) [22], charge pump (CP), and current
sink for correcting the delay time of the 16 fast-delay-cells. This
locking mechanism will minimize the effect of process variation on the propagation delay. As a result, the newly proposed
DPWM can operate at higher frequency without losing its accuracy.
IV. DESIGN OF DIGITAL COMPENSATORS
As mentioned in the introduction, the digital compensators
could be implemented by coding the DSP/FPGA/microcontroller. Their main disadvantages are high power consumption
and high cost. Therefore, it is not suitable for a low power
switching converter application.
In contrast, the look-up-table (LUT) approach for implementing the digital compensators is more suitable for low-power
applications. The LUT approach also has the advantage of a
small computation delay because it is a one-to-one mapping
table.

After those gain constants have been designed, Table A, B,

and
and store the precalculated values of
, respectively. Once the error signal
is available,
is obtained by summing all the output of those
the
tables. In general, the lengths of the Table A, B and are equal
. For example, if
to the number of all possible values of
is a 4-bit signal, the lengths of Table A, B, and will be equal
.
to
One of the main drawbacks of using LUT is that there are
many storage elements; a large chip area is needed for those tables. Therefore, it is necessary to make the table size as small
as possible. One solution is to reduce the length of those tables,
thereby reducing the chip area. This is achieved by constructing
a full-set of the table entries from a reduced-set of entries. In
other words, this is done by utilizing the linear combination
property of the entries. For instance, Table II lists all the posand the number of bit
sible values of Table A by letting
.
of
There are 15 entries [Table II(a)] in the full-set of Table A.
In the reduced-set table, the full set of Table A entries can be
generated by using only five entries as shown in Table II(b).
The entry 70, for example, can be calculated from the two
entries 10 and 80. The rest of the entries can be obtained
in a similar way. The cost of this implementation is that three
extra subtractors are needed as shown in Fig. 14. As a result,
although the entries of the tables have been reduced three times,
the chip area reduction of the LUT is less than three times. The
following estimates the total memory size before and after the
.
table entries reduction by using the number of bits of
Before the tables reduction,
(16)
(17)

CHAN AND MOK: DESIGN AND IMPLEMENTATION OF FULLY INTEGRATED DIGITALLY CONTROLLED CURRENT-MODE BUCK CONVERTER

1987

TABLE II
FULL-SET OF TABLE A GENERATION DEMONSTRATION (A) ORIGINAL FULL-SET
OF TABLE A, (B) REDUCED-SET OF TABLE A

Fig. 16. Block diagram of the current control law.

is 21.4% reduction in chip area. This shows that the newly proposed algorithm can reduce the chip area to implement the LUT
digital compensators.
B. Current-Loop Digital Compensator
The current-loop digital compensator is based on the onecycle predictive current control as derived in [8]. The current
control law is restated as follows:
(20)

Fig. 14. Block diagram of reduced-set LUT implementation of PID digital

compensator.

where is a constant,
is the current command,
is the sensed inductor current and D is the steady-state duty
cycle. The steady-state duty cycle D is obtained by using a
moving-average low-pass filter on d[n]. In z-domain, the block
diagram is shown in Fig. 16. There is a parameter in the filter
LP(z) to determine its low frequency pole. If the pole is too low,
the steady state D takes a long time to settle. If the pole is too
high, the D is not at steady state. The low frequency pole of
the filter LP(z) is optimized by Matlab simulation. By choosing
, the hardware implementation of the filter is
in the register and addisimply the number of shifts
tion operation [21].
is actuAs mentioned before, the current command
ally from the voltage-loop digital compensator as stated in (15).
can be rewritten as the
In the z-domain, the compensator
following:
(21)
The constants
and are the same constant as defined
before in (15). Moreover, according to Fig. 16, the z-domain
transfer function of the current-loop digital compensator
is stated as the following:

Fig. 15. Chip area comparison of the: (a) original full-set of Table A and (b)
reduced-set of Table A.

(22)
After the tables reduction,
(18)
(19)
Fig. 15 shows the layout of Table A, B, and C. The left one
is the full-set of tables while the right one is the reduced-set tables. The memory structures used in the layout for comparison
are D-flip flop while other memory structures can be used to
implement the tables. It can be seen that the actual chip area is
497.2 m) - (234 m 110 m)
reduced from (612.2 m
= 0.2676 mm to 521 m 404 m
mm , which

In designing the gain of the whole system, precautions have

to be taken to prevent the limit cycle from happening. One
such precaution is to make sure that the gain of the DPWM is
larger than that of the output voltage of the ADC [32]. Table III
summarizes the parameters used for simulation in the Matlab.
Fig. 17 shows the loop gain simulation of the current-mode
buck converter. It shows that the bandwidth of the converter is
about 200 kHz with a phase margin of about 73 .
Fig. 18 shows that the inductor current responses to the cur. The upper waveform is the switching node
rent command
between the n-type and the p-type power MOSFET. The middle
waveform is the inductor current while the lower waveform is

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS, VOL. 58, NO. 8, AUGUST 2011

Fig. 19. Die photo of the fully integrated digitally controlled current-mode
buck converter with the single time-multiplex.
Fig. 17. Loop gain simulation of the current-mode buck converter.
TABLE III
PARAMETERS USED IN MATLAB SIMULATION

Fig. 20. Measurement setup.

the standard memory cells are not available in the AMS process.
The look-up-table is then implemented with D-flip flops. Therefore, the chip area can be further reduced if the memory cells are
used. Also, it is noted that a large chip area on the left hand side
of the die is used for testing purpose during the measurement.
A. Steady-State Output Voltage

Fig. 18. Inductor current response to the current command i

[n]

the current command

. It can be seen that the inductor current is responding to the current command and the current-loop
is operating properly.
V. EXPERIMENTAL RESULTS
The digital current-mode controller of a buck converter is implemented with AustriaMicroSystems (AMS) 0.35 m CMOS
process with a chip area of 1049 m 1533 m. The die photo
is shown in Fig. 19. It can be seen that the voltage-loop digital compensator occupies a large chip area. The reason is that

The steady-state output voltage is obtained with the measurement setup shown in Fig. 20. The input voltage
ranges
regulated at 1.5 V or 1.9 V for
from 2.5 V to 3 V with
testing. The switching frequency of the buck converter is about
2.5 MHz. The ESR of the inductor and the capacitor are 11.2 m
and 10 m , respectively, which is quoted from the manufacturer. Fig. 21 shows the measurement result of the steady-state
dc-coupled output voltage and the inductor current . Those
are measured under different input voltages. For example, the
top left graph of Fig. 21 is at the steady state response with
V,
V and
mA.
The waveforms in Fig. 22 are captured under the same
measurement condition as shown in Fig. 21. The difference is
that the output voltage is measured with ac-coupled. The ripple
voltage is around 40 mV in all cases. The spikes in Fig. 22 are
from the switching noise generated by the parasitic inductance
in PCB. These closed-loop steady state measurement results
show that the buck converter can operate properly and remain
stable with the single TM-ADC under different input/output
voltage conditions. These also show that the buck converter can

CHAN AND MOK: DESIGN AND IMPLEMENTATION OF FULLY INTEGRATED DIGITALLY CONTROLLED CURRENT-MODE BUCK CONVERTER

Fig. 21. Steady state dc-coupled output voltage and inductor current.

1989

Fig. 23. Step-up load transient responses.

Fig. 22. Steady state ac-coupled output voltage and inductor current.
Fig. 24. Step-down load transient responses.

operate properly without any limit-cycle oscillation with the

single TM-ADC.
B. Load Transient
The load transient is obtained by applying a current step
change at the output of the buck converter. For the case of
V, the current step is from 63 mA to 250 mA while
V, the step is from 50 mA to 250 mA. The current
for
step is generated by N-type BJT transistor (2N3904). The
rise time and fall time of the current step are about 1 s. The
measurement set up is also shown in Fig. 20.
The step-up load transient response is captured in Fig. 23.
For example, the top right graph shows the step-up transient at
and inductor current
with
the output voltage
V,
V. The current step
is from 50 mA to 250
in all the graphs correspond to the current step.
mA. The
Similarly, the current step-down transient response is in Fig. 24.

In both cases, the output voltage drop is about 200 mV and the
response time is 20 s.
All these measurement results show that the buck converter is
stable under different loading conditions. The concept of using a
single ADC for current-mode control has proven to be feasible.
Table IV shows the comparison of different digital controller
ICs for Buck converter. Both voltage-mode and current-mode
current converters have been included. It can be observed that
the voltage-mode converters generally have slower load transient responses time than the current-mode converters.
In fact, the inductor value will also limit the transient response
time because it limits how fast the loading current can ramp
up/down. Given the similar inductor value like 2.5 H in [9], this
work has similar transient response time. Among the currentmode converters, the buck converter in this paper is among the
fastest in terms of load transient responses.

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS, VOL. 58, NO. 8, AUGUST 2011

TABLE IV
COMPARISON OF DIFFERENT DIGITAL CONTROLLER ICS FOR BUCK CONVERTER

Fig. 25. Power efficiency with different input voltages.

C. Power Efficiency
The plot of the power efficiency with different input voltages
is shown in Fig. 25. The power efficiency is measured with
the output voltage regulated at 1.9 V. It can be seen that the
highest power efficiency of the buck converter is close to 85%.
The plot of the power efficiency with different output voltages
is shown in Fig. 26. The power efficiency is measured with
the fixed input voltage at 2.5 V. The highest power efficiency is
also close to 85%.
The efficiency is relatively low compared with others in the
Table IV. However, the 0.35 m process is relatively old compared with others. The 0.35 m process has higher parasitic than
the advanced process like 40 nm or 0.13 m.

Fig. 26. Power efficiency with different output voltages.

The buck converter is fabricated with a standard 0.35 m

CMOS process. It consists of the DLL DPWM, voltage-loop
and current-loop digital compensators, the TM-ADC, the
memory cells and the 500 mA power MOSFETs. All of them
are integrated in a single die with a chip area of 1049 m 1533
m. The converter requires no external component except for
the LC filter.
Measurement results show that the buck converter is stable
under different operation conditions. No limit-cycle occurs with
the use of a single TM-ADC. The 20 s load transient response
time is comparable with the other digitally controlled buck converters. All of these proved that it is possible to use a single
TM-ADC for a stable and fast dual-loop digitally controlled
converter.

VI. CONCLUSION
The challenges and design considerations of implementing
a fully integrated digitally controlled current-mode buck converter has been addressed and discussed. Throughout the design of the converter, the implementation of the TM-ADC, the
DLL DPWM and the chip-area reduction algorithm has been
discussed.

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Man Pun Chan (S08) received the B.Eng. and
M.Phil. degrees in electronic and computer engineering from the Hong Kong University of Science
and Technology (HKUST) in 2006 and 2008, respectively. He is currently working toward the Ph.D.
degree in electronic and computer engineering at
HKUST, with the Integrated Power Electronics Lab
(IPEL).
He was a part-time IC Design Engineer from
Jan. 2005 to May 2006 in Lexiwave Technology
(HK) Ltd. His current research interest is in digitally
controlled SMPC, low-power ADC and mix-signal design.
Mr. Chan was the recipient of the STMicroelectronics Ltd Scholarship in
2005. He has won first prize both in the Student Paper Contest of the 2008
IEEE International Conference on Electron Devices and Solid-State Circuits
(EDSSC) and the 2010 IEEE Asia Pacific Conference on Circuits and Systems
(APCCAS).
Philip K. T. Mok (S86M95SM02) received the
B.A.Sc., M.A.Sc., and Ph.D. degrees in electrical
and computer engineering from the University of
Toronto, Toronto, ON, Canada, in 1986, 1989 and
1995, respectively.
In January 1995, he joined the Department of
Electronic and Computer Engineering, Hong Kong
University of Science and Technology, Hong Kong,
China, where he is currently a Professor. His research
interests include semiconductor devices, processing
technologies and circuit designs for power electronics and telecommunications applications, with current emphasis on power
management integrated circuits, low-voltage analog integrated circuits, and RF
integrated circuits design.
Dr. Mok received the Henry G. Acres Medal, the W.S. Wilson Medal and
a Teaching Assistant Award from the University of Toronto, and the Teaching
Excellence Appreciation Award three times from The Hong Kong University
of Science and Technology. He is also a corecipient of the Best Student Paper
Award in the 2002 and 2009 IEEE Custom Integrated Circuits Conference. In
addition, he has been a member of the International Technical Program Committees of the IEEE International Solid-State Circuits Conference (ISSCC) from
2005 to 2010 and he served as an Associate Editor for the IEEE TRANSACTIONS
ON CIRCUITS AND SYSTEMSPART II: EXPRESS BRIEFS from 2005 to 2007, the
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSPART I: REGULAR PAPERS
from 2007 to 2009, and the IEEE JOURNAL OF SOLID-STATE CIRCUITS since
2006.