Idesa RF Lecture8 Kuzmicz 20080514

IDESA
Implementation of widespread IC design skills

in advanced deep submicron technologies
at European Academia
Advanced RF implementation flow

90nm design verification
22 May 2008
Wieslaw Kuzmicz - Warsaw University of
Technology, Warsaw, Poland
Copyright Statement
The development of this material was funded by the European
Community through the 7th Framework Program.
This material can be used in the curricula of regular master courses at
European academia. Use for commercial benefit is prohibited.
IDESA - IC Design Skills for Advanced DSM Technologies
Outline
Goal of this presentation: discussion of design verification
techniques, with special emphasis on realistic post-layout
simulation and on layout verification issues in DSM
technologies
Verification goals and flows
Circuit extraction for post-layout simulation
Basic concepts
Parasitic extraction
Special cases
Design Rule Checking and Design for Manufacturability
Design Rules and Checks

Recommended rules for DfM
Layout postprocessing and mask preparation

Wieslaw Kuzmicz - Warsaw University of Technology IDESA 2008 |
Chip verification 15 years ago
and now
Formal verification
complexity: 10x more rules

DRC
Nominal circuit extraction, ERC and LVS
Functional verification
Circuit extraction with parasitics
Post-layout simulation
2D->3D, extraction for RF

new complex device models
Verification of manufacturability and DfM

New classes of design rules
recommended rules
additional restrictions
Layout postprocessing
Modifications for CMP, layer density rules
Resolution enhancement techniques: OPC, PSM, SRAF
Analog verification and chip finishing - the old way

Design
Circuit and layout design

DRC
OK?
Traditional
verification
flow
Extraction, ERC and LVS

OK?
Designers
job
Parasitic extraction and postlayout simulations: nominal, at

PVT corners, Monte Carlo
OK?
Chip finishing
Pad ring, logo etc. and final DRC OK
Fab line
DSM analog verification and chip finishing

Circuit and complete layout design
Traditional verification flow
Not OK
Always
designers
job
OK
DfM layout improvements

Layer density verification
OK?
Layout redesign
Y
Traditional verification flow
Not OK
OK
Usually
manufacturers
job
Applying RET (OPC, PSM, SRAF)

Optionally
designers
job
Litho simulation
Parasitic extraction
and post-layout simulations (optional)
Often
designers
job
Not OK
OK
Fab line
Derived layers
Creating derived layers for circuit extraction
M1_to_N_S/D capacitor =
NMOS_S/D Metal1 !Contact cut
Metal1
N implant
NMOS_channel =
Active N implant Poly
(note: this capacitor

is shorted here)
Poly
Active
Contact cut
NMOS_S/D =
Active N implant
NMOS_S/D contact =
NMOS_S/D Metal1 Contact cut
Derived layers
Creating derived layers for circuit extraction
Poly_contact =
Poly Metal Contact cut
Poly
Metal1
(note: this capacitor

is shorted)
M1_to_poly_capacitor =
Poly Metal !Contact cut
Derived layers
Creating derived layers for design rule check (DRC)
0.5 DPA
Poly_DRC
Poly
Acive_DRC
DPA = Min polyactive spacing
No overlap - no error here
Active
DPA = Min polyactive spacing
Poly
Poly_to_active_error =
Poly_DRC Active_DRC
Marker layers
Marker layers: auxiliary layers for better control of circuit
extraction and DRC. Markers at marker layers are polygons that
may indicate:
Regions excluded from circuit extraction (e.g. I/O pads),
Regions excluded from DRC (e.g. I/O pads),
Regions excluded from other actions (e.g. dummy fill insertion),
Regions selected for some action (e.g. dummy fill insertion),
Regions that should be treated separately (e.g. digital part of the
chip and analog part of the chip),
Devices that cannot be recognized in the usual way (e.g.
inductors).
10
Circuit extraction
Device recognition and connectivity analysis:
MOS devices and resistors
NMOS_channel property:
MOS device,
L=90nm, W=120 nm
Metal1 property:
resistive, Rs=0.09/
1
Poly property:
2
resistive, Rs=10/
NMOS_S/D property:
resistive, Rs=9/
1
GND
M1,120/90
3
Nominal extraction (MOS

devices only)
3
R1 = Rmet1+Rcont +RSD
R3 = Rpoly
NMOS_SD_contact property:
resistive, R=15
1
2
R2 = Rmet1+Rcont +RSD
GND
M1,120/90
3
Extraction with parasitic resistances
11
Circuit extraction
Device recognition and connectivity analysis:
some exceptions
Connection exists
No connection
Connection exists
No connection
12
Circuit extraction
Device recognition and connectivity analysis: capacitors
C: M1 to poly capacitance
(area = overlap area)
R: contact resistance
C negligible
R negligible
C: M1 to poly capacitance
(area = overlap area - contact area)
13
Circuit extraction
Creating netlist
From analysis of the database of layers (primary
and derived)
1
2
GND
M1,120/90
3
M1 1 2 3 GND NCH W=120E-9 L=90E-9...

.MODEL NCH NMOS LEVEL=14 VTO=0.35...
MOS device model added from the PDK
R1
5
R3
1
2
GND
M1,120/90
3
R2
M1 1 2 3 GND NCH W=120E-9 L=90E-9...

R1 1 5 27
Resistances calculated by
R2 3 7 30
the extractor
R3 2 6 33
.MODEL NCH NMOS LEVEL=14 VTO=0.35...
14
Circuit extraction
Parasitic capacitances in DSM technologies
Old technologies: lateral
dimensions much larger
than vertical ones, lateral
capacitances negligible
compared to interlayer
(vertical) ones.
DSM technologies: lateral
and vertical dimensions
comparable, lateral
capacitances no longer
negligible, many more
metal layers.
Computational complexity of true 3D multilayer capacitance extraction is very high.
Extractors simplify this process extracting only short range capacitances.
15
Circuit extraction
Parasitic capacitances in DSM technologies
Example: capacitances extracted by Calibre xRC tool:
Lateral single layer
capacitance
Metal2
Plate
capacitance
Lateral interlayer
capacitance
Fringe
capacitance
Metal2
Fringe
capacitance
Plate
capacitance
Metal1
Fringe
capacitance
Plate
capacitance
Semiconductor
16
Circuit extraction
Too many components - netlist reduction
Extraction of all components (MOS devices, resistances of all conducting
paths on all layers, all interlayer and lateral capacitances and all diodes)
creates huge netlists. Example: full extraction of a simple opamp gives a
netlist with 1162 R, C and D components. Only few of them affect operation
of the circuit! Netlist reduction performed by extractors is rather limited.
NMOS devices: 6
PMOS devices: 3
Diodes: 29
Capacitors: 69
Resistors: 1064
It doesnt make sense to extract everything, a wise selection must be made!
17
Circuit extraction: special cases

Bipolar devices in CMOS circuits
Every NMOS device is also a lateral bipolar npn transistor. In DSM
technologies base width of this device is below 100 nm.
Every PMOS device on a n-well is also a lateral pnp bipolar transistor, and
source and drain regions create substrate pnp transistors.
n
p
Extraction would add huge number of bipolar devices to the netlist, in the
off state in most cases. Therefore bipolar devices are usually not
extracted.
Intentionally used bipolar transistors are usually precharacterized library components, not easily scalable.
Emitter
They are often represented by subcircuits in the netlist.
Base
Grey shape: marker layer this is bipolar transistor

Collector
18

Inductors and parasitic inductances
There is no simple and accurate way to find parasitic inductance of an
interconnection wire over a semi-conducting substrate in the vicinity of other
wires (skin effect, proximity of other wires, uncertain return path). However,
extractors do have tools for estimation of parasitic inductances. Normally
these inductances are very small and can be neglected even in RF circuits.
Inductors are shaped as spiral metal wires, often over
special patterns on other layers (e.g. pn junctions
blocking eddy currents). Although they are easily
recognized by a human, it is not easy to extract such
structures as inductors automatically, and it is even
more difficult to calculate their inductance and Q-factor.
Blue shape: marker layer this is an inductor
Inductors are not easily scalable. They are usually pre-characterized library
components, often represented by subcircuits in the netlist.
19

Example: inductances in Calibre xL tool - some options
Inductance ERC
Intended to estimate magnetic noise due to mutual inductance
of intentional inductors; finds the magnetic noise parameter K
defined as the ratio of the mutual inductance between two
intentional devices normalized to the geometric mean of the
two self inductances.
Sufficiently accurate if distance larger than 1/10 of the
inductors dimensions
Point-to-point inductance extraction

Extracts self-inductance of single paths
Endpoints (driver and receiver) must be specified on the
layout
Performed for paths longer than 100 m
20

Example: inductances in Calibre xL tool - some options
Self- and mutual inductance extraction

Intended to estimate the effect of magnetic coupling between
long parallel paths
Aggressor and victim paths must be identified: for a given
victim all paths within a tube of radius R (default = 60 m) are
aggressors
aggressor
path
R
victim
path
not
aggressor
path
aggressor
path
21

Parasitics in MOS devices - extraction and modeling
If source/drain diodes of MOS devices are treated as internal parts of these devices,
it is difficult to avoid ambiguities.
MN1 1 2 3 0 Nchan W=325E-9 L=65E-9
+PD=1040E-9 AD=6.34E-14
D2
MN2 3 4 5 0 Nchan W=325E-9 L=65E-9

+PD=1040E-9 AD=6.34E-14
G2
S2
D2
G1
G2
S2 and D1
G1
S1
S1
D1
OK for layout 1 (separate source2 and drain1)

Wrong for layout 2 (shared source2/drain1)
Area and perimeter of the shared D1/S2
diode overestimated -> overestimated
capacitance and leakage current.
It is safer to treat source/drain diodes as separate devices. If they are

extracted separately, MOS models must not include them.
22

Parasitics in MOS devices - extraction and modeling
A way to avoid ambiguities is to use parametrized device cells (p-cells).
The devices designed using p-cells have models parametrized to match the
device layout, with parasitics (e.g. S/D resistances and capacitances) included.
The extractor must not extract any parasitics inside the p-cell.
p-cell: no parasitics extraction
inside (included in device model)
Outside p-cell: extraction of

parasitic R and C
23

Floating nets
Isolated shapes on conducting layers may be extracted as capacitors with one
terminal disconnected. Such isolated shapes are common in DSM layouts.
Metal1 connection
Isolated piece of metal2
Floating net
Circuit simulators usually dont accept floating nets (their potential is

undefined). Extractors offer several options:
Extract floating nets and leave them in the netlist.
Extract floating nets together with their net-to-ground capacitances.
Extract floating nets but delete them from the netlist.
Connect floating nets to ground.
The last two options are safe for circuit simulation, but either underestimate
or overestimate the total interconnect parasitic capacitance.
24

Distributed RC networks
Extractors offer option to extract long interconnects as RC networks. Coupling
capacitance between adjacent paths can be included.
or
25
Circuit extraction - summary

Extraction is a set of logical and geometrical operations on 2D
geometrical objects.
Extractors know very little about real 3D structures of ICs.
Extractors do not do any simulation of active devices.
Resistances and capacitances are calculated from layer physical
properties and device geometry; usually simple formulas are used for
computational efficiency.
Extraction of some classes of devices requires understanding of the
intention of the designer; special markers are used to indicate these
devices.
Some devices are not easily scalable, usually pre-defined.
Extraction in analog and RF domains is not automatic - good
understanding of circuit and device operation is needed to select
proper layout and extraction options in order to obtain realistic postlayout simulation results.
26
DRC
Simple geometrical rules: min. width, spacing, overlap,
enclosure, extension
Voltage dependent rules: min. spacing depending on the bias
voltage
Current density rules: min. metal width necessary for a given
average or pulse current
Latchup rules: to prevent latchup
Antenna rules: max. area of poly and/or metal connected to MOS
gates to avoid thin oxide breakdown due to ion-induced charge
Layer density rules: min. and max. density of layout features for
process uniformity
DfM (recommended) rules: yield enhancing recommendations
27
DRC
Simple geometrical rules
a: minimum width
b: minimum spacing (same or different layers)
c: minimum enclosure
d: minimum overlap
e: minimum extension
f: min. and max. dimension (usually contact cuts)
In DSM technologies:
more rules per layer
many more layers (10+
metal layers)
-> huge total number of rules
In DSM technologies layer width and spacing are often not independent:
larger width -> larger minimum spacing
28
DRC
Simple geometrical rules - example (metal rules)
Old technology: simple
a: minimum width 1 m
b: minimum spacing 1 m
DSM technology: no longer simple
a: minimum width 0.15 m
b: minimum spacing:
for width w (m)
min. spacing (m)
w < 0.20
0.15
0.20 < w < 1.5
0.2
1.5 < w < 5.0
1.5
5.0 < w
5.0
a b
c: min. width for 45 path: 0.19 m

d: min. spacing for 45 path: 0.19 m
e: min. width in spiral inductors: 1.5 m
f: min. spacing in spiral inductors: 1.5 m
c
a b
29
DRC
Voltage dependent rules
d1
d2
Minimum spacing may depend on the voltage applied, e.g. d1 < d2 if A and B
are at the same potential while B and C are not.
Such rules, if exist, are difficult to verify - DRC tools dont know anything about
voltages in the circuit.
30
DRC
Current density rules
Minimum metal width depends on the lithography resolution and on the maximum
current density (determined by reliability considerations). Large widths may be
necessary for power and ground nets.
DRC tools do not verify the current density. However, special tools exist in EDA
toolsets for design of power nets in large VLSI circuits.
Current is also limited in contacts and vias. If the
maximum current exceeds such a limit, multiple
contacts or vias must be used. This also reduces
contact or via resistance, improves yield and
reliability.
Max. currents in minimum size metal paths in

DSM circuits are very low!
31
DRC
Current density rules - example
The maximum current density is a function of metal path width and thickness,
current waveform (DC, pulse, sinusoidal) and maximum operating temperature.
IDC (mA)
Layer no.
105C
Ipeak (mA)
125C
105C
125C
M1
3*(W-0.02)
0.75*(W-0.02)
15 * IDC
60 * IDC
M2
4*(W-0.02)
1*(W-0.02)
7.5 * IDC
30 * IDC
M3
4*(W-0.02)
1*(W-0.02)
7.5 * IDC
30 * IDC
M4
4*(W-0.02)
1*(W-0.02)
7.5 * IDC
30 * IDC
M5
4*(W-0.02)
1*(W-0.02)
7.5 * IDC
30 * IDC
M6
10*(W-0.02)
2.5*(W-0.02)
5 * IDC
20 * IDC
M7
10*(W-0.02)
2.5*(W-0.02)
5 * IDC
20 * IDC
W - width in m
All metal layers are copper layers

32
DRC
Latchup rules
Latchup may occur when at least one of the source/drain pn junctions of MOS
devices becomes forward biased. In a well designed circuit this may happen
when the substrate is non-equipotential due to transient currents flowing in it.
Therefore the general rule to avoid latchup is very simple: make the substrate
equipotential using as many contacts to the ground node (for p-wells or p-type
substrate) or the VDD node (for n-wells) as possible.
Example of DSM latchup rule:
max. distance from the body contact
to the boundaries of source/drain
regions < 25 m.
For I/O cells guard rings connecting
the well or substrate to VDD or
ground are used.
33
DRC
Antenna rules
Plasma processes (e.g. reactive ion etching) result in accumulation of charge on
conducting paths. This charge may destroy thin gate oxide in MOS devices during
fabrication. Antenna rules specify the maximum area of conducting layers (poly and
metal) that can be safely connected to MOS device gates. If the total area (sum of
areas of all layers exposed to ions) is not too big, no danger exists.
Ions
n
Antenna error:
too large metal1
area
34
DRC
Antenna rules
Ion induced damage will not occur if ion charge is drained by a diode connected
between the conducting antenna and semiconductor substrate.
In CMOS circuits all transistor gates are connected to such diodes in completed
circuit. However, during fabrication such a connection may not exist yet when a
big conducting antenna is already attached to a MOS device gate.
m2
Damage during m1
m1
etching, m2 does
not exist yet.
n
n
n
35
DRC
Antenna rules
Antenna effect prevention when a large conducting area must be connected to a
gate:
m2
m1
Diode insertion
Area too small

to collect
dangerous
charge
Bridging
m2
m1
36
DRC
Antenna rules - example
Maximum ratio R of the area of the conducting layer (antenna) connected to
the gate to the area of the gate for unprotected gates (no diode):
R=
Aantenna
Agate
For poly (area): R < 200

For poly (sidewall area): R < 450
For metal (cumulative area): R < 1000
where
Poly sidewall area = poly perimeter * poly thickness
Metal cumulative area = sum of areas of all metal layers
37
DRC
Layer density rules
Fairly uniform density of mask features on some layers is a must for good process
control.
Density affects etching speed:
Faster etching here
Slower etching here
Resist
Density affects chemical-mechanical planarization (CMP, crucial in DSM processes):

Copper is soft->fast polishing
Dishing
Ta is hard->slow polishing
Ta barrier
Copper
To achieve uniform density, dummy fills (extra shapes) are added where needed.
38
DRC
Layer density rules
Usually min. density (20% - 30%) and max. density (60% - 80%)
These numbers are layer-dependent
Checks show areas where density rules are violated
Dummy fills may be added:
manually
automatically (markers used to exclude some areas)
by the foundry (markers used to exclude some areas)
Dummy fills on conductive layers affect parasitic capacitances

In wide metal areas slots must be added
or
39
DRC
Layer density rules
Layer density rules are checked in moving windows, areas violating the density
rule are indicated.
Av. density = 40%: wrong!
Av. density = 40%: OK!
40
DRC
Layer density rules
Dummy fills on active

41
DRC
Layer density rules
Dummy fills on poly

42
DRC
Layer density rules
Dummy fills on two metal layers

43
DRC
Recommended rules and DfM
These rules help to maximize manufacturing yield. They are usually not verified.
Examples:
Recommended width and spacing larger than minimum
Same orientation for all shapes on the layer
Path spreading (equal distances)
Multiple contacts and vias wherever possible
44
DRC
Recommended rules and DfM
Analysis of critical area
Critical area for shorts: area in the layout where
a spot defect (extra piece of conducting material)
of radius R creates a short
Critical area for opens: area in the layout where
a spot defect (missing piece of conducting material)
of radius R creates a path break
Some DRC tools offer critical area analysis. Visualization of critical areas helps
to find weak spots in the layout - areas sensitive to spot defects. This allows
to optimize the layout (minimize defect sensitivity). The defect density and defect
size distribution are needed. They are process-specific foundry proprietary data,
usually not available in ordinary PDKs.
45
Layout postprocessing and mask data preparation

Resolution Enhancement Techniques (RET)
Subresolution Assist Features (SRAF) - addition of unprintable
mask features that improve lithography resolution, e.g. scattering bars
Optical and Process Correction (OPC) - predistortion of mask shapes in order
to improve final (printed) shapes
Phase Shifting Masks (PSM) - use phase shifts and interference to make subwavelength printing possible (e.g. by means of double exposure with two
different masks)
Layout postprocessing is normally performed by the foundry.
OPC picture courtesy of J-M. Brunet, IEEE Web Seminar, November 9, 2006, reproduced with permission
46
DRC - summary
DRC in DSM technologies is not just simple
verification of geometry of layout features.
To obtain a manufacturable design, modifications of
the original layout beyond correction of simple DRC
violations may be needed.
DRC-clean designs not always guarantee high
manufacturing yield.
Recommended rules provide guidelines how to
improve the layout to make it more litho-friendly.
DfM-oriented layout analysis and layout
postprocessing are theoretically possible (tools exist)
but require deep processing knowledge and processspecific data normally not available for the designer.
47
IC Design Skills for Advanced DSM Technologies

Idesa RF Lecture8 Kuzmicz 20080514

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IDESA

Implementation of widespread IC design skills

Advanced RF implementation flow

IDESA - IC Design Skills for Advanced DSM Technologies

Design Rule Checking and Design for Manufacturability

Design Rules and Checks

Layout postprocessing and mask preparation

IDESA - IC Design Skills for Advanced DSM Technologies

Chip verification 15 years ago

complexity: 10x more rules

2D->3D, extraction for RF

Verification of manufacturability and DfM

IDESA - IC Design Skills for Advanced DSM Technologies

Analog verification and chip finishing - the old way

Circuit and layout design

Extraction, ERC and LVS

Parasitic extraction and postlayout simulations: nominal, at

Pad ring, logo etc. and final DRC OK

Wieslaw Kuzmicz - Warsaw University of Technology IDESA 2008 |

IDESA - IC Design Skills for Advanced DSM Technologies

DSM analog verification and chip finishing

DfM layout improvements

Applying RET (OPC, PSM, SRAF)

Wieslaw Kuzmicz - Warsaw University of Technology IDESA 2008 |

IDESA - IC Design Skills for Advanced DSM Technologies

(note: this capacitor

Wieslaw Kuzmicz - Warsaw University of Technology IDESA 2008 |

IDESA - IC Design Skills for Advanced DSM Technologies

(note: this capacitor

Wieslaw Kuzmicz - Warsaw University of Technology IDESA 2008 |

IDESA - IC Design Skills for Advanced DSM Technologies

No overlap - no error here

Wieslaw Kuzmicz - Warsaw University of Technology IDESA 2008 |

IDESA - IC Design Skills for Advanced DSM Technologies

Wieslaw Kuzmicz - Warsaw University of Technology IDESA 2008 |

IDESA - IC Design Skills for Advanced DSM Technologies

Nominal extraction (MOS

Extraction with parasitic resistances

Wieslaw Kuzmicz - Warsaw University of Technology IDESA 2008 |

IDESA - IC Design Skills for Advanced DSM Technologies

Wieslaw Kuzmicz - Warsaw University of Technology IDESA 2008 |

IDESA - IC Design Skills for Advanced DSM Technologies

Wieslaw Kuzmicz - Warsaw University of Technology IDESA 2008 |

IDESA - IC Design Skills for Advanced DSM Technologies

M1 1 2 3 GND NCH W=120E-9 L=90E-9...

M1 1 2 3 GND NCH W=120E-9 L=90E-9...

Wieslaw Kuzmicz - Warsaw University of Technology IDESA 2008 |

IDESA - IC Design Skills for Advanced DSM Technologies

IDESA - IC Design Skills for Advanced DSM Technologies

Wieslaw Kuzmicz - Warsaw University of Technology IDESA 2008 |

IDESA - IC Design Skills for Advanced DSM Technologies

IDESA - IC Design Skills for Advanced DSM Technologies

Circuit extraction: special cases

Grey shape: marker layer this is bipolar transistor

IDESA - IC Design Skills for Advanced DSM Technologies

Circuit extraction: special cases

IDESA - IC Design Skills for Advanced DSM Technologies

Circuit extraction: special cases

Point-to-point inductance extraction

Wieslaw Kuzmicz - Warsaw University of Technology IDESA 2008 |

IDESA - IC Design Skills for Advanced DSM Technologies

Circuit extraction: special cases

Self- and mutual inductance extraction