Input Output Interface

Introduction
In addition to memory, a computer system must also provide interfaces with other
external devices, such as display unit, keyboard etc. All these external devices are
regarded as Input/Output devices (usually we simply use the term I/O). In general,
memory can also be considered as some kinds of I/O from the CPUs point of view.
The I/O (Input/Output) interface permits the microprocessor to communicate with the
outside world. How can you connect a keyboard, or a mouse, to an 8086 microprocessor?
In the 8086 microprocessor, I/O devices are connected via the address and data buses
and the mechanism is similar to the memory interface. Data transfer takes place over the
multiplexed address/data bus.

The above figure shows how the I/O devices are connected to the system. As you can see
the major difference between connection to a memory and connecting to I/O devices is
the signal level of M/IO. When accessing memory devices M/IO is 1. While M/IO is
0 when accessing I/O devices.
Similar to memory devices, as there are many I/O devices connected to the buses
therefore, decoding is also required for I/O system.
The 8086 minimum mode I/O interface

Interface circuitry, as depicted in Figure 7.1, is used to bridge the microprocessor and the
I/O (Input/Output) devices. Functions of the interface are to select the I/O port, latch
output data, adjust the signal levels etc. Only address/data lines from 0-15 are used (but
for memory devices address lines A0 to A19 are used.) In addition, the I/O interface
circuit is also similar to the memory decoder.
I/O address space
Unlike the 89C51, or the ADuC832, there are no I/O ports available in the 8086. All
I/O devices are connected to the address bus and data bus. However, we still use the
term I/O port to describe the connection between the 8086 and an I/O device. Since only
address lines A0 to A15 are used by I/O devices so a total of 64K devices can be
connected to the system. Imagine there are virtual I/O ports then the ports are numbered
from 0 to 64K-1. Similar to memory devices, byte is the basic unit for data transfer so if
an I/O device transfers 16-bit data then it will occupy 2 ports. So I/O ports could be 8-bit
or 16-bit.
I/O port number (16-bit) are generated by microprocessor via the ADn lines and after
proper decoding, correct I/O port can be selected. AD16 to AD19 are held at 0 for I/O
operations.
Software for accessing I/O ports
When accessing memory, we use move (MOV) operations. When accessing I/O port,
we use IN and OUT. There are two forms of IN OUT instructions: direct and indirect.
In Direct instruction, we can address 256 ports (8-bit) only. The format of IN OUT is:

IN - input from port into AL or AX

OUT - Output from AL or AX to port
IN AL, a-8-bit-value representing the port number,
eg IN AL, #FFH (move a byte in from port FF)
OUT an-8-bit-value representing the port number, AL ,
eg OUT #FFH, AL (move a byte out from AL)
The 8-bit value is used to represent a port, since it is 8-bit so only Port 0 to Port 255 can
be manipulated.
For accessing Port greater than 255 then Indirect addressing is used. And the format
is
IN AL, DX
Where DX is 16-bit and stores the port number.
Indirect addressing can access 64K ports (WHY?)
Example:
MOV DX, #1234H
MOV AL, #12h
OUT DX, AL ; SEND THE VALUE 12H TO PORT 1234H
Program example
Data are to be read in from two byte-wide input ports at port AA and A9, respectively,
and then output as a word to a word-wide output port at port B000. The data comes
from Port AA is the high byte. Write a sequence of instructions to perform these I/O
operations.
IN
MOV
IN
MOV
OUT

AL, AA
AH,AL
AL,A9 ; now the data becomes 16-bit and stored in AX
DX, B000
DX, AX
; can I do OUT B000, AX instead ??????

Since the port number B000 is larger then 8-bit so indirect is used.
I/O bus cycle
Accessing I/O devices are very similar to accessing memory therefore, to read/write data
to or from an I/O device, a proper cycle is performed. A read cycle for I/O also takes 4
cycles and the signals are very similar to the memory read cycle except the M/IO signal.

Input cycle (you should compare this with the memory read/write cycle)

Timing for an output cycle (write)

Hardware configuration for Output devices

Figure 7.8 Input/output decoding

The device 8282, as shown in the above diagram, is only a latch for storing data. The
8205 (similar to a 3x8 multiplexer) is used as a decoder. When the 8086 issues a Port
Number via its address bus, the number is decoded so that a proper I/O device can be
selected. In the circuit, the decoder output is used to control the STB (Strobe) of the
8282. Since the circuit only supports output therefore, the signal /WR is also used as part
of a control for the STB.
Are you able to determine the Port addresses represented by the 8282?
Example
Refer to the Figure 7.8, to which port are data written when the address put on the bus
during an output bus cycle is 8002(Hex)
Write a series of instructions that will output the byte contents of the memory location
called DATA to output Port 0 as shown in Figure 7.8.
Answer
The input select (ABC) for the 8205 is driven by A1 A2 and A3, refer to the diagram
For the address 8002H, the 3 bits are 001 (2Hex)
So Port 1 is selected

The control required to select the Port 0 is

8000H (refer to above, Port 1 is 8002)
The instruction is
Mov DX, 8000H
Mov AL, DATA
Out DX, AL ; using indirect
8255A Programmable Peripheral Interface (PPI)
As you can see in Figure 7.8, in order to connect to an I/O device, a buffer, or latch is
required. If your system is connected to many I/O devices then a lot of latches are
required. Usually, a computer system makes use of some ICs instead of standard latches
to interface with the I/O devices and the 8255A is the most common interface used in a
computer system.
The 8255A is an LSI peripheral designed to permit easy implementation of parallel I/O in
the PC systems. It provides a flexible parallel interface, such as input and output ports;
level-sensitive inputs; latched outputs; strobed inputs or outputs; and strobed bidirectional
input/outputs. These features are selected under software control. 8255 can interface any
TTL-compatible I/O device to the microprocessor. You can obtain a full description of the
8255 by downloading its data sheet, or the document PIO_8255.doc in the ftp site.
Usually the 8255 is used to interface with a keyboard and parallel printer port in the past
but now most of the interfaces are based on USB. However, the 8255 is still applied in
interfacing with non-standard devices. For example, if you want to use a PC to control a
motor etc.
The block diagram of the 8255 is shown below.

The major features of the 8255 include:

1. there are 3 8-bit bi-direction ports (the Ports are called Port A, Port B, and Port
C)
2. ports are controlled by software

To/From
PortA
To/From
PortB

8255A
To/From
CPU

To/From
PortC

Referring to the block diagram, you can see that the 8255 is similar to a multiplexer with
1 interface with the CPU but 3 interfaces with I/O devices. Therefore, there must be
some selection mechanism so that data can be channeled to the proper Port. This is
achieved via the 2 input control (A0 and A1).
Address A0 and A1 (these are input of 8255 not 8086) are used to select the port.
Data are transferred through an 8-bit bidirectional data bus between the 8255 and the
CPU.
Chip select (/CS) of the 8255 must be enabled before you can program or access the
8255.
With 2 control bits (A0 and A1), there are 4 combinations, as shown below
Select code A1 A0
00
Port A
01
Port B
10
Port C
11
Control Register
The control bits (A0 and A1) usually come from the address lines of the CPU implying
that the 8255 will occupy at least 4 I/O ports of the computer system.
Example
If PortA occupies port location 1238H and PortB occupies 123AH, can you determine
port numbers occupied by other Ports? What address lines are connected to A1A0 of the
8255?
Consider the port number in binary form
0001 0010 0011 1000 (1238H)
0001 0010 0011 1010 (123AH)
According to the table PortA is selected when A1A0 are 00 and PortB is selected when
A1A0 are 01 so the other ports should be 123CH and 123EH (when A1A0 = 10 and 11).
The address lines used are A2A1 with A2 connected to A1 of 8255 and A1 connected to
A0 of 8255.

Connect to uP

Connect to I/O
devices

Data connect to data bus of processor

/RD connect to /RD of the uP (active when reading data from 8255)
/WR connect to /WR of the uP (active when writing data to 8255)
/CS connect to decoding device (active when reading or writing to or from 8255)
Control of the 8255
Before you can make use of the 8255, you must first program the device according to
your design. For example, you may want Port A as input, Port B and C as output. The
program is done via the internal control register, which is selected when A1A0 are 11.
The control register is represented by (or divided into) group A and group B control
blocks. Input/Output operations of the Ports A, B, C are controlled by different bitpatterns.
To program the 8255, you must set A1A0 = 11 then write the control pattern to the 8255.

The control word bit functions are given in the table.

D0

Group B

Port C lower

D1

Port B

D2

Mode selection

D3

Group A

Port C upper

D4

Port A

D6, D5

Mode selection

D7

Command type

0
1
0
1
0
1
0
1
0
1
00
01
1X
0
1

Output
Input
Output
Input
Mode 0
Mode 1
Output
Input
Output
Input
Mode 0
Mode 1
Mode 2
Bit set/reset
Mode set

Control bits definitions

D7 to D0 represent bits of the control register
D0 set input/output for lower 4-bit of Port C (1 for input; 0 for output )
D1 set input/output for 8-bit of Port B
D2 mode selection (0 mode 0; 1 mode 1)
D3 same as D0 but for upper 4-bit
D4 same as D1 but for Port A
D6 & D5 mode selection (00 mode 0, 01 mode 1, 1X mode 2)
D7 mode set flag ( 1- active)
Mode selection
Mode set flag is the D7 bit in the control register, it must be at logic 1 whenever the
mode operation is to be changed (i.e when you want to program the device). There
are three modes of operation which are known as mode 0, mode 1, and mode 2
respectively.
Mode 0 selects simple I/O operation, i.e., the lines of the port can be configured as
level-sensitive inputs or latched output.
Output ports are latched. Input ports are not latched????
Output ports are latched implying data remain in the output port until you perform
another output operation, or when you write another byte to the port then you overwrite the previous data. Since for input, data comes from an external device and there is

no buffer to store the input data. When the external device removes the data from the
data bus then the data will be gone.
Example
What is the mode and I/O configuration for ports A, B, and C of an 8255A after its
control register is loaded with 82Hex.
According to the bit definition
The binary pattern is 1000 0010 (82H)
D0 = 0 lower 4 bits of Port C are outputs
D1 = 1 Port B are inputs
D2 = 0 mode 0 operation for both Port B and the lower 4 bits of Port C
D3 = 0 upper 4 bits of Port C are outputs
D4 = 0 Port A are outputs
D6D5 = 00 mode 0 operation for both Port A and the upper part of Port C
D7 =1 mode enable
Mode 1
Mode 1 represents what is known as strobed I/O. In this mode, the A and B ports are
configured as two independent byte-wide I/O ports, each of which has a 4-bit
control/data port associated with it. The control/data ports are formed from the lower
and upper 4-bit of port C respectively.
Both input and output are latched ie buffers available to store the input data as well
as the output data. But in Mode 0 only has buffer for output data.
Data applied to an input port must be strobed-in with a signal produced by an external
hardware.
Handshake signal is provided for an output port to coordinate the data transfer.
Handshaking represents steps that must be completed before data (or communication)
between two devices can be exchanged or transferred.
Handshake signals in 8255 represent the available of data, or when an external device has
read these data.
The 8255 is only serving as an agent or a middle-man between an external device and the
CPU. So after receiving data from a device (input) then 8255 must inform the CPU to
read the data. Similarly, after receiving data from CPU (output), it will inform the
external device to get the data.

From I/O devices

To uPor I/O
To uP

The above diagram illustrates the application of the control bits (bits from Port C) when
the device is in Mode 1 input for PortA. The STB, IBF and INTR are used for
handshake and these bits come from PortC.
In Mode 1, the 8255 provides buffer (or store, or latch) to hold the incoming or outgoing
data. However, the buffer can only store 1-byte of data so there is a mechanism to store
the data as well as signal to inform external devices that the buffer is full!
Strobe Input (STB)
Strobed input (mode 1) causes port A and/or port B to function as latching input devices.
External data is stored in the port until the microprocessor is ready to retrieve it by
issuing a /RD signal. Referring to the above diagram, the strobe input is connected to
PC4 (Port C bit 4).
Strobed input port captures data from the port when the /STB is activated.
The /STB signal (1->0) causes data to be captured, or stored, and it activates the IBF
(Input Buffer Full) and INTR (Interrupt Request).
IBF (PC5) (a 1) indicates that data is available in port A.
Once the microprocessor notices that data are strobed into the port, it executes an IN
instruction to read the port.
The act of reading the port restores both IBF and INTR
IBF reset by the rising edge of /RD input
INTR reset by a falling edge of /RD
The operation sequence for strobe input:
1. External device put data into the port A or B
2. external device issues the strobe signal (/STB) to latch data into the port
3. 8255 issue signal IBF and INTR to the microprocessor to indicate that data is
available

4. Microprocessor read data by issuing the signal /RD

5. After data has been read, IBF and INTR are reset
6. Ready to get another input data as the buffer is empty

The INTE (interrupt enable) is the signal for enabling or disabling the issue of the INTR
(interrupt request). As shown in the above diagram, the INTR is ANDed result of IBF and
INTE. Therefore, after data is being strobed in, the IBF is active but INTR will only be
active if INTE is enabled.
The INTE is bit 4 of Port C.
Strobed Output
Handshake signals are OBF, ACK, and INTR. Now data is being sent by the CPU via
the 8255 to external devices.

Data are written to a port (A or B) by the microprocessor

/OBF (Output Buffer Full) becomes a logic 0 to indicate data are present in the port (the
signal changes from 1 to 0)
External device monitors the OBF signal to check if data is available when OBF is low
then external device read the data and by strobing (1->0) the /ACK input to the port
After receiving the /ACK signal, the 8255 returns the /OBF to logic 1 and clear the INTR
signal as well.
The INTR signal inform the host microprocessor data has been read and can send another
byte of data.

To I/O devices or uP
From I/O devices
To uP

The operation sequence for mode 1 output:

1. CPU put data into the port A or B
2. The output buffer full (/OBF) is active
3. External device monitors the /OBF signal when this is active then device read the
data
4. After reading the data, the device issues the acknowledge /ACK
5. The /ACK signal resets the INTR and the /OBF
6. By interrupt or knowing that OBF is high, the CPU can send another byte of
data to the 8255
Example
When control register is 1010XXXX then Port A is set to output
PC7 represents output buffer full (/OBF) (output)
When this is active (low) implying data are available at the port outputs. Data are written
by the microprocessor.
PC6 acknowledge (/ACK) (input)
This is input by external device after reading the data at the port
This signal also reset the /OBF with its low going edge
PC3 interrupt (output) (INTR)

Interrupt will be generated when data is read and external device acknowledge so signal
the microprocessor to send other data
INTR is reset when /ACK, /OBF, and INTE are 1
INTE interrupt enable and this signal must be set to 1 if you want to active the
interrupt request (INTR) to the CPU during the different I/O operations.
How does the CPU read data from the 8255?
Usually, we need to write a program to check for the available of data, refer to the
following example.
What is the purposes of the following very simple assembly codes?
Hints: consider what does Bit5 represent?
Read:
IN AL, PortC
AND AL, 0010 0000B
JZ Read
IN AL, PortA

; PortC represent port number occupied by Port

; C of 8255
; test if bit5 of portC is 1
; jump to READ if result of AND is zero
; IN read data from Port A

Ret
In Mode 1 input, bit 5 of Port C is the IBF for Port A. When data is available then
IBF is 1 so after the logical AND if IBF is 1 then result is not zero so can read data
from Port A. Otherwise loop back to READ to check the bit again.
Mode 2 (Will not be examined!!!!)
Mode 2 is strobed bidirectional I/O
The port can be either inputs or outputs, depends on the /WR and /RD signals.
Only Port A can be used for this mode.
Control register is written with bit pattern 11XXXXXX.
Inputs and outputs are both latched
PC3-PC7 are used for generating/accepting handshake signals
PC2-PC0 can still be used for I/O
Operation mechanism of Mode 2
Mode 2 is the combination of INPUT and OUTPUT. This is similar to Mode 1 but now
you get both INPUT and OUTPUT operations to consider.
PC7 output buffer full (output) (low = buffer full) CPU has written data to port A
PC6 acknowledge (input) (low) acknowledges that the previous data byte is received by
the destination and the next byte may be sent by the processor
PC4 strobe (input) to strobe in the data into the input latches
PC5 input buffer full (output) (high = buffer full) used as an acknowledge that the data
has been received by the receiver

PC3 interrupt (output) (active high)

PC2-0 general purpose I/O pins and controlled by the bit set and reset command
Bi-direction operation of Mode 2 (write)
First test the /OBF (output buffer full) signal to test if output buffer is empty.
Buffer is empty then sent data to output buffer (using OUT instruction).
External device monitors the /OBF signal to decide whether data is available.
If /OBF is 0 then external device sends /ACK to remove the data.
Code example
Tran:
IN
AND
JZ
mov
OUT

AL, PortC
AL, 10000000B
Tran
AL, AH
PortA, AL

; test for output buffer

Bi-direction operation of Mode 2 (read)

To read data from an external device, CPU tests IBF (Input Buffer full)
If IBF=1, data are input using the IN instruction
External device sends data using /STB
IBF is clear when microprocessor doing the IN
Write a simple program to read data from PortA
Code example
Read:
IN
AND
JZ
In

AL, PortC
AL, 00100000
Read
; loop until data is available
AL,PortA

Bit Set/Reset feature

This feature allows the individual bits of Port C to be set or reset (clear). To do this, the
D7 bit in the control register must be set to 0. The relationship between the set/reset
control word and input/output lines is illustrated in the followed figure. Only 1 bit can be
set or reset at each time. The control pattern is written to the control register not
PortC!!!!

Example
If pattern 00001111 is written to the control register
Then the logic level to be set is 1 represented by D0
The bit to be set is 111 represented by D3D2D1 (i.e 7 in this case )
So after the control word is written PC7 is set to 1
Why want to set the bits of Port C?
The INTE (Interrupt enable) is one of the signal that can be configured using the bit
set/reset feature

The above figure illustrates the different operating modes provided by the 8255.
Example
What control word must be written to the control register of the 8255A such that Port A is
configured for bi-directional operation and Port B is setup with Mode 1 output?

Write the sequence of instructions needed to load the control register of an 8255 with the
control word C4H. Assume that the 8255 resides at address 0FH of the I/O address space.
Applications of 8255A

8255

Printer
PB
D0-D7

PC4

Strobe

PC2

ACK

Connecting to a printer via an 8255 in Mode 1 via Port B (PB). PC4 is used as control to
signal the printer that data is available and PC4 should be a 0->1 transition. PC2 is used
as acknowledge when printer read the data.
Code example based on the above hardware setup
PortC equ 62H
PortB equ 61H
CMD equ 63H ; internal control register
Print:
IN AL, PortC
AND AL, 00000010 ; test if buffer is full
JZ Print
mov AL, AH
OUT PortB, AL
mov AL, 8
; send a strobe
OUT CMD, AL ; using set/reset to send a pulse
mov AL, 9
OUT CMD, AL
Another version of sending data to printer

; Port number of control register is F6H

; Port C is F2H
; Port B is
;Software that sends ASCII-coded character in BL to the printer
mov BL, AL
mov AL, 0A2H ; control word for 8255
out 0F6H, AL ; address for control word
Busy: IN AL, 0F2H
AND AL, 08H ; test the INTR
JZ
Busy
mov AL, BL
out
0F0H, AL ; send data to Port A
NOP ; the following generate a pulse using bit in PortC
Mov AL, 08H
; pull /strobe low
Out 0F6H, AL
NOP
MOV AL, 09H
; raise /strobe High
Out 0F6H, AL
HLT

8255 Parallel Input/Output (PIO)

Figure 7.17 16-bit parallel I/O system

Parallel input/output implies either 8-bit or 16-bit data can be sent or received via the I/O
ports.
The above diagram demonstrates how a system of parallel I/O can be developed using a
number of 8255. From the circuit, there are a total of 16 8255 that will give you 48 8-bit
Ports.
Similar to memory system, the 8255 are also divided into Even and Odd. Devices in the
even group will occupy even port numbers.
Each group has its own 8205 address decoder (similar to a 3-to-8 multiplexer)
One group is for odd port number, while the other group for even port number
A2A1 select the port (A, B, or C)
A5A4A3 select the 8255 device (a total of 8)
According to the drawing, the device 0 will occupy port numbers 0, 2, 4, 6 (prove this
yourself and make sure that you know how to determine port numbers for other 8255!)

Another PIO setup for an 80386 CPU

Code example
Refer to the diagram (figure 7.17) for the Parallel I/O setup, what must be the
address inputs of the even-addressed group of 8255 if Port C of PPI 14 is to be
chosen?
To enable PPI 14, the lower 8205 must be enabled for operation
And its 07 output switched to logic 0 (active low).
This requires enable
Input A0 = 0 and chip select code A5A4A3 = 111
A0 = 0 to enable 8205 (the even address)
A5A4A3 = 111 select PPI 14
Port C of PPI 14 is selected with A1A0 = 10
A2A1 = 10 access Port C
The rest of the address bits are dont care states
So the final pattern A19-A6 dont cares then 111100 = 0003C
Refer to the PPT file, or past exam papers for more examples on PIO.
Memory mapped I/O
In general memory is also one form of I/O! Is it possible to treat I/O devices as some
form of memory? The answer is YES and this is called memory mapped I/O.

Definition of memory mapped I/O - I/O devices are placed in memory address space of
the microprocessor. Therefore to access memory mapped I/O, you use MOVE instead
of IN/OUT. I/O ports are treated just like a memory location.
Some memory address space is dedicated to I/O purposes and can be accessed using
memory oriented instructions.
How many I/O space are available in an 8086????

The above illustrates the hardware setup for memory mapped I/O, can you identify the
major difference between memory mapped I/O system and an ordinary I/O system?

Standard I/O hardware setup

Check the connection of the M/IO control in both circuits.
Features of using memory mapped I/O
Memory space is reduced
Memory operation is slower
More flexible because memory oriented (move and various addressing modes)
instruction can be used
Code example
Which I/O port is selected for operation when the memory address output on the
bus is 00402 hex? (Refer to following diagram)
A10 = 1 and A0 =0 will enable the lower address decoder
A5A4A3 = 000 selects the PPI 0
A2A1 = 01 select Port B

Applications of 8255
Using an 8255 to control 8 7-segment displays
Port A is used as output to determine the pattern
Port B is used to enable the different 7-segment unit

Using an 8255 to drive a LCD display

Port A supplies command and data (8-bit)
Port B supplies the control signals (only 3 bits are used)

Exercises
1. An 8255 PPI is interfaced to a microprocessor. Port B occupies port number 94 and
Port C occupies 110. Determine the address lines of the microprocessor that are
connected to A0A1 inputs of the 8255.
2. A student has designed an I/O system based on the 8255 PPI. If the Port A occupies
port number 48 and Port B occupies port number 52. Write down the statements that
can configure the device such that Port A is for input and Port B is for output under
Mode 1.
If Port A is now connected to the 8-bit data input of a printer and the student has
written the following program using the polling method to send data to the printer as
well as generating a strobe. Determine feasible values (there could be more than one
correct answer) represented by the symbols AA, BB, CC, and DD.
Which pin is being used to generate the strobe?
; program to interface with the printer
; PORT addresses are the same as before
; Polling

Busy:
IN AL, AA ; Read from a PORT
AND AL, BB ; test a bit
JZ
Busy
; jump zero
MOV AL, BL
OUT 48, AL ; send data to Port A
NOP ; the following generate a pulse using bit in Port C
MOV AL, 08H
; pull /strobe low
OUT DD, AL
NOP
MOV AL, CC
; raise /strobe High
Out DD, AL
HLT
3. A student has designed an I/O system based on the 8255 PPI. If Port A occupies port
number 68 and Port B occupies port number 72. Determine the address lines that are
connected to the A0A1 inputs of the 8255.
Write down assembly language statements for configuring the device such that Port A is
used for input and Port B is for output both in Mode 1.
The following provides useful information related to the 8255 PIO
http://tams-www.informatik.uni-hamburg.de/applets/hades/webdemos/50-rtlib/60pio8255/pio.html

NOTE: in the above the question, you should based on the data flow direction shown in
Figure 2ca !!!