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Computer Engineering
0403202
Spring 2013-2014
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Experiment No. 1
Introduction
The aim of this experiment is to implement simple digital gates (INV, BUFFER, AND,
OR, NAND, NOR, XOR, and XNOR) on Altera's DE2 board using Verilog description
languages and Quartus II 6.1
Content
Verilog Structural Models
QuartusII 6.1
Compilation
Simulation
Programming
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5. A pop-up window will appear as shown in Figure 4. Select a folder for the
project, "DLD_BASICS".
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Figure
8.
Final
Project
Summary
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showing
Device
selection
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A
B
AB_AND
AB_OR
AB_NAND
AB_NOR
AB_XOR
AB_XNOR
A_INV
B_BUF
Figure 9. Top-level entity
TABLE 1: Verilog module signal description of Basic_Gates
Signal Name
Type
Description
A
Input
One bit
B
Input
One bit
AB_AND
Output
A and B
AB_OR
Output
A or B
AB_NAND
Output
A nand B
AB_NOR
Output
A nor B
AB_XOR
Output
A xor B
AB_XNOR
Output
A xnor B
A_INV
Output
A'
B_BUFF
Output
B
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1. Go to File New and choose Verilog on the Device Design Type as shown in
Figure 10.
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module Basic_Gates (
A,
B,
AB_AND,
AB_OR,
AB_NAND,
AB_NOR,
AB_XOR,
AB_XNOR,
A_INV,
B_BUFF
);
// List all the inputs
input A;
input B;
// List all outputs
output AB_AND;
output AB_OR;
output AB_NAND;
output AB_NOR;
output AB_XOR;
output AB_XNOR;
output A_INV;
output B_BUFF;
// Structural Module
and (AB_AND, A, B);
or (AB_OR, A, B);
nand (AB_NAND, A, B);
nor (AB_NOR, A, B);
xor (AB_XOR, A, B);
xnor (AB_XNOR, A, B);
not (A_INV, A);
buf (B_BUFF, B);
endmodule
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AB_
XOR
AB_X
NOR
A_I
NV
B_B
UFF
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5. Pin Assignments
In this section we will use only the switches and the Red Light Emitting Diodes (LEDs)
to assign the inputs and outputs of the function.
1. Go to Assignment Assignment Editor as shown in Figure 23.
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6. Save your design and recompile it. You should get 2 warnings only. Ignore these
warnings and go to next step.
Table 3: Pin Assignments
A
PIN_N25
B
PIN_N26
AB_AND
PIN_AE23
AB_OR
PIN_AF23
AB_NAND
PIN_AB21
AB_NOR
PIN_AC22
AB_XOR
PIN_AD22
AB_XNOR
PIN_AD23
A_INV
PIN_AD21
B_BUFF
PIN_AC21
Select Program/Configure
Make sure the Hardware Setup USB-Blaster[USB0] is selected.
Push the Start Button to start programming the board.
The lights on the board will indicate the chip is configured. Test the chip
with the same test as the input.
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AB_
NOR
AB_
XOR
AB_X
NOR
A_I
NV
B_B
UFF
B
0
0
1
1
0
0
1
1
Cin
0
1
0
1
0
1
0
1
Sum
0
1
1
0
1
0
0
1
Cout
0
0
0
1
0
1
1
1
Cin
Full Adder
Cout
Sum
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Appendix
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Experiment No. 2
Implementation in Verilog (Part I)
Objectives
In this lab, you have to solve the following problems during lab time as a group work and
submit your solution at the end of the lab session. For each problem, you have to write
the verilog code using Quartus software and show your output on waveforms and altera
boards.
Problems:
Problem 1: Design a 4-bit comparator ( X>Y, X=Y, X<Y)
The comparator should have two 4-bt inputs for x and y, and three outputs E, G and L.
When X= Y, E=1
When X>Y, G=1
When X< Y, L=1
Display the output of your program on:
a) Waveform
b) Digital LEDs
X
Y
Selector
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Problem 3: The following code represent a 4-bit binary counter. Simulate the below
code using Quartus Software. Download the program on the Altera board and show
the output on:
a) Waveform
b) Digital LEDs
module problem3 (count, clock);
input clock;
output reg [3:0] count;
count=0;
always@(posedge clock(
begin
count=count+1;
end
endmodule
Problem 4: You need now to display the output of the above counter on a 7-segment
display, using the following code:
module problem4 (count,hex0,clock);
input clock;
output reg [3:0] count;
output reg [6:0] hex0;
count=0;
always@(posedge clock(
begin
count=count+1;
case(count(
4'b0000:hex0=7'b1000000;
4'b0001:hex0=7'b1111001;
4'b0010:hex0=7'b0100100;
4'b0011:hex0=7'b0110000;
4'b0100:hex0=7'b0011001;
4'b0101:hex0=7'b0010010;
4'b0110:hex0=7'b0000010;
4'b0111:hex0=7'b1111000;
4'b1000:hex0=7'b0000000;
4'b1001:hex0=7'b0011000;
default: hex0=7'b1000000;
endcase
end
endmodule
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Assignment 1: Design an even counter that counts from 0, 2, 4, 6, 8 and then back to
0. Display your output on 7-Segment display
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Experiment No. 3
Introduction
The aim of this lab is to implement simple FSM (sequential circuit) on Altera's DE2
board using Verilog description languages and Quartus II 6.1
Content
Verilog Behavioral Models
QuartusII 6.1
Compilation
Simulation
Programming
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F
Counter Four
FSM
Figure 2. Top-level entity
Signal Name
x
F
Type
Input
Output
Description
One bit
One Bit
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1. Type in the Verilog module shown in Figure 4. Note that the name of the
module must be the Project Name.
2. To insert a gate from a template. Go to Edit Insert Template.
3. Save the file. Note that the file name needs to be the same as the Project
Name.
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(RST == 1'b1)
State = 3'b000;
// Reset state
else
begin
case (State)
3'b000:begin
if (x == 1'b1)
begin
State = 3'b001;
F=0;
end
else
begin
State = 3'b000;
F=0;
end
end
3'b001:begin
if (x == 1'b1)
begin
State = 3'b010;
F=0;
end
else
begin
State = 3'b000;
F=0;
end
end
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3'b010:begin
if (x == 1'b1)
begin
State = 3'b011;
F=0;
end
else
begin
State = 3'b000;
F=0;
end
end
3'b011:begin
if (x == 1'b1)
begin
State = 3'b100;
F=0;
end
else
begin
State = 3'b000;
F=0;
end
end
3'b100:begin
if (x == 1'b1)
begin
State = 3'b100;
F=1;
end
else
begin
State = 3'b000;
F=0;
end
end
default :begin
State = 3'b000;
F=0;
end
endcase
end
//end case-statement
endmodule
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5. Pin Assignments
In this section we will use only the External Clock, Switches, Push Buttons, and the
Green Light Emitting Diodes (LEDs) to assign the inputs and outputs of the function.
7. Go to Assignment Assignment Editor.
8. In the "Category:" option select "Pin"
9. Double click with your mouse button on line#1, and type in TABLE 2. For more
information, look in the Appendix (or Altera DE2 Manual) for a complete list of
Switches, LEDs, and Pushbuttons assignment.
10. Save your design and recompile it. You should get 3 warnings only. Ignore these
warnings and go to next step.
Table 2: Pin Assignments
CLOCK
PIN_P26
RST
PIN_N25
x
PIN_N26
F
PIN_AE22
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Assignment:
Q1: Design a sequential machine that counts the number of one's when input x
is equal to one and display the count number on LEDs.
Hint use only a register of four bits width.
RST
5-Bit Counter
Output:
5 Bits
Binary
Counter
Clock
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Appendix
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Experiment No. 4
Implementation in Verilog (Part 2)
Objectives:
In this lab you will practice on verilog programming.
Problems:
You have to solve the following problems using Altera DE2 board and
Quartus II 6.1 during lab
time as an individual work and submit your solution at the end of the lab
session.
For each problem, you have to write a program using verilog code and
Quartus software. Show
your outputs on waveforms and altera board.
Problem 1: Design 2*4 decoder: Using two methods: a) if-else statement
b) case statement
The following is the truth table for 2x4 Decoder:
Truth table for 2x4 Decoder
A B | D3 D2 D1 D0
---------+----------------0 0 | 0 0 0 1
0 1 | 0 0 1 0
1 0 | 0 1 0 0
1 1 | 1 0 0 0
Problem 2: Compare between three numbers and display the maximum
number of them on a 7-segment display of altera board.
Problem 3: Design a multiplexer 2*1, the inputs of the multiplex (x and y)
is a 4-bit width. If selector is one, then it will pass an output from a 3-bit
even counter. If selector is zero, then it will pass the output from a 3-bit odd
counter.
Problem 4: Design an even counter that counts from zero to 18 and then go
back to zero. Display the output on two segment displays of the altera board.
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Appendix
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Experiment No. 5
Introduction to Digital Logic Design Lab using Basic
Logic Gates
Objectives
Introduction
Components
The components mainly used in this lab are various types of digital
integrated circuits (Digital ICs or chips). These digital ICs are classified not
only by their logic operation, but also the specific logic-circuit family to
which they belong. Each logic family has its own basic electronic circuit
upon which more complex digital circuits and functions are developed. The
most frequently used logic families are TTL (Transistor-Transistor Logic)
and CMOS (Complementary metal-oxide semiconductor). TTL has a well
established popularity among Logic families and are used in this lab. CMOS
is widely used in large scale integrated circuits because of their high
component density and relatively low power consumption.
TTL ICs are usually distinguished by numerical designation 5400 and 7400
series and the power supply for TTL ICs usually is 5V. The common CMOS
type ICs are in the 4000 series and the power supply for CMOS ICs ranges
from 3V to 15V. Table below shows the standard logic levels for TTL gates
Logic Level
LOW (0)
Undefined
HIGH (1)
TTL Volts
0.0 to 0.8 V
0.8 to 2V
2.2 to 5V
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figure 1.1. You will have to read the datasheet of each IC before using it
in your circuits to know the function of each pin. The pin numbers of an
IC can be identified easily by a notch or dot. The pin on the top left side
of the notch/dot is always pin number 1 and pin on the top right side is
always the last pin as shown in fig 1.1
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Figure 1.2
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Figure 1.3
To use the breadboard, the legs of component are placed in the holes. The
holes are made so that they will hold the components in place. Each hole is
connected to one of the metal strips running underneath the board. The long
top, middle and bottom rows are usually used for power supply connections.
The circuit is built by placing components and connecting them together with
jumper wires. The ICs should be placed on the board in such a way that the
pins of the ICs are electrically isolated (no connection between pins).
The correct (and wrong) way of placing ICs on the bread board is shown in
figure 1.4.
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Figure 1.4
Logic Probes
Logic probe is a useful device to detect the logic state of an IC and provides
a quick, inexpensive way for you to locate the fault. The Logic probes can
show you immediately whether a specific point in the circuit is low, high,
open, or pulsing. These probes are usually connected directly to the power
supply of the device being tested. A logic probe has three visible indicators Red, Green and Yellow LEDs.
Red LED (HI) The voltage is a valid HIGH (logic 1)
Green LED (LO) The voltage is a valid LOW (Logic 0)
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Yellow LED (Pulse): The yellow or pulse LED comes on for approximately
200 ms to indicate a pulse without regards to its width. This feature enables
one to observe a short duration pulse that would otherwise not be seen on the
red and green LEDs. The brightness of the HIGH and LOW LEDs are an
indication of the duty cycle.
Multi-meter
Used for measuring voltage, current and resistance
Building the Circuit
The steps for wiring a circuit should be completed in the order described
below:
1. Make sure the power is off before building your circuits
2. Connect the +5V and ground (GND) leads of the trainer to the power
and ground bus strips on your breadboard (long connections on the
bread board)
3. Plug the chips you will be using into the breadboard properly. Point
all the chips in the same direction.
4. Connect +5V and GND pins of each chip to the power and ground bus
strips on the breadboard
5. Select a connection on your schematic and place a piece of hook-up
wire between corresponding pins of the chips on your breadboard. It is
better to make the short connections before the longer ones. Mark
each connection on your schematic as you go, so as not to try to make
the same connection again at a later stage.
6. Get one of your group members to check the connections, before you
turn the power on
7. If an error is made and is not spotted before you turn the power on,
turn the power off immediately before you begin to rewire the circuit.
8. At the end of the laboratory session, collect your hook-up wires,
components and all equipment and leave it in the same condition as it
was before you started.
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Figure 1.5
Inputs
A
B
0
0
1
1
Logical Output F
Expected
Experimental
0
1
0
1
Table 1.1
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Logical Level of F
Expected
0
1
2
Figure 1.6
Experimental
0
0
Table 1.2
Logical Level of F
Expected Experimental
Table 1.3
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3. Construct the simplified logic circuit, note the output F for each
combination of input and complete the output column (F2) of table 1.4
4. Compare the outputs obtained in steps 1 & 3 above and write your
comments.
Figure 1.8
A
0
0
0
0
1
1
1
1
Inputs
B
0
0
1
1
1
0
1
1
F1
F2
C Step 1 Step 3
0
1
0
1
0
1
0
1
Table 1.4
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Experiment No. 6
Introduction
Figure 4.1 shows the block diagram of a combinational logic circuit. It
consists of input variables, logic circuit (Combination of logic gates) and
output variables. The logic circuit accepts signals from the inputs and
generates signals to the outputs. The operation of a combinational logic
circuit can be specified with a truth table that lists the output values for each
combination of input variables. Also, it can be described by m Boolean
functions, one for each output variable. Each output function is expressed in
terms of n input variables.
n inputs
Combinational
Logic Circuits
m outputs
Figure 4.1
A combinational logic circuit can be implemented in many different logics
such as AND-OR, OR-AND, NAND-NAND (NAND logic), NOR-NOR
(NOR logic) etc. Since NAND and NOR gates are easier to fabricate with
electronic components and are the basic gates used in all IC digital families,
NAND or NOR logic are extensively used for implementing combinational
logic circuits. In this experiment students will learn how to design and
implement logic circuit using different logics.
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1
3
1
1
1
ICs of
ICs of
ICs of
ICs of
ICs of
Computer Engineering
Procedure
Part 1
For each of the design problem stated below:
1. Obtain the Truth Table from the problem statement.
2. Using K Map, obtain simplified Boolean expressions for each of the
output variable and draw the logic diagram using the gates specified
in the design constraints.
3. Using circuit maker simulate the circuit and verify the truth table.
Part 2
Construct the circuit for problem 3 and experimentally verify the truth table.
Problem 1
Design a combinational circuit with three inputs, A, B and C, and two
outputs, X and Y. The output X becomes 1 when the binary input,
ABC (taking A as MSB), is a multiple of 3. The output Y becomes 1
when the binary input, ABC, is a multiple of 2 and 3 both. Do not
consider 0 as a multiple of any number.
Design Constraint: 3-input AND gates and Inverters ONLY.
Problem 2
Design a 3-bit majority circuit. A majority circuit is a combinational
circuit whose output is equal to 1 if the input variable has more 1's
than 0's. The output is 0 otherwise.
Design Constraint: 2-input and 3-input NAND gates ONLY.
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Problem 3
Design a combinational circuit to count the number of 1's in a 3-bit
input. The output represents the number of 1's in binary i.e. if the
input is '101' then the output will be '10' representing two 1's in the
input.
Design Constraint: 2-input and 3-input NAND gates and 2-input
XOR gates ONLY.
Problem 4
A combinational switching network has three inputs (A, B, and C) and
two outputs X, Y. The output X is 1 if the input number is a prime
number. Y is 1 if the decimal value of its inputs is not a multiple of
three.
Note: The two input combinations 001 & 100 are forbidden.
Design constraint: 2-input NAND, Inverter, & 3-input NAND gates
ONLY.
Problem 5
Design an error detection circuit for 3-bit input. The circuit must have
two outputs X and Y. The output X becomes 1 when there are two
consecutive 1's in the binary input. Similarly, the output Y becomes 1
when there are two consecutive 0's in the binary input. In all other
cases the outputs should be 0.
Design Constraint: 2-input NOR gates ONLY.
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Experiment No. 7
Introduction
One of the primary functions any calculator or digital computer must
perform is binary addition. A combinational logic circuit that performs the
addition of two bits and produces the sum and carry is called a half adder
(fig 5.1a)
b
Figure 5.1
The circuit that performs addition of three bits (two significant bits and a
previous carry) and produces the sum and carry is called a full adder (figure
5.1b). The names of the circuit derived from the fact that a full adder can be
implemented with two half adders.
An n-bit binary adder can be constructed with n-full adders connected in
cascade, with the output carry from each full adder connected to the input
carry of the next full adder connected in chain. Such binary adders are
available in IC form. Figure 5.2 shows the block diagram of 4-bit binary
adder IC (74LS83). It can add two 4-bit numbers, say A (= A4 A3 A2 A1) and
B (= B4 B3 B2 B1) and produce sum output S (= S4 S3 S2 S1). C0 is the initial
carry input and C4 is the final carry output.
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Figure 5.3
the first operand A directly and other operand B through XOR gates. Each
XOR gates receives mode input M and one of the inputs of B. When M=0
the circuit is an adder and when M=1 it becomes subtractor as explained
below.
When M = 0, the initial carry C0 = 0, one of the input of each XOR gates is 0
and each XOR gate passes the other input to its output (because X0 = X).
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When M = 1, the initial carry C0 = 1, one of the input of each XOR gates is 1
and each XOR gate produces the complement of its other input (because
X1 = X). Thus the second input to 7483 is 1s complement of B. This 1s
complement plus C0 (1) becomes 2s complement of B. Thus circuit adds 2s
complement of B to A (i.e. subtraction by 2s complement).
C4 C3 C2 C1 1 +
First operand
A=
A4 A3 A2 A1 +
Second operand (1s complement of B) =
B4 B3 B2 B1
Sum output
S=
C4 S4 S3 S2 S1
The circuit of figure 4.3 in subtractor mode can be used as a 4-bit magnitude
comparator for checking the conditions A = B, A < B and A > B. For this
you will have to design a combinational logic circuit with C4, S4, S3, S2, S1, as
inputs and E, L and G as outputs.
Output E= 1 if A = B (When A = B, S = 0000)
Output L= 1 if A < B (When A < B, carry out put C4= 0)
Output G= 1 if A > B (When A > B, C4 = 1 and S 0000)
Decoders & Encoders:
Digital systems contain binary-coded data and information. Decoder and
encoder circuits are used in digital system for changing data from one type
of code to another. Since this is a common operation in digital systems these
circuits are available in IC forms. In this experiment we will concentrate on
BCD to 7-segment decoder and a Decimal to BCD encoder.
The 7-segment display, used for displaying decimal numbers (0 to 9)
consists of 7 segments a, b, c, d, e, f, g and seven inputs as shown in figure
5.4 (a). Each segment is a Light emitting Diode LED (figure 5.4 (b)) that
emits lights when current passes through it. There are two types of displays
1) Common anode and 2) Common Cathode. A common anode type ties all
of the + voltage sides (Anode) of the LEDs together to a common point and
this common point must be connected to +5V as shown in figure 5.4 (c). In
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(a)
(b)
(c)
Figure 5.4
Equipment & Components Required
DIGITAL TRAINER , LOGIC PROBE
2 IC of 7483 4-BIT BINARY ADDER
1 IC of 7421 4-input AND GATE
2 IC of 7404 INVERTERS
1 ICs of 7486 QUAD 2-I/P'S XOR GATE
1 IC of 74147 ENCODER
1 IC of 7447 BCD TO 7-SEGMENT DECODER/DRIVER
1 IC of 74154 4-to-16 DECODER
1 IC of 7432 2-INPUT OR GATE
2 IC of 7420 4-INPUT NAND GATE
1 Resistor pack (contains 8 resistors) of 270 ohms
1 Seven Segment display Common anode type.
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Procedure
Part 1: Parallel Adder-Subtractor:
1. Using circuit maker simulate the operation of circuit in figure 5.3 with
three different inputs of your choice (with M=0 and M=1) using ICs
7483 and 7486. Show clearly the inputs and outputs in table 5.1
2. Construct the circuit in figure 5.3 by connecting the inputs A (A1
through A4) and B (B1 through B4) to the toggle switches and the sum
output S (S1 through S4) and carry output C4 to the LEDs on the
trainer. You may connect the mode control input M to GND to set
M=0 and to Vcc to set M = 1.
3. Experimentally verify the results obtained in step 1 and write your
comments.
M=0
M=1
Inputs
Outputs
Inputs
Outputs
A4A3A2A1
B4B3 B2B1
C4 S4S3S2 S1
A4A3A2A1
B4B3 B2B1
C4 S4S3S2 S1
Table 5.1
4. Keep the connection of this circuit, dont disconnect it, you will use it
for the next part.
Part 2: Decoder:
1. Refer the datasheet of 7447, 7-segment display and construct the circuit
in Fig 5.5.
2. Experimentally verify your results and fill it in table 5.2.
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Figure 5.5
Note: Seven resistors are used to guarantee that the same current flows through all
segments that are currently on (keeping all segments at a uniform brightness).
BCD inputs
0 0 0 0
Decimal display
0 0 0 1
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
Table 5.2
3. Now, go back to the previous part, disconnect the inputs from the
switches.
4. Connect the output of the adder to the input of the decoder and display
the output result.
5. Experimentally verify the results obtained in the previous part.
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Outputs
B4 B3 B2 B1
Table 5.3
Part 5: Encoder:/
1. Simulate the operation of circuit shown in figure 5.6 using circuit maker.
2. Construct the circuit in figure 5.6 and experimentally verify the results
obtained in step 1.
Figure 5.6
3. Verify your result using the 7-segment display.
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Experiment No. 8
Introduction:
In the previous experiments, the logic circuits introduced were combinational.
The output of these circuits depends on the present combination of the inputs
and these circuits do not have any memory cells. Memory cells are very
important in digital systems and are used for temporary storage of the outputs
produced by a combinational logic circuit for use at a later time in the operation
of a digital system. Logic circuits that incorporate memory cells are called
sequential logic circuits; their output depends not only upon the present value
(state) of the input but also upon the previous values (state). Usually a
sequential logic circuit requires timing signal or clock signal for their operation.
A clock pulse is a signal that has two different voltage levels as shown in figure
6.1. It remains at the high level for a time called the pulse width (t w), and then
returns to the low level. A periodic pulse train repeats itself in a regular
manner. The time for one complete cycle in a periodic signal is called period
(T). The reciprocal of the period is the frequency (f), which is the number of
cycles per second. A second characteristic of a periodic pulse is the duty cycle.
The duty cycle is the pulse width (tw) divided by the period (T) and it is usually
given as a percentage. These definitions are shown in figure 6.1.
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The flip-flop (also called latch) is a basic bi-stable memory cell widely used
in sequential logic circuits. Usually there are two outputs, Q and its
complement Q. They are called state variables. State variables which
change only between logic 1 and logic 0 are called binary state variables.
There are various types of flip-flops such as Basic R-S Flip-flop, Clocked RS flip-flops, D-Flip-flops, J-K Flip-flop etc. Flip-flops are seem to be
everywhere in digital systems such as counters, memories, registers,
arithmetic circuits, timing and control circuits, frequency dividers etc. These
flip-flops can be implemented with logic gates. Since flip-flops are the basic
building block of a sequential circuits, they are commercially available in IC
form (D flip-flop IC 7474, J-K Flip-flop IC 7476).
Sequential Circuits
The behavior of a sequential circuit can be described by means of state
equations or state diagram or state table. It means one can build a sequential
circuit from a set of state equations or from a state table or from a state
diagram. In this experiment you will build a sequential circuit from a given
state diagram. The State diagram is a graphical representation of a sequential
circuit. In this diagram the state is represented with a circle and the transition
between states are indicated by the directed lines connecting the circles. The
binary number inside each circle identifies the state of the flip-flops. The
directed lines are labeled with two binary numbers separated by a slash. The
first one represents the input value during the present state and second one
(after the slash) represents the output during the present state with the given
input.
DIGITAL TRAINER
LOGIC PROBE
2 ICs of 7400 QUAD NAND GATE
1 IC of 7476 DUAL M/S F/F
1 IC of 7474 DUAL D F/F
1 IC of 7486 XOR GATE
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Procedure
Part 1. Flip-flop circuits using logic gates
Design the following flip-flop circuits using NAND gates. Simulate the
operation of these flip-flop circuits using circuit maker and verify their truthtables
1. Basic R-S Flip-flop
2. Clocked R-S Flip-flops
3. D-Flip-flops
Part 2: D flip-flop IC 7474
1. Refer the datasheet and study the functions of input, output and control
pins of D Flip-flop IC (74LS74).
(The 7474 IC contains two independent positive-edge-triggered flip-flops,
each has input/ output lines as shown in figure 6.2. The information on the
D input is accepted by the flip-flops on the positive going edge of the
clock pulse (indicated with an upward arrow in the function table 6.4).
The preset (PR)and Clear (CLR) are active low control inputs (bubble on
these lines indicate active low a logic 0 on the PR or CLR inputs will set
or reset the outputs regardless of the logic levels of the other inputs)
2. Connect CLK input to a pulse switch and other inputs (D, PR and CLR) to
logic switches. Connect all output to LEDs on the trainer
3. Proceed through the conditions on the truth table 6.1 and record the
results.
Inputs
Outputs
PR CLR CLK D Q
Q
L
H
X
X
H
L
X
X
L
L
X
X
H
H
H
H
H
L
H
H
L
X
Figure 6.2
Table 6.1
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Figure 6.3
Inputs
PR CL
R
L
H
H
L
L
L
H
H
H
H
H
H
H
H
CL
K
X
X
X
Outputs
K Q
Q
X
X
X
L
L
H
H
X
X
X
L
H
L
H
Table 6.2
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Figure 6.4
Present
State
A(t) B(t)
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
Output
A(t+1) B(t+1)
Flip-flop inputs
JA KA
JB KB
Table 6.3
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Experiment No. 9
Introduction
Registers:
The term register can be used in a variety of specific applications, but in all
cases it refers to a group of flip-flops. Each flip-flop is capable of storing 1
bit of information. Thus an n-bit register consists of a group of n flip-flops to
store n bits of binary information.
Different types of registers are available commercially. The simplest is one
that consists of only flip-flops without any gates. Figure 7.1 shows a simple
4-bit parallel register with D flip-flop. It is called a parallel register because
all bits of information are loaded simultaneously (in parallel) with a
common clock pulse.
Figure 7.1
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Figure 7.2
In addition to the flip-flops, a register may have combinational gates that
perform certain data processing tasks such as shift the data right or left,
parallel in parallel out, serial in parallel out etc. Since such functions are
common in digital systems, TTL ICs capable of performing these tasks are
commercially available (Example: Universal Shift Register IC 74194).
Figure 7.3 shows the block diagram of 7494 IC. This bidirectional shift
register incorporates operations such as parallel load, right-shift, left-shift,
Clear etc. These modes of operations are controlled by the selection lines S0
and S1 as shown in the function table 8.1. The parallel loading is
accomplished by applying the four bits of data and taking both mode control
inputs, S0 and S1, logic 1. The data is loaded into the associated flip-flops
and appear at the outputs after the positive transition of the clock input.
During loading, serial data flow is inhibited. Shift right is accomplished
synchronously with the rising edge of the clock pulse when S0 is at 1 and S1
is at 0. Serial data for this mode is entered at the shift-right data input. When
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S0 is 0 and S1 is 1, data shifts left and new data is entered at the shift-left
serial input. Clocking of the flip-flop is inhibited when both mode control
inputs are low.
Figure 7.3
Table 7.1
Counter
A counter is a sequential circuit which goes through a predetermined
sequence of states upon the application of input pulses. The counters may be
classified as asynchronous (ripple counter) or synchronous depending on the
way in which the clock input is applied.
In a ripple counter the clock input of flip-flops are not triggered by the
common clock pulse. The output of each flip-flop connected to the clock
input of the nest higher order flip-flop as shown in figure 7.4. Whereas in a
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DIGITAL TRAINER
LOGIC PROBE
1 IC of 74194 UNIVERSAL SHIFT REGISTERED
2 ICs of 7474 DUAL D- F/F
2 IC of 7476 J-K FLIP-FLOP
1 IC of 7493 COUNTER
1 IC of 7408 2-INPUT AND GATE
Procedure
Part 1: 4-bit Parallel in parallel out register
Using circuit maker simulate the operation of circuit in figure 7.1 by
observing the output for each condition of CLR, PR and CLK inputs
listed in table 7.2. The data input A B C D may be set to any desired
value. If no change in the output is observed you may simply write No
change in the output column
CLR
PR
CLK
0
1
1
1
1
0
1
1
X
X
L
INPUTS
A B C D
OUTPUTS
QA QB QC QD
Table 7.2
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Mode
Clear
S1
S0
0
1
1
1
1
1
1
1
0
0
1
0
0
1
1
0
0
0
1
1
1
0
0
0
Clock
Outputs
Serial
Left
1
1
1
1
1
0
1
1
Right
1
1
1
0
1
0
1
1
Parallel
A B C D
QA QB QC QD
Table 7.3
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Figure 7.4
Part 5: Ripple counter using IC 7493
1. Refer the datasheet and study the functions of input/output lines of 7493
IC.
2. Make necessary connections to clock inputs (CP0 and CP1) and reset
inputs (R1 and R2) in the block diagram of 7493 in figure 7.5 so as to
operate it as a 4-bit binary counter. Write explanations for your
connections.
3. Construct the circuit and test it by applying clock pulses and observing
the output sequences.
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Figure 7.5
Part 6: Combination between counter and universal shift register:
1. Now, keep the connection of the previous circuit and connect the output
of the counter to the inputs of the universal shift register.
2. Perform all the operations of the shift register. Make all the necessary
connections of the shift register. Put your result in table 7.4.
Inputs
Mode
Clear
S1
S0
0
1
1
1
1
1
1
1
0
0
1
0
0
1
1
0
0
0
1
1
1
0
0
0
Clock
Outputs
Serial
Left
Right
Parallel
A B C D
QA QB QC QD
Table 7.4
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Figure 7.6
2. Construct circuit and test the operation by applying clock pulses
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