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4.1
4.2
4.3
n input
combinational
.
m output
circuit
Diagram 1
Examples of Combinational circuits in the computer system are decoder, parallel adder,
and multiplexer.
(Note: Students are encouraged to obtain examples of combinational circuits stated
above)
Sequential Logic Circuit
Sequential Logic Circuit contains logic gates arranged in parallel and its output is not
only determined by the combination of the current input, but also the prior output. The
circuit also contains memory elements that enable it to store the information of the prior
output. Generally, sequential circuits can be depicted by Diagram 2 below:
n input
sequential
logic
circuit
m output
memory
elements
Diagram 2
Examples of sequential circuits in the computer system are like registers, counters and
serial adders
Decoder, etc
The circuits learnt in chapter 3 are combinational circuits. The steps to design
combinational circuits are as the following:
1. Understand the problem
2. Determine the number of input and output variables that are needed
3. Give symbols for the stated input and output
4. Construct a truth table that defines the relationship between the input and
output
5. Obtain the Boolean function or the logical expression from the truth table in
(4) using Karnaugh Map or other known methods.
6. Draw a logic circuit based on the expression obtained from (5) above.
(Note : Chapter 3.8 is an example of designing a combinational circuit Alarm
System)
Below are examples of designing combinational circuits that are in the computer system
that is the adder. Because computers use binary system for its data, its adder is based on
the addition of the binary system. There are 2 kinds of addition, which are identified to be
half addition and full addition.
Half addition is the addition of 2 bits data (doesnt involve carry) that produces 2 bits
output, that is the result and the carrier. Full addition is the addition of 3 bits data (2 bits
data and 1 bit carry) that produces 2 bits output (sum and carry). Logic circuit for half
addition is known as Half Adder while the logic circuit for full addition is known as Full
Adder
y
0
1
0
1
OUTPUT
s
c
0
0
1
0
1
0
0
1
1
1
1
s=xy+xy
=x + y
For c
x
1
c = xy
x
s = xy + xy
y
c = xy
OR
x
x + y=s
y
xy = c
A Block Diagram for HA is as below:
x
input
s
HA
output
c
INPUT
y
0
0
1
1
0
0
1
1
OUTPUT
s
co
0
0
1
0
1
0
0
1
1
0
0
1
0
1
1
1
ci
0
1
0
1
0
1
0
1
5. Obtain the expression for r and co using Karnaugh Map (Students are required
to try this out themselves):
will obtain
s = x y pi + x y ci + x y ci + x y ci
= x + y + ci
and
co = x y + y ci + x ci
6. Draw the circuit for FA (Students are required to try this out themselves):
FA
co
ci
To construct a 4-bit parallel adder, 3 FA and 1 HA are required like the diagram below
with the input as X = x3x2x1x0 and Y = y3y2y1y0 (X and Y are binary numbers 4-bit) and
the output (addition result) is r3r2r1r0.
INPUT
x3 y3
x2 y2
x1 y1
x0 y0
FA
FA
FA
HA
c2
OUTPUT
c3
s3
c1
c0
s2
s1
s0
OR
INPUT
x3 y3
x2 y2
x1 y1
x0 y0
FA
FA
FA
FA
c2
OUTPUT
c3
s3
c1
c0
s2
s1
s0
Name
Graphical Symbol
S
Feature Table
Q
Clock
S-R
Q
Clock
J-K
Clock
S
0
0
1
1
R
0
1
0
1
Qn+1
Qn
0
1
-
J
0
0
1
1
K
0
1
0
1
Qn+1
Qn
0
1
Change
condition
D
0
1
Qn+1
0
1
S-R Flip-flop
S-R flip-flop has 2 inputs, S (set) and R (reset) like Diagram 3 below. In the diagram
below, (also for JK and D flip-flops), there use another input called clock. It is to control
the movement of input that is input will only occur when given a clock pulse
(synchronous circuit)
The features of S-R flip-flop can be depicted in Table 2 below. It can be summarized
that:
1. If the value of both S and R are 0, the flip-flop will remain in its present condition
(either 0 or 1).
2. If S = 0 and R = 1 (reset), then the flip-flop condition will change to 0 (its output, Q =
0).
3. If S = 1 (set) and R = 0, then the flip-flop condition will change to 1 (output, Q = 1).
4. This circuit does not allow combinational input of input S = 1 and R = 1.
S
Q
clock
R
Diagram 3 : S-R Flip-flop
S
0
R
0
Qn
0
10
Qn+1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
1
0
0
1
1
-
J-K Flip-flop
J-K flip-flop also has 2 inputs, J and K. The function of clock is same as S-R flip-flop.
Unlike S-R flip-flop, J-K flip-flop allows all combination of inputs. The logic circuit for
J-K flip-flop is shown in Diagram 4 below. Table 3 shows the features of J-K flip-flop.
From the table, it can be summarized that:
1. If J = 0 and K = 0, it will maintain the flip-flop condition like before
2. If J = 0 and K = 1, it will cause flip-flop to change to condition 0 (reset).
3. If J = 1 and K = 0, it will cause flip-flop to change to condition 1 (set).
4. If J = 1 and K = 1, it will change the flip-flop condition, that is it will become
complementary to the initial or prior condition
It can be observed that J-K flip-flop is built to address the input problem of S = R = 1 in
S-R flip-flop. Features 1 till 3 are same as S-R flip-flop.
J
Q
Clock
11
K
0
0
1
1
0
0
1
1
Qn
0
1
0
1
0
1
0
1
Qn+1
0
1
0
0
1
1
1
0
Q
clock
12
Diagram 5 : D Flip-flop
D
0
0
1
1
Qn
0
1
0
1
Qn+1
0
0
1
1
13
I1
I2
I3
Clock
I4
Clock
Clock
Clock
Clock
Pulse
Q1
Q2
Q3
14
Q4
In the above diagram, 4 bits of input is admitted simultaneously, that is I 1, I2, I3 and I4,
whereas its output is also is simultaneous or parallel, that is Q1, Q2, Q3 and Q4.
In shift register, only one output is produced at a time. There are 2 types of shift register
that is shift to right and shift to left. Shift to right register means the rightmost bit of the
stated will be taken out first followed by the following bits after a given clock beat. Its
vice versa for move to shift to left register. Diagram 7 below is an example of 4-bit shift
to right register that utilizes J-K flip-flop.
Input
Clock
Clock
Clock
Clock
Output
Clock
Pulse
Diagram 7: Shift to Right Register Using J-K Flip-flop
Parallel Adder
In the computer environment, there are 2 types of adders:
1. Parallel Adder
2. Serial Adder
Parallel adder is an adder that performs addition concurrently for each bit involved.
Adder in section 4.2 is called a serial adder. Serial Adder performs addition bit by bit
starting with the rightmost bit, followed by the following bits. Diagram 8 below is an
example of a serial 4-bit adder. This adder uses two Shift to Right Registers, X and Y to
hold operand 1 (A = A3A2AIA0) and operand 2 (B = B3B2B1B0), a full adder (see section
4.2) and a flip-flop (usually D flip-flop) to hold the carrier value.
15
A
33
B3
X Register
A2 A1 A0
B2 B1 B0
Y Register
Ai
Bi
Ci
Si
Full
Adder
Ci+1
D flipflop
Carry
Clock
Pulse
16