Ex No 1

Study of PIC Development Board

Peripheral Interface Controller(16f877A) :

High-Performance RISC CPU

Only 35 single-word instructions to learn

All single-cycle instructions except for program
branches, which are two-cycle
Operating speed: DC 20 MHz clock input
DC 200 ns instruction cycle
Up to 8K x 14 words of Flash Program Memory,
Up to 368 x 8 bytes of Data Memory (RAM),
Up to 256 x 8 bytes of EEPROM Data Memory
Pinout compatible to other 28-pin or 40/44-pin
PIC16CXXX and PIC16FXXX microcontrollers.

Peripheral Features
Timer0: 8-bit timer/counter with 8-bit prescaler
Timer1: 16-bit timer/counter with prescaler,can be incremented during
Sleep via external crystal/clock
Timer2: 8-bit timer/counter with 8-bit period register, prescaler and
postscaler
Two Capture, Compare, PWM modules
Capture is 16-bit, max. resolution is 12.5 ns
Compare is 16-bit, max. resolution is 200 ns
PWM max. resolution is 10-bit
Synchronous Serial Port (SSP) with SPI (Master mode) and I2C
(Master/Slave)
Universal Synchronous Asynchronous Receiver Transmitter (USART/SCI)
with 9-bit address detection
Parallel Slave Port (PSP) 8 bits wide withexternal RD, WR and CS
controls (40/44-pin only)
Brown-out detection circuitry for Brown-out Reset (BOR)
Analog Features :
10-bit, up to 8-channel Analog-to-Digital Converter (A/D)
Brown-out Reset (BOR)
Analog Comparator module with:Two analog comparators
Programmable on-chip voltage reference (VREF) module
Programmable input multiplexing from device inputs and internal voltage
reference
Comparator outputs are externally accessible.

Special Microcontroller Features:

100,000 erase/write cycle Enhanced Flash program memory typical

1,000,000 erase/write cycle Data EEPROM memory typical
Data EEPROM Retention > 40 years
Self-reprogrammable under software control
In-Circuit Serial Programming (ICSP) via two pins
Single-supply 5V In-Circuit Serial Programming
Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable
operation
Programmable code protection
Power saving Sleep mode
Selectable oscillator options
In-Circuit Debug (ICD) via two pins

Fig.PIC 16f877 A

Architecture of PIC16F877
PIC microcontrollers are based on advanced RISC architecture.RISC stands for Reduced
Instruction Set Computing. In this architecture, the instruction set of hardware gets reduced which
increases the execution rate (speed) of system. PIC microcontrollers follow Harvard architecture for

internal data transfer. In Harvard architecture there are two separate memories for program and data.
These two memories are accessed through different buses for data communication between memories
and CPU core. This architecture improves the speed of system over Von Neumann architecture in
which program and data are fetched from the same memory using the same bus. PIC16 series
controllers are 8-bit instruction set. PIC18 series controllers are based on 16-bit instruction set.In
addition, the PIC family is based on a Reduced Instruction Set Computer (RISC) configuration which
it use fewer instructions than a Complex Instruction Set Computer (CISC). All the PIC devices use
less than 60 instructions.In general, the PIC16XXX devices have only 35 instructions, whereas the
PIC17XXX devices have only 58 instructions. There is a substantial amount of program code
compatibility amongst 9 different devices in the PIC family. A program written for one PIC device
can easily be assembled and used in another device type with a minimum number of modifications.
The PIC family is fully static devices, meaning that they preserve the contents of their
registers when the clock frequency is reduced to zero. In PIC microcontrollers, each instruction takes
four clock periods to execute. If a 1MHz clock frequency is used, the corresponding clock period is
1sec, so each instruction will take 4secthis time is called the instruction cycle time.The fastest
devices in the PIC family can operate at clock frequencies up to 33MHz, with corresponding
instruction cycle times of 121nsec. Most instructions execute in one instruction cycle, but some
require two cycles because they need to branch to some destination other than the next address in the
PC.Microchip characterizes PIC microcontrollers according to their instruction word lengths.
The low-end PICs, such as the eight pin 12C5XX series, have 12 bit word length
instructions. The midrange PICs, such as the PIC16XXX, have 14 bit instructions and the high-end
17XXX PICs have 16 bit instructions. All PIC microcontrollers are, however, classified as eight bit
microcontrollers as they all manipulate data in byte units on an eight bit wide data bus.A detailed
knowledge or understanding of these concepts is not essential to actually use PIC microcontrollers;
all that is needed is practice in writing programs and some experimentation with microcontroller
circuits to gain experience.

The question may arise that if PIC18 are called 8-bit microcontrollers, then what about them being
based on 16-bit instructions set. PIC18 is an 8-bit microcontroller this statement means that the
CPU core can receive/transmit or process a maximum of 8-bit data at a time. On the other hand the
statement PIC18 microcontrollers are based on 16-bit instruction set means that the assembly
instruction sets are of 16-bit.

The data memory is interfaced with 8-bit bus and program memory is interfaced with 16-bit bus as
depicted in the following figure.

The high performance of the PICmicro devices can be attributed to a number of architectural
features commonly found in RISC microprocessors. These include:

Harvard architecture

Long Word Instructions

Single Word Instructions

Single Cycle Instructions

Instruction Pipelining

Reduced Instruction Set

Register File Architecture

Orthogonal (Symmetric) Instructions

Harvard Architecture

Harvard architecture has the program memory and data memory as separate memories and is
accessed from separate buses.

This improves bandwidth over traditional von Neumann architecture in which program and data are
fetched from the same memory using the same bus. To execute an instruction, a von Neumann
machine must make one or more (generally more) accesses across the 8-bit bus to fetch the
instruction.

Then data may need to be fetched, operated on, and possibly written. As can be seen from this
description, that bus can be extremely contested. While with a Harvard architecture, the instruction is
fetched in a single instruction cycle (all 14-bits).

While the program memory is being accessed, the data memory is on an independent bus and can be
read and written. These separated buses allow one instruction to execute while the next instruction is
fetched.

Long Word Instructions

Long word instructions have a wider (more bits) instruction bus than the 8-bit Data Memory Bus.

This is possible because the two buses are separate. This further allows instructions to be sized
differently than the 8-bit wide data word which allows a more efficient use of the program memory,
since the program memory width is optimized to the architectural requirements.

Single Word Instructions

Single Word instruction opcodes are 14-bits wide making it possible to have all single word
instructions. A 14-bit wide program memory access bus fetches a 14-bit instruction in a single cycle.
With single word instructions, the number of words of program memory locations equals the number
of instructions for the device. This means that all locations are valid instructions.

Typically in the von Neumann architecture, most instructions are multi-byte. In general, a device
with 4-KBytes of program memory would allow approximately 2K of instructions. This 2:1 ratio is
generalized and dependent on the application code.

Instruction Pipeline

The instruction pipeline is a two-stage pipeline which overlaps the fetch and execution of
instructions.

The fetch of the instruction takes one TCY, while the execution takes another TCY. However, due to
the overlap of the fetch of current instruction and execution of previous instruction, an instruction is
fetched and another instruction is executed every single TCY.

Single Cycle Instructions

With the Program Memory bus being 14-bits wide, the entire instruction is fetched in a single
machine cycle (TCY). The instruction contains all the information required and is executed in a
single cycle.

There may be a one cycle delay in execution if the result of the instruction modified the contents of
the Program Counter. This requires the pipeline to be flushed and a new instruction to be fetched.

Reduced Instruction Set

When an instruction set is well designed and highly orthogonal (symmetric), fewer instructions are
required to perform all needed tasks. With fewer instructions, the whole set can be more rapidly
learned.

Register File Architecture

The register files/data memory can be directly or indirectly addressed. All special function registers,
including the program counter, are mapped in the data memory.

Orthogonal (Symmetric) Instructions

Orthogonal instructions make it possible to carry out any operation on any register using any
addressing mode. This symmetrical nature and lack of special instructions make programming
simple yet efficient. In addition, the learning curve is reduced significantly.

The mid-range instruction set uses only two non-register oriented instructions, which are used for
two of the cores features.

One is the SLEEP instruction which places the device into the lowest power use mode. The other is
the CLRWDT instruction which verifies the chip is operating properly by preventing the on-chip
Watchdog Timer (WDT) from overflowing and resetting the device.

Instruction Flow/Pipelining

An Instruction Cycle consists of four Q cycles (Q1, Q2, Q3, and Q4). Fetch takes one instruction
cycle while decode and execute takes another instruction cycle. However, due to Pipelining, each
instruction effectively executes in one cycle. If an instruction causes the program counter to change
(e.g. GOTO) then an extra cycle is required to complete the instruction.

The instruction fetch begins with the program counter incrementing in Q1.

In the execution cycle, the fetched instruction is latched into the Instruction Register (IR) in cycle
Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles. Data memory is
read during Q2 (operand read) and written during Q4 (destination writes).

The above process occurs in a single machine cycle. In PIC microcontroller, a single machine cycle
consists of 4 oscillation periods. Thus an instruction needs 4 clock periods to be executed. This
makes it faster than other 8051 microcontrollers.

Early processors and controllers could fetch or execute a single instruction in a unit of time. The PIC
microcontrollers are able to fetch and execute the instructions in the same unit of time thus increasing
their instruction throughput.

This technique is known as instruction pipelining where the processing of instructions is split into a
number of independent steps.

MEMORY ORGANIZATION OF PIC16F877

There are two memory blocks in the Memory Organization; program memory and data memory.
Each block has its own bus, so that access to each block can occur during the same oscillator cycle.
The data memory can further be broken down into General Purpose RAM and the Special Function
Registers (SFRs).

The operations of the SFRs that control the core are described here. The SFRs used to control the
peripheral modules are described in the section discussing each individual peripheral module.

The memory of a PIC 16F877 chip is divided into 3 sections. They are,

Program memory

Data memory and

Data EEPROM

Program memory

Program memory contains the programs that are written by the user. The program counter (PC)
executes these stored commands one by one. Usually PIC16F877 devices have a 13 bit wide program
counter that is capable of addressing 8K14 bit program memory space. This memory is primarily
used for storing the programs that are written (burned) to be used by the PIC.

These devices also have 8K*14 bits of flash memory that can be electrically erasable /reprogrammed.
Each time we write a new program to the controller, we must delete the old one at that time. The
figure below shows the program memory map and stack.

Reset Vector

On any device, a reset forces the Program Counter (PC) to address 0h. We call this address the Reset
Vector Address since this is the address that program execution will branch to when a device reset
occurs. Any reset will also clear the contents of the PCLATH register. This means that any branch at
the Reset Vector Address (0h) will jump to that location in PAGE0 of the program memory.

Interrupt Vector

When an interrupt is acknowledged the PC is forced to address 0004h. We call this the Interrupt
Vector Address.

When the PC is forced to the interrupt vector, the PCLATH register is not modified. Once in the
service interrupt routine (ISR), this means that before any write to the PC, the PCLATH register
should be written with the value that will specify the desired location in program memory. Before the
PCLATH register is modified by the Interrupt Service Routine (ISR) the contents of the PCLATH
may need to be saved, so it can be restored before returning from the ISR.

Calibration Information

Some devices have calibration information stored in their program memory. This information is
programmed by Microchip when the device is under final test. The use of these values allows the
application to achieve better results. The calibration information is typically at the end of program
memory, and is implemented as a RETLW instruction with the literal value being the specified
calibration information.

Program Counter (PC)

The program counter (PC) specifies the address of the instruction to fetch for execution. The PC is
13-bits wide. The low byte is called the PCL register. This register is readable and writable. The high
byte is called the PCH register. This register contains the PC<12:8> bits and is not directly readable
or writable. All updates to the PCH register go through the PCLATH register.

Stack

The stack allows a combination of up to 8 program calls and interrupts to occur. The stack contains
the return address from this branch in program execution. Mid-Range MCU devices have an 8-level
deep x 13-bit wide hardware stack. The stack space is not part of either program or data space and
the stack pointer are not readable or writable. The PC is pushed onto the stack when a CALL
instruction is executed or an interrupt causes a branch.

The stack is popped in the event of a RETURN, RETLW or a RETFIE instruction execution.
PCLATH is not modified when the stack is Pushed or Popped.

After the stack has been pushed eight times, the ninth push overwrites the value that was stored from
the first push. The tenth push overwrites the second push.

Note 1:

There are no status bits to indicate stack overflow or stack underflow conditions. There are no
instructions/mnemonics called PUSH or POP. These are actions that occur from the execution of the
CALL, RETURN, RETLW, and RETFIE instructions, or the vectoring to an interrupt address.

Program Memory Paging

Some devices have program memory sizes greater then 2K words, but the CALL and GOTO
instructions only have a 11-bit address range. This 11-bit address range allows a branch within a 2K
program memory page size.

To allow CALL and GOTO instructions to address the entire 1K program memory address range,
there must be other two bits to specify the program memory page. These paging bits come from the
PCLATH<4:3> bits. When doing a CALL or GOTO instruction, the user must ensure that page bits
(PCLATH<4:3>) are programmed so that the desired program memory page is addressed. When one
of the return instructions is executed, the entire 13-bit PC is popped from the stack. Therefore,
manipulation of the PCLATH<4:3> is not required for the return instructions.

Data Memory Organization

The data memory of PIC16F877 is separated into multiple banks which contain the general purpose
registers (GPR) and special function registers (SPR). According to the type of the microcontroller,
these banks may vary. The PIC16F877 chip only has four banks (BANK 0, BANK 1, BANK 2, and
BANK4). Each bank holds 128 bytes of addressable memory.

Data memory is made up of the Special Function Registers (SFR) area, and the General Purpose
Registers (GPR) area. The SFRs control the operation of the device, while GPRs are the general area
for data storage and scratch pad operations.

The data memory is banked for both the GPR and SFR areas. The GPR area is banked to allow
greater than 96 bytes of general purpose RAM to be addressed. SFRs are for the registers that control
the peripheral and core functions. Banking requires the use of control bits for bank selection.

These control bits are located in the STATUS Register (STATUS<7:5>). To move values from one
register to another register, the value must pass through the W register. This means that for all
register-to-register moves, two instruction cycles are required. The entire data memory can be
accessed either directly or indirectly. Direct addressing may require the use of the RP1:RP0 bits.
Indirect addressing requires the use of the File Select Register (FSR).

Indirect addressing uses the Indirect Register Pointer (IRP) bit of the STATUS register for accesses
into the Bank0 / Bank1 or the Bank2 / Bank3 areas of data memory.

General Purpose Registers (GPR)

Some Mid-Range MCU devices have banked memory in the GPR area. GPRs are not initialized by a
Power-on Reset and are unchanged on all other resets. The register file can be accessed either
directly, or using the File Select Register FSR, indirectly. Some devices have areas that are shared
across the data memory banks, so a read / write to that area will appear as the same location (value)
regardless of the current bank.

Special Function Registers (SFR)

The SFRs are used by the CPU and Peripheral Modules for controlling the desired operation of the
device. These registers are implemented as static RAM.

The SFRs can be classified into two sets, those associated with the core function and those related
to the peripheral functions. All Mid-Range MCU devices have banked memory in the SFR area.
Switching between these banks requires the RP0 and RP1 bits in the STATUS register to be
configured for the desired bank. Some SFRs are initialized by a Power-on Reset and other resets,
while other SFRs are unaffected. The register file can be accessed either directly, or using the File
Select Register FSR, indirectly.

Note: The Special Function Register (SFR) Area may have General Purpose Registers (GPRs)
mapped in these locations.

Banking

The data memory is partitioned into four banks. Each bank contains General Purpose Registers and
Special Function Registers.

Switching between these banks requires the RP0 and RP1 bits in the STATUS register to be
configured for the desired bank when using direct addressing. The IRP bit in the STATUS register is
used for indirect addressing.

Each Bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the
Special Function Registers. Above the Special Function Registers are General Purpose Registers.

All data memory is implemented as static RAM. All Banks may contain special function registers.
Some high use special function registers from Bank0 are mirrored in the other banks for code
reduction and quicker access.

STATUS Register

The STATUS register contains the arithmetic status of the ALU, the RESET status and the bank
select bits for data memory. The STATUS register can be the destination for any instruction, as with
any other register.

If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the
write to these three bits is disabled. These bits are set or cleared according to the device logic.
Furthermore, the TO and PD bits are not writable, therefore, the result of an instruction with the
STATUS register as destination may be different than intended.

OPTION_REG Register

The OPTION_REG Register is a readable and writable register, which contains various control bits
to configure the TMR0 pre-scaler/WDT post-scaler, the External INT Interrupt, TMR0 and the weak
pull-ups on PORTB.

INTCON Register

The INTCON Register is a readable and writable register, which contains various enable and flag bits
for the TMR0 register overflow, RB Port change and External RB0/INT pin interrupts.

Note:

Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its
corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure
the appropriate interrupt flag bits are clear prior to enabling an interrupt.

PIE1 Register

The PIE1 register contains the individual enable bits for the peripheral interrupts.

PIR1 Register

The PIR1 register contains the individual flag bits for the peripheral interrupts.

Note:

Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its
corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure
the appropriate interrupt bits are clear prior to enabling an interrupt.

PIE2 Register

The PIE2 register contains the individual enable bits for the CCP2 peripheral interrupt, the SSP bus
collision interrupt, and the EEPROM write operation interrupt.

PIR2 Register

The PIR2 register contains the flag bits for the CCP2 interrupt, the SSP bus collision interrupt and the
EEPROM write operation interrupt.

Note:

Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its
corresponding enable bit or the global enable bit, GIE (INTCON<7>).

User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.

PCON Register

The Power Control (PCON) Register contains flag bits to allow differentiation between a Power-on
Reset (POR), a Brown-out Reset (BOR), a Watchdog Reset (WDT), and an external MCLR Reset.

Note

BOR is unknown on POR. It must be set by the user and checked on subsequent RESETS to see if
BOR is clear, indicating a brown-out has occurred. The BOR status bit is a dont care and is not
predictable if the brown-out circuit is disabled (by clearing the BODEN bit in the configuration
word).

Indirect Addressing, INDF, and FSR Registers

Indirect addressing is a mode of addressing data memory where the data memory address in the
instruction is not fixed. An SFR register is used as a pointer to the data memory location that is to be
read or written.

Since this pointer is in RAM, the contents can be modified by the program. This can be useful for
data tables in the data memory. Indirect addressing is possible by using the INDF register. Any

instruction using the INDF register actually accesses the register pointed to by the File Select
Register, FSR.

Reading the INDF register itself indirectly (FSR = '0') will read 00h. Writing to the INDF register
indirectly results in a no-operation (although status bits may be affected). An effective 9-bit address
is generated by the concatenation of the IRP bit (STATUS<7>) with the 8-bit FSR register.

Data EEPROM and FLASH Memory

The data EEPROM and Flash program memory is readable and writable during normal operation
(over the full VDD range). This memory is not directly mapped in the register file space. Instead, it is
indirectly addressed through the Special Function Registers.

The EEPROM data memory allows single-byte read and writes. The Flash program memory allows
single-word reads and four-word block writes. Program memory write operations automatically
perform an erase-before write on blocks of four words. A byte write in data EEPROM memory
automatically erases the location and writes the new data (erase-before-write). The write time is
controlled by an on-chip timer. The write/erase voltages are generated by an on-chip charge pump,
rated to operate over the voltage range of the device for byte or word operations.

The EEPROM Data memory is rated for high erase/ writes cycles. The FLASH program memory is
rated much lower, because EEPROM data memory can be used to store frequently updated values.
An on-chip timer controls the right time and it will vary with voltage and temperature, as well as
from chip to chip.

A byte or word write automatically erases the location and writes the new value. Writing to
EEPROM data memory does not impact the operation of the device.

Writing to program memory will cease the execution of instructions until the write is complete. The
program memory cannot be accessed during the write. During the write operation, the oscillator
continues to run, the peripherals continue to function and interrupt events will be detected and
essentially queued until the write is complete. When the write completes, the next instruction in the
pipeline is executed and the branch to the interrupt vector will take place, if the interrupt is enabled
and occurred during the write.

Read and write access to both memories take place indirectly through a set of Special Function
Registers (SFR). The six SFRs used are:

EEDATA

EEDATH
EEADR

EEADRH
EECON1

EECON2

The EEPROM data memory allows byte read and writes operations without interfering with the
normal operation of the microcontroller.

When interfacing to EEPROM data memory, the EEADR register holds the address to be accessed.
Depending on the operation, the EEDATA register holds the data to be written, or the data read, at the
address in EEADR.

The PIC16F873/874 devices have 128 bytes of EEPROM data memory and therefore, require that the
MSB of EEADR remain clear. The EEPROM data memory on these devices does not wrap around to
0, i.e., 0x80 in the EEADR does not map to 0x00. The PIC16F876/877 device has 256 bytes of
EEPROM data memory and therefore, uses all 8-bits of the EEADR.

The FLASH program memories allows non-intrusive read access, but write operations cause the
device to stop executing instructions, until the write completes.

When interfacing to the program memory, the EEADRH: EEADR registers form a two-byte word,
which holds the 13-bit address of the memory location being accessed. The register combination of
EEDATH: EEDATA holds the 14-bit data for writes, or reflects the value of program memory after a
read operation.

Just as in EEPROM data memory accesses, the value of the EEADRH: EEADR registers must be
within the valid range of program memory, depending on the device: 0000h to 1FFFh for the
PIC16F873/874, or 0000h to 3FFFh for the PIC16F876/877. Addresses outside of this range do not
wrap around to 0000h.

EECON1 and EECON2 Registers

The EECON1 register is the control register for configuring and initiating the access. The EECON2
register is not a physically implemented register, but is used exclusively in the memory write
sequence to prevent inadvertent writes.

There are many bits used to control the read and write operations to EEPROM data and FLASH
program memory. The EEPGD bit determines if the access will be a program or data memory access.
When clear, any subsequent operations will work on the EEPROM data memory. When set, all
subsequent operations will operate in the program memory.

Read operations only use one additional bit, RD, which initiates the read operation from the desired
memory location. Once this bit is set, the value of the desired memory location will be available in
the data registers.

This bit cannot be cleared by firmware. It is automatically cleared at the end of the read operation.
For EEPROM data memory reads, the data will be available in the EEDATA register in the very next
instruction cycle after the RD bit is set. For program memory reads, the data will be loaded into the
EEDATH: EEDATA registers; following the second instruction after the RD bit is set.

Write operations have two control bits, WR and WREN, and two status bits, WRERR and EEIF. The
WREN bit is used to enable or disable the write operation. When WREN is clear, the write operation
will be disabled.

Therefore, the WREN bit must be set before executing a write operation. The WR bit is used to
initiate the write operation. It also is automatically cleared at the end of the write operation. The
interrupt flag EEIF is used to determine when the memory write completes. This flag must be cleared
in software before setting the WR bit.

For EEPROM data memory, once the WREN bit and the WR bit have been set, the desired memory
address in EEADR will be erased, followed by a write of the data in EEDATA. This operation takes
place in parallel with the microcontroller continuing to execute normally.

When the write is complete, the EEIF flag bit will be set. For program memory, once the WREN bit
and the WR bit have been set, the microcontroller will cease to execute instructions.

The desired memory location pointed to by EEADRH: EEADR will be erased. Then, the data value
in EEDATH: EEDATA will be programmed. When complete, the EEIF flag bit will be set and the
microcontroller will continue to execute code.

The WRERR bit is used to indicate when the PIC16F87X device has been reset during a write
operation. WRERR should be cleared after Power-on Reset. Thereafter, it should be checked on any
other RESET.

The WRERR bit is set when a write operation is interrupted by a MCLR Reset, or a WDT Time-out
Reset, during normal operation. In these situations, following a RESET, the user should check the
WRERR bit and rewrite the memory location, if set.

The contents of the data registers, address registers and EEPGD bit are not affected by either MCLR
Reset, or WDT Timeout Reset, during normal operation.

Reading the EEPROM Data Memory

Reading EEPROM data memory only requires that the desired address to access be written to the
EEADR register and clear the EEPGD bit. After the RD bit is set, data will be available in the
EEDATA register on the very next instruction cycle.

EEDATA will hold this value until another read operation is initiated or until it is written by
firmware.

The steps to reading the EEPROM data memory are:

Write the address to EEDATA. Make sure that the address is not larger than the memory size of the PIC16F87X device.

Clear the EEPGD bit to point to EEPROM data memory.

Set the RD bit to start the read operation.

Read the data from the EEDATA register.

Writing to the EEPROM Data Memory

There are many steps in writing to the EEPROM data memory. Both address and data values must be
written to the SFRs. The EEPGD bit must be cleared, and the WREN bit must be set, to enable
writes. The WREN bit should be kept clear at all times, except when writing to the EEPROM data.

The WR bit can only be set if the WREN bit was set in a previous operation, i.e., they both cannot be
set in the same operation. The WREN bit should then be cleared by firmware after the write. Clearing
the WREN bit before the write actually completes will not terminate the write in progress.

Writes to EEPROM data memory must also be prefaced with a special sequence of instructions that
prevent inadvertent write operations. This is a sequence of five instructions that must be executed
without interruptions.

The firmware should verify that a write is not in progress, before starting another cycle.

The steps to write to EEPROM data memory are:

If step 10 is not implemented, check the WR bit to see if a write is in progress.

Write the address to EEADR. Make sure that the address is not larger than the memory size of the PIC16F87X device.

Write the 8-bit data value to be programmed in the EEDATA register.

Clear the EEPGD bit to point to EEPROM data memory.

Set the WREN bit to enable program operations.

Disable interrupts (if enabled).

Execute
the
Write
55h
to
EECON2
Write
AA
to
EECON2
- Set the WR bit
Enable interrupts (if using interrupts).

special
in
two
in
two

five
instruction
steps
(first
to
W,then
steps
(first
to
W,
then

to
to

sequence:
EECON2)
EECON2)

Clear the WREN bit to disable program operations.

At the completion of the write cycle, the WR bit is cleared and the EEIF interrupt flag bit is set.

Reading the FLASH Program Memory

Reading FLASH program memory is much like that of EEPROM data memory, only two NOP
instructions must be inserted after the RD bit is set.

These two instruction cycles that the NOP instructions execute, will be used by the microcontroller to
read the data out of program memory and insert the value into the EEDATH: EEDATA registers.
Data will be available following the second NOP instruction. EEDATH and EEDATA will hold their
value until another read operation is initiated, or until they are written by firmware.

The steps to reading the FLASH program memory are:

Write the address to EEADRH: EEADR. Make sure that the address is not larger than the memory size of the PIC16F87X
device.

Set the EEPGD bit to point to FLASH program memory.

Set the RD bit to start the read operation.

Execute two NOP instructions to allow the microcontroller to read out of program memory.
Read the data from the EEDATH: EEDATA registers.

Writing to the FLASH Program Memory

Writing to FLASH program memory is unique, in that the microcontroller does not execute
instructions while programming is taking place. The oscillator continues to run and all peripherals
continue to operate and queue interrupts, if enabled. Once the write operation completes, the
processor begins executing code from where it left off. Just like EEPROM data memory, there are
many steps in writing to the FLASH program memory.

Both address and data values must be written to the SFRs. The EEPGD bit must be set, and the
WREN bit must be set to enable writes. The WREN bit should be kept clear at all times, except when
writing to the FLASH Program memory. The WR bit can only be set if the WREN bit was set in a
previous operation, i.e., they both cannot be set in the same operation. The WREN bit should then be
cleared by firmware after the write. Clearing the WREN bit before the write actually completes will
not terminate the write in progress.

Writes to program memory must also be prefaced with a special sequence of instructions that prevent
inadvertent write operations. This is a sequence of five instructions that must be executed without
interruption for each byte written. These instructions must then be followed by two NOP instructions
to allow the microcontroller to setup for the write operation. Once the write is complete, the
execution of instructions starts with the instruction after the second NOP.

The steps to write to program memory are:

Write the address to EEADRH: EEADR. Make sure that the address is not larger than the memory size of the PIC16F87X
device.

Write the 14-bit data value to be programmed in the EEDATH: EEDATA registers.
Set the EEPGD bit to point to FLASH memory.

Set the WREN bit to enable program operations.

Disable interrupts (if enabled).

Execute
the
special
five
instruction
Write
55h
to
EECON2
in
two
steps
(first
to
W,
then
Write
AA
to
EECON2
in
two
steps
(first
to
W,
then
- Set the WR bit
Execute two NOP instructions to allow the microcontroller to setup for write operation.
Enable interrupts (if using interrupts).
Clear the WREN bit to disable program operations.

to
to

sequence:
EECON2)
EECON2)

I/O Registers

These registers are used for the I/O control. Every I/O port in the PIC microcontroller has two
registers: port data register and port direction control register.

Port data register has the same name as the port it controls. For example, the PIC16F877A
microcontroller has five port data registers, PORTA, PORTB, PORTC, PORTD and PORTE. Eight
bits of data can be sent to any port, or 8 bits of data can be read from the ports. It is also possible to
read or write to individual port pins. For example, any bit of a given port can be set or cleared, or
data can be read from one or more port pins at the same time.

Ports in a PIC microcontroller are bidirectional. Thus, each pin of a port can be used as an input or an
output pin. Port direction control register configures the port pins as either inputs or outputs. This
register is called the TRIS register and every port has a TRIS register named after its port name.

For example, TRISA is the direction control register for PORTA. Similarly, TRISB is the direction
control register for PORTB and so on.

Setting a bit in the TRIS register makes the corresponding port register pin as input. Clearing a bit in
the TRIS register makes the corresponding port pin an output. For example, to make bits 0 and 1 of
PORTB input and the other bits output; we have to load the TRISB register with the bit pattern.

00000011

Timer Registers

Depending on the model used, some PIC microcontrollers have only one timer, and some may have
up to three timers. In this section we shall look at the PIC16F84 microcontroller, which has only one
timer. The extension to several timers is similar and we shall see in the projects section how to use
more than one timer.

The timer in the PIC16F84 microcontroller is an 8-bit register (called TMR0), which can be used as a
timer or a counter. When used as a counter, the register increments each time a clock pulse is applied
to pin T0CK1 of the microcontroller.

When used as a timer, the register increments at a rate determined by the system clock frequency and
a pre-scaler selected by register OPTION_REG. Prescaler rates vary from 1:2 to 1:256. For example,
when using a 4-MHz clock, the basic instruction cycle is 1 _s (the clock is internally divided by
four). If we select a pre-scaler rate of 1:16, the counter will be incremented at every 16 _s. The
TMR0 register has address 01 in the RAM.

A timer interrupt is generated when the timer overflows from 255 to 0. This interrupt can be enabled
or disabled by our program. Thus, for example, if we need to generate interrupts at intervals of 200
_s using a 4-MHz clock, we can select a pre-scaler value of 1:4 and enable timer interrupts.

The timer clock rate is then 4 _s. For a time-out of 200 _s, we have to send 50 clocks to the timer.
Thus, the TMR0 register should be loaded with 256 50 _ 206i.e., a count of 50 before an
overflow occurs. The watchdog timers oscillator is independent from the CPU clock and the timeout is 18 ms.

To prevent a time-out condition the watchdog must be reset periodically via software. If the
watchdog timer is not reset before it times out, the microprocessor will be forced to jump to the reset

address. The pre-scaler can be used to extend the time-out period and valid rates are 1, 2, 4, 8, 16, 32,
64, and 128. For example, when set to 128, the time-out period is about 2 s (18 _ 128 _ 2304 ms).
The watchdog timer can be disabled during programming of the device if it is not used.

A/D Converter Registers

The A/D converter is used to interface analog signals to the microcontroller.

The A/D converts analog signals (e.g., voltage) into digital form so that they can be connected to a
computer. A/D converter registers are used to control the A/D converter ports. On most PIC
microcontrollers equipped with A/D, PORTA pins are used for analog input and these port pins are
shared between digital and analog functions.

PIC16F876 includes five A/D converters. Similarly, PIC16F877 includes eight A/D converters. The
width of the A/D converter can be 8 bits or 10 bits. Both PIC16F876 and PIC16F877 have 10-bit
converters. PIC16F73 has 8-bit converters. The A/D converter requires a reference voltage to
operate.

Interrupts

Interrupts are an important feature of all microcontrollers. An interrupt can either occur
asynchronously or synchronously. Asynchronous interrupts are usually external events which
interrupt the microcontroller and request service.

For example, pin INT (RB0) of a PIC16F84 microcontroller is the external interrupt pin and this pin
can be used to interrupt the microcontroller asynchronously; i.e., the interrupt can occur at any time
independent of the program being executed inside the microcontroller. Synchronous interrupts are

usually timer interrupts, such as the timer overflow generating an interrupt. Depending on the model
used, different PIC microcontrollers may have a different number of interrupt sources. For example,
the PIC16F84 microcontroller has the following four sources of interrupts:

External interrupts from INT (RB0) pin

TMR0 interrupt caused by timer overflow

External interrupts when the state of RB4, RB5, RB6,or RB7 pins change

Termination of writing data to the EEPROM.

Interrupts are enabled and disabled by the INTCON register. Each interrupt source has two bits to
control it.

One enables interrupts, and the other one detects when an interrupt occurs. There is a common bit
called GIE which can be used to disable all sources of interrupts.

CPU and ALU

The Central Processing Unit is responsible for using the information in the program memory
(instructions) to control the operation of the device. Many of these instructions operate on data
memory. To operate on data memory, the Arithmetic Logical Unit is required. In addition to
performing arithmetical and logical operations, the ALU controls status bits. The result of some
instructions forces status bits to a value depending on the state of the result.

Central Processing Unit (CPU)

The CPU can be thought of as the brains of the device. It is responsible for fetching the correct
instruction for execution, decoding that instruction, and then executing that instruction.

The CPU sometimes works in conjunction with the ALU to complete the execution of the instruction
(in arithmetic and logical operations). The CPU controls the program memory address bus, the data
memory address bus, and accesses to the stack.

Instruction Clock

Each instruction cycle (TCY) is comprised of four Q cycles (Q1-Q4). The Q cycle time is the same
as the device oscillator cycle time (TOSC). The Q cycles provide the timing/designation for the
Decode, Read, Process Data, Write, etc., of each instruction cycle. The following diagram shows the
relationship of the Q cycles to the instruction cycle.

The four Q cycles that make up an instruction cycle (TCY) can be generalized as:

Q1: Instruction Decode Cycle or forced No operation

Q2: Instruction Read Data Cycle or No operation

Q3: Process the Data

Q4: Instruction Write Data Cycle or No operation

Each instruction will show a detailed Q cycle operation for the instruction.

Arithmetic Logical Unit (ALU)

PICmicro MCUs contain an 8-bit ALU and an 8-bit working register. The ALU is a general purpose
arithmetic and logical unit. It performs arithmetic and Boolean functions between the data in the
working register and any register file.

The ALU is 8-bits wide and is capable of addition, subtraction, shift and logical operations. Unless
otherwise mentioned, arithmetic operations are two's complement in nature. In two-operand
instructions, typically one operand is the working register. The other operand is a file register or an
immediate constant. In single operand instructions, the operand is either the W register or a file
register.

The W register is an 8-bit working register used for ALU operations. It is not an addressable register.

Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry
(DC), and Zero (Z) bits in the STATUS register. The C and DC bits operate as a borrow bit and a
digit borrow out bit, respectively, in subtraction.

Crystal Oscillator :
The internal oscillator circuit is used to generate the device clock. The device
clock is requiredfor the device to execute instructions and for the peripherals to function.
Four device clock periods generate one internal instruction clock (TCY) cycle. There are
up to eight different modes which the oscillator may have. There are two modes
whichallow the selection of the internal RC oscillator clock out (CLKOUT) to be driven
on an I/O pin, orallow that I/O pin to be used for a general purpose function. The
oscillator mode is selected by the device conguration bits. The device conguration bits

are nonvolatile memory locations and the operating mode is determined by the value
written during device programming. The oscillator modes are:
LP Low Frequency (Power) Crystal
XT Crystal/Resonator
HS High Speed Crystal/Resonator
RC External Resistor/Capacitor (same as EXTRC with CLKOUT)
EXTRC External Resistor/Capacitor
EXTRC External Resistor/Capacitor with CLKOUT
INTRC Internal 4 MHz Resistor/Capacitor
INTRC Internal 4 MHz Resistor/Capacitor with CLKOUT
These oscillator options are made available to allow a single device type the exibility to
t applications with different oscillator requirements.
High Speed
Provides highest drive level available for crystals and ceramic resonators
Designed for 4 MHz and higher frequency crystals and and most ceramic
resonators
Highest current consumption, but the fastest mode available
Popular mode for resonators since they tend to require a stronger drive than
crystals
Alphanumeric LCD :
LCD (Liquid Crystal Display) screen is an electronic display module and find a
wide range of applications. A 16x2 LCD display is very basic module and is very
commonly used in various devices and circuits. These modules are preferred over seven
segments and other multi segment LEDs. The reasons being: LCDs are economical;
easily programmable; have no limitation of displaying special & even custom
characters (unlike in seven segments), animations and so on.
A 16x2 LCD means it can display 16 characters per line and there are 2 such
lines. In this LCD each character is displayed in 5x7 pixel matrix. This LCD has two
registers, namely, Command and Data. The command register stores the command
instructions given to the LCD. A command is an instruction given to LCD to do a
predefined task like initializing it, clearing its screen, setting the cursor position,
controlling display etc. The data register stores the data to be displayed on the LCD. The

data is the ASCII value of the character to be displayed on the LCD. Click to learn more
about internal structure of a LCD.

Pin Description:

4*4 matrix display :

This 16-button keypad provides a useful human interface component for
microcontroller projects. Convenient adhesive backing provides a simple way to mount
the keypad in a variety of applications.
Matrix keypads use a combination of four rows and four columns to provide
button states to the host device, typically a microcontroller. Underneath each key is a
pushbutton, with one end connected to one row, and the other end connected to one
column. These connections are shown in Figure 1.
Pin
No
1
2
3

Function

Name

Ground (0V)
Supply voltage; 5V (4.7V 5.3V)
Contrast adjustment; through a variable resistor

Ground
Vcc
VEE

Selects command register when low; and data register when high

Register Select

5
6
7
8
9
10
11
12
13
14
15

Low to write to the register; High to read from the register

Sends data to data pins when a high to low pulse is given

Backlight VCC (5V)

Read/write
Enable
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
Led+

16

Backlight Ground (0V)

Led-

8-bit data pins

Figure 1: Matrix Keypad Connections

In order for the microcontroller to determine which button is pressed, it first needs to pull each of
the four columns (pins 1-4) either low or high one at a time, and then poll the states of the four rows (pins
5-8). Depending on the states of the columns, the microcontroller can tell which button is pressed. For
example, say your program pulls all four columns low and then pulls the first row high. It then reads the
input states of each column, and reads pin 1 high. This means that a contact has been made between column
4 and row 1, so button A has been pressed.
MAX 232 :

The MAX232 is an IC, first created in 1987 by Maxim Integrated Products, that converts
signals from an RS-232 serial port to signals suitable for use in TTL compatible digital logic circuits.
The MAX232 is a dual driver/receiver and typically converts the RX, TX, CTS and RTS signals. The
drivers provide RS-232 voltage level outputs (approx. 7.5 V) from a single + 5 V supply via on-

chip charge pumps and external capacitors. This makes it useful for implementing RS-232 in devices
that otherwise do not need any voltages outside the 0 V to + 5 V range, as power supply design does
not need to be made more complicated just for driving the RS-232 in this case. The receivers reduce
RS-232 inputs (which may be as high as 25 V), to standard 5 V TTL levels. These receivers have a
typical threshold of 1.3 V, and a typical hysteresis of 0.5 V.
It is helpful to understand what occurs to the voltage levels. When a MAX232 IC receives a
TTL level to convert, it changes a TTL logic 0 to between +3 and +15 V, and changes TTL logic 1 to
between -3 to -15 V, and vice versa for converting from RS232 to TTL. This can be confusing when
you realize that the RS232 data transmission voltages at a certain logic state are opposite from the
RS232 control line voltages at the same logic state
RS232 line type and logic level

RS232 voltage

TTL voltage to/from MAX232

Data transmission (Rx/Tx) logic 0

+3 V to +15 V

0V

Data transmission (Rx/Tx) logic 1

-3 V to -15 V

5V

Control signals (RTS/CTS/DTR/DSR) logic 0

-3 V to -15 V

5V

Control signals (RTS/CTS/DTR/DSR) logic 1

+3 V to +15 V

0V

Fig.MAX 232

MAX232 to RS232 DB9 Connection as a DCE

MAX232 Pin Nbr.

MAX232 Pin Name

Signal

Voltage

DB9 Pin

T2out

RTS

RS-232

R2in

CTS

RS-232

R2out

CTS

TTL

n/a

10

T2in

RTS

TTL

n/a

11

T1in

TX

TTL

n/a

12

R1out

RX

TTL

n/a

13

R1in

TX

RS-232

14

T1out

RX

RS-232

15

GND

GND

SEVEN SEGMENT DISPLAY:

An LED or Light Emitting Diode, is a solid state optical PN-junction diode which emits light energy
in the form of photons when it is forward biased by a voltage allowing current to flow across its junction,
and in Electronics we call this process electroluminescence.
The actual colour of the visible light emitted by an LED, ranging from blue to red to orange, is decided by the
spectral wavelength of the emitted light which itself is dependent upon the mixture of the various impurities added
to the semiconductor materials used to produce it.

7-segment Display
Light Emitting Diodes have many advantages over traditional bulbs and lamps, with the main ones being their small
size, long life, various colours, cheapness and are readily available, as well as being easy to interface with various
other electronic components and digital circuits.
But the main advantage of light emitting diodes is that because of their small die size, several of them can be
connected together within one small and compact package producing what is generally called a 7-segment Display.
The 7-segment display, also written as seven segment display, consists of seven LEDs (hence its name) arranged
in a rectangular fashion as shown. Each of the seven LEDs is called a segment because when illuminated the

segment forms part of a numerical digit (both Decimal and Hex) to be displayed. An additional 8th LED is
sometimes used within the same package thus allowing the indication of a decimal point, (DP) when two or more 7segment displays are connected together to display numbers greater than ten.
Each one of the seven LEDs in the display is given a positional segment with one of its connection pins being
brought straight out of the rectangular plastic package. These individually LED pins are labelled from a through
to g representing each individual LED. The other LED pins are connected together and wired to form a common pin.
So by forward biasing the appropriate pins of the LED segments in a particular order, some segments will be light
and others will be dark allowing the desired character pattern of the number to be generated on the display. This then
allows us to display each of the ten decimal digits 0 through to 9on the same 7-segment display.
The displays common pin is generally used to identify which type of 7-segment display it is. As each LED has two
connecting pins, one called the Anode and the other called the Cathode, there are therefore two types of LED 7segment display called: Common Cathode (CC) and Common Anode(CA).
The difference between the two displays, as their name suggests, is that the common cathode has all the cathodes of
the 7-segments connected directly together and the common anode has all the anodes of the 7-segments connected
together and is illuminated as follows.

1. The Common Cathode (CC) In the common cathode display, all the cathode connections of the LED segments
are joined together to logic 0 or ground. The individual segments are illuminated by application of a HIGH, or
logic 1 signal via a current limiting resistor to forward bias the individual Anode terminals (a-g).

Common Cathode 7-segment Display

2. The Common Anode (CA) In the common anode display, all the anode connections of the LED segments are
joined together to logic 1. The individual segments are illuminated by applying a ground, logic 0 or LOW
signal via a suitable current limiting resistor to the Cathode of the particular segment (a-g).

Common Anode 7-segment Display

In general, common anode displays are more popular as many logic circuits can sink more current than they can
source. Also note that a common cathode display is not a direct replacement in a circuit for a common anode display
and vice versa, as it is the same as connecting the LEDs in reverse, and hence light emission will not take place.
Depending upon the decimal digit to be displayed, the particular set of LEDs is forward biased. For instance, to
display the numerical digit 0, we will need to light up six of the LED segments corresponding to a, b, c, d, e and f.
Then the various digits from 0 through 9 can be displayed using a 7-segment display as shown.
7-Segment Display Segments for all Numbers.

Then for a 7-segment display, we can produce a truth table giving the individual segments that need to be
illuminated in order to produce the required decimal digit from 0 through 9 as shown below.

7-segment Display Truth Table

Decimal
Digit
0

Individual Segments Illuminated

a

1
2

Driving a 7-segment Display

Although a 7-segment display can be thought of as a single display, it is still seven individual LEDs within a single
package and as such these LEDs need protection from over current. LEDs produce light only when it is forward
biased with the amount of light emitted being proportional to the forward current.
This means then that an LEDs light intensity increases in an approximately linear manner with an increasing current.
So this forward current must be controlled and limited to a safe value by an external resistor to prevent damage to
the LED segments.
The forward voltage drop across a red LED segment is very low at about 2-to-2.2 volts, (blue and white LEDs can
be as high as 3.6 volts) so to illuminate correctly, the LED segments should be connected to a voltage source in
excess of this forward voltage value with a series resistance used to limit the forward current to a desirable value.
Typically for a standard red coloured 7-segment display, each LED segment can draw about 15 mA to illuminated
correctly, so on a 5 volt digital logic circuit, the value of the current limiting resistor would be about 200 (5v
2v)/15mA, or 220 to the nearest higher preferred value.
So to understand how the segments of the display are connected to a 220 current limiting resistor consider the
circuit below.

Driving a 7-segment Display

In this example, the segments of a common anode display are illuminated using the switches. If switch a is closed,
current will flow through the a segment of the LED to the current limiting resistor connected to pin a and to 0
volts, making the circuit. Then only segment a will be illuminated. So a LOW condition (switch to ground) is
required to activate the LED segments on this common anode display.
But suppose we want the decimal number 4 to illuminate on the display. Then switches b, c, f and g would be
closed to light the corresponding LED segments. Likewise for a decimal number 7, switches a, b, c would be
closed. But illuminating 7-segment displays using individual switches is not very practical.
7-segment Displays are usually driven by a special type of integrated circuit (IC) commonly known as a 7-segment
decoder/driver, such as the CMOS 4511. This 7-segment display driver which is known as a Binary Coded Decimal
or BCD to 7-segment display decoder and driver, is able to illuminate both common anode or common cathode
displays. But there are many other single and dual display drivers available such as the very popular TTL 7447.
This BCD-to-7 segment decoder/driver takes a four-bit BCD input labelled A, B, C and D for the digits of the binary
weighting of 1, 2, 4 and8 respectively, has seven outputs that will pass current through the appropriate segments to
display the decimal digit of the numeric LED display.
The digital outputs of the CD4511 are different from the usual CMOS outputs because they can provide up to 25mA
of current each to drive the LED segments directly allowing different coloured LED displays to be used and driven.

Driving a 7-segment Display using a 4511

In this simple circuit, each LED segment of the common cathode display has its own anode terminal connected
directly to the 4511 driver with its cathodes connected to ground. The current from each output passes through a
1k resistor that limits it to a safe amount. The binary input to the 4511 is via the four switches. Then we can see
that using a BCD to 7-segment display driver such as the CMOS 4511, we can control the LED display using just
four switches (instead of the previous 8) or a 4-bit binary signal allowing up to 16 different combinations.
Most digital equipment use 7-segment Displays for converting digital signals into a form that can be displayed and
understood by the user. This information is often numerical data in the form of numbers, characters and symbols.
Common anode and common cathode seven-segment displays produce the required number by illuminating the
individual segments in various combinations.
LED based 7-segment displays are very popular amongst Electronics hobbyists as they are easy to use and easy to
understand. In most practical applications, 7-segment displays are driven by a suitable decoder/driver IC such as the
CMOS 4511 or TTL 7447 from a 4-bit BCD input. Today, LED based 7-segment displays have been largely replaced
by liquid crystal displays (LCDs) which consume less current