Analog Baseband Blocks For Multistandard Wireless Transmitters

UNIVERSIT DEGLI STUDI DI PAVIA
DIPARTIMENTO DI ELETTRONICA
DOTTORATO DI RICERCA
IN INGEGNERIA ELETTRONICA, INFORMATICA ED ELETTRICA
XVIII CICLO
ANALOG BASEBAND BLOCKS FOR

MULTISTANDARD WIRELESS TRANSMITTERS
Tutors:
Chiar.mo Prof. Piero Malcovati
Chiar.mo Prof. Guido Torelli
Co-Tutor:
Chiar.mo Prof. Andrea Baschirotto
Coordinatore del Corso di Dottorato:
Chiar.mo Prof. Giuseppe Conciauro
Tesi di Dottorato
di Nicola Ghittori
Anno Accademico 20042005
This research has been supported by the national program FIRB, Enabling technologies for wireless recongurable terminals, n RBNE01F582.
Ai miei nonni
Contents
List of Acronyms
Introduction
1.1 Recongurable multistandard terminals . . . . . . . . . . . . . . . . . . .
1.2 This thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Outline of the thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
4
6
7
Multistandard Transmitters for Wireless Applications

2.1 Wireless Local Area Networks . . . . . . . . . . . . . .
2.2 Orthogonal Frequency Division Multiplexing modulation
2.3 Universal Mobile Telecommunication System . . . . . .
2.4 Spread spectrum signals . . . . . . . . . . . . . . . . .
2.5 Transmitter architectures for recongurable terminals . .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
9
9
11
13
13
15
Performance Evaluation
3.1 Transmitter model and performance evaluation . . .
3.2 WLAN digital modulator . . . . . . . . . . . . . . .
3.3 UMTS digital modulator . . . . . . . . . . . . . . .
3.4 Baseband section of the direct conversion transmitter
3.5 Block specications for WLAN 802.11a and UMTS .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
18
18
20
20
27
27
.
.
.
.
.
.
.
.
.
.
Circuit Design
4.1 Choice of the digital-to-analog converter architecture . . . .
4.2 Pelgrom model of the random mismatch . . . . . . . . . . .
4.3 Eect of the current sources mismatch on the INL and DNL
4.4 INL and DNL yield . . . . . . . . . . . . . . . . . . . . . .
4.5 Eect of the current sources mismatch on the SNDR . . . .
4.6 Dimensioning of the unit cell . . . . . . . . . . . . . . . . .
4.7 Driving circuits . . . . . . . . . . . . . . . . . . . . . . . .
4.8 DAC-lter interface . . . . . . . . . . . . . . . . . . . . . .
4.9 Analog reconstruction lter . . . . . . . . . . . . . . . . . .
4.10 Simulation results . . . . . . . . . . . . . . . . . . . . . . .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
39
39
44
47
49
52
54
56
56
59
62
Experimental Results
5.1 Layout strategies . . . .
5.2 Measurement setup . . .
5.3 Static characterization . .
5.4 Dynamic characterization
5.5 Conclusions . . . . . . .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
71
71
75
76
78
87
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
CONTENTS
High Frequency Baseband Section

6.1 High frequency baseband section . . . . . . . . . .
6.2 Digital interpolator lter . . . . . . . . . . . . . .
6.3 Design of the 600-MHz digital-to-analog converter
6.4 Experimental results . . . . . . . . . . . . . . . .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
89
. 89
. 93
. 101
. 102
Crosstalk Eects in Mixed-Signal CMOS ICs

7.1 Fabrication technology issues . . . . . . .
7.2 Model of o-chip parasitics . . . . . . . .
7.3 Test-chip description . . . . . . . . . . .
7.4 Simulation results . . . . . . . . . . . . .
7.5 Experimental results . . . . . . . . . . .
7.6 Conclusion . . . . . . . . . . . . . . . .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
Conlusions
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
110
111
111
112
114
119
127
128
A Appendix
130
A.1 Crest factor of a signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
A.2 Linearity of a transfer function . . . . . . . . . . . . . . . . . . . . . . . . 130
A.3 INL and DNL denition for a DAC . . . . . . . . . . . . . . . . . . . . . . 132
References
134
Acknowledgements
139
List of Acronyms
16-QAM
16-quadrature amplitude modulation
64-QAM
64-quadrature amplitude modulation
BER
bit error rate
BPSK
binary phase-shift keying
CCK
complementary code keying
CMFB
common-mode feedback
DAC
digital-to-analog converter
DBPSK
dierential binary phase-shift keying
DEM
Dynamic element matching
DFT
discrete Fourier transform
DNL
dierential non-linearity
DPCCH
dedicated physical control channel
DPDCH
dedicated physical data channel
DQPSK
dierential quadrature phase-shift keying
DR
dynamic range
DS-CDMA
direct-sequence code division multiple access
DSP
digital signal processor
DSSS
direct-sequence spread spectrum
EVM
error vector magnitude
FDM
frequency division multiplexing
FFT
fast Fourier transform
FHSS
frequency-hopping spread spectrum
FIR
nite impulse response
FOM
gure of merit
FS
full-scale
GSM
Global System for Mobile Communications
HD3
third-order harmonic distortion
IC
integrated circuit
IDFT
inverse discrete Fourier transform
IFFT
inverse fast Fourier transform
IIP2
input second-order intercept point
IIP3
input third-order intercept point
IIR
innite impulse response
IMD3
third-order intermodulation distortion
INL
integral non-linearity
LINC
linear amplication with non-linear components
OFDM
Orthogonal Frequency Division Multiplexing
OIP3
output third-order intercept point
OSR
oversampling ratio
PA
power amplier
PCB
printed circuit board
PLL
phase-locked loops
QPSK
quadrature phase-shift keying
RF
radio-frequency
RX
receiver
SF
spreading factor
SFDR
spurious-free dynamic range
SNDR
signal-to-noise-and-distortion ratio
SNR
signal-to-noise ratio
THSS
time-hopping spread spectrum
TX
transmitter
UMTS
Universal Mobile Telecommunication System
UNII
Universal Networking Information Structure
VCO
voltage controlled oscillator
VGA
variable gain amplier
WLAN
Wireless Local Area Network
WMAN
Wireless Metropolitan Area Network
Chapter 1
Introduction
1.1
Recongurable multistandard terminals
The implementation of fully-integrated multistandard transceivers is nowadays driving the

telecommunication research worldwide, due to the evolution of the protocols and the growing importance of interoperability requirements among dierent standards. State-of-the-art
fully-integrated solutions in the scientic literature and on the market do not cover all of
the four most important telecommunication standards, namely Global System for Mobile
Communications (GSM), Universal Mobile Telecommunication System (UMTS), Bluetooth, and Wireless Local Area Networks (WLANs). In order to obtain a mobile terminal
oering to the user voice and data services in a seamless way, all the mentioned standards
must be considered together. As a matter of fact, GSM and UMTS are the dominant standards for voice and mixed voice/data mobile services, while WLANs based on the IEEE
802.11a/b/g protocols are the most important standards for high data rate wireless internet access. Finally, Bluetooth enables short-range wireless connection between portable
devices at low data rates.
The project Enabling technologies for wireless recongurable terminals funded in the
framework of the Italian National Project FIRB [13] is a rst step toward the above mentioned multistandard integrated transceiver. The aim of the project is the implementation of
fully-integrated solutions which support interoperability between dierent standards in an
ecient way.
An integrated multistandard transceiver competitive with discrete solutions based on
the combination of separate devices for the dierent standards needs a consistent reduction
in the silicon area and the power consumption. The maximum possible hardware sharing
among the transceivers for the dierent standards is therefore of crucial importance. If a
transceiver chain is recongurable between two dierent standards, they can not be employed together at the same time. Therefore, it is necessary to dene which standards must
operate simultaneously. In the framework of the FIRB project, it is assumed that only two
standards among the supported ones can operate concurrently at a given time (e.g WLAN
with Bluetooth or GSM/UMTS with Bluetooth or GSM/UMTS with WLAN) and that no
handover is supported for Bluetooth.
In view of these consideration, the receiver and transmitter architectures, shown in Figure 1.1 and Figure 1.2 respectively, are proposed. These architectures reect the following
basic ideas:
two parallel receiver (RX) chains based on the direct conversion architecture are implemented, one supporting all cellular standards (GSM/UMTS) and Bluetooth, while the
other supporting all WLAN standards and Bluetooth;
Introduction
GSM/UMTS/Bluetooth RX
Antenna
VGA
Low-pass
Filter
VGA
Low-pass
Filter
Digital processor
ADC
VGA
I/Q
Demodulator
LNA
Phone BP
Filter
LNA
WLAN BP
Filter
Antenna
ADC
I/Q
Demodulator
WLAN/Bluetooth RX
System on Chip RX
RF
Analog Baseband
Digital Baseband
Figure 1.1: Block diagram of the receiver architectures for GSM/UMTS/Bluetooth and
WLAN/Bluetooth.
GSM/UMTS/Bluetooth TX
Antenna
Modulator
PLL
Digital Baseband Phone

Modulator (LINC)
PPA
PA
LINC
Combiner
Balun
PA
Differential
antenna
Digital Baseband WLAN
Modulator
DAC
Low-pass
Filter
I/Q
Modulator
PPA
PA
WLAN/Bluetooth TX
System on Chip TX
RF
Analog Baseband
Digital Baseband
Figure 1.2: Block diagram of the transmitter architectures for GSM/UMTS/Bluetooth and
WLAN/Bluetooth.
two parallel transmitter (TX) chains are implemented, one based on direct modulation for
GSM, Bluetooth and, eventually, UMTS, while the other, based on the direct conversion
architecture, for all WLAN standards and Bluetooth;
the RX and TX chains covering the cellular standards can recongure themselves in a
short time (less than 200 s), thus allowing vertical handover between GSM and UMTS,
which do not need to operate concurrently;
vertical handover between cellular and WLAN standards, which can operate concurrently, is based on the use of two dierent transceivers.
In particular, several dierent chips, which represent a preliminary step toward the nal device, are presently under fabrication: receiver and transmitter for GSM, UMTS, and
Bluetooth; receiver and transmitter for WLAN at 2.4 GHz and 5 GHz and Bluetooth, as
well as the digital processor for all standards. Moreover several basic building blocks of the
presented transceivers have been integrated and characterized in the framework of the FIRB
activity.
1.2
Chapter 1
This thesis
The research activity reported in this thesis, carried out together with Andrea Vigna at the
Integrated Microsystem Laboratory of University of Pavia [4], in collaboration with the
Department of Innovation Engineering of University of Lecce [5], has been focused on
the realization of several baseband sections for recongurable transmitters using a direct
conversion architecture. In particular four dierent test-chips have been integrated:
Device #1: baseband section for the WLAN/UMTS standards consisting of digital-toanalog converter (DAC), output transimpedance stage and reconstruction lter, with a
total power consumption of 20 mW for WLAN and 16.8 mW for UMTS;
Device #2: baseband section for the WLAN/UMTS standards consisting of DAC, passive
output stage and reconstruction lter, which achieves the same performance of device #1,
but with a reduction in the power consumption, which is equal to 11 mW for WLAN and
8.4 mW for UMTS;
Device #3: baseband section for the WLAN/Bluetooth standards consisting of DAC,
passive output stage and reconstruction lter, with a power consumption of 8 mW for
WLAN and 5.4 mW for Bluetooth;
Device #4: high-frequency baseband section for the WLAN standard, which avoids the
use of an active reconstruction lter achieving a power consumption of 2.4 mW.
The experimental results obtained from the test-chip measurements show that all the devices
fulll the specications imposed by the dierent standards, even with the low 1.2-V supply
voltage adopted for the design. In particular the device #3 has been integrated together with
the radio-frequency (RF) section to implement the TX chain of Figure 1.2 for WLAN and
Bluetooth standards. The idea of recongurability for a multistandard terminal, the use of
a challenging supply voltage as low as 1.2 V and the low power consumption achieved for
all the implemented devices represent the main aspects of interest related to this research
activity. In this thesis the attention is focused on the couple of devices #2 and #4, which
present innovative solutions both at the architectural and at the design level.
The low power consumption has always been one of the key issue in the design of analog
and digital blocks for mobile applications. A proper choice of the architecture of the entire
system allows an optimization of this parameter. Moreover, the power consumption could
be strongly limited with a progressive reduction of the supply voltages used in wireless
applications, justied also by the diusion of ultra-scaled-down technologies. However,
the low voltage trend implies also some drawbacks in the design of the analog blocks of
wireless systems, mainly because a low supply voltage strongly limits the output dynamic
range as well as the achievable linearity performance of such blocks. This makes dicult
the implementation of low voltage transceivers, since these devices usually require high
linearity performance and large output swing. As a matter of fact, considering the state-ofthe-art literature [6], the use of a supply voltage such as 1.2 V or lower is actually unusual
in the realization of wireless transceivers, and the implementation of high-linearity analog
blocks when a low supply voltage is used can still be considered a challenge for designers.
Considering this scenario, the rst part of this thesis presents a recongurable baseband analog block realized by the cascade of a DAC and a reconstruction lter (device #2),
capable of operating in a multistandard wireless transmitter. The implemented block can
be digitally programmed to satisfy the specications of WLAN IEEE 802.11a/b/g (with a
maximum baseband signal bandwidth of 10 MHz) and UMTS (with a maximum baseband
signal bandwidth of 2.34 MHz). The complete device is fabricated in a standard 0.13-m
Introduction
CMOS technology and operates with a 1.2-V supply voltage. The choice of this low supply
voltage, in conjunction with the co-design of the two functional blocks, allows a signicant power reduction as required for mobile applications, while fullling the resolution and
linearity targets.
The second part of the thesis presents a high-frequency solution suitable for a direct
conversion WLAN transmitter (device #4). The use of a DAC conversion frequency as high
as 600 MHz allows us to avoid the use of an active reconstruction lter, with a signicant
reduction in power consumption. The device realizes the baseband digital-to-analog conversion of WLAN signals with the highest eciency if compared with state-of-the-art DACs,
as revealed by the highest value of gure of merit achieved for signals up to 10 MHz (the
band of WLAN 802.11a/b/g) and 14 MHz (the band of the upcoming WLAN 802.16).
The last part of the thesis deals with the study of crosstalk eects in mixed-signal integrated circuits (ICs). This is a research activity carried out in the framework of the FIRB
project which aims at studying the injection of noise by the digital switching sections and its
propagation toward the analog parts. The nal goal is to develop models for computer simulation of the relevant eects, and to develop adequate guidelines for design and layout, with
the purpose of minimizing these eects. These aspects are of primary concern especially
when dealing with fully-integrated transceivers for wireless applications. In particular some
of the design and layout choices regarding the baseband sections described in this thesis
were done on the basis of the results obtained by this analysis.
1.3
Outline of the thesis
This thesis is organized as follows:

in Chapter 2 a brief description of the considered standards (WLAN and UMTS) is given,
focusing in particular on the characteristics of the orthogonal frequency division multiplexing modulation and of the spread spectrum techniques. An overview of direct conversion transmitters for wireless applications is then presented.
in Chapter 3 the features of the Matlab model of the WLAN 802.11a/UMTS direct conversion transmitter is presented. The developed time-domain model allowed us to obtain
the specications of the basic building blocks for device #2 and #4. In particular the
chapter presents the results regarding device #2, indicating the DAC input number of
bits, its conversion frequency and the type of the lter transfer function.
in Chapter 4 the design of device #2 is presented, describing the digital-to-analog converter, as well as the features of the interface between the DAC and the following reconstruction lter. Simulation results of the entire baseband section implemented at a
fully-transistor level are presented.
in Chapter 5 the experimental results regarding device #2 are presented, including static
and dynamic tests. Comparisons between the target specications and measured performance are given.
Chapter 6 deals with the high-frequency baseband section implemented in device #4.
The required performance obtained with the Matlab model are rst indicated. The design
of the 600-MHz block is described in detail and the obtained experimental results are
reported.
Chapter 7 describes the study performed on the crosstalk eects in mixed-signal ICs. The
experimental results of two test-chips implemented for the validation of crosstalk models
are described.
Chapter 1
in Chapter 8 the conclusions and the future developments of the activity are given.
Chapter 2
Multistandard Transmitters for
Wireless Applications
This chapter presents the main characteristics of the two standards considered for the implementation of the baseband sections described in this thesis. The existing WLAN protocols
(802.11a/b/g) as well as the upcoming ones (802.11n and 802.16) are described in Section 2.1, while the features of the Orthogonal Frequency Division Multiplexing (OFDM)
techniques, on which the WLAN 802.11a standard is based, are presented in Section 2.2.
The UMTS standard is presented in Section 2.3, while Section 2.4 is dedicated to the description of the spread spectrum techniques, used in the UMTS standard. Finally in Section 2.5 the direct conversion architecture, chosen for the implementation of the recongurable transmitter, is briey reviewed.
2.1
Wireless Local Area Networks
The purpose of the IEEE 802.11 standard [7], formalized in 1999, was to allow high data
rate wireless network connectivity between personal computers or workstations. The standard then evolved allowing the use of WLAN as high-speed internet access. The original 802.11 standard provides a maximum data rate of 2 Mbps and uses frequency-hopping
spread spectrum (FHSS) or direct-sequence spread spectrum (DSSS) techniques to modulate the signal in the 2.4 GHz band. The growing demand of higher communication speed
led to the development of new standards, namely the 802.11a, 802.11b and 802.11g. Moreover the formalization of a next generation WLAN standard (802.16) has been performed
in the past years, while discussion of an upcoming 802.11n standard is still going on.
The IEEE 802.11a standard [8] achieves a high data rate (up to 54 Mbps) in the 5.4 GHz
band. In particular the frequency range allocated in the United States is called Universal
Networking Information Structure (UNII) band and it is composed of three parts: the
UNII-1 and UNII-2 (from 5.1 GHz to 5.35 GHz) are intended for indoor and outdoor
use, while the UNII-3 (from 5.725 GHz to 5.85 GHz) is for outdoor use exclusively.
Within each UNII band four non-overlapping WLAN radio channels with a bandwidth
of 20 MHz each are included. The data rate can vary from 6 Mbps to 54 Mbps. Each
channel uses the OFDM modulation and it is composed of 48 orthogonal subcarriers and
4 pilot tones used for the synchronization. Each subcarrier can be modulated by binary
phase-shift keying (BPSK), quadrature phase-shift keying (QPSK), 16-quadrature amplitude modulation (16-QAM) or 64-quadrature amplitude modulation (64-QAM). The data
rates achievable with the dierent modulation schemes for the subcarriers are summa-
10
Chapter 2
rized in Table 2.1. In Europe the WLAN standard in the 5 GHz band has been formalized
by the ETSI. The proposed standard, called HiperLAN2 [9], is similar to the 802.11a for
the use of the OFDM modulation and the achievable data rate of 54 Mbps. The major
dierence is the allocated spectrum, which is from 5.15 GHz to 5.35 GHz for indoor use
and from 5.47 GHz to 5.725 GHz for outdoor applications.
Table 2.1: Achievable data rate for the IEEE 802.11a standard depending on the used modulation
scheme.
Data rate (Mbps)
Modulation
Coding rate (R)
BPSK
1/2
BPSK
3/4
12
QPSK
1/2
18
QPSK
3/4
24
16-QAM
1/2
36
16-QAM
3/4
48
64-QAM
2/3
54
64-QAM
3/4
The IEEE 802.11b standard [10] species two radio transmission solutions for wireless communication in the band from 2.4 GHz to 2.4835 GHz, with a maximum data
rate of 2 Mbps. The rst uses the FHSS technique, while the second uses DSSS technique. In the case of the DSSS solution, the radio channel of 14 MHz is modulated
with a dierential binary phase-shift keying (DBPSK) or dierential quadrature phaseshift keying (DQPSK) to provide a data rate of 1 Mbps and 2 Mbps respectively. This
solution was enhanced to a data rate of 11 Mbps with the use of complementary code
keying (CCK).
The IEEE 802.11g standard [11] improves the data rate in the 2.4 GHz band up to a value
of 54 Mbps and at the same time it is backward compatible with 802.11b. To do this, the
standard uses the same modulation techniques to achieve compatibility and data rate of
the 802.11b standard, while allowing also the OFDM modulation to obtain the 802.11a
data throughputs.
The IEEE 802.11n standard is an amendment to the original 802.11 standard started in
January 2004 and intended for local area wireless networks. The real data throughput
is estimated to reach a theoretical value of 540 Mbps (which may require an even larger
raw data rate at the physical layer) and should be up to 10 times faster than the 802.11a/g
and near 40 times faster than the 802.11b. The 802.11n is build upon previous 802.11
standards by adding to the OFDM the use of multiple transmitter and receiver antennas
(multiple-input multiple-output antennas or MIMO) to allow for increased data throughput through spatial multiplexing. The standardization process is expected to be completed
by April 2007.
The IEEE 802.16 standard [12], completed in October 2001, denes the air interface
specications for the Wireless Metropolitan Area Networks (WMANs). As currently dened by the standard, a WMAN provides network access to buildings through exterior
antennas communicating with central radio base stations (BS). Therefore the WMAN
oers an alternative to cabled access networks, such as ber optic links or digital sub-
single
subcarrier
11
guard
band
f
conventional FDM multicarrier modulation technique
bandwidth saving
OFDM multicarrier modulation technique
Figure 2.1: Conventional FDM subcarriers frequency allocation vs OFDM subcarriers frequency allocation.
scriber line (DSL) links. IEEE 802.16 provides up to 50 km (31 miles) of linear service
area range and allows connectivity without a direct line of sight to the base station. The
user inside the building will connect to WMAN with conventional in-building networks,
such for example Ethernet or 802.11 Wireless LANs. Two ranges of frequencies are allocated to the 802.16 standard. The rst one is from 10 GHz to 66 GHz, using a single
carrier modulation and a time division multiple access protocol (TDMA). On the other
hand, the band from 2 GHz to 11 GHz is addressed from the 802.16a standard and it
is driven by non-line-of-sight operation. The channel spacing ranges from 20 MHz to
28 MHz and the maximum data throughput is 134 Mbps.
2.2
Orthogonal Frequency Division Multiplexing modulation
The principles of OFDM modulation are employed in data delivery systems over the phone
line (as in asynchronous digital subscriber line, ADSL), digital radio, television (like in terrestrial digital video broadcast, DVB-T), and in wireless networking systems. The OFDM
techniques use a set of subcarriers that are orthogonal to each other, reaching a higher level
of spectral eciency with respect to simple frequency division multiplexing (FDM) techniques. As a matter of fact, the guard bands that are necessary to allow the individual
demodulation of the subcarriers in an FDM system are no longer used. In the case of the
OFDM systems the spectra of the subcarriers overlap one with each other, but as long as
their orthogonality is ensured, it is possible to recover the individual subcarrier signals.
Let us consider a group of N complex symbols (N is equal to 64 in the WLAN 802.11a
case), indicated as dn (with integer n = N/2, ..., N/2 and n 0), taken from a constellation
12
Chapter 2
of complex numbers (for example one of the PSK or QAM constellations used in the WLAN
modulation scheme):
(2.1)
dn = an + jbn .
The complex symbols are used to modulate a set of N orthogonal functions in a time interval
t [0, T ]. The chosen orthogonal functions fn (t) correspond to sinusoids in the complex
plane, as they are rotating points on the unit circle, describing an integer number of cycles
in the time interval [0, T ]:
(2.2)
fn (t) = e j2n f0 t ,
where f0 = 1/T . Note that as we are considering complex signals, the frequency can be
positive or negative, corresponding to clockwise or counterclockwise rotation. The chosen
set of functions are orthogonal as:
e j2n f0 t e j2m f0 t dt = T, if m = n;
(2.3)
e j2n f0 t e j2m f0 t dt = 0, if m n.
(2.4)
Considering the symbol dn , the corresponding modulated function is:

yn (t) = dn e j2n f0 t = |dn | e j2n f0 t+(dn ) ,
(2.5)
while the overall modulated signal can be written as:

s(t) =
N/2

n=N/2
yn (t) =
N/2
dn e j2n f0 t .
(2.6)
n=N/2
The spectrum of the single modulated function yn (t) is a sinc function located around the
subcarrier frequency n f0 and it is equal to zero in correspondence of the peaks of the other
subcarriers, so realizing the orthogonality (Figure 2.1). The value of the spectrum of yn (t)
calculated in n f0 is therefore not inuenced by the adjacent subcarriers and it allows the
value of the modulating complex symbol dn to be recovered. The overall spectrum of the
complex signal consists of N subcarriers spaced apart of f0 . In the WLAN 802.11a case
f0 is equal to 0.3125 MHz and the spectrum of the complex baseband modulated signal is
included between 10 MHz and 10 MHz.
An OFDM system treats the source symbols dn (e.g., the PSK or QAM symbols) at the
transmitter as if they are in the frequency domain. These symbols are used as the inputs
to a modulator block that brings the signal into the time domain. This block takes in N
symbols at a time, where N is the number of subcarriers in the system. Each input symbol
acts like a complex weight for the corresponding sinusoidal basis function. Since the input
symbols are complex, the value of the symbol determines both the amplitude and phase of
the complex sinusoid for that subcarrier. The output of the block is the summation of all the
N complex sinusoids.
The idea behind the analog implementation of the OFDM system can be extended to
the digital domain by using the discrete Fourier transform (DFT) and its counterpart, the
inverse discrete Fourier transform (IDFT). These mathematical operations are widely used
for transforming data between the time domain and the frequency domain. In practice,
OFDM systems are implemented using a combination of fast Fourier transform (FFT) and
13
inverse fast Fourier transform (IFFT) blocks that are mathematically equivalent versions of
the DFT and IDFT, respectively, but more ecient to implement.
If we consider the sampled version of the overall modulated function s(t):

N/2

kT
=
dn e j2nk/N ,
(2.7)
s t=
N
n=N/2
with k going from 0 to N 1, we can pass from the set of N complex symbols dn to the
N complex samples of the modulated signal using an IFFT block. Thus, the IFFT block
provides a simple way to modulate data onto N orthogonal subcarriers. The block of N
output samples from the IFFT make up a single OFDM symbol. The length of the OFDM
symbol is T . After some additional processing, the time-domain signal that results from the
IFFT is split into a real and imaginary part and it is transmitted across the channel. At the
receiver, an FFT block is used to process the received signal and bring it into the frequency
domain. Ideally, the FFT output will be the original symbols that were sent to the IFFT at
the transmitter. When plotted in the complex plane, the FFT output samples will form the
original transmitted constellation.
2.3
Universal Mobile Telecommunication System
The third generation (3G) of global wireless systems provides voice and information services with dierent data rates using the wide-band code-division multiple access (WCDMA)
protocol. The European version of the third generation telecommunication system, called
UMTS [13], can achieve a data rate of 384 Kbps for outdoor applications and of 2 Mbps for
indoor applications. The bit-stream carrying the user information is modulated by a pseudorandom sequence (indicated as spreading code). Through the spreading process the signal
bandwidth (ranging from 8 kHz to 384 kHz) is increased to the bandwidth of the spreading
code (3.84 MHz). At the receiver the despreading process uses the same code applied in the
transmitter to recover the original spectrum of the data signal, whose power spectral density
increases by an amount given by the spreading factor (SF). The spreading factor is dened
as the ratio between the rate of the spreading code and the one of the original signal.
The UMTS mobile terminal is a continuously transmitting and receiving frequency division duplexing (FDD) system. The transmission band is located between 1920 MHz and
1980 MHz, while the receiver band is located between 2110 MHz and 2170 MHz. The
minimum spacing between the TX and RX band is therefore 135 MHz, while the channel
spacing is 5 MHz.
2.4
Spread spectrum signals
The UMTS standard uses a coding process of the signal implying a modication of its
spectrum, which results to be spread in a wider bandwidth with respect with to the original
one. For this reason the resulting transmitted signal is called spread spectrum signal and
the protocol used is called spread spectrum multiple access protocol (SSMA). A spread
spectrum system must meet two criteria: the transmitted bandwidth is much wider than
the bandwidth of the information being sent; the spreading signal is independent of the
information bearing signal. According to the process which realizes the spreading of the
signal, the spread spectrum systems can be classied into three main groups:
14
Chapter 2
Bit rate
chip rate
Bit rate
TX spreading
f
Code
SF
RX despreading
f
Code
Figure 2.2: Spreading and despreading process.

direct-sequence spread spectrum, in which the spreading is done by a multiplication of
the data carrying signal with a code sequence of much larger bandwidth;
frequency-hopping spread spectrum, in which the spreading is accomplished by periodically changing the carrier frequency according to a spreading code;
time-hopping spread spectrum (THSS), in which the signal is not transmitted in a continuous way, but it is fragmented in bursts whose temporal position is decided by the
spreading code.
Another technique which implies a spreading of the signal spectrum is the chirp modulation,
usually reserved for military applications. In this technique the carrier frequency of the
transmitted signal varies continuously (usually linearly) over a wide frequency range. As
there is not a code univocally identifying each user, the chirp modulation is not a CDMA
technique, even if it is a spread spectrum technique as there is a spreading of the information
signal in a larger bandwidth.
The third generation systems, like UMTS, use the direct-sequence code division multiple access (DS-CDMA), which is the one that oers the best advantages. In the DS-CDMA
technique the signal carrying the information is directly modulated by the code. The spreading sequence (called also chip sequence) is associated to each user and it is orthogonal to
the spreading sequences of the other users. A representation of the coding process is shown
in Figure 2.2 in which the data signal is multiplied by a high frequency pseudo random
code. At the receiver the despreading of the signal is performed by the demodulator which
multiplies the signal by the same code used in the transmission modulator. In this way the
signal is restored in its original form.
The DS-CDMA, like the other spread spectrum techniques, has an inherent resistance
against interference and jamming. Suppose that a narrow-band interferer is present in the
received signal, as indicated in Figure 2.3. Due to the high correlation between the wanted
signal (which was spread in the transmitter by the same sequence) and the locally generated
code for despreading, the signal level increases. At the same time the interference signal is
spread to a larger bandwidth and therefore the interference power in the receiver bandwidth
decreases.
The main advantage of the DS-CDMA is the high simplicity of the spreading process,
which results to be just a multiplication of the data signal with the spreading code. On the
other hand a crucial point is represented by the synchronization of the received signal and
the locally generated code for the despreading. Therefore obtaining initial synchronization
15
and keeping the code synchronized by a code tracking loop is mandatory in DS-CDMA
system design.
2.5
Transmitter architectures for recongurable terminals
Transmitters performs three basic functions in a digital communication system: modulation,

frequency translation and amplication of the signal. Therefore the main parameters of
interest when dealing with a transmitter are modulation accuracy, spectral emission and
output power level. Among the others, two dierent transmitter architectures are interesting
for the possibility of a complete integration and recongurability between several standards:
direct conversion architecture and phase-locked loops (PLL) based architecture.
The direct conversion architecture, called also zero intermediate frequency (zero-IF),
performs the frequency translation of the transmitted signal in one step (Figure 2.4). Two
digital-to-analog converters convert the I and Q digital modulated signals coming from the
digital signal processor (DSP) into analog waveforms, which are smoothed by the following
low-pass reconstruction lters and amplied by means of a variable gain amplier (VGA).
These baseband signals are then shifted to RF by two quadrature mixers, and summed up to
obtain the nal waveform to be transmitted at the antenna, after the amplication provided
by the power amplier (PA).
Since no intermediate frequency exists with respect to the RF nal center frequency of
the signal, there is no need of an IF lter. For this reason, the direct conversion architecture is
the most interesting when dealing with highly-integrated multistandard solutions. A ltering
stage before the PA reduces the unwanted harmonics and noise from the up-conversion
process. However, if the bandpass lter before the PA is removed to achieve a high level of
integration, a higher performance RF lter may be required after the PA. This requirement
in turns implies a larger insertion loss through the RF lter, thus reducing the eciency of
the PA due to the reduction of the output power at the antenna for a given signal level at the
PA input. This signal level must therefore be increased, with a consequent increase in the
interferer
spread interferer
chip rate
chip rate
Bit rate
RX despreading
f
Code
interferer
Figure 2.3: An interfering signal is spread by a code sequence resulting in a lower power
spectral density, while the wanted signal level is increased due to the high correlation of the
spreading code and the signal.
16
Chapter 2
DAC
VGA
RF S AW
RF FILTE R
LO
90
PA
Q
VGA
DAC
Figure 2.4: Model of the direct conversion transmitter.

f0
20 bits
20 bits
d((t)+(t))/dt
from
DSP
3 bits
PLL
N
20 bits
d/dt
arccos
3 bits
PD
LPF
PD
LPF
S 1(t)
quartz
20 bits
RFsignal
PA
20 bits
20 bits
S 2(t)
d((t)-(t))/dt
f0
PA
3 bits
PLL
Figure 2.5: Model of the direct modulation transmitter.

power consumption. The level of RF ltering is a compromise between power consumption
an achievable integration.
On the other hand, another drawback of a direct conversion architecture is represented
by the local oscillator (LO) pulling. The output of the I/Q modulator, of the power amplier
and of the local oscillator run at the same frequency, which is the standard RF frequency. As
a consequence, the output of the local oscillator may be pulled by the large signal emitted
by the PA, so resulting in a modulation of the input mixer frequency. The solution is to
keep a high level of isolation between the PA and the voltage controlled oscillator (VCO),
which is however dicult to implement in a fully-integrated solution. Otherwise dierent
schemes, using two VCOs functioning at dierent frequencies with respect to the RF one,
can be used to overcome this problem.
Another architecture which has the advantage of reducing the requirements of the RF ltering is the PLL based transmitter architecture (called also direct modulation architecture).
This transmitter can be combined with a digital section based on linear amplication with
non-linear components (LINC), as shown in Figure 2.5. The main processing of the signal
is performed in the digital domain, while the analog section is limited to some parts of the
PLL and the power amplication stage. The input of the digital section consists of the modulated signal carrying the user information. Such a signal (that is generally modulated both
in phase and in amplitude) feeds a DSP section whose outputs are the instantaneous phases
of the two wideband (and constant envelope) LINC signal S 1 (t) and S 2 (t). Such information, quantized in 2 words of 20 bits each, is then digitally processed and used to modulate
the carrier of two wideband PLLs, through their modulator. The two PLL outputs are
the constant envelope RF LINC signals S 1 (t) and S 2 (t) that may then be amplied through
the nal power ampliers. Their outputs are then on-chip recombined and transmitted to the
antenna.
17
In the framework of the FIRB project a direct conversion architecture has been chosen
for the WLAN/Bluetooth recongurable transmitter, while the direct modulation architecture has been chosen for the GMS/UMTS/Bluetooth recongurable transmitter. On the other
hand, all the devices developed in our research activity are intended for direct conversion
architectures (no matter which standards are supported), and therefore they consist of the
cascade of a DAC and a ltering stage (which is active for device #1, #2, #3 and passive for
device #4).
Chapter 3
In this chapter the features of the Matlab model of the WLAN 802.11a/UMTS direct conversion transmitter are presented. The developed time-domain model allowed us to obtain
the specications of the basic building blocks for the devices presented in this thesis. Section 3.1 describes the overall model and indicates the tests that have to be performed on the
transmitted signal to verify the compliance to the standard specications. Sections 3.2 and
3.3 describe the simplied models for the WLAN 802.11a and UMTS digital modulators,
while Section 3.4 deals with the developed models for the analog baseband blocks. Finally
Section 3.5 presents the required performance for the baseband analog section implemented
in device #2. Even if the part of the model regarding the WLAN is limited to the 802.11a
standard, an overall system-level study developed in the framework of the FIRB activity
conrms the obtained specications also for 802.11b and 802.11g standards.
3.1
Transmitter model and performance evaluation
A model of the direct conversion transmitter has been developed in the Matlab environment.
A time-domain model has been preferred to a frequency-domain one as it allows a more accurate description of the non-idealities of the blocks, at the expense of more computational
time. Moreover a time-domain model allows to deal directly with the real signals that ow
through the blocks of the system, and hence to evaluate the parameters of interest, like the
signal-to-noise ratio (SNR).
The model consists of two parts. The rst one describes a simplied version of the digital modulator for the WLAN 802.11a and UMTS standards. The second part includes the
models of the building blocks used in the analog baseband section of the direct conversion
transmitter. The DAC and the following reconstruction lter have been modeled taking into
account the most important design parameters and the main non-idealities.
As indicated by the standards, the quality of the transmitted signal is specied evaluating the error vector magnitude (EVM) at the antenna. An ideal receiver performs the
demodulation of the transmitted signal, obtaining a constellation of points in the complex
plane representing the received symbols. Each point of the constellation (indicated as Z) is
compared with the ideal one R (i.e. the one coming from an ideal transmitter), as shown in
Figure 3.1. The EVM (expressed as a percentage) can be calculated as follows:

N
2
1 |Z R|
(3.1)
EVM =
N 2 100%,
1 |R|
where N is the number of received symbols. Considering for example the case of UMTS,
the EVM has to be less than 17.5% to ensure the achievement of the necessary bit error
19
R (ideal constellation point)
range of real
constellation points
Z (real constellation point)
Figure 3.1: Constellation points coming from an ideal transmitter and a real one.
rate (BER) at the receiver. The EVM can also be related to the signal-to-noise-and-distortion
ratio (SNDR) of the signal at the antenna, noting that it can be expressed as:

Perror
100%,
(3.2)
EVM =
Preference
where Preference is the mean power of the reference signal (i.e. the output of an ideal chain
in which the various blocks do not introduce distortion and noise) and Perror is the mean
power of the error signal (i.e. the dierence between the reference signal and the real signal
processed by the transmitter chain). An EVM value of 17.5% implies an SNDR of 15 dB.
Table 3.1 summarizes the required EVM at the antenna for the two dierent standards.
The evaluation of the error signal as a dierence between the signal processed by the real
transmitter and the one processed by an ideal transmitter accounts for all the sources of noise
and distortion. The noise can be quantization noise or thermal one, while the distortion is
caused by the non-linearity of the blocks or by the non-constant transfer function amplitude
in the band of the signal. In the model the distortion caused by the non-linear phase response
of the blocks is not taken into account. As a matter of fact, the phase component of the
blocks transfer function is always equal to zero and therefore the blocks do not introduce
delays.
The transmitter chain performance is evaluated not only with WLAN or UMTS application signals but also with sinusoidal inputs. This gives the possibility to characterize
the quality of the baseband processing with parameters like spurious-free dynamic range
(SFDR), input third-order intercept point (IIP3) or output third-order intercept point (OIP3).
Moreover the power of the transmitted signal has to be suciently low out of band, as specied by the mask indicated in the standard, to avoid interference with adjacent channels.
This represents the second test performed on the transmitted signal.
20
3.2
Chapter 3
WLAN digital modulator
A model of the WLAN 802.11a digital modulator has been realized in the Matlab environment. The model has been implemented on the basis of existing tools [14] and simplied to
allow more simulation exibility and cosimulation with models of analog blocks.
The scheme of the WLAN digital modulator is reported in Figure 3.2. The input bitstream is modulated into a complex bit-stream using a modulation scheme chosen among
BPSK, QPSK, 16-QAM or 64-QAM according to the desired data rate. The resulting complex symbols are grouped in packets of 64 (48 data symbols, 4 pilot symbols and 12 zero
symbols) in order to apply the IFFT algorithm. The length of the packet is further increased
to 80 by adding a cyclic extension, whose aim is to reduce the eect of the intersymbol
interference (ISI). The complex stream is then parallel-to-serial converted and nally split
into a real and an imaginary part sampled at 20 MHz and applied to the digital-to-analog
converters. Figure 3.3 shows the constellation of the complex symbols in the case of a 64QAM modulation scheme. Figure 3.4 shows the spectrum of two orthogonal subcarriers,
while the overall spectrum of the OFDM modulated signal is shown in Figure 3.5.
3.3
UMTS digital modulator
As in the WLAN case, a simplied model of the UMTS digital modulator has been realized
in the Matlab environment (Figure 3.6) on the basis of an existing commercial tool [15].
The section taken into account is the one which allows the multiplexing of up to six uplink
dedicated physical channels prior to the transmission.
A schematic representation of the modulator is given in Figure 3.7. The six dedicated
physical data channels (DPDCH1-6) are multiplexed together with the dedicated physical
control channel (DPCCH), which contains the control information for the data channels. In
order to split the seven channels, to each one is assigned a dierent orthogonal spreading
Table 3.1: EVM requirements for WLAN 802.11a and UMTS.

Standard and modulation scheme
EVM upper limit
SNDR
WLAN, BPSK
39.8% (with 9 Mbits/s)
8 dB
WLAN, QPSK
13 dB
WLAN, 16QAM
20 dB
WLAN, 64QAM
25 dB
UMTS
17.5%
15 dB
48
64
...
...
64
MODULATOR
BIT-STREAM
(BPSK, QPS K,
16QAM, 64QAM)
Serial to
parallel
Pilot/Zero
insertion
IFFT
...
COMPLEX
BIT ST REAM
...
Cyclic
extension
Parallel to
serial
F DSP =
Figure 3.2: Schematic representation of the WLAN digital modulator.
20 MHz
21
1.5
zero and pilot symbols
Q component digital value
0.5
0.5
1.5
1.5
0.5
0
0.5
I component digital value
1.5
Figure 3.3: Constellation of the complex symbols in the case of a 64-QAM modulation
scheme.
20
orthogonal subcarriers
10
0
Power (dBr)
10
20
30
40
50
60
500
0
500
Frequency (kHz)
1000
Figure 3.4: Spectrum of two orthogonal subcarriers.
22
Chapter 3
10
pilot subcarriers
0
Power (dBr)
10
20
30
40
50
60
10
0
Frequency (MHz)
10
Figure 3.5: Spectrum of an OFDM modulated complex WLAN signal.
Figure 3.6: Screenshot of the developed Matlab code to model the UMTS digital modulator.
code. The spreading blocks convert each symbol into a series of chips and the frequency of
the resulting chip-stream is enhanced with respect to the frequency of the bit-stream by the
spreading factor (SF). When these channels are transmitted together, the orthogonality of
these codes ensures that the receiver can extract the overlapping data streams from the received message. The standard makes certain assumption on the spreading operation. When
there is more than one DPDCH present, the spreading factor for all the data channels must
be set equal to 4. Note that half of the DPDCHs, the rst three in the system, are assigned
to the in-phase channel, while the other three DPDCHs are assigned to the quadrature channel. Within each I/Q group the only way of recognizing the data channel is through their
spreading codes and so dierent spreading codes are assigned to each of them. However
since the data in the I channel can be distinguished anyway from the data in the Q channel
(they are orthogonal), the same code can be used in both groups. Figure 3.8 and Figure 3.9
23
DPDCH1
BPSK symbol
mapper
OVSF
spreader
DPDCH3
BPSK symbol
mapper
OVSF
spreader
DPDCH5
BPSK symbol
mapper
OVSF
spreader
DPDCH2
BPSK symbol
mapper
OVSF
spreader
BPSK symbol
mapper
DPCCH
Root Raised
Cosine Digital
Filter
I BIT
STREAM
Re-Im to
Compl
OVSF
spreader
UPLINK Compl to
Re-Im
Scrambler
Q BIT
STREAM
Root Raised
Cosine Digital
Filter
Figure 3.7: Schematic representation of the UMTS digital modulator.
1
0.8
0.6
Digital value
0.4
0.2
0
0.2
0.4
0.6
0.8
1
0
3
Time (Rs)
Figure 3.8: DPDCH before the spreading. The data-period is 4 times the chip-period
(0.26 s), so the spreading factor must be set equal to 4.
show an example of the bit-stream associated with one of the DPDCH before and after the
spreading process.
The spreading enhances the rate of the input symbols to 3.84 MHz (this value is called
chip-rate). A group of 2560 chips constitutes a slot, whose length is 2/3 ms. The allowable
values for the SF are 4, 8, 16, 32, 64, 128 and 256, which in turn determine the allowable
value of the data-rate at the input of the spreading blocks. Like the DPDCHs, the control
channel must be spread to 2560 chips per slot. Since the DPCCH includes just 10 bits per
slot, the spreading factor is always set to 256.
After the spreading each chip-stream is passed through a gain block. The amount of gain
24
Chapter 3
1
0.8
0.6
Digital value
0.4
0.2
0
0.2
0.4
0.6
0.8
1
0
3
Time (Rs)
Figure 3.9: DPDCH after the spreading, with a spreading factor equal to 4. The spreading
code is equal to: (1,1,1,1). The chip-period is 0.26 s.
is specied by the standard and is set to 1 for all the DPDCHs and 0.6 for the DPCCH. The
DPCCH is then summed with the three channels that make up the Q group, while the three
channels forming the I group are summed separately. The resulting chip-streams obtained
after the summation are reported in Figure 3.10 and Figure 3.11 for the I branch and the Q
branch respectively. The two chip-streams are then combined together to obtain a complex
chip-stream. The possible values which can be assumed by the complex chip-stream can be
plotted in the complex plane, as done in Figure 3.12.
The chip-stream is then passed through a scrambling code, which is a slot-dependent
sequence of 2560 complex numbers. The eect of the scrambling on the constellation can
be seen in Figure 3.13. The scrambling implies a rotation of the transmitted complex bits.
The purpose of the uplink scrambling is to enable more user equipments (UEs) to use the
same RF channel. Each transmitting UE scrambles its data dierently (but in such a way
that the bandwidth of the transmitted signal is not altered by the scrambling) so that the
receiving node can identify the UE sending the data. Since scrambling eectively separates
the signals from various transmitters, dierent transmitters can spread data on the physical
channels with the same spreading codes as the other transmitters.
The scrambled chip-stream is then divided again into a real and an imaginary part. Note
that at this point the rate of the digital signal of the I and Q branch is equal to the chip-stream
(3.84 MHz) and the complex spectrum is included between 1.92 MHz and 1.92 MHz. The
two streams must be ltered by a root raised cosine lter with roll-o equal to 0.22. This
implies that the bandwidth of the transmitted signal is enhanced to 1.92 (1+0.22) MHz and
that the shaping lter must act also as an interpolation lter with an interpolation factor at
least equal to 2.
25
Digital value
3
Time (Rs)
Figure 3.10: Chip-stream relative to the I component, after the application of the gain blocks
and the summation of DPDCH1, DPDCH3, DPDCH5.
4
3
Digital value
2
1
0
1
2
3
4
3
Time (Rs)
Figure 3.11: Chip-stream relative to the Q component, after the application of the gain
blocks and the summation of DPDCH2, DPDCH4, DPDCH6, DPCCH.
26
Chapter 3
4
3
2
1
0
1
2
3
4
4
1
0
1
Figure 3.12: Constellation of the complex chip-stream after the combination of the I and Q
components.
8
6
4
2
0
2
4
6
8
8
2
0
2
Figure 3.13: Eect of the scrambling on the constellation of the complex chip-stream.
IN
27
OUT
a x+ a2x + a x
1
3
non-linearity
effects
transfer
function
saturation
limits
white noise
Figure 3.14: Model of the lter block including non-idealities.
3.4
Baseband section of the direct conversion transmitter
The two analog blocks constituting the baseband section of the transmitter have been described by time-domain Matlab models. The DAC has been characterized with its input
number of bits and conversion frequency as well as with appropriate noise and distortion
eects. An interpolation block between the DSP and the DAC has been considered in order to enhance the signal sampling frequency to the value required by the DAC. Moreover
the DAC model takes into account dierent types of current-steering architectures (binary,
thermometric or segmented). As it will be explained in the next chapter, these are the most
used architectures for telecommunication applications.
The analog reconstruction lter model includes four sources of non-idealities: noise,
distortion, the implemented transfer function and a saturation limit. The resulting model is
shown in Figure 3.14. Noise is modeled as a random Gaussian signal summed at the block
input, while distortion is modeled in terms of input second-order intercept point (IIP2) and
IIP3, assuming the presence of a polynomial input-output relation of the type:
y = a1 x + a2 x2 + a3 x3 .
(3.3)
The saturation limit comes from the available supply voltage (1.2 V), assuming the use of
a fully-dierential architecture. The linear part of the block is represented by a transfer
function. For an easier calculation of parameters like SNDR, the phase component of the
transfer function has been set equal to zero (this means no delay between the input and the
output signal).
3.5
Block specications for WLAN 802.11a and UMTS
The developed Matlab model has allowed us to determine the specications for each block
of the baseband section in order to satisfy the requirements of the two standards. In particular we deal with device #2 which can be embedded in a recongurable transmitter for
WLAN and UMTS. The main parameters of interest are:
DAC input number of bits N;
DAC conversion frequency Fc ;
the type of transfer function that the reconstruction lter must provide;
the signal amplitudes at the DAC output and at the lter output (and hence the presence
of an eventual lter gain);
the linearity of the lter in terms of IIP3 and IIP2.
The specications have been determined including in the model only one parameter at
a time, while all the rest of the transmitter was supposed ideal. In this way we can evaluate the dependence of the SNDR on the parameter of interest, founding in particular where
28
Chapter 3
Main parameters specification: N, F c, filter transfer function
Time-domain transmitter Matlab model
Standard
requirements met?
NO
NO
Standard
requirements met?
SYSTEM-LEVEL STUDY
YES
Transistor
level design
YES
END
Block non idealities

(thermal noise,
mismatch, ...)
TRANSISTOR-LEVEL DESIGN
Figure 3.15: Flow diagram of the adopted approach for the system-level study and the
analog blocks design.
its eect is minimized and does not inuence the performance of the overall transmitter.
Moreover the spectrum of the signal at the output of the blocks is analyzed to verify that it
lies under the emission mask indicated by the standard. The model has also been used for
a verication of the eectiveness of the two blocks transistor-level design. The baseband
section non-idealities, such as the thermal noise or the transistor mismatch, have been characterized on the basis of transistor-level simulations and included in the Matlab model to
verify the impact of each non-ideality on the transmitter performance. The ow diagram of
the adopted approach for the system-level study and the transistor-level design of the two
analog blocks is illustrated in Figure 3.15.
The rst parameter to be found is the DAC input number of bits. The number of bits
N used to quantize the digital signal coming from the DSP determines the resolution of the
signal at the DAC output and consequently its SNR. If we suppose that the DAC has the
lowest allowable conversion frequency (two times the signal bandwidth) and that the following reconstruction lter is ideal, the SNR in the signal bandwidth (equal to the Nyquist
frequency) is given only by the quantization noise. The signal eective number of bits is
therefore equal to the DAC input number of bits. The SNR value, expressed in dB, is equal
to:
SNR = 6.02 N + 1.76 ,
(3.4)
where the quantity accounts for the dierent crest factor of a WLAN/UMTS signal and
a sinusoidal signal (as explained in A.1). In the worst case the value of is equal to about
9 dB for the WLAN signal and 7 dB for the UMTS signal. In Figure 3.16 the SNR as a
function of the DAC input number of bits is reported for both standards. The minimum
required SNR at the antenna is also indicated. A suitable choice is to x the signal eective
number of bits to 8. This lets a margin of 15 dB for the non-idealities of the other blocks of
the transmitter.
29
80
70
60
UMTS SNR
SNR (dB)
50
WLAN SNR
40
15 dB
30
WLAN SNR limit (64QAM)
20
UMTS SNR limit
10
0
8
10
Input nuber of bits
12
14
Figure 3.16: SNR as a function of DAC input number of bits for WLAN and UMTS.
This level of in-band quantization noise can be obtained with dierent combinations
of DAC input number of bits and conversion frequency. Frequency planning aects also
the digital interpolator lter before the DAC and the analog reconstruction lter following
the DAC (Figure 3.17). A high conversion frequency increases the complexity of the rst
block, a low conversion frequency makes dicult the design of the analog lter. In the
WLAN case, the system-level study shows that with a conversion frequency Fc of 100 MHz
(i.e. 5 times the DSP output rate) a nite impulse response (FIR) interpolator digital lter
can be used between the digital signal processor and the DAC to perform the upsample [16],
while an analog fourth-order Bessel low-pass lter with cut-o frequency of 11 MHz can be
used to suppress the images of the signal around the integer multiples of Fc well below the
emission mask. Moreover a value of Fc equal to 100 MHz sets the oversampling ratio to 5,
giving about 1 bit of additional resolution in the signal bandwidth with respect to the DAC
original resolution. To take a robust design margin we however xed the input number of
bits to 8.
In the case of UMTS the conversion frequency is set to 50 MHz, while the ltering transfer function remains a fourth-order Bessel low-pass, with a cut-o frequency of 2.5 MHz.
The values obtained from the system-level study are conrmed by many works in literature [1719], where the typical values of the DAC conversion frequency are about one
hundred MHz, the DAC number of bits is between 8 and 11 and the ltering is done with
an order between 3 and 4.
The simulation results coming from the system-level study performed with the WLAN
time-domain model are reported as an example. Figure 3.18 shows the spectrum of the
WLAN signal at the output of an ideal interpolator lter increasing the signal sampling frequency from 20 MHz to 100 MHz. The baseband spectrum, whose bandwidth is 10 MHz, is
30
Chapter 3
high DAC conversion frequency

|S|
|S|
FDSP 2F DSP 3F DSP
DIGITAL
INPUT
Fc
0
1
0
1
1
N
digital
interpolator filter
|S|
Fc
analog
filter
|S|
|S|
Fc
ANALOG
OUTPUT
DAC
Fc
1
1
0
0
1
|S|
FDSP 2F DSP 3F DSP
|S|
|S|
Fc
Fc
low DAC conversion frequency
Figure 3.17: Impact of the DAC conversion frequency on the digital interpolator lter and
on the analog reconstruction lter implementation.
50
baseband signal
0
50
Power (dBr)
100
150
200
250
300
350
400
50
100
150
200
Frequency (MHz)
250
300
Figure 3.18: Spectrum of the ideal 100-MHz WLAN signal.
replicated around the multiples of the sampling frequency. Figure 3.19 shows the spectrum
of one of the two components of the WLAN signal at the output of the DAC. The presence
of the 8-bit quantization noise as well as the eect of the sinc attenuation are apparent
in the spectrum. Figure 3.20 shows the spectrum at the output of the analog reconstruction
lter, where the signal replicas are attenuated well below the standard emission mask.
31
20
baseband signal
sinc attenuated replicas
Power (dBr)
20
40
60
80
100
120
50
100
150
200
Frequency (MHz)
250
300
Figure 3.19: Spectrum of the WLAN signal at the output of the 8-bit 100-MHz DAC.
baseband signal
0
attenuated replicas
Power (dBr)
50
100
150
200
0
50
100
150
200
Frequency (MHz)
250
300
Figure 3.20: Spectrum of the WLAN signal at the output of the 4th-order low-pass Bessel
lter.
32
Chapter 3
Considering only the quantization noise from zero to innity, the eect of the Bessel
lter is to enhance the SNR of the WLAN signal from 41 dB (the value at the DAC output)
to 47 dB (which are equivalent to 8 bits and 9 bits respectively, accounting for the WLAN
signal crest factor).
If the signal at the output of the block is compared with an ideal WLAN signal (i.e.
the one coming from a transmitter with no quantization and an ideal 10-MHz low-pass
ltering), the SNDR results in about 32 dB. As we are accounting all the sources of noise
and distortion (quantization noise, signal replicas and in-band amplitude distortion of the
signal provided by the DAC sinc ltering and the low-pass ltering) this value represents
the most pessimistic evaluation of the signal resolution. The in-band amplitude distortion is
the most signicant component in the SNDR, as if we limit the SNDR evaluation from zero
to 10 MHz the obtained value remains unchanged with respect to the previous one. The
value of 32 dB is higher than the SNDR target for the 64-QAM modulation, equal to 25 dB.
The eective number of bits in this case cannot be calculated on the basis of the equivalent full-scale (FS) sinusoidal signal as done before. If we consider only the quantization,
the noise oor is the same for a WLAN input signal and for a sinusoidal input signal, so the
WLAN crest factor can be correctly used to obtain the WLAN signal eective number of
bits. If we account for the distortion components such as the signal replicas or the in-band
amplitude distortion, the use of the equivalent full-scale sinusoidal signal is no longer valid,
as the noise and distortion components relative to the WLAN signal are greater than the
noise and distortion components relative to the sinusoidal signal. The eective number of
bits calculated in this way represent however a worst-case estimation. With 32 dBm we
obtain a value of 6.6 bits. Figure 3.21 shows the overall noise and distortion components of
the error at the lter output. The eect of the quantization noise alone is also indicated.
In the case of an input sinusoidal signal the noise and distortion components are represented by the quantization noise and signal replicas. In the SNDR calculation the eect of
amplitude error caused by the lter transfer function is not taken into account (Figure 3.22).
In this case the SNDR at the lter output is equal to 55.6 dB (9 bits).
In the case of UMTS the low-pass ltering increases the SNR due to the quantization
noise from 43 dB to 53 dB (which are equivalent to 8 bits and 9.7 bits respectively, accounting for the UMTS signal crest factor). The SNDR at the output of the lter calculated
considering all sources of noise and distortion is equal to 32 dB, equivalent to 6.2 bits. As
in the previous case, the dominant source of distortion is represented by the in-band signal
amplitude distortion due to the DAC sinc ltering and the low-pass lter transfer function. In the case of a sinusoidal signal, we obtain a total SNDR at the lter output of 60 dB
(9.7 bits).
The amplitudes of the signals at the output of the DAC and lter come from a systemlevel partitioning of the overall transmitter gain. A suitable dierential signal level at the
DAC output is 700 mVpp , which corresponds to a WLAN signal power of 8 dBm and an
UMTS signal power of 6 dBm, while at the lter output the dierential signal amplitude
is equal to 1.8 Vpp , which corresponds to a WLAN signal power of 0 dBm and an UMTS
signal power of 2 dBm. Thus a lter gain of 8 dB is necessary.
The last parameter considered is the maximum allowable distortion introduced by the
lter, evaluated in terms of IIP3 and IIP2. Figure 3.23 and Figure 3.24 report the SNDR of
the WLAN/UMTS signal at the lter output as a function of the lter IIP3 and IIP2. The
signal amplitudes and the lter gain are the one indicated before. In order to minimize the
eect of the non-linearity on the transmitter, the lter must exhibit an IIP3 of at least 20 dBm
33
0
sinc and filter amplitude distortion
20
40
quantization noise
Power (dBr)
60
signal replicas
80
100
120
140
160
180
50
100
150
200
Frequency (MHz)
250
300
Figure 3.21: Spectrum of the quantization noise and of the overall noise and distortion
components at the output of the lter (WLAN signal).
0
20
40
Power (dBr)
60
80
100
120
140
160
180
200
50
100
150
200
Frequency (MHz)
250
300
Figure 3.22: Spectrum of the quantization noise and distortion components at the output of
the lter in the case of a sinusoidal signal).
34
Chapter 3
35
30
SNDR vs IIP3
SNDR (dB)
SNDR vs IIP2
25
20
15
10
10
20
30
40
50
IIP3 (dBm), IIP2 (dBm)
60
70
Figure 3.23: SNDR of the WLAN signal at the lter output as a function of the lter IIP3
and IIP2.
and an IIP2 of at least 50 dBm. In the two cases the saturation value of 32 dB comes from
the combined eect of quantization noise, signal replicas and in-band amplitude distortion.
The same analysis has been performed for a sinusoidal signal at the input of the DAC.
Figure 3.25 shows the SNDR as a function of the lter IIP3 for the WLAN case and the
UMTS case. The saturation values for high values of IIP3 correspond to the ones indicated
before.
As the test of the baseband block is usually performed not only with real applicationdependent signals, but also with sinusoidal input signals, it is important to relate the IIP3
required performance with other parameters as third-order harmonic distortion (HD3) or
third-order intermodulation distortion (IMD3).
The time-domain models used for the evaluation of the minimum value of IIP3 allows
us to nd the relationship between the lter IIP3 and the output HD3 when a full-scale input
sinusoidal signal is applied at the input of the DAC. This is indicated in Figure 3.26 for
a 3-MHz full-scale input tone in the WLAN case and a 600-kHz full-scale input tone in
UMTS case. In the graph the theoretical value of the HD3 as a function of the lter IIP3 is
also reported. The relationship between HD3 and IIP3 is [20]:
HD3 = 2 IIP3 2 Psig,dBm + 2 Glter,dB + 9 dB,
(3.5)
where Psig,dBm is the power of the sinusoidal signal at the lter output expressed in dBm.
The required value of HD3 at the lter output for the two standards is therefore equal to
about 47 dB.
35
35
30
SNDR vs IIP3
SNDR vs IIP2
SNDR (dB)
25
20
15
10
5
10
20
30
40
50
IIP3 (dBm), IIP2 (dBm)
60
70
Figure 3.24: SNDR of the UMTS signal at the lter output as a function of the lter IIP3
and IIP2.
70
UMTS case (9.7 bits)
60
WLAN case (9 bits)
50
SNDR (dB)
40
30
20
10
0
10
10
20
30
40
IIP3 (dBm)
50
60
70
Figure 3.25: SNDR for a sinusoidal signal at the lter output as a function of the lter IIP3
for the WLAN case and the UMTS case.
36
Chapter 3
80
third harmonic
quantization noise limit
70
60
SFDR (dB)
50
40
30
20
10
0
10
20
30
40
IIP3 (dBm)
50
60
70
Figure 3.26: SFDR for a full-scale 3-MHz sinusoidal signal (WLAN case) and a full-scale
600-kHz sinusoidal signal (UMTS case) at the lter output vs the lter IIP3 (black line).
The theoretical HD3 vs the lter IIP3 is also reported (blue line).
The IMD3 at the output of the baseband block is related to the lter IIP3 by the following
relationship:
(3.6)
IMD3 = 2 IIP3 2 Psig,dBm + 2 Glter,dB ,
where Psig,dBm is the power of each of the two tones at the lter output. Figure 3.27 shows
the IMD3 at the lter output when two 6-dB full-scale sinusoidal signals are applied at the
DAC input as a function of the lter IIP3. It is apparent that the required IMD3 at the block
output is equal to about 50 dB.
Table 3.2 and Table 3.3 summarize the main parameters and required performance for
the DAC and the lter as derived from the system-level study.
90
37
third order distortion
quantization noise
80
70
IMD3 (dB)
60
50
40
30
20
10
0
10
20
30
40
IIP3 (dBm)
50
60
70
Figure 3.27: IMD3 for two 6-dB full-scale sinusoidal signals (1 MHz and 1.5 MHz in the
WLAN case, 100 kHz and 200 kHz in the UMTS case) at the lter output vs the lter IIP3
(black line). The theoretical IMD3 vs the lter IIP3 is also reported (blue line).
Table 3.2: DAC specications for WLAN and UMTS.

Parameter
DAC conversion frequency
Oversampling ratio
WLAN
UMTS
100 MHz
50 MHz
10
Input number of bits
Dierential signal full-scale amplitude

Full-scale application signal power
700 mVpp
8 dBm
Full-scale sinusoidal signal power
6 dBm
1 dBm
49 dBm
49 dBm
Output SNR (application full-scale signal)
41 dB (8 bits)
43 dBm (8 bits)
Output SNR (sinusoidal full-scale signal)
50 dB (8 bits)
50 dB (8 bits)
Output quantization noise power (DC to Nyquist)
38
Chapter 3
Table 3.3: Filter specications for WLAN and UMTS.

Parameter
WLAN
UMTS
Transfer function
Bessel 4th-order, low-pass
Cut-o frequency
11 MHz
2.5 MHz
Gain
8 dB
Dierential signal full-scale amplitude

Full-scale application signal power
1.8 Vpp
0 dBm
Full-scale sinusoidal signal power
2 dBm
9 dBm
Output SNR (application full-scale signal)
47 dB (9 bits)
53 dB (9.7 bits)
Output SNR (sinusoidal full-scale signal)
56 dB (9 bits)
60 dB (9.7 bits)
Required output SNR (application full-scale signal)
41 dB (8 bits)
43 dB (8 bits)
Design margin
6 dB (1 bit)
10 dB (1.7 bits)
Output SNDR (application full-scale signal)
32 dB (6.6 bits)
32 dB (6.2 bits)
Output SNDR (sinusoidal full-scale signal)
55.6 dB (9 bits)
60 dB (9.7 bits)
Required IIP3
20 dBm
20 dBm
Required in-band HD3 @ full-scale
47 dBm
47 dBm
Required IMD3 @ 6-dB full-scale
50 dBm
50 dBm
Required IIP2
50 dBm
50 dBm
Chapter 4
Circuit Design
In this chapter the circuit design of the baseband blocks (device #2) for the WLAN/UMTS
multistandard wireless transmitter is presented. The attention is focused in particular on the
8-bit 100-MHz digital-to-analog converter. The choice of the most suitable architecture to
achieve the performance requirements is presented in Section 4.1. Considerations about the
high conversion frequency and the linearity requirements lead to the choice of a dierential
current-steering fully-thermometric DAC.
The most important design issue is represented by the matching of the unit current
sources realizing the digital-to-analog conversion. Therefore the Pelgrom model for the
matching of transistors is reviewed in Section 4.2. The eect of the mismatch error on each
current source is taken into account in Section 4.3, indicating the relationship between the
DAC integral non-linearity (INL) and dierential non-linearity (DNL) to the relative variance of the mismatch error. An upper bound for the relative variance is then found in order
to obtain INL and DNL yields of 99.9% (Section 4.4). The eect of the current sources
mismatch on the SNDR is then considered, observing that with the chosen relative variance
the degradation of the SNDR is negligible (Section 4.5). Using the Pelgrom model a lower
bound for the transistor area is found, once the overdrive voltage is xed. The power consumption budget xes the value of the unit current, while the headroom constraint, deriving
from the 1.2-V supply voltage, limits the maximum allowable overdrive voltage. The width
and length of the unit current transistor can be found from the Pelgrom relation and the
expression of the transistor saturation current (Section 4.6).
The circuits used to drive the switches of the unit current sources are then described in
Section 4.7, as well as the stage which converts the output current into a voltage signal to be
ltered by the subsequent block (Section 4.8). Comparisons with other conventional output
stages lead to the conclusion that the adopted solution is the one that limits to a minimum
the power consumption, while achieving low static and dynamic distortion. The analog
reconstruction lter which follows the DAC is briey described in Section 4.9.
Simulation results concerning static, dynamic and noise performance are then reported
in Section 4.10, conrming the eectiveness of the adopted design choices.
4.1
Choice of the digital-to-analog converter architecture
The dierence among the variuos types of digital-to-analog converters is basically the output
analog quantity which corresponds to the input digital code. As a matter of fact, the digital
word can be converted into a voltage, a certain amount of charge or a current. Thus three
types of digital-to-analog converters can be distinguished: voltage-scaling DACs, chargescaling DACs or current-steering DACs. For all the types of DACs we assume that the input
40
Chapter 4
digital binary code is is composed by N bits bN1 ...b1 b0 , where bN1 is the most signicant
bit (MSB), b0 is the least signicant bit (LSB) and bi {0, 1} i. The decimal value of the
code is indicated as k and its value is:
k=
N1
2i bi .
(4.1)
i=0
A voltage-scaling DAC usually employs a string of resistances, connected between the

supply voltage and the ground, to generate the analog voltage levels. For an N-bit DAC the
resistive string must have 2N 1 unit resistances (whose value is equal to R) to obtain the 2N
quantized levels. The dierence between the output values corresponding to two successive
codes is indicated as LSB and in this case it is equal to VDD /2N . Two resistances equal to
R/2 are usually added at the top and at the bottom of the string to give to the analog voltage
levels an 1/2 LSB oset. The input digital binary code can select the desired voltage level
among the available ones. As indicated in Figure 4.1, a switch tree selector can be used for
this purpose. The expression for the output voltage is therefore:
Vout (k) =
1 VDD VDD
+ N k.
2 2N
2
(4.2)
The advantages of this type of approach are the high level of regularity, which makes it
suitable for the CMOS integration, and the intrinsic monotonicity oered by the structure.
On the other hand this architecture is very sensitive to the parasitic capacitances connected
to each node, resulting in poor performance in high frequency applications. Moreover the
switch tree selector structure, as well as the needed control lines, increases exponentially
with the number of bits.
The charge-scaling digital-to-analog converter performs the conversion by splitting or
redistributing a given amount of charge within an array of capacitances. An example of
this architecture is shown in Figure 4.2. Two clock phases, indicated as 1 (phase 1) and
2 (phase 2), control a set of switches which connect the capacitances to the ground or to
a reference voltage Vref . During phase 1 all the capacitances of the array are discharged.
During phase 2 the capacitances associated with the bits at high logic level are connected
to Vref , while the ones associated to the bits at low logic level are connected to ground.
Considering the capacive divider composed by the capacitances connected to Vref in series
with the ones connected to ground, the voltage Vout on the output node can be expressed as:

Vref
b0
bN2
Vref
Vout (k) = N
(4.3)
+ ... +
+ bN1
=k N .
2 1
2
2
2
The number of elements of the charge-scaling DAC increases exponentially with the input
number of bits, while the unity capacitance cannot be scaled down below a given limit
because of matching requirements and practical issues. This implies an increase of the
silicon area as well as an increase of the capacitive load for the generator of the reference
voltage.
The current-steering digital-to-analog converter employs a set of binary weighted current sources to make the conversion of the input code into an analog output value. As indicated in Figure 4.3 a switch associated with each current source deviates the current toward
the positive output or the negative one according to the corresponding bit. As the currents
can be switched in an extremely fast way, this architecture is indicated for high conversion
Circuit Design
41
VDD
R/2
b0
b1
b0
b2
R
b0
b1
b0
Vout
b0
b1
b0
b2
b0
b1
R
b0
R/2
Figure 4.1: Scheme of a 3-bit voltage-scaling digital-to-analog converter.
+
C/(2N-1)
...
C/(2N-1)
C/2
C
-
2 b0
2 b0
Vref
2 bN-2
2 bN-2
Vref
2 bN-1
2 bN-1
Vref
Figure 4.2: Scheme of an N-bit charge-scaling digital-to-analog converter.
Vout
42
Chapter 4
Iout(k) = Iout+(k) - Iout-(k)

Iout-(k)
Iout+(k)
bN-1
(2N-1)I
bN-2
b1
b2
...
(2N-2)I
4I
b0
2I
Figure 4.3: Scheme of an N-bit dierential binary current-steering digital-to-analog converter.

frequency applications. As a matter of fact, current-steering DACs are the most used in
wireless transceivers, where high operating frequency and high resolution are required.
Several possible coding schemes can be used for the input digital word. The simplest
solution, as indicated before, is to use a binary code bN1 ...b1 b0 which controls the switches
associated with each current source. The current source relative to the bit bi has the value:
Ii = 2i I,
(4.4)
where I is the current associated with the LSB. The current at the output of the converter in
correspondence of the code k is therefore given by:
+
(k) Iout
(k) =
Iout (k) = Iout
N1
(1)bi Ii =
i=0
N1
(1)bi 2i I = (2N 1 2k)I.
(4.5)
i=0
Being the structure dierential, the analog value of the LSB is equal to two times the unit
current I.
Another possibile coding scheme for the input digital word is to use a thermometric
code. In this case, the input binary word bN1 ...b1 b0 is converted into a thermometric code
t2N 1 ...t1 , i.e. a (2N 1)-bit digital word with a number of high logic levels equal to k. In this
solution there are 2N 1 current sources with a current value equal to I. The thermometric
code controls the switches associated with each current source so that a number of current
sources equal to k is connected to the positive output, while the remaining current sources
are connected to the negative one (Figure 4.4). The resulting output current is given by the
following expression:
+
(k) Iout
(k) =
Iout (k) = Iout
k

i=1
N
2
1
I = (2N 1 2k)I.
(4.6)
i=k+1
Even if the expression of the output current is equal in the case of a binary or thermometric structure, the two solutions dier substantially in terms of the achievable performances.
Circuit Design
43

Iout+(k)
Iout-(k)
t2
t1
...
t2N-3
t2N-2
t2N-1
2N-3
2N-1
2N-2
Figure 4.4: Scheme of an N-bit dierential fully-thermometric current-steering digital-toanalog converter.

Iout (k) = Iout +(k) - I out -(k)
b 9,,b
Iout + (k)
I out -(k)
...
4MSB
DECODER
t 15
t0
t 15
t0
b1
b5
b0
b 5,,b
26I
...
26I
25I
...
2I
...
6LSB
DELAY
b5
15
b0
THERMOMETRIC SECTION
BINARY SECTION
Figure 4.5: Scheme of a 10-bit dierential segmented current-steering digital-to-analog

converter. The 4 MSBs are realized with a thermometric structure, the 6 LSBs are realized
with a binary structure.
The advantage of a binary approach is essentially its simplicity: no decoding logic is necessary as the input code can directly drive the switches associated with each current source.
On the other hand the main drawback of the binary solution is represented by the poor linearity performance. Considering for example the mid-code transition we have that the current
source associated with the most signicant bit must be switched to the positive output, while
the current sources associated with all the other remaining bits must be switched to the negative output. Due to the mismatch error associated with the current sources this transition
can lead to a lack of monotonicity or at least to a strong non-linearity in the transfer char-
44
Chapter 4
acteristic of the DAC. Moreover the errors caused by the dynamic behavior of the switches
can cause glitches in the output signal. This problem is more cumbersome in the case of the
mid-code transition, as all the switches are changing position simultaneously. The glitches
generate spurious components in the frequency domain as well as signal harmonics if they
are correlated with the signal.
The thermometric structure is intrinsically monotonic since when passing from one code
to the successive one a single current source must be switched from one output to the other.
In the case of the mid-code transition only one switch is changing position, with a consequent reduction of the glitches in the output signal. The main disadvantage of the thermometric solution is represented by the presence of the binary-to-thermometric decoder which
can increase substantially the area occupation of the DAC (especially for a number of bits
greater than 8) and the power consumption (especially for high conversion frequencies).
For a value of input number of bits greater than 8 usually a segmented architecture is
adopted. A segmented architecture is a compromise between the binary and the thermometric solution. Usually the DAC is divided in two sub-DACs, one for the MSBs and one for
the LSBs. A thermometric coding is used in the MSBs where it is more important a high
accuracy, while the LSB section is realized with a binary architecture. In Figure 4.5 an example of a segmented 10-bit DAC is shown. The 4 MSBs are realized with a thermometric
coding, while the 6 LSBs with a binary coding.
For the 8-bit 100-MHz digital-to-analog converter described in this chapter a dierential
fully-thermometric current-steering architecture has been chosen, as it is most suitable in
order to achieve the requirements of high conversion frequency and linearity.
4.2
Pelgrom model of the random mismatch
The dierential fully-thermometric architecture chosen in the previous section is implemented at a transistor level realizing each unit current source with an NMOS device biased
in the saturation region. The switches which deviate the unit current toward the positive or
the negative output are realized with a couple of NMOS devices driven by two complementary signals setting the switches in the on or o position (Figure 4.6).
switches
unit current
source
V G,cs
I
Figure 4.6: Transistor implementation of the unit current source and of the couple of corresponding switches.
Circuit Design
45
W
Device A: effective
lengths L A,1 , L A,2 ,...
L A,1
3W
L A,2
Device B: effective
lengths L B,1 , L B,2 ,...
L B,1
3W
L B,2
Figure 4.7: Local variation of the channel length L for two transistors with dierent widths.
The variance in the eective length is less for the device B.
As the technological processes used to realize the transistors are not perfect, equally
designed devices in a single chip will result in having dierent properties. If the values of
the unit current sources are not equal to the ideal one I, an error in converting each code
will result at the output. This implies a loss of eective resolution of the signal at the DAC
output and the presence of unwanted components in the signal spectrum, causing an overall
degradation of the transmitter performance.
This section shows how the matching properties of the current sources can be related to
the characteristics of the transistors implementing them. The basis for mismatch modeling
was proposed in [21] and [22], where the concept of local variation of physical quantities
was introduced (from now on statistical variables are indicated with bold typeface). Considering for example the local variation of the transistor channel length, the uctuation in the
observed length L of the designed transistor depends on the width of the device (Figure 4.7).
The eective length is a random variable whose variance is inversely proportional to W:
2L =
A2L
,
W
(4.7)
where AL is a technological dependent parameter. The same analysis is valid for the transistor width :
A2
2
W
= W.
(4.8)
L
The local variation of parameters such as sheet resistances, channel dopant concentration, mobility and gate oxide thickness has an area dependency, as postulated by Pelgrom
in [23]. Indicating as P the parameter of interest, its variance is inversely proportional to
46
Chapter 4
the area of the transistor through a process dependent parameter AP :

2P =
A2P
.
WL
(4.9)
Qualitatively, local variations decrease as the device size increases since the parameter averages over a greater distance or area.
These technological considerations about the mismatch of physical parameters can be
applied to the expression of the saturation current of a unit current source:
I=
Cox W
(VGS Vth )2 = k (VGS Vth )2 .
2 L
(4.10)
We suppose that the current factor k and the threshold voltage Vth are Gaussian random
variables with mean value k and Vth respectively and variance 2k and 2Vth respectively. As
a consequence the unit current is a random variable with mean value equal to:
I = k (VGS Vth )2 ,
(4.11)
and with relative variance equal to:

2
I

2
k
+4
2Vth
(VGS Vth )
4r
Vth
k
,
k (VGS Vth )
(4.12)
where r is the correlation factor between the two random variables, which can be considered
zero as they depend on dierent physical processes. The variance of the threshold voltage
can be expressed using the Pelgrom relation:
2Vth =
A2Vth
WL
(4.13)
The current factor k is dened as the product of statistically independent random variables,
deriving from dierent physical processes. As a consequence the relative variance of the
current factor is given by:

2
k

2
W

2
L

+
Cox
Cox
2

+
2
.
(4.14)
The mismatch properties of the gate oxide capacitance and of the mobility are treated in
accordance with the Pelgrom model, while for the variance of the transistor dimensions the
Equations (4.7) and (4.8) are used, obtaining:

2
k
2 2 2 2
A2
A A AC A
k .
= 2W + L 2 + ox +
WL
WL
WL
W L
WL
(4.15)
If we substitute the expressions (4.13) and (4.15) in (4.12) we obtain the relative variance
of the unit current as a function of the transistor dimensions and of the overdrive voltage
VGS Vth used:
A2Vth
1
2
Ak + 4
=
.
(4.16)
WL
I
(VGS Vth )
Circuit Design
47
In our technology, Ak is equal to 0.0132 m and AVth is equal to 4.5 mVm. It is clear that if
we x the maximum value of the unit current source relative variance, we can x for a given
overdrive voltage the minimum area of the transistor constituting the unit current source:
A2Vth
2
(WL)min =
Ak + 4
.
(4.17)
2
(/I)2max
(VGS Vth )
The maximum allowable value of the unit current source mismatch can be estimated
considering its eect on the analog output values corresponding to the input codes. Mismatch errors cause non-linearity in the transfer characteristic of the digital-to-analog converter, which in turn determines distortion on the output signal.
4.3
Eect of the current sources mismatch on the INL and

DNL
In the presence of random mismatch, each current source of the fully-thermometric structure (I1 , I2 , ..., I2N 1 ) can be modeled as a Gaussian random variable with mean value equal
to I and variance equal to 2 . I represents the ideal value of the current sources without
mismatch. The two random variables In and In are supposed statistically independent for
each couple of n and n (we are supposing to neglect the presence of process gradients).
Similarly the dierence between the value of the current source In and the ideal value I is a
random variable with mean value equal to zero and variance equal to 2 . This random variable is indicated as n and the two random variables n and n are statistically independent
for each couple of n and n . As indicated in Figure 4.8 the random mismatch corresponds
to the presence of an error current source n in parallel with each ideal current source I.
Considering the eect of random mismatch, the Equation (4.6) expressing the output
current for a dierential fully-thermometric structure in correspondence of the code k is

Iout-(k)
Iout+(k)
t2N-2
t2
t1
I
1
I
2
...
I
2N-2
t2N-1
2N-2
2N-1
2N-1
Figure 4.8: Scheme of an N-bit dierential fully-thermometric current-steering digital-toanalog converter with random mismatch on the unit current sources .
48
Chapter 4
modied in the following way:

Iout (k)
+
Iout
(k)
Iout
(k)
k
Ii
i=1
(2N 1 2k)I +
N
2
1
Ii =
i=1
N
2
1
(I + i )
i=1
i=k+1
k
k
N
2
1
(I + i ) =
i=k+1
i .
(4.18)
i=k+1
The rst term in (4.18) is the ideal output current of the DAC, i.e. the output current without
error on the unit current sources, while the second term represents the error introduced by
the current sources mismatch:
(k) =
k

i=1
N
2
1
i .
(4.19)
i=k+1
The error (k) introduced in converting the code k is a Gaussian random variable with mean
value equal to zero and variance equal to (2N 1)2 . The two random variables (k) and
(k ) are statistically dependent for each couple of codes k and k , as they are dened on the
same set of random variables 1 , ..., 2N 1 .
If compared with an ideal DAC, i.e. a DAC not aected by mismatch errors on the unit
current sources, the real DAC has an oset error given by:

(4.20)
oset = Iout (0) (2N 1)I .
Dening as DAC gain the dierence between the last analog output value (the one corresponding to the code 2N 1) and the rst one (corresponding to the code 0), the ratio
between the ideal DAC gain and the real DAC gain is given by:
gain =
(2N 1)2I
.
Iout (2N 1) Iout (0)
(4.21)
The value of the integral non-linearity for each code can be calculated eliminating from
the output values Iout (k) the oset and gain errors, as indicated in Appendix A.2 and A.3,
and comparing the corrected values with the ideal ones:

(4.22)
INL(k) = gain Iout (k) (2N 1)I gain Iout (0) Iout,id (k).
Expressing the INL in LSB units we obtain:
(2N 1)
INLLSB (k) = 2N 1
Ii k.
i=1 Ii i=1
k
(4.23)
After rst-order approximations the Equation (4.23) can be rewritten as:

N

k
2
1
k
i
2N 1 k i
INLLSB (k) =
N
.
2N 1 i=1 I
2 1 i=k+1 I
(4.24)
The dierential non-linearity in LSB units can be calculated in a similar way, obtaining the
following expression:
DNLLSB (k) =
N

2
1
1
i
2N 1 k k
.
2N 1
I
2N 1 i=1,ik I
(4.25)
Circuit Design
49
Since INLLSB (k) and DNLLSB (k) are both linear combination of 2N 1 independent random
variables (1 , ..., 2N 1 ) with normal distribution, they follow also normal distribution for
each k. As a matter of fact we have that INLLSB (k) has mean value equal to zero and
variance dependent on k equal to:
(2N 1 k)k
2
2INLLSB (k) =
,
(4.26)
2N 1
I
while DNLLSB (k) has mean value equal to zero and variance equal to:
(2N 1 1)
2
.
2DNLLSB (k) =
2N 1
I
(4.27)
From the expressions given above we have that the maximum standard deviation for the
INL it is located at the mid-code and it is equal to:

1
1
.
(4.28)
2N 1 N
INLLSB (k) max =
2
2 1 I
The standard deviation of the DNL is independent of the code k and it is smaller than the
maximum value of the INL standard deviation, as it is approximately equal to the relative
standard deviation of the unit current source:

.
(4.29)
DNLLSB (k)
I
As an example in Figure 4.9 Montecarlo simulations of a Matlab model of an 8-bit differential fully-thermometric DAC aected by random mismatch are shown. The standard
deviation of INLLSB (k) and DNLLSB (k) with a 2% relative standard deviation for the unit
current sources are reported. In accordance with Equations (4.28) and (4.29), we note that
the maximum value of the INL standard deviation is equal to 0.16 LSB, while the value of
DNL standard deviation is equal to 0.02 LSB.
4.4
INL and DNL yield
Usually the adopted design approach when dealing with the current sources mismatch in
a DAC is to ensure that a given percentage of the fabricated devices satises the linearity
requirements. The parameters which are used in this approach are the INL and DNL yield.
The INL yield is dened as the probability that the integral non-linearity is less than a
given value (usually 0.5 LSB) for each code k at the input of the DAC:

(4.30)
INLyield = Prob |INLLSB (k)| < 0.5 k = 0, ..., 2N 1 .
A similar denition holds for the DNL yield:

DNLyield = Prob |DNLLSB (k)| < 0.5 k = 1, ..., 2N 1 .
(4.31)
The two random variables INLLSB (k) and INLLSB (k ) are statistically dependent, as they
are dened on the basis of the same set of random variables 1 , ..., 2N 1 . As a consequence we should calculate the joint probability density function for the 2N random variables INLLSB (2N 1), ..., INLLSB (0) and then integrate this function in a N-dimensional
space:
0.5
0.5
0.5
dx0
dx1 ...
dx2N 1 pdf(x0 x1 x2N 1 ).
(4.32)
INLyield =
0.5
0.5
0.5
50
Chapter 4
0.16
X
INL
(k)
LSB
0.14
0.1
0.08
XINL
LSB
(k)
,XDNL
LSB
(k)
0.12
0.06
0.04
X
DNL
0.02
0
(k)
LSB
50
100
150
200
Input code (0,..,255), Transition between codes (1,...,255)
250
Figure 4.9: Standard deviation of INLLSB (k) and DNLLSB (k) for an 8-bit dierential fullythermometric DAC with a unit current relative standard deviation /I equal to 2%.
No one has reported a method for accurately calculating the integral (4.32) without using
numerical methods. Lakshmikumar has presented two rough bounds for the INL yield in
binary-weighted DACs [24, 25]. One is pessimistic ignoring the strong correlation between
dierent analog outputs and the other is rather optimistic only considering the contribution
of the two mid-scale codes. The limitations of the two bounds were clearly shown in [26].
Another formula proposed by Bosh [27] for the INL yield is based on a non-standard INL
denition where each output value is compared to the ideal one without correcting the oset
and gain errors. As a result with this approximated formula the matching accuracy of the
unit current sources is overestimated and this, as we will see in the next Section, leads to
the overdimensioning of the unit current source area.
We decided to exploit numerical calculation to correctly estimate the required matching. Through Matlab Montecarlo simulations we can obtain the relation between the INL
and DNL yield and the unit current source relative standard deviation (namely /I). The
results for an 8-bit dierential fully-thermometric digital-to-analog converter are shown in
Figure 4.10. As it is apparent in the detail of Figure 4.11, in order to ensure an INL yield
of 99.9%, a unit current source relative standard deviation of 1% is necessary. This in turn
ensures even a better value of DNL yield. From the equation obtained in the previous section, this implies a maximum value of the INL standard deviation of 0.08 LSB and a DNL
standard deviation equal to 0.01 LSB.
Circuit Design
51
1
DNLyield
0.9
INL
0.8
yield
DNL
yield
,INL
yield
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
3
10
10
10
Unit current relative standard deviation
10
Figure 4.10: INL yield and DNL yield as a function of the unit current source relative
standard deviation for an 8-bit dierential fully-thermometric DAC.
0.95
INLyield
0.9
0.85
0.8
0.75
0.7
0.01
0.015
0.02
0.025
Figure 4.11: Detail of the INL yield as a function of the unit current source relative standard
deviation for an 8-bit dierential fully-thermometric DAC.
52
4.5
Chapter 4
Eect of the current sources mismatch on the SNDR
In this section we consider the eect of the unit current source mismatch on the SNDR,
following the approach suggested in [28] for the case of a binary single-ended structure. As
indicated in Section 4.3, the total output error introduced by the mismatch on the unit current
sources in a dierential fully-thermometric DAC follows a normal distribution with mean
value equal to zero. The variance is independent of the code k and it is equal to (2N 1)2 .
If the error introduced for each code is corrected from the oset and gain terms (which do
not contribute to distortion), its value is indicated as INL(k). The variance for the random
variable INL(k) is dependent on the code k and it is equal to:
2INL(k) = (2I)2 2INLLSB (k) = 4
(2N 1 k)k 2
.
2N 1
(4.33)
Suppose that we apply at the input of the digital-to-analog converter an N-bit sinusoidal
sequence of codes, indicated as k(t). The mean value of k(t) is equal to (2N 1)/2, the period
of the input sequence is M samples and the amplitude is equal to the full-scale (2N 1). The
sampling frequency of the input codes is indicated as Fc . In the ideal case the input codes are
converted into the corresponding analog output values and the SNDR of the output signal
will be limited by the quantization noise.
In the DAC aected by mismatch, the ideal output signal is summed with an error contribution which depends on the code that is applied at the input. The spectrum of the resulting
output signal will present distortion components which limit its eective resolution. Due to
the gain and oset errors in the transfer characteristic of the real digital-to-analog converter,
the sinusoidal signal at the DAC output will have also a dierent amplitude and mean value
with respect to the ideal one. However these eects are usually ignored when the SNDR of
a sinusoidal signal is calculated. Therefore we consider as mismatch error components the
values INL(k) corrected from the gain and oset terms. In this way we are only accounting
for the distortion components coming from the transfer characteristic of the real DAC.
If we consider a sampled signal in which the amplitude of each sample is a random
variable with mean value equal to zero and variance 2 , the integral of its power spectral
density between 0 and the Nyquist frequency Fc /2 is equal to 2 . In the case of the error
contribution coming from the unit current source mismatch, we have at the DAC output a
sampled signal in which the amplitude of each sample is a random variable whose variance
is function of the corresponding code at the input of the DAC. The result is a time-dependent
expression for the variance of the error samples:

2N 1 k(t) k(t)
2
(4.34)
2 .
INL(k) (t) = 4
2N 1
Note that for the sake of simplicity we are ignoring the eect of the zero-order-hold introduced by the conversion of the input codes into analog values. The code-averaged variance
of the mismatch errors can be expressed as:
M 2N 1 k(t) k(t)
1
2N 1 2
2
2
4
dt
=
(4.35)
.
mean =
M 0
2N 1
2
This value represents the total power Pm of the distortion components coming from the unit
current source mismatch between 0 and the Nyquist frequency.
Circuit Design
53
55
50
SNDR (dBc)
45
40
35
30
25
20
4
10
10
10
10
10
Figure 4.12: SNDR as a function of the unit current source relative standard deviation for an
8-bit dierential fully-thermometric DAC as obtained from Matlab Montecarlo simulations
(thick line) and from Equation (4.38) (thin line with markers).
At the output of the DAC the power of the ideal sinusoidal signal is:

2
2N 1 (2I)2
.
Psig =
8
(4.36)
Being the LSB of the dierential structure equal to 2I, the power of the quantization noise
between 0 and the Nyquist frequency is given by:
Pqn =
(2I)2
.
12
(4.37)
Adding to the quantization noise the contribution due to the mismatch errors on the unit
current sources given by the Equation (4.35), we have that the total SNDR of the signal at
the output is given by:
2

2N
2N 1 (2I)2 /8
Psig
=0 2 12
=
.
(4.38)
SNDR =
N
2
2
Pq + Pm (2I) /12 + 2 1 /2
8
Figure 4.12 shows the SNDR as a function of the unit current source relative standard deviation for an 8-bit dierential fully-thermometric DAC as obtained from (4.38) and from
Matlab Montecarlo simulations, with 100 runs for each value of /I. We can conclude that
the value of 1% of the unit current source relative standard deviation, which was the limit
xed in Section 4.3 for an INL and DNL yield of 99.9%, causes a degradation in the SNDR
with respect to the ideal value of less than 1 dB, which can be considered negligible.
54
4.6
Chapter 4
Dimensioning of the unit cell
The rst design choice for the transistor-level dimensioning of the DAC unit cell is the one
concerning the value of the unit current. This choice is a trade-o between the total current
consumption of the DAC and the achievable conversion frequency. The total budget of
power consumption assigned to the DAC in the system-level study of the TX chain leads us
to set the unit current to a value of 5 A. The current consumption for the 255 unit cells is
therefore equal to 1.275 mA.
As explained in Section 4.2, the mismatch performance of the transistors realizing the
unit current sources depends on the occupied area and on the overdrive voltage Vov . Moreover, once the maximum allowable relative variance which ensures a certain INL yield and
SNDR target is found, the minimum area of the transistor is xed for a given overdrive voltage (Equation 4.17). The choice of Vov is a trade-o between the low sensitivity to threshold
voltage mismatch (which would require a large Vov ) and the available headroom from the
1.2-V supply (which limits the maximum value of Vov ). As the switches on the top of each
current source must act as cascode transistors when they are in the on state, we have to ensure that both transistors are in the saturation region. As a consequence the sum of the two
overdrive voltages (Vov and Vov,sw ) must be less than the minimum voltage Vout,min present
on the output node:
(4.39)
Vov + Vov,sw Vout,min .
Moreover a design margin Vsafe must be taken with respect to the maximum overdrive
voltages to prevent the transistors to enter in the triode region under worst case conditions
of temperature, supply voltage and process parameters:
Vov + Vov,sw = Vout,min Vsafe .
(4.40)
As explained in the following, the output stage of the DAC, converting the current signal
into a voltage, is such that the minimum voltage at the output node is equal to the analog
ground (600 mV) minus the amplitude of the single-ended voltage signal (175 mV). A
design margin Vsafe equal to 180 mV has been chosen so that the sum of the two overdrive
voltages must be equal to 245 mV.
In order to minimize the entity of the glitches injected on the output nodes during the
switching of the unit current, the dimensions of the switches are set to the minimum values
allowed by the technology (Wsw = 0.5 m and Lsw = 0.13 m). Once the dimensions of the
switches are xed, the current owing when they are in the on state determines the overdrive
voltage:

I
.
(4.41)
Vov,sw =
C W
ox
sw
Lsw
With the technology current factor k equal to 380 A/V2 and with the chosen unit current,
we obtain a value of Vov,sw equal to 85 mV.
The remaining available voltage swing is assigned to the current source overdrive voltage Vov , which is xed to 160 mV. As the threshold voltage of the NMOS devices is 280 mV,
the voltage VG on the current source gate must be equal to 440 mV. The area WL of the
transistor implementing the unit current source can be found from Equation 4.16. With the
technology mismatch parameters indicated in Section 4.2 and with a value of /I equal to
1%, we obtain an area of 36 m2 . Moreover, the unit current of 5 A and the value of the
overdrive voltage indicated before determine an aspect ratio (W/L) of the transistor equal to
Circuit Design
55
V out,min= 425 mV
switches
V G,sw = 785 mV
W sw = 0.5 m
L sw = 0.13 m
320 mV
V D,cs= 320 mV
W = 6 m
V G = 440 mV
L = 6 m
unit current source
I = 5 A
Figure 4.13: Unit cell design values.

1. We can conclude that the unit current source must have a width of 6 m and a length of
6 m.
The voltage VG,sw on the gate of the switch in the on position is chosen with the aim
of giving to the transistors a margin to avoid the triode region. The threshold voltage of
the adopted scaled-down technology strongly depends on the channel length, passing from
280 mV for long channel devices to 380 mV for minimum length (0.13 m) devices. This
determines a value of the switch gate-to-source voltage VGS,sw equal to about 465 mV. As
the unit current source must be in the saturation region, this implies a minimum value for
the switch gate voltage:
(4.42)
VG,sw,min = Vov,cs + VGS,sw .
On the other hand increasing the switch gate voltage to higher values pushes the switch in
the on position toward the triode region. The maximum value for the switch gate voltage is
therefore:
(4.43)
VG,sw,max = Vout,min + Vth,sw .
As a consequence the allowable values for the switch gate voltage are included between
625 mV and 805 mV. We choose to give more design margin to the transistor realizing the
unit current source. The value of VGS,sw is therefore xed to 785 mV.
In order to minimize the amplitude of the glitches in the output nodes, the signals driving
the switches associated with each current source must exhibit a reduced swing. In this way
the charge injection is limited to a minimum value. The gate of the switch in the o state
cannot be higher with respect to the common source than a threshold voltage. This implies
that the minimum dierence between the driving signals must be at least equal to the switch
overdrive voltage. Moreover a design margin must be taken with respect to this value to
avoid that both switches are in the on state during the switching instants. A suitable value
of 320 mV is chosen for the gate voltage of the switch in the o state.
Figure 4.13 summarizes the design values of the DAC unit cell, while Figure 4.14 illustrates the adopted design ow.
56
4.7
Chapter 4
Driving circuits
The switches of each unit cell are driven with low swing signals, according to the thermometric code coming from the binary-to-thermometric decoder. The scheme of the driving
circuit is shown in Figure 4.15. A latch resynchronizes the signal coming from the decoder
and drives an analog multiplexer which passes at the output the high level (785 mV) or the
low level (320 mV), thus switching the unit cell current toward the positive output node or
the negative one. The choice of the number of driving circuits is a trade-o between power
consumption and dynamic performance. The use of one driver for each unit cell ensures less
coupling between the dierent cells during the switching and consequently less glitches on
the output nodes. Being the linearity performance of primary concern, one driver biased
with a 5 A current for each unit cell is used .
4.8
DAC-lter interface
The interface between the DAC and the following reconstruction lter represents one of the
most critical issue in the design. Conventional solutions for the output stage of a DAC use
output load resistors or a transimpedance stage to convert the output current signal into a
voltage one [2931].
The drawback of the rst approach (Figure 4.16) is that the common mode of the output
voltage signal is dierent from the analog ground (VDD /2) and a power consuming level
shifter is so necessary to provide to the following block the correct input. In the second
solution (Figure 4.17) the output current of the DAC is sent to the virtual ground of an
opamp (which can be a simple transimpedance stage or the rst ltering stage). This ensures
INL yield = 99%

DNL yield = 99%
effect of mismatch
on the SNDR
Pelgrom model
maximum relative
standard deviation of the
unit current source
minimization of the
glitches
minimum dimensions
for the switches
Wsw = 0.5 um,
Lsw = 0.13 um
headroom constraint
current consumption
budget
unit current I = 5 uA
switch overdrive voltage

Vov,sw = 60 mV
current source overdrive

voltage Vov,sw = 200 mV
current source
aspect ratio
current source area
W = 6 um, L = 6 um
Figure 4.14: Adopted design ow for the dimensioning of the unit current cell.
Circuit Design
57
LATCH 1
DRIVER 1
MULTIPLEXER 1
UNIT CELL 1
VDD
from
decoder
D
Q1
Q1
Vhigh
Q1neg
CK
Q1neg
VB2
Q1neg
Vlow
Q1
VB1
VG,cs
Idriver
clock latch
...
LATCH 255
DRIVER 255
MULTIPLEXER 255
UNIT CELL 255
VDD
from
decoder
D
Q255
Vhigh
Q255
Q255neg
CK
Q255neg VB2
Vlow
Q255neg
Q255
VB1
clock latch
Idriver
VG,cs
Figure 4.15: Scheme of the driving circuit for each unit cell.
that the output node of the unit current sources is kept stable by the virtual ground, thus
ensuring a low contribution of the current sources output impedance to the overall signal
distortion. Nevertheless this approach implies that the output current of the DAC must
be supplied by the transimpedance stage. Moreover the opamp must be able to drive the
feedback resistances with high linearity and this implies an increase in power consumption.
The adopted solution is shown in Figure 4.18. Two load resistors RL are placed between
the positive and the negative output node of the DAC, with two PMOS current sources that
set the common mode output current of each branch to zero. This allows us to decouple the
DAC output current from the output current of the following reconstruction lter, which can
be designed to be much smaller than the rst one. As a consequence, to achieve the desired
output swing at the lter output, large resistors in the lter structure have been used, and
the lter input impedance is much higher than RL . This power consumption reduction is
obtained at the cost of a larger thermal noise in the lter, which, however, has be designed
to be negligible with respect to the quantization noise.
The common mode of the output single-ended voltages is xed to the analog ground
through a common-mode feedback (CMFB) acting on the top PMOS devices. The maximum swing on each of the output nodes is xed to 350 mVpp around the analog ground as
a trade-o between having a signicant input signal for the following lter and introducing
a negligible signal distortion due to the current source output impedance, which is anyway
relatively large thanks to the cascoding action of the current switches, as mentioned above.
This choice implies a value of 300 for each of the two output resistances, considering
that the full-scale dierential current is equal to 1.275 mApp . The CMFB is implemented
58
Chapter 4
VDD
RL
RL
Vout+ (k)
Iout
t1
+(k)
Iout
t2
...
Vout- (k)
-(k)
t2N-2
t2N-1
2N-2
2N-1
Figure 4.16: Conventional DAC output stage with two load resistors toward VDD .
RL
VDD
(2N-1) I
2
(2N-1) I
2
t1
t2N-2
t2
Iout+(k)
Vout+ (k)
Iout-(k)
Vout- (k)
t2N-1
RL
I
1
I
2
...
I
2N-2
I
2N-1
Figure 4.17: DAC output stage with a transimpedance stage to convert the output current
into a voltage.
Circuit Design
600 mV
59
V DD
+
(2N-1) I
2
RL
(2N-1) I
2
RL
Vout+ (k)
Vout- (k)
t2
t1
I
1
...
t2N-2
t2N-1
2 N-2
2 N-1
Figure 4.18: Adopted DAC output stage.

comparing the voltage of the common node between the two resistances with the analog
ground and controlling the bias voltages of the two PMOS devices.
To compare the eectiveness of the adopted DAC output stage with respect to the transimpedance stage, the static integral and dierential non-linearity of the DAC transfer characteristic have been evaluated in the two cases. Figure 4.19 and Figure 4.20 show the obtained results for the INL and DNL respectively. As expected due to the presence of the virtual ground, the achieved linearity in the transimpedance case is better than in the adopted
solution. Nevertheless the maximum value of INL (equal to 0.06 LSB) obtained with the
output resistances is such that it causes a negligible distortion on the output signal.
The current I is generated with the bias circuit shown in Figure 4.21, which makes I
equal to Vref /RB . The resistance RB is matched with the load resistances RL in order to make
the ratio RB /RL constant. This reduces the dependence of the DAC output voltage amplitude
on the technology spread of uncorrelated features (MOS parameters and resistances).
4.9
Analog reconstruction lter
The analog reconstruction lter has been placed after the digital-to-analog converter in order to eliminate the DAC spectral images. The lter has been designed at the Department
of Innovation Engineering of University of Lecce [5]. The 4th-order Bessel low-pass reconstruction lter has been designed to satisfy the bandwidth requirements of the two considered standards, as required to implement a programmable device. In addition particular care
was taken in reducing power consumption.
The lter is realized with the cascade of two identical multipath active-RC biquads (Figure 4.22). Active-RC allows us to achieve a suciently large linear range, while the use of
60
Chapter 4
0.06
resistances solution
0.04
LSB
0.02
0
transimpedance solution
0.02
0.04
0.06
50
100
150
Input code (0,...,255)
200
250
Figure 4.19: Integral non-linearity for the solution with output resistances and the solution
with the transimpedance stage.
3
1.5
x 10
resistance solution
1
0.5
0
LSB
transimpedence solution
0.5
1
1.5
2
2.5
3
50
100
150
200
Transition between codes (1,...,255)
250
Figure 4.20: Dierential non-linearity for the solution with output resistances and the solution with the transimpedance stage.
Circuit Design
61
VDD
RB
Vout- (k)
...
RL
...
...
Vout+ (k)
RL
+
Vref
VDD
...
BIAS CIRCUIT
CELL 1
CELL 255
Figure 4.21: Circuit for the unit current generation.
a single opamp to synthesize two poles reduces power consumption. In this structure the
opamp bandwidth has to be about 50-100 times higher than the lter poles. The used opamps
are based on a fully-dierential Miller-compensated two-stage topology, which allows railto-rail output swing. The full-scale dierential output voltage of the baseband block must
be 1.8 Vpp for the two standards, which means a lter DC gain of about 8 dB, considering
the DAC dierential output swing of 700 mVpp . The opamp bandwidth is reduced for the
lower lter cut-o frequency used in the UMTS case by reducing the bias current. As a
consequence also the power consumption is reduced when the UMTS transmission mode is
set.
The lter transfer function can be programmed for two bandwidth values, 11 MHz and
2.5 MHz, to satisfy the WLAN and UMTS standards respectively. This is obtained through
a selection bit (BS), which digitally controls the value of the resistors, and, accordingly,
the in-band noise oor. The smaller band for the UMTS standard (obtained with larger
resistance values) can accept the consequent larger noise oor. The choice of programming
the cut-o frequency with the resistance values allows us to reduce the power consumption
for low bandwidth, as the required output swing can be obtained with lower current. For
the WLAN case the lter current consumption results in 4.7 mA, while for the UMTS it is
equal to 2.5 mA.
The selection switches have been introduced carefully in order to limit their parasitic
eects. The switches are indeed connected to virtual ground nodes (opamp inputs, with
a limited voltage swing on the parasitic capacitances) or to low impedance nodes (opamp
outputs). In addition the values of the capacitors can be adjusted within 35% with a 4-bit
62
Chapter 4
BS
BS
BS
+
VIN
V CM
VOUT
-
BS
BS
BS
BS
Filter Stage
Figure 4.22: Single stage of the 4th-order Bessel low-pass lter.
digital word in order to control the technology spread or to allow a ne selection of the lter
bandwidth.
Finally, the implemented lter structure allows also the optimization of the area occupation. The change of the lter operation mode implies only the change of the resistance
values and of the opamp bias currents, as described, while all the capacitors and the opamp
transistor sizes remain the same. The sharing of all the capacitors for the two standards minimizes the overall lter area which is usually dominated by these capacitors. Figure 4.23
and Figure 4.24 show the programmable lter transfer function for the two considered standards, while Table 4.1 summarizes the main features of the implemented lter.
4.10
Simulation results
This section presents the simulation results of the baseband block, with all the blocks implemented at a transistor level. The eect of the pads and of the parasitic inductances associated
with the bonding wires is also taken into account.
The functionality of the designed unit cell and of the driving circuits switching the current toward the positive or the negative output is veried with a 10-MHz input tone sampled
at 100 MHz and quantized with 8 bits. The chosen frequency represents the maximum
value in the case of the WLAN standard and therefore the worst operating condition for the
dynamic behavior of the circuitry. Figure 4.25 shows the signals driving the switches of a
unit cell, coming from the cascade of the driver and multiplexer block. Figure 4.26 shows
the signals present at the DAC output and the voltages on the gate and drain nodes of a unit
Circuit Design
63
20
0
20
Gain (dB)
40
60
80
100
120
140
160
4
10
10
10
10
Frequency (MHz)
10
10
Figure 4.23: Programmable lter transfer function (WLAN setting).
Gain (dB)
50
100
150
200
250
4
10
10
10
10
Frequency (MHz)
10
10
Figure 4.24: Programmable lter transfer function (UMTS setting).
64
Chapter 4
Table 4.1: Features of the analog reconstruction lter.

Parameter
Value
Technology
CMOS 0.13 m
Supply voltage
1.2 V
Architecture
4th-order Bessel low-pass
DC gain
8 dB
Standard
WLAN
UMTS
Cut-o frequency
11 MHz
2.5 MHz
Current consumption
4.7 mA
Full-scale dierential output swing
2.5 mA
1.8Vpp
current source. Finally in Figure 4.27 the currents owing through the switches of a unit
cell are reported.
The eectiveness of the dimensioning of the unit current sources in terms of the mismatch performance has been veried with Montecarlo simulations of the static integral and
dierential non-linearity of the digital-to-analog converter. Figure 4.28 shows the standard
deviation of the INL and DNL when 5 runs of Montecarlo simulations are performed on
the DAC. The obtained maximum values of the INL and DNL standard deviation (about
0.05 LSB and 0.006 LSB respectively) are in accordance with the one predicted by the
0.9
0.8
Voltage (V)
0.7
0.6
0.5
0.4
0.3
0.2
50
100
Time (ns)
150
200
Figure 4.25: Transient waveforms of the signals driving the switches of a unit cell.
Circuit Design
65
0.9
V
out,pos
0.8
out,neg
Voltage (V)
0.7
0.6
0.5
V
G,cs
0.4
0.3
0.2
D,cs
50
100
Time (ns)
150
200
Figure 4.26: Transient waveforms of the signals at the DAC output and of the voltages on
gate and drain nodes of a unit current source.
8
7
6
Current (RA)
5
4
3
2
1
0
1
50
100
Time (ns)
150
200
Figure 4.27: Transient waveforms of the currents owing through the switches of a unit cell.
66
Chapter 4
design.
The performance of the digital-to-analog conversion and of the successive reconstruction ltering are veried by applying at the input of the DAC a full-scale tone or two
6-dBFS tones, with the DAC conversion frequency set to 100 MHz for WLAN and to
50 MHz for UMTS. In the rst case the SFDR at the output of the DAC and of the lter is
evaluated. With the WLAN setting a frequency of 3 MHz has been chosen in order to have
the third harmonic of the signal included in the lter bandwidth. The intermodulation test
on the contrary can be performed with two frequencies near the WLAN signal bandwidth.
If the two tones are suciently near in frequency, the third-order intermodulation products
fall close by and the IMD3 can be evaluated without the eect of the lter attenuation. From
both tests the value of the OIP3 and of the IIP3 of the blocks can be extrapolated.
Figures 4.29, 4.30, 4.31 and 4.32 show the spectra at the output of the DAC and of
the lter when a full-scale 3-MHz single tone is applied at the input. The WLAN operation mode is set in this case (100-MHz DAC conversion frequency, 11-MHz lter cut-o
frequency). Being the output of the DAC and of the lter two analog signals, the waveforms are sampled by the simulator with a frequency much higher than the DAC conversion
frequency, in order to distinguish the frequency-domain eects of the block non-idealities
(glitches, output resistance, harmonic distortion). Moreover the frequency of the input sampled sinusoidal signal is chosen in a way that the 100-MHz input samples are taken from
a prime number of sinusoidal periods. In this way we ensure that the error associated with
the 8-bit quantization is not periodic into the sequence of samples applied at the DAC input
(otherwise we would see tones associated with the quantization noise at the DAC output).
At the DAC output, the SFDR between 0 and the Nyquist frequency (50 MHz) is dominated by the third-order harmonic and it is equal to 61 dB, while the SNDR is equal to
50.5 dB (8 bits). This values increase to 55 dB (8.8 bits) in the WLAN signal bandwidth
(between 0 and 10 MHz). The power of the signal at the DAC output is equal to 1 dBm
(700 mVpp ), as expected from design.
The SFDR at the output of the lter is equal to 56 dB, while the SNDR calculated
between 0 and innity is equal to 52.2 dB (8.4 bits). The same value can be obtained if
the SNDR is calculated between 0 and 50 MHz, while in the signal bandwidth it is equal to
53.2 dB (8.5 bits). Moreover from Figure 4.31 we can see that the signal replicas around
the DAC conversion frequency are attenuated of about 77.5 dB. The power of the signal at
the lter output is equal to 9 dBm (1.8 Vpp ), as expected from design.
The intermodulation tests have been performed with two 6-dBFS input tones, with frequencies equal to 8.2 MHz and 9 MHz (Figure 4.33 and Figure 4.34). The intermodulation
products at the DAC output do not raise over the quantization noise oor due to the limited
length of simulation input codes (2048). Nevertheless we can conclude that the IMD3 at the
DAC output is better than 68 dB. The IMD3 at the lter output is equal to 58.3 dB.
Finally the noise performance of the cascade of two blocks has been veried with noise
simulations. Figure 4.35 shows the output noise power spectral density at the lter output
when the WLAN mode is set. The power spectral density integrated between 0 and innity
gives a noise power of 6 nW (on a 50 resistor), corresponding to 52 dBm. This value is
lower than the quantization noise power which is present in the lter bandwidth.
Circuit Design
67
0.06
0.05
0.03
XINL
LSB
(k)
,XDNL
LSB
(k)
0.04
0.02
0.01
50
100
150
200
Input code (0,...,255), Transition between codes (1,...,255)
250
Figure 4.28: Simulated standard deviation of INLLSB (k) and DNLLSB (k).
baseband signal
Power (dBm)
signal replicas
50
100
150
50
100
150
Frequency (MHz)
200
250
Figure 4.29: Spectrum of the signal at the DAC output with a full-scale 3-MHz single tone
at the input (WLAN setting, FFT frequency bin of 48 kHz).
68
Chapter 4
10
0
10
Power (dBm)
20
SFDR = 61 dB
30
40
50
60
70
80
90
100
10
20
30
Frequency (MHz)
40
50
Figure 4.30: Spectrum of the signal at the DAC output with a full-scale 3-MHz single tone
at the input (WLAN setting, FFT frequency bin of 48 kHz).
20
baseband signal
0
20
attenuated signal replicas
Power (dBm)
40
60
80
100
120
140
0
50
100
150
Frequency (MHz)
200
250
Figure 4.31: Spectrum of the signal at the lter output with a full-scale 3-MHz single tone
at the DAC input (WLAN setting, FFT frequency bin of 48 kHz).
Circuit Design
69
20
0
SFDR = 56 dB
Power (dBm)
20
40
60
80
100
120
10
20
30
Frequency (MHz)
40
50
Figure 4.32: Spectrum of the signal at the lter output with a full-scale 3-MHz single tone
at the DAC input (WLAN setting, FFT frequency bin of 48 kHz).
0
10
20
Power (dB)
30
IMD3 > 68 dB
40
50
60
70
80
90
100
9
10
Frequency (MHz)
11
12
Figure 4.33: Spectrum of the signal at the DAC output with two 6-dBFS input tones at
8.2 MHz and 9 MHz (WLAN setting, FFT frequency bin of 48 kHz).
70
Chapter 4
10
0
10
20
IMD3 = 53.8 dB
Power (dB)
30
40
50
60
70
80
90
100
9
10
Frequency (MHz)
11
12
Figure 4.34: Spectrum of the signal at the lter output with two 6-dBFS input tones at
8.2 MHz and 9 MHz (WLAN setting, FFT frequency bin of 48 kHz).
Noise power spectral density (nV/sqrt(Hz))
1000
100
0.1
10
Frequency (MHz)
Figure 4.35: Total noise power spectral density at the lter output (WLAN setting).
Chapter 5
In this chapter the implementation in a standard 0.13-m CMOS technology of the baseband block (DAC and reconstruction lter) for the WLAN/UMTS recongurable transmitter (device #2) is presented [32]. In Section 5.1 the strategies followed for the layout of
the digital-to-analog converter are presented, while in Section 5.2 the experimental setup
adopted for the characterization of the circuit is described. In Section 5.3 and Section 5.4 the
experimental results are reported, focusing on the static behavior as well as on the dynamic
performance. Finally conclusions on the implemented test-chip are drawn in Section 5.5.
5.1
Layout strategies
The layout is a key issue when dealing with high-speed digital-to-analog converters. In
particular the layout of the current sources matrix can severely aect static and dynamic
performance of the DAC, due to the presence of systematic errors caused by fabrication process gradients. Moreover the crosstalk between the analog and the digital part, the coupling
between switching and static nodes, and the presence of unwanted parasitic capacitances
can lead to a degradation of the expected performance. So a careful oorplan of the blocks
constituting the DAC has been done before the realization of the layout.
A number of studies has been done in literature on the eect of systematic errors on
the current sources matrix due to the presence of process gradients. Usually the adopted
solution is to split the unit current sources in dierent parts and to place them in a common
centroid structure. Moreover particular switching sequences of the matrix elements are
adopted to compensate the eect of the gradients [3338]. Dynamic element matching
(DEM) is also used to make the gradient related errors independent of the input signal and
to avoid distortion [39,40]. For resolution higher than 12 bits, calibration of the unit current
sources or trimming of the elements are typically used to achieve the desired linearity.
Considering the dimensions of the unit current source (36 m2 ) and the relatively low
number of bits, the area occupation of the whole current sources matrix is low (about
0.01 mm2 ). Previous experience on the used technology indicated us that with this area the
eect of systematic errors can be considered negligible. So no dynamic element matching
or randomization of the switching sequence are used. We however chose to use a common
centroid sequence of switching which is usually adopted in DAC layout and which allows
the compensation of parabolic and linear gradients. Moreover dummy transistors are used
in each side of the matrix to give each current source the same boundary conditions.
Another aspect which can be usually found in literature [41] is the division of the current
sources matrix from the switches which deviate the current on the positive output or on
the negative one. The typical oorplan used for the current-steering DAC is reported in
72
Chapter 5
Current sources matrix
Switches matrix
Differential switching pair
Current source
Figure 5.1: Conventional oorplan for the current-steering DAC.

Figure 5.1. The advantage of this approach is that the area of the matrix can be kept as
small as possible and that there is little coupling between the current sources and the highfrequency switching signals driving the switches. The main drawback of this approach is
represented by the fact that a long routing is necessary to connect the current sources to each
switch. This implies the presence of a parasitic capacitance that can cause a second-order
distortion on the output signal [42]. To avoid this problem we chose to put each pair of
switches near to the corresponding element of the current sources matrix (Figure 5.2). The
coupling between the switch driving signals and the current sources is minimized by the
presence of a metal-4 shield layer connected to ground which divides each current source
from the high frequency signals routed in metal-6 (Figure 5.3). With this approach the area
of the DAC unit cell, consisting of the current source transistor and the current switches,
becomes 88 m2 . This value is larger than the area of the single current source transistor
(36 m2 ) and leads to an increase of the overall DAC matrix area (approximately 0.05 mm2 ).
Nevertheless this value can still be considered small enough to neglect the process gradients
errors and to avoid the use of dynamic element matching or randomization sequences.
The driving circuits for the unit cells are composed by the driver, the analog multiplexer,
the latch and a bypass capacitance (as shown in Figure 5.4). These blocks are placed on the
two sides of the current sources matrix (Figure 5.5).
The crosstalk between the analog and digital parts represents a limit aecting the overall system performance [43, 44]. Some of the implemented strategies for the reduction
of crosstalk eects derive from the considerations reported in Chapter 7. Substrate noise
73
Unit cells matrix
Differential switching pair
Current source
Figure 5.2: Adopted oorplan for the current-steering DAC.
M4 shielding plane
M6 switch driving lines
current switches
negative output node
positive output node
current source transistor
Figure 5.3: Layout of the unit cell composed by the current source transistor and the current
switches.
74
Chapter 5
latch
multiplexer
driver
filter capacitance
latches+drivers+multiplexers
latches+drivers+multiplexers
Figure 5.4: Layout of the driving circuit for the current switches, composed by the driver,
the analog multiplexer, the latch and a bypass capacitance.
unit cells matrix

Figure 5.5: Layout of the unit cells matrix surrounded by the driving circuits.
75
filter
DAC
decoder
Figure 5.6: Layout of the test-chip.

coming from the digital part is reduced using a triple well for the binary-to-thermometric
decoder. Moreover the analog and digital power supplies are split and multiple pads are
assigned to each supply voltage to reduce the eect of parasitic inductances associated with
the package bonding wires. A picture of the layout is reported in Figure 5.6, with the main
building blocks highlighted (binary-to-thermometric decoder, DAC, lter).
5.2
Measurement setup
The chip is mounted in a JLCC 52-pin ceramic package (Figure 5.7). A microphotograph
of the chip is shown in Figure 5.8. The core area is 0.8 mm2 , while the total area of the chip
(including pads) is 3.25 mm2 . The average length of the bonding wires is equal to 5 mm,
leading to a parasitic inductance of about 5 nH in series with each wire. The package is
mounted on a dual layer printed circuit board (PCB) for the testing. The external elements
on the PCB are minimized in order to reduce the eect of parasitics. To reduce the crosstalk
between the sensitive analog part and the digital part, the analog and the digital supply
voltages have been divided on the PCB (the same is done in the chip). Two distinct batteries
provide to the circuit the supply voltages. A 100-F capacitance in parallel with a 1-nF one
lters the supply voltages. The package is mounted on the PCB through a 64-leads socket.
This ensures more exibility for the testing of multiple devices, even if it can worsen the
chip performance for the presence of parasitic elements.
The measurements setup includes the following instrumentation: Tektronix TLA 715
digital pattern generator for the generation of 8-bit input codes at frequencies up to 100 MHz;
76
Chapter 5
Figure 5.7: Bonding diagram for the JLCC 52-pin ceramic package.
Tektronix P6474 LVCMOS probe for shifting the output digital levels from 3.3 V (the default for the pattern generator) to 1.2 V; dierential probe for the conversion of the output signals from dierential to single-ended; TDS5104 digital phosphor oscilloscope and
8-GHz Rhode-Schwarz spectrum analyzer for the time-domain and frequency-domain analysis of the output signal. A scheme of the measurement setup is shown in Figure 5.9.
5.3
Static characterization
The chip is rst of all tested in static conditions to evaluate the transfer characteristic at the
DAC and at the lter output. A sequence of input codes from 0 to 255 is applied at the input
of the DAC together with a low frequency clock. The dierential DAC output is measured
with a digital multimeter. The mean value of 100 acquisitions is calculated in order to eliminate the eect of the DAC thermal noise. The goal is to study the non-linearity associated
only with the random and systematic mismatches of the unit current sources. Figure 5.10
and Figure 5.11 show the measured INL and DNL (corrected from oset and gain errors)
for a sample of the test-chip. The non-linearity error, which includes the eect of the current
source output impedance and mismatch, is lower than 0.25 LSB. This performance is conrmed also for other samples of the test-chip, as indicated in Figure 5.12 and Figure 5.13,
where more measurements are superimposed on the same graph.
Static linearity has been measured also at the output of the lter. The transfer characteristics at the output of the two blocks are reported in Figure 5.14, where it is evident the
DC gain of the lter equal to 2.5 (8 dB). The INL and DNL at the lter output remain lower
77
Figure 5.8: Microphotograph of the test-chip.
TDS5104 DIGITAL
OSCILLOSCOPE
SPECTRUM
ANALYZER
DIFFERENTIAL
PROBE
Vout
+
Vout
BIAS
DUT
TLA715 P ATTERN
GENERATOR
8bits,1.2V
P6474
LVCMOS
PROBE
CLK 1.2V
01011100
10100101
00100100
CLK 3.3V
8bits,3.3V
Figure 5.9: Scheme of the measurement setup.
78
Chapter 5
then 0.6 LSB as reported in Figure 5.15 and Figure 5.16. All these results, being evaluated
in static conditions, are independent of the selected standard.
The entity of the thermal and crosstalk noise has been evaluated applying a static code
at the input of the DAC and a 100-MHz clock. The output power spectral density of the
noise is measured through the spectrum analyzer. The results obtained for the two standards
are shown in Figure 5.17. The total output thermal noise, obtained integrating the noise
power spectral density between 0 and innity, is 447 Vrms (equal to 54 dBm) for the
WLAN and 487 Vrms (equal to 53.2 dBm) for the UMTS, resulting 6 dB lower than the
quantization noise. The overall dynamic range (DR), obtained adding also the quantization
noise, is 54 dB for the WLAN and 58 dB for the UMTS.
5.4
Dynamic characterization
Dynamic characterization is carried out with single tones, intermodulation tests and application dependent signals. The measurements are done at the DAC output and at the lter
output, with a clock frequency equal to 100 MHz for the WLAN standard and 50 MHz for
the UMTS standard.
Figure 5.18 shows the lter transfer function (measured as lter gain for dierent DAC
input signal frequencies) for the two possible settings. For each setting the transfer function
with the minimum and maximum bandwidth controlled by the 4-bit word is shown.
For the WLAN setting, the linearity performance has been tested with a FS 3-MHz
single tone (as shown in Figure 5.19) leading to a SFDR of 54 dB, and a two 6-dBFS input
tones at 6.5 MHz and 7 MHz (as shown in Figure 5.20) leading to a IMD3 of 52 dB (which
means an OIP3 of 29.3 dBm). The IMD3 performance has also been tested as a function of
the center frequency of the two tones. Figure 5.21 shows that the IMD3 remains higher than
51 dB for the whole WLAN frequency range. Similar linearity tests have been performed
for the UMTS setting. From Figure 5.22 and Figure 5.23 a SFDR of 61 dB and an IMD3 of
60 dB (which means an OIP3 of 32.5 dBm) are evaluated.
In order to verify the robustness of the design some measurements have been performed
with a clock frequency higher than 100 MHz and with a supply voltage 15% lower than the
nominal one (i.e with a supply voltage equal to 1 V). As shown in Figure 5.24 the HD3 at
the lter output is higher than 53 dB even with these stressed operating conditions (clock
frequency up to 240 MHz). The reduction of the supply voltage to 1 V gives an improvement
of the linearity performance thanks to the reduced amplitude of the signals at the output of
the blocks.
Finally the device is tested with an application-dependent signal. For both cases, the
I component of a quadrature signal is considered. In the WLAN case (Figure 5.25) the
spectrum is compared with the emission mask (dened by the standard for the I+Q RF
signal) to verify the out-of-band linearity. Similarly, Figure 5.26 shows the output power
spectrum with an UMTS input signal compared with the corresponding emission mask. In
the two cases the in-band spectrum is not at due to the nite length of the pattern generator
sequence and the fact that the measurement is done on one component of a complex signal.
79
0.25
0.2
0.15
LSB units (8 bit)
0.1
0.05
0
0.05
0.1
0.15
0.2
0.25
50
100
150
200
250
Figure 5.10: Measured integral non-linearity at the DAC output.
0.25
0.2
0.15
LSB units (8 bit)
0.1
0.05
0
0.05
0.1
0.15
0.2
0.25
50
100
150
200
250
Figure 5.11: Measured dierential non-linearity at the DAC output.
80
Chapter 5
0.3
0.2
LSB units (8 bit)
0.1
0.1
0.2
0.3
50
100
150
200
250
Figure 5.12: Measured integral non-linearity at the DAC output across various samples of
the test-chip.
0.25
0.2
0.15
LSB units (8 bit)
0.1
0.05
0
0.05
0.1
0.15
0.2
0.25
50
100
150
200
250
Figure 5.13: Measured dierential non-linearity at the DAC output across various samples
of the test-chip.
81
1
0.8
Filter
0.6
Output voltage (V)
0.4
0.2
DAC
0
0.2
0.4
0.6
0.8
1
50
100
150
200
250
Figure 5.14: Transfer characteristic at the DAC output and at the lter output .
0.6
LSB units (8 bit)
0.4
0.2
0.2
0.4
0.6
0
50
100
150
200
250
Figure 5.15: Measured integral non-linearity at the lter output.
82
Chapter 5
0.6
0.4
Output voltage (V)
0.2
0.2
0.4
0.6
50
100
150
200
250
Figure 5.16: Measured dierential non-linearity at the lter output.
220
UMTS
Noise power spectral density (nV/sqrt(Hz))
200
180
160
140
WLAN
120
100
80
60
40
20
0.1
10
Frequency (MHz)
Figure 5.17: Noise power spectral density measured at the lter output.
83
10
Gain (dB)
10
20
WLAN range
30
40
50
UMTS range
60
10
Frequency (MHz)
100
Figure 5.18: Programmable low-pass lter transfer function.
10
0
Power (dBm)
10
SFDR=54 dB
20
30
40
50
60
4
6
Frequency (MHz)
10
Figure 5.19: Output spectrum at the lter output with a 3-MHz FS tone (WLAN setting,
Fc = 100 MHz).
84
Chapter 5
10
0
Power (dBm)
10
20
IMD3 = 52 dB
30
40
50
60
70
5.5
6.5
7
Frequency (MHz)
7.5
Figure 5.20: Output spectrum at the lter output with two 6-dBFS tones at 6.5 MHz and
7 MHz (WLAN setting, Fc = 100 MHz).
65
60
55
IMD3 (dB)
) f = 500 kHz
50
45
40
35
30
5
6
Frequency (MHz)
Figure 5.21: Third-order intermodulation distortion at the lter output as a function of the
two tones center frequency (WLAN setting, Fc = 100 MHz).
85
10
0
10
Power (dBm)
20
SFDR = 61 dB
30
40
50
60
70
80
0.5
1
1.5
Frequency (MHz)
2.5
Figure 5.22: Output spectrum at the lter output with a 600-kHz FS tone (UMTS setting,
Fc = 50 MHz).
10
0
10
Power (dBm)
20
IMD3 = 60 dB
30
40
50
60
70
80
0.5
1
1.5
Frequency (MHz)
2.5
Figure 5.23: Output spectrum at the lter output with two 6-dBFS tones at 1 MHz and
1.5 MHz (UMTS setting, Fc = 50 MHz).
86
Chapter 5
70
68
DAC output 1 V
66
HD3 (dB)
64
62
DAC output 1.2 V
60
58 Filter output 1 V
Filter output 1.2 V
56
54
52
50
100
120
140
160
180
200
Clock frequency (MHz)
220
240
260
Figure 5.24: Third-order harmonic distortion as a function of the clock frequency with an
input FS tone at 1 MHz.
0
5
WLAN emission mask
Power (dBr)
10
15
WLAN signal spectrum
20
25
30
35
40
45
10
15
20
Frequency (MHz)
25
30
35
Figure 5.25: Output spectrum of the I component of a WLAN signal compared with the
emission mask provided by the standard.
87
10
UMTS emission mask
Power (dBr)
20
UMTS signal spectrum
30
40
50
60
4
6
Frequency (MHz)
10
Figure 5.26: Output spectrum of the I component of an UMTS signal compared with the
emission mask provided in [45].
5.5
Conclusions
A baseband block to be embedded in low-voltage transmitters for recongurable multistandard terminals has been presented. The device can be digitally recongured between
the WLAN 802.11a/b/g and UMTS standards. The baseband section is realized with the
cascade of an 8-bit 100-MHz dierential current-steering DAC and a 4th-order low-pass
reconstruction lter. The device has been fabricated in a 0.13-m CMOS technology, and
occupy 0.8 mm2 . It operates with the challenging low supply voltage of 1.2 V, nonetheless
guaranteeing the required linearity features. The DAC conversion frequency and the lter
bandwidth can be programmed to satisfy the specications of the considered standards. The
design of the proposed block has been focused on the reduction of the power consumption, as required for mobile applications. Moreover, proper architectural choices and blocks
dimensioning allow the devices to achieve good linearity performance even with a low supply voltage such as 1.2 V. For all the considered standards the measured OIP3 is larger than
29 dBm, while the SFDR is 54dB for WLAN and 61dB for UMTS. The power consumption
of device is 11 mW for the WLAN setting and 8.4 mW for the UMTS setting.
A summary of the measured performance of the implemented baseband block is reported
in Table 5.1. The comparison between the target performance coming from the system-level
study and the experimental results is given in Table 5.2 and Table 5.3.
88
Chapter 5
Table 5.1: Summary of the transmitter analog baseband section features.

Parameter
Value
Technology
CMOS 0.13 m
Supply voltage
1.2 V
0.8 mm2
Core area
Standard
WLAN
UMTS
Fc
100 MHz
50 MHz
Filter bandwidth
11 MHz
2.5 MHz
Dierential output swing
1.8 Vpp
1.8 Vpp
DR (@ FS)
54 dB
58 dB
54 dB (@ 3 MHz)
61 dB (@ 0.6 MHz)
29.3 dBm
32.5 dBm
DAC power consumption
5.4 mW
5.4 mW
Filter power consumption
5.6 mW
3 mW
Total power consumption
11 mW
8.4 mW
SFDR (@ FS)
OIP3
Table 5.2: Comparison between the target performance of the baseband section and the
experimental results (WLAN case).
Parameter
Target
Simulation
Measurements
DR (@ FS)
50 dB
56 dB
54 dB
In-band HD3
47 dB
56 dB
54 dB
In-band IMD3
50 dB
54 dB
52 dB
IIP3
20 dBm
22.3 dBm
21.3 dBm
OIP3
28 dBm
30.3 dBm
29.3 dBm
Table 5.3: Comparison between the target performance of the baseband section and the
experimental results (UMTS case).
Parameter
Target
Simulation
Measurements
DR (@ FS)
50 dB
60 dB
58 dB
In-band HD3
47 dB
63 dB
61 dB
In-band IMD3
50 dB
62 dB
60 dB
IIP3
20 dBm
25.5 dBm
24.5 dBm
OIP3
28 dBm
33.5 dBm
32.5 dBm
Chapter 6
This chapter presents the baseband section for a WLAN transmitter which employs the DAC
oversampling ratio (OSR) to avoid the use of an active analog reconstruction lter (device
#4). As a matter of fact, the DAC conversion frequency is enhanced to 600 MHz. As shown
in Section 6.1, a 40-MHz single pole, combined with the sinc ltering inherently provided
by the DAC, suitably suppresses the signal replicas around the conversion frequency under
the standard emission mask. Section 6.2 is devoted to the performance evaluation of the
digital interpolator lter which must be inserted between the DSP and the digital-to-analog
converter to boost the signal sampling rate from 20 MHz to 600 MHz. Section 6.3 describes
the design issues of the implemented DAC, while Section 6.4 reports the achieved experimental results. A comparison with recently published DACs shows that the proposed block
performs the baseband digital-to-analog conversion for the WLAN signal with the highest
eciency. Moreover it achieves a reduction of the overall power consumption of about 50%
with respect to the conventional solution presented in the previous chapters.
6.1
High frequency baseband section
As indicated in Chapter 2, traditional baseband architectures for wireless transmitters consist of the cascade of a digital-to-analog converter receiving the DSP bit-stream and an
analog reconstruction lter suppressing the DAC spectral images. Typical values for the
conversion frequency are around 100 MHz, while the ltering action is implemented using
active lters with order between 3 and 4 [17, 18].
On the other hand the technological trend indicates that the amount of processing performed in the digital domain is increasing and, due to the scaled supply voltage, is becoming
more ecient than analog solutions. Indeed, higher operating frequencies for the digital part
are available and well-shielded technology (mainly exploited in the receiver path, but available also for the transmitter) are used. These technology considerations lead to the baseband
section proposed in this chapter for the WLAN standard. The architecture consists of a digital interpolator lter from 20 MHz to 600 MHz and an 8-bit DAC operating at 600 MHz. In
this way the use of an active reconstruction lter, which is critical at this low supply voltage
in terms of dynamic range and linearity, is avoided, resulting in a signicant reduction of
power consumption.
The basic idea is that increasing the oversampling ratio and hence the DAC conversion
frequency with respect to the signal bandwidth pushes at high frequency the DAC spectral
images, thus allowing a relaxed implementation of the following low-pass reconstruction
lter, as shown in Figure 6.1. If the conversion frequency is as high as 600 MHz, a single
pole ltering with cut-o frequency of 40 MHz (which can be provided by a passive load
90
Chapter 6
relaxed implementation of the

low-pass reconstruction folter
|S|
|S|
20
40
60
|S|
|S|
600
f (MHz)
f (MHz)
600
f (MHz)
600
f (MHz)
600 MHz DAC conversion frequency
DIGITAL
INPUT
0
1
0
1
1
digital
interpolator filter
ANALOG
OUTPUT
1
1
0
0
1
DAC
analog
filter
Figure 6.1: Proposed high frequency baseband section. A 600-MHz DAC conversion frequency allows a relaxed implementation of the following low-pass reconstruction lter.
at the DAC output), combined with the sinc attenuation inherently provided by the DAC,
suitably suppresses the signal replicas around the multiples of the conversion frequency. As
a matter of fact, the expression for the total attenuation AttdB ( f ) given by the sinc ltering
provided by a DAC with conversion frequency of Fc combined with a single pole at Fpole is
given by:

2
sin ( f /Fc )
1
+ 10log10
(6.1)
AttdB ( f ) = 10log10
2 .

f /Fc
1 + f /F
pole
Considering the WLAN signal bandwidth of 10 MHz, the DAC conversion frequency equal
to 600 MHz and the output pole frequency at 40 MHz, the total attenuation of the rst
signal replica (at the lowest frequency equal to 590 MHz) is about 60 dB (Figure 6.2), thus
ensuring that all the spectral images lie under the standard emission mask. In Figure 6.3,
Figure 6.4 and Figure 6.5 the attenuation provided by the 600-MHz DAC sinc ltering
and the 40-MHz single pole ltering are reported.
The eective resolution of the signal at the output of the baseband section can be found
considering the 8-bit quantization noise which is ltered by the DAC output single pole (to
simplify the mathematical expressions we are neglecting the eect of the sinc ltering
provided by the DAC zero-order-hold). The total quantization noise power Pq at the block
output is calculated integrating from zero and innity the 8-bit quantization noise power
spectral density PSDq ltered by the single pole:

2
+
2Fpole

1
Pq =
PSDq
.
(6.2)
d f = PSDq

1
+
(j
f
/F
)
4
pole
0
The quantization noise power spectral density is given by quantization noise power 2 /12
uniformly distributed over the Nyquist bandwidth:
PSDq =
2 1
1

,
12 R Fc /2
(6.3)
where is the amplitude of the quantization step and R is the 50 reference resistance.
Therefore Equation (6.2) can be expressed as:
Pq =
2Fpole
2 1
1

.
12 R Fc /2
4
(6.4)
91
10
Attenuation (dB)
20
30
40
50
60
70
100
200
300
400
500
Frequency (MHz)
600
700
800
Figure 6.2: Attenuation at Fc 10 MHz as a function of Fc .
0
sinc attenuation
5
10
Attenuation (dB)
15
20
25
single pole attenuation
30
35
40
45
50
100
200
300
400
500
Frequency (MHz)
600
700
800
Figure 6.3: Attenuation of the sinc ltering and of the single pole ltering as a function
of the signal frequency.
92
Chapter 6
10
sinc attenuation
0
Attenuation (dB)
10
single pole attenuation
20
30
40
50
10
100
Frequency (MHz)
Figure 6.4: Attenuation of the sinc ltering and of the single pole ltering as a function
of the signal frequency (logarithmic scale).
40
spectral image bandwidth
50
Attenuation (dB)
60
70
80
90
100
560
570
580
590
600
610
Frequency (MHz)
620
630
640
Figure 6.5: Total attenuation provided by the sinc ltering and the single pole ltering
around the DAC conversion frequency.
93
Supposing the dierential FS amplitude at the output of the block equal to 520 mVpp , a value
coming from the TX chain system-level study, the quantization step results in 2 mV. With the
frequencies indicated above this leads to a total integrated quantization noise power equal
to 58 dBm, while the WLAN signal power is equal to 10.7 dBm. The SNR is therefore
equal to 47.3 dB. The full-scale sinusoidal signal, whose power is 1.7 dBm, presents an
SNR equal to 56.3 dB, equivalent to an eective resolution of 9 bits. This value increase to
10.6 bits if we consider the quantization noise limited from zero to the signal bandwidth of
10 MHz.
If the signal at the output of the block is compared with an ideal WLAN signal (i.e. a
signal coming from an ideal transmitter with no quantization and an ideal 10-MHz low-pass
ltering), the SNDR results in about 40 dB. As we are accounting for all the sources of
noise and distortion (quantization noise, signal replicas and in-band amplitude distortion of
the signal provided by the sinc ltering and the low-pass ltering) this value represents
the most pessimistic evaluation of the signal resolution. The in-band amplitude distortion is
the most signicant component in the SNDR, as if we limit the SNDR evaluation from zero
to 10 MHz the obtained value remains unchanged with respect to the previous one. With
40 dBm we obtain an eective resolution of 7.8 bits.
Figures 6.6, 6.7 and 6.8 show the spectra of the signals at the output of the dierent
blocks composing the baseband section, in the case of the WLAN 802.11a standard. The
8-bit digital signal at the input of the DAC have the spectral images around the multiples
of the sampling frequency. The bit-stream is then converted into an analog signal by the
DAC, whose zero-order-hold introduces a sinc ltering on the input spectrum. A 40-MHz
single pole attenuates the signal replicas under the emission mask. Figure 6.9 shows the
overall noise and distortion components of the error at the lter output. The eect of the
quantization noise alone is also indicated.
Apart from the elimination of the low-pass reconstruction lter, the proposed architecture for the baseband section can present another advantage coming from the high conversion frequency. The oversampling ratio determines an improvement in the dynamic linearity
performance due to the reduced amplitude of the transition between successive codes. On
the other hand the main drawback of the architecture may be the distributed noise due to
the high operating frequency of the interpolator preceding the DAC. An estimation of the
characteristics of the interpolator is carried out in the following section. The low number of
output bits determines a very small interpolator section, the large OSR reduces the number
of cells switching at 600 MHz, and the technology shielding reduces crosstalk. Moreover,
dierently than in the receiver, in the transmitter a signicant signal power level is present,
reducing the dynamic range requirements. The experimental results demonstrate that this
distributed noise is not critical.
6.2
Digital interpolator lter
A digital interpolator lter between the DSP and the DAC is necessary to increase the signal
sampling frequency from 20 MHz to 600 MHz. To compare the high frequency baseband
section proposed in this chapter with the one described in the Chapter 2, functioning at
100 MHz, we estimate the performance required by an interpolator lter from 100 MHz to
600 MHz, i.e. with an interpolation factor of 6. We suppose that an ideal 100 MHz digital
signal is available from the DSP.
94
Chapter 6
baseband signal
20
signal replicas
Power (dBr)
20
40
60
80
100
500
1000
1500
2000
Frequency (MHz)
2500
3000
Figure 6.6: Spectrum of the 8-bit 600-MHz WLAN digital signal at the input of the DAC.
baseband signal
20
Power (dBr)
0
sinc attenuated signal replicas
20
40
60
80
100
500
1000
1500
2000
Frequency (MHz)
2500
3000
Figure 6.7: Spectrum of the WLAN signal ltered by the DAC sinc eect.
20
95
baseband signal
0
20
Power (dBr)
40
60
80
100
120
140
160
500
1000
1500
2000
Frequency (MHz)
2500
3000
Figure 6.8: Spectrum of the WLAN signal ltered at the output of the DAC single pole
output stage.
As well-known from digital communication theory [46], the interpolation of a digital
signal from a frequency F1 to an higher frequency F2 consists in a rate expansion, achieved
by inserting zero samples in the original signal, followed by a digital ltering. The eect
of the digital ltering is to suppress the input signal replicas around integer multiples of F1
included between F1 /2 and F2 F1 /2. In a real implementation these replicas are attenuated
with a factor that depends on the type of used lter. Moreover, to perform the interpolation
of the input signal with the correct amplitude, the pass-band gain of the digital lter has to
be equal to the interpolation factor.
A multirate interpolator digital lter performs the upsampling of the input signal in
dierent steps. In our case a convenient choice is to split the interpolation section in two
parts, the rst raising the signal frequency from 100 MHz to 200 MHz (interpolation factor
of 2) and the second from 200 MHz to 600 MHz (interpolation factor of 3). In this way
we are reducing the part of the interpolator lter operating at 600 MHz, with a signicant
power saving. The attenuation of the replica around 100 MHz, the most critical to lter, is
done at the relatively low frequency of 200 MHz.
A system-level study of the implemented baseband section shows that a convenient
choice for the rst stage digital ltering is a nite impulse response (FIR) lter with an
order equal to 10 and a cut-o frequency of 50 MHz. The pass-band gain is equal to 6 dB
(corresponding to the interpolation factor of 2). The FIR lter has been chosen to preserve
the integrity of the transmitted signal, which otherwise would be distorted using non-linear
phase digital lters, as the innite impulse response (IIR) lters. Moreover the FIR lters
are intrinsically stable and the realized transfer function is less dependent on the length of
the xed point arithmetic used for the implementation with respect to the IIR lters. The
96
Chapter 6
0
sinc and filter amplitude distortion
20
signal replica
quantization noise
Power (dBr)
40
60
80
100
120
140
100
200
300
400
500
Frequency (MHz)
600
700
800
Figure 6.9: Spectrum of the quantization noise and of the overall noise and distortion components at the output of the lter.
second stage digital ltering is implemented with a FIR lter with an order equal to 10 and
a cut-o frequency of 80 MHz. The pass-band gain is equal to 9.5 dB (corresponding to
the interpolation factor of 3). Figures 6.10, 6.11 and 6.12 show the transfer functions of
the rst and second stage FIR lters as well as the transfer function of the overall digital
interpolator lter. The transfer function of the rst stage is periodical with a period equal
to 200 MHz, while the transfer functions of the second stage and of the overall interpolator
have a period of 600 MHz.
Figures 6.13, 6.14, and 6.15 report the spectrum of the ideal WLAN signal sampled at
100 MHz, the spectrum of the signal sampled at 200 MHz at the output of the rst stage
of the digital interpolator lter and the spectrum of the signal sampled at 600 MHz at the
output of the second stage, respectively. It is evident that the signal replicas are attenuated
so that they remain under the emission mask. The addition of the 8-bit quantization noise
is then reported in Figure 6.16. The eect of the designed interpolator lter on the overall
transmitter can be considered negligible. Including the distortion coming from the signal
replicas and the in-band amplitude distortion of the lter transfer function, the SNDR at the
output of the digital block, with no quantization, is about 50 dB (equal to 9.5 bits). The
SNDR after the 8-bit quantization is therefore dominated by the quantization noise and it
is equal to 40 dB (8 bits). The eect of the following blocks (DAC and low-pass lter) has
been considered in the previous section and leads to the same values for the WLAN signal
SNDR obtained before (40 dB, 7.8 bits).
The implementation of the two stages can be done with a 16-bit xed point arithmetic.
This is sucient to make negligible the mismatch between the quantized interpolator lter
and the innite precision one (innite precision relates actually to the Matlab precision). An
97
20
Gain (dB)
20
40
60
80
100
50
100
Frequency (MHz)
150
200
Figure 6.10: Transfer function of the digital interpolator rst stage (10-taps FIR, cut-o
frequency equal to 50 MHz, pass-band gain equal to 6 dB).
20
Gain (dB)
20
40
60
80
100
120
100
200
300
400
Frequency (MHz)
500
600
Figure 6.11: Transfer function of the digital interpolator second stage (10-taps FIR, cut-o
frequency equal to 80 MHz, pass-band gain equal to 9.5 dB).
98
Chapter 6
20
0
20
Gain (dB)
40
60
80
100
120
140
100
200
300
400
Frequency (MHz)
500
600
Figure 6.12: Transfer function of the digital interpolator lter (cascade of the two stages,
pass-band gain equal to 15.5 dB).
50
baseband signal
0
50
Power (dBr)
100
150
200
250
300
350
400
100
200
300
400
Frequency (MHz)
500
600
Figure 6.13: Spectrum of the 100-MHz ideal WLAN signal coming from the DSP.
99
10
baseband signal
0
10
Power (dBr)
20
attenuated signal
replica
30
40
50
60
70
80
90
100
200
300
400
Frequency (MHz)
500
600
Figure 6.14: Spectrum of the 200-MHz signal at the output of the rst stage of the digital
interpolator lter.
20
baseband signal
0
Power (dBr)
20
40
60
80
100
120
140
100
200
300
400
Frequency (MHz)
500
600
Figure 6.15: Spectrum of the 600-MHz signal at the output of the interpolator lter.
100
Chapter 6
20
baseband signal
0
Power (dBr)
20
40
60
80
100
120
100
200
300
400
Frequency (MHz)
500
600
Figure 6.16: Spectrum of the 8-bit 600-MHz signal at the output of the interpolator lter.
automatic synthesis of the VHDL code describing the two blocks gives a power consumption of 1.2 mW for the rst block and of 1.1 mW for the second one. The estimated area
consumption is of 0.1 mm2 (1 kgates) for each of the two stages. The performance summary
for the overall block is described in Table 6.1.
Table 6.1: Digital interpolator lter performance summary.

Parameter
First stage
Second stage
Architecture
FIR
FIR
Interpolation factor
Input signal frequency
100 MHz
200 MHz
Output signal frequency
200 MHz
600 MHz
Order
10
10
Fixed point arithmetic length
16 bits
16 bits
Power consumption
1.2 mW
1.1 mW
Area occupation
0.1 mm2
0.1 mm2
6.3
101
Design of the 600-MHz digital-to-analog converter
The architecture of the proposed DAC is reported in Figure 6.17. It is similar to the architecture described in the previous chapters for the traditional approach. As a matter of fact
the dimensioning of the unit current sources used for the 100-MHz solution allows also the
correct operation at a frequency as high as 600 MHz. Using a fully-thermometric structure,
the equivalent switching frequency of the unit current cell is equal to two times the maximum frequency of the input signal (in this case 10 MHz). Therefore a unit current value of
5 A ensures the desired switching frequency of the cells.
As in the 100-MHz design, a fully-thermometric dierential current-steering structure
guarantees high static and dynamic linearity performance. Due to the low resolution, a negligible increase in area results from the presence of the binary-to-thermometric decoder. The
unit current cell is sized to reduce the eect of random mismatch. A relative standard deviation in the current value equal to 1% ensures an INL yield and a DNL yield of 99.9%, with
0.5 LSB as upper limit. The overall dimensions of the current source matrix (0.05 mm2 ) are
such that systematic errors due to process variations do not aect the linearity of the device.
The switches, which deviate the unit current toward the positive output or the negative one,
are driven with low-swing signals to limit the energy of glitches (800 mV as on voltage
and 300 mV as o voltage). Their sizes are kept to minimum values to reduce the charge
injection eects on the unit current sources during the switching phase.
Dierently from the solution presented in the previous chapters, only two drivers, placed
after the synchronization latches, are used to generate the desired voltage levels. Each driver
is biased with a current of 100 A. This choice leads to a reduction of the total driver current
consumption of about 60% with respect to the solution described in the previous chapter, at
the cost of a worst linearity performance. The increase of non-linearity due to the presence
of only two drivers is mitigated by the the high OSR used for this solution.
VDD
DAC Output Stage

VCM
C
To RF
...
... section
...
GND
Unit cell
Figure 6.17: Scheme of the 600-MHz digital-to-analog converter.
Chapter 6
code 2048
code 2047
CODE SELECTOR
...
SHIFT-REGISTER
MEMORY
...
code 3
code 2
code 1
b7
b6
b5
b4
b3
b2
b1
b0
BINARY TO THERMOMETRIC DECODER
102
255
600-MHz clock
Figure 6.18: Scheme of the digital part used for the high frequency testing of the DAC.
The output stage is used to convert the output currents into a voltage signal and to lter
the signal replica. Referring to Figure 6.17, a resistance R equal to 220 in parallel with a
capacitance C of 17.5 pF implements the required 40-MHz single pole transfer function. A
common-mode feedback circuit, which acts on the two xed PMOS current sources, adjusts
the voltage of the common node of the two impedances to 600 mV. The voltage swing
of 520 mVpp on the output nodes does not aect the linearity of the DAC thanks to the
high output impedance of the current cells. This is achieved by the cascoding action of the
switches in the on state.
6.4
Experimental results
The DAC system is realized in a standard 0.13-m CMOS technology. The chip includes a
dedicated digital part used for the high-frequency testing. This part consists of a 2048 8
bit shift-register which is used for the initial loading of the desired sequence of 8-bit words.
A pointer selects successively one of the shift-register rows thus allowing the resulting binary code to be applied to the binary-to-thermometric decoder. All the digital operations
are inserted in a pipeline structure to allow the correct operation at the high frequency of
600 MHz. A ring oscillator with an external tunable oscillating frequency is used to generate the desired clock for the DAC. A scheme of the digital part used for testing is shown in
Figure 6.18.
The need of a dedicated part for the testing of the DAC comes from the maximum allowable operating frequency of the digital pattern generator, which is equal to 250 MHz.
Moreover the digital interpolator lter described in Section 6.2, which could be used as in-
103
terface between the pattern generator and the DAC, was not available at the time of the chip
integration. The main drawbacks of the adopted approach are the area and power consumption of the digital part (equal to 2.5 mm2 and 216 mW respectively), and the disturbances
coming from the high frequency switching of the digital cells. However the crosstalk between the digital and the analog part is kept as low as possible using a shielding triple well,
separated power supplies and multiple bonding wires to reduce parasitic inductances. The
eectiveness of the crosstalk reduction strategies (mainly derived from the considerations
described in Chapter 7) have been conrmed by the experimental results. The described
digital part will not be included in a fully-integrated transmitter.
All the measurement results described in the following are performed with a DAC conversion frequency of 600 MHz. The linearity performance is evaluated applying a full-scale
single tone with a frequency Fin up to 20 MHz. The HD3 is higher than 59 dB over the
whole input frequency range and in particular reaches 68 dB for Fin equal to 12.5 MHz.
The IMD3 is evaluated applying two 6-dBFS input tones. The frequency distance F between the two input tones is equal to 1 MHz, while the center frequency is between 1 MHz
and 20 MHz. The IMD3 results higher than 50 dB for the whole input frequency range. Figure 6.19 reports the measured HD3 and IMD3 as a function of the input signal frequency.
In the HD3 test the single pole at the DAC output lters the third harmonic component with
an attenuation that depends on the input signal frequency. In Figure 6.19 the values of HD3
corrected from the eect of the single pole attenuation (i.e. as if the third harmonic was not
ltered by the single pole) are reported.
Figure 6.20 shows the output spectrum of a 9-MHz FS tone. As expected the replicas of
the signal around the conversion frequency remain under the level indicated by the standard
emission mask. The measured attenuation deriving from the DAC sinc ltering and the
single pole ltering at the frequency of the replica corresponds to the one indicated in the
previous section. Figures 6.21 and 6.22 show the output spectra for the intermodulation
test with the two tones center frequency set to 9 MHz and 14 MHz respectively. Finally
Figure 6.23 shows the output spectrum when a WLAN signal is applied at the DAC input.
The output thermal noise is evaluated with a static code at the input of the DAC and a
clock frequency of 600 MHz. The power spectral density integrated between 0 and 600 MHz
leads to a noise power of 57 dBm. The resulting FS DR of the system, obtained adding
the contribution of the 8-bit quantization noise ltered by the single pole, is equal to about
52.6 dB (corresponding to 8.5 bits of eective resolution).
The chip core consumes 2.5 mW from a single 1.2-V supply voltage and occupies
0.27 mm2 . The chip including the digital testing part and the pads occupies 7.74 mm2 .
The performance summary and the microphotograph of the core are reported in Table 6.2
and Figure 6.24, respectively. A comparison with other recently published DACs can be
made using the gure of merit (FOM) reported in [29]:
Vswing
(6.5)
Fin 10SFDR/20 ,
P
where Vswing is the maximum output dierential peak-to-peak swing expressed in V, P is
the power consumption expressed in mW, Fin is the frequency in kHz at which the SFDR is
measured. Figure 6.25 shows that for signal frequencies of 10 MHz and 14 MHz the proposed block performs the baseband digital-to-analog processing with the highest eciency.
The signal frequencies of 10 MHz and 14 MHz account for the baseband signal bandwidths
of the WLAN 802.11a/g and of the next generation WLAN 802.16 respectively. Note that in
the FOM calculation for the proposed DAC the value of the SFDR used is the one corrected
FOM =
104
Chapter 6
70
68
HD3 not corrected
66
HD3 (dB), IMD3 (dB)
64
62
HD3 corrected
60
58
56
IMD3
54
52
50
48
10
Frequency (MHz)
15
20
Figure 6.19: HD3 (measured and corrected from the eect of the DAC output single pole)
as a function of the input signal frequency; IMD3 as a function of the two 6-dBFS tones
center frequency.
Figure 6.20: Spectrum of a 9-MHz FS input tone.
Figure 6.21: Spectrum of two 6-dBFS input tones at 8.4 MHz and 10.8 MHz.
Figure 6.22: Spectrum of two 6-dBFS input tones at 13.6 MHz and 15.4 MHz.
105
106
Chapter 6
WLAN baseband signal
10
Power (dBr)
20
30
WLAN emission mask
40
50
60
70
80
10
100
700
Frequency (MHz)
Figure 6.23: Spectrum of the WLAN signal.

from the eect of the DAC output single pole (i.e. a value lower than the measured one).
Moreover the implemented DAC is the only one up to now operating with a supply voltage
as low as 1.2 V, while guaranteeing the standard requirements. In Table 6.3 and 6.4 the
values used for the calculation of the gure of merit for the dierent DACs are reported. A
comparison between the baseband section presented in the previous chapters on the implemented one is shown in Figure 6.26, considering the I and Q channels. The absence of the
analog reconstruction lter, which is replaced by the digital interpolator, leads to a reduction of the overall power consumption of about 50%. This reduction is achieved also if we
consider the PLL which must provide a clock 6 times higher than the 100-MHz solution.
107
Digital test structure
DAC
Figure 6.24: Microphotograph of the test chip.
x 10
Figure of merit [(V \ mW) kHz]
FOM at 10MHz
FOM at 14MHz
this work
this work
4
Cong (ISSCC03)
Clara (ISSCC05)
OSullivan (JSSCC04)
Clara (ISSCC05)
2
Schofield
(ISSCC03)
Deveugele (ISSCC04)
Doris (ISSCC04)
Hyde (JSSCC03)
Huang (ISSCC04)
Chen (ESSCIRC04)
1.2
1.5
1.8
2.5
Analog supply voltage [V]
3.3
Figure 6.25: FOM with an input signal frequencies of 10 MHz and 14 MHz for recently
published DACs and for the implemented one.
108
Chapter 6
Baseband Analog Section [device #2]
20 MHz DSP
bit-stream
20 MHz CLK
20 MHz DSP
bit-stream
Digital Interpolator Filter x5

20MHz
100MHz
PLL
DAC 8 bit,
100 MHz, 5.4mW
Low-pass filter,
4-th order,
5.6mW
To RF
section
DAC 8 bit,
100 MHz, 5.4mW
Low-pass filter,
4-th order,
5.6mW
To RF
section
100 MHz CLK

20MHz
100MHz
Power consumption = 22 mW
Baseband Analog Section [device #4]
20 MHz DSP
bit-stream
20 MHz CLK
20 MHz DSP
bit-stream

20MHz
100MHz
PLL
Interpolator Filter x6
100MHz
600MHz
DAC+output stage,
8 bits, 600 MHz,
2.4 mW
To RF
section
Interpolator Filter x6
100MHz
600MHz
DAC+output stage,
8 bits, 600 MHz,
2.4 mW
To RF
section
600 MHz CLK

20MHz
100MHz
Power consumption = 9.4 mW
Figure 6.26: Comparison between the traditional baseband section for direct conversion
transmitters presented in the previous chapters and the implemented one.
Table 6.2: Performance summary.

Parameter
Value
Technology
CMOS 0.13 m
Supply voltage
1.2 V
Core area
0.27 mm2
Maximum conversion rate
600 Msamples/s
Power consumption
2.4 mW
Dierential FS output swing
520 mVpp
INL/DNL
<0.25LSB
SFDR @ FS, Fin = 12 MHz, Fc = 600 MHz
68 dB
IMD3 @ -6dBFS, Fcenter = 12 MHz, F = 1MHz, Fc = 600 MHz
57 dB
DR @ FS
58.6 dB (8.5 bits)
DR @ FS, 0-10 MHz
60.6 dB (9.7 bits)
109
Table 6.3: FOM with an input signal frequency of 10 MHz for recently published DACs and for the
implemented one.
VDD (V)
P (mW)
Vswing (V)
SFDR (dB)
Fin (kHz)
FOM
This work
1.2
2.4
0.52
67
10000
4.9 106
Cong [47]
1.5
16.7
76
10000
3.8 106
OSullivan [41]
3.3
82
80
10000
2.4 106
Clara [30]
1.5
45
1.536
76
10000
2.2 106
Schoeld [42]
3.3
400
1 (1)
95
10000
1.4 106
Deveugele [48]
1.8
22
0.5
73
10000
106
80
10000
9.4 105
72
10000
7.5 105
73
10000
3.7 105
49
10000
1.4 105
Doris [49]
1.8
160
Hyde [50]
3.3
53
Huang [51]
1.8
97
Chen [52]
2.5
103
1.5
(2)
1 (3)
0.8
(4)
5 (5)
(1) from the value of the FS GSM/EGDE modulated carrier power equal to 0 dBm;
(2) from the value of FS output current of 15 mA delivered on a 50 resistance;
(5) maximum allowable dierential output swing with the 2.5 V supply voltage.
Table 6.4: FOM with an input signal frequency of 14 MHz for recently published DACs and for the
implemented one.
VDD (V)
P (mW)
Vswing (V)
SFDR (dB)
Fin (kHz)
FOM
This work
1.2
2.4
0.52
65.5
14000
6.1 106
Cong [47]
1.5
16.7
72
14000
3.6 106
Clara [30]
1.5
45
1.536
76
14000
3.2 106
OSullivan [41]
3.3
82
77
14000
2.6 106
Doris [49]
1.8
160
1.5
80
14000
1.4 106
Schoeld [42]
3.3
400
90
14000
1.2 106
Deveugele [48]
1.8
22
0.5
70
14000
1.1 106
Hyde [50]
3.3
53
72
14000
1.1 106
Huang [51]
1.8
97
0.8
72
14000
4.9 105
Chen [52]
2.5
103
45
14000
1.3 105
Chapter 7
Crosstalk Eects in Mixed-Signal
CMOS ICs
Mixed analog-digital integrated circuits are aected by digital switching noise, which can
be a limiting factor for overall system performance [53]. It is well known that the noise
propagates through the substrate and the bonding/package interconnections, and interferes
with the voltages of the analog section of the circuit, limiting the accuracy of analog operations [54]. The crosstalk issue is of primary concern especially when we deal with fullyintegrated wireless transceivers, where large digital sections must function together with
sensitive analog parts. It is therefore necessary to study crosstalk mechanisms in order to
understand the propagation paths toward the analog blocks, and to design suitable protection
structures.
In the framework of the FIRB project, a task is dedicated to the study of these issues. This chapter presents some of the research activity devoted to the investigation of
the crosstalk mechanisms. The activity aims at studying the injection of noise by the digital
switching sections and its propagation toward the analog parts, with a twofold goal, namely,
to develop models for computer simulation of the relevant eects, and to develop adequate
guidelines for design and layout, with the purpose of minimizing these eects. The impact
of the used mounting technology is also taken into account. The achieved results have been
extensively used in the design of the baseband sections for wireless transmitters, which was
the subject of the previous chapters. In particular some of the adopted design and layout
choices regarding the implemented digital-to-analog converters were derived from this research.
The chapter is organized as follows. First of all, the shielding options provided by the
fabrication technology have been considered, as described in Section 7.1. A realistic model
of interconnection and package parasitics is derived and used for crosstalk simulations. This
aspect is discussed in Section 7.2. To validate simulation results, we have designed two testchips, which have been assembled into a package and with chip-on-board technology. In
this way, we can compare simulated and experimental results, evaluating eects of dierent
mounting technologies. The test-chips are described in Section 7.3. Simulations of crosstalk
eects are reported in Section 7.4. Finally, Section 7.5 presents the results of measurements
on the test-chips.
7.1
111
Fabrication technology issues
To investigate crosstalk eects, two test-chips were designed in a 0.18-m CMOS technology with high-resistivity p-type substrate, twin wells, and an n-isolation layer that can be
used for shielding purposes. Figure 7.1 shows a vertical section of MOS devices with and
without the n-isolation layer. Local p-wells are isolated from the global p-substrate by the
n-isolation layer (buried n-iso contacted with lateral n-wells), as shown on the rightmost
side of Figure 7.1. The isolated p-well is contacted to a ground (VSS p-well) dierent from
the substrate one (VSS sub). P-wells designed outside the n-isolation layer are connected
through the common substrate, as shown on the leftmost side of Figure 7.1. A p-well guard
ring, biased at the substrate voltage (VSS sub), can be placed around the devices. When the
n-isolation layer is used together with the guard ring, the p-well guard ring is external to the
n-isolation.
NMOS
p+
n+
p+
n+
n-WELL
n-WELL
PMOS
V DD
V SS p-well
V SS sub
NMOS
PMOS
n+
p+
p+
p-WELL
n+
p-WELL
p-SUB
n-WELL
V DD
n-WELL
n-ISO
Figure 7.1: Section view of NMOS and PMOS devices in the used technology.
7.2
Model of o-chip parasitics
Bonding and package parasitics eects cannot be neglected in an accurate mixed-signal IC

design, as they severely aect the stability of bias voltages. In particular, bondwire and pin
parasitic resistance, inductance and capacitance constitute an RLC network which can cause
the internal supply voltages to be signicantly dierent from external voltages.
Moreover, mutual inductance and cross-capacitance between bondwires cause electromagnetic coupling between digital and analog supplies. Therefore, the advantage of kelvin
ground for substrate bias vanishes, as disturbances due to digital switching currents propagate through mutual inductances and cross-capacitances.
To evaluate eects of such parasitic elements, a suitable model has been developed.
Figure 7.2 illustrates a simplied model of bonding and package parasitics for two adjacent
wires [55]. The instantaneous current iDD due to digital switching of logic gates produces a
voltage drop, which aects the on-chip digital supply VDD , and propagates to the adjacent
wires through both capacitive coupling due to the capacitance between wires, C, and inductive coupling due to the mutual inductance represented by K. Therefore, the analog on-chip
voltage v(t) is no more equal to the external voltage vs , but it results to be a function of the
voltage vs and of the digital switching current iDD and its derivative:

diDD
.
v(t) = f vs , iDD ,
dt
(7.1)
112
Chapter 7
iDD
VDD
VDD
(external)
L/2
R/2
CGND
L/2
R/2
L/2
R/2
(on-chip)
v(t)
L/2
R/2
vs
CGND
Figure 7.2: Simplied equivalent circuit of bondwire and package parasitics for digital
switching noise.
From these considerations, it is apparent that an accurate analysis of a mixed-signal circuit must evaluate eects of switching currents, accounting for both on-chip and o-chip
parasitic elements.
A realistic model for o-chip parasitics has been derived from Figure 7.2. For each
pin, we consider parasitic coupling with the nearest four wires on both sides. This results
in a SPICE subcircuit used to perform time-domain simulations. Values of parasitic elements (extracted for a ceramic JLCC-24 package) are: inductance L = 2 nH, resistance R
= 100 m, ground capacitance CGND = 5 fF, capacitance between wires C = 30 fF, and
mutual inductance coupling factor K = 0.2.
7.3
Test-chip description
Two test-chips for evaluation of crosstalk eects were designed in a 0.18-m CMOS technology. In each test-chip, digital noise injecting structures are integrated together with
analog noise collecting structures.
Figure 7.3 illustrates a schematic diagram of the digital structures included in the rst
test-chip (test-chip A). The noise injecting structures consist of a ring oscillator with a frequency externally controlled by using an adequate bias current IREF , and a tapered inverter
chain driven by an external clock. The ring oscillator works at low frequency (about 1 MHz)
to allow the noise injection spikes to be correctly distinguished. Both structures drive a capacitance Cinj with a value of 5 pF, which behaves as a large clock net in a synchronous
digital circuit.
Figure 7.4 shows the analog structures used for noise collection. They consist of four
open-drain MOS transistors, each biased with an external gate voltage. Every MOS transistor drain is connected to a supply voltage (VDD or ground) through an external resistance
REXT , to properly bias the transistor. Two complementary MOS transistors (A and B) are
placed over the chip global substrate, while the other two transistors (C and D) are in local wells within the n-isolation layer. Figure 7.4 shows also the most important parasitic
elements, which contribute to digital switching noise propagation: series inductances (L),
capacitances between substrate and wells (C1 , C2 , C3 , and C4 ), and substrate resistance
(Rsub ). Figure 7.5 shows the layout of the test-chip.
VDD 1.2 V ext

Bonding
parasitics
113
VDD 1.2 V
digital
ENABLE
RING
OSCILLATOR
EXT
CLK
IREF
Cinj
Cinj
RSUB
Bonding
parasitics
SUB
RSUB
Figure 7.3: Schematic diagram of the digital injecting structures in test-chip A.

MOSFET in n-iso
VDD 2.5 V ext
NMOS OPEN
DRAIN
VDD
analog
R EXT
Bonding
parasitics
R SUB
VSS
analog
VDD 2.5 V ext
PMOS GATE
BIAS
C
PMOS
OPEN DRAIN
Bonding
parasitics
R EXT
VDD n -iso
R EXT
NMOS OPEN
DRAIN
NMOS GATE
BIAS
Bonding
parasitics
VDD 2.5 V ext
Bonding
parasitics
VSS
p-well
Bonding
parasitics
NMOS
GATE BIAS
PMOS
OPEN DRAIN
VDD 2.5 V ext

Bonding
parasitics
PMOS
GATE BIAS
Bonding
parasitics
Bonding
parasitics
R EXT
C3
C1
C2
C4
Figure 7.4: Schematic diagram of the analog noise collecting structures in test-chip A.
ANALOG
STRUCTURES
INJECTION
CAPACITANCE
MICROPROBE TEST
POINT
TAPERED CHAIN
RING OSCILLATOR
Figure 7.5: Layout of test-chip A.
114
Chapter 7
VDD 2.5 V ext
VDD 1.2 V ext
VDD 2.5 V
digital
VDD 2.5 V
analog
VDD 2.5 V ext
VDD 1.2 V
digital
PHASE
GENERATOR
without n-iso
PHASE
GENERATOR
with n-iso
BAND
GAP
BG
OUT
RSUB
SUB
VSS analog
VSS p-well
C1
VSS p-well C
3
C2
C4
Figure 7.6: Schematic diagram of test-chip B.

The second test-chip (test-chip B) includes building blocks designed for a pipeline A/D
converter. These structures were isolated and re-layouted in various congurations, to investigate the best solution in terms of crosstalk immunity. Six dierent injection structures
were integrated. Each of them includes a non-overlapping phase generator working at a
frequency of 4 MHz. Driving stages are cascaded to the generated phases, as the capacitive load of the original circuit was quite high (about 10 pF). The six congurations dier
in the distance from the collecting structures, the use of the n-iso layer, and the use of a
p-well guard ring. The analog noise-collecting structure is a band-gap voltage reference.
Figure 7.6 shows a schematic diagram of the second test-chip. The layout is illustrated in
Figure 7.7.
The phase generators are composed of two sections with dierent supply voltages: 1.2 V
and 2.5 V. Considering the congurations of the phase generator within the n-isolation layer,
the following parasitic elements can be individuated: two capacitances (C1 and C3 ) between the p-well and the n-isolation layer, and two capacitances (C2 and C4 ) between the
n-isolation layer and the p-substrate. These elements are considered in the simulation of the
structure to estimate crosstalk eects.
7.4
Simulation results
A fast but accurate analysis of current consumption during logic transitions is required to
evaluate the noise due to the switching activity of digital cells [56]. Digital simulation tools
are mostly optimized for simulation speed and for average power consumption. On the
other hand, analog circuit-level simulators (e.g. SPICE or SPECTRE) are quite inecient
for the analysis of large digital circuits.
Therefore, for mixed analog-digital circuits, to speed up simulation time, we propose a
method based on the separate analysis of the digital and the analog section, as illustrated in
Figure 7.8. In collaboration with the Department of Information Technologies of University of Milano, we developed a dedicated simulation algorithm in C++ in order to analyze
115
BAND GAP
PHASE GENp-well
shield, n-iso
PHASE GENn-iso
PHASE GEN without

n-iso
PHASE GENp-well
shield,without n-iso
MICROPROBE TEST
POINT
PHASE GENn-iso PHASE GEN without

n-iso
Figure 7.7: Layout of test-chip B.

INPUT
STIMULI
DIGITAL
CIRCUIT
ANALOG
CIRCUIT
DESIGN
Dedicated
algorithm
PROTOTYPE
iDD(t), iSS(t)
(PWL)
SPICE/
SPECTRE
MEASUREMENT
OUTPUT
VALIDATION
Figure 7.8: Flow diagram of the proposed approach.
current waveforms in digital circuits by using time-continuous functions, instead of sample

sequences, to represent signals. The algorithm saves a piece-wise linear (PWL) description
of current waveforms, that can be used as an input for subsequent circuit-level simulation
of the analog section of a mixed-signal circuit [57, 58].
Simulation results demonstrate that parasitics can severely degrade mixed-signal ICs
performance. The current drawn by digital blocks produces a voltage drop across o-chip
interconnect parasitics, described in Section 7.2, which aects the chip substrate. As a consequence, the substrate bias voltage is not kept at a constant value and displays the ground
bounce eect, as shown in the plot of Figure 7.9, which was obtained by simulating the
circuit in Figure 7.3 when the inverter chain is working.
116
Chapter 7
80
Substrate voltage [mV]
60
40
20
20
40
0
50
100
150
200
250
Time [ns]
Figure 7.9: Simulated substrate voltage aected by ground bounce due to the current drawn
by the digital section and bondwire/package parasitics.
12
AC coupled NMOS output voltage [mV]
10
8
6
4
2
0
2
4
0
50
100
150
200
250
Time [ns]
Figure 7.10: Simulated output voltage of the NMOS transistor A in Figure 7.4, with bondwire and package parasitics.
117
12
AC coupled PMOS output voltage [mV]
10
8
6
4
2
0
2
4
0
50
100
150
200
250
Time [ns]
Figure 7.11: Simulated output voltage of the PMOS transistor B in Figure 7.4, with bondwire and package parasitics.
To evaluate the eect of the ground bounce on the output of an MOS transistor [55], we
consider the drain current in the saturation region, given by:
iD =
W
1
Cox (VGS Vth )2 ,
2
L
(7.2)
with obvious meaning of symbols. A variation in the source-to-substrate voltage vSB causes
a variation in the transistor threshold voltage, since

(7.3)
Vth = Vt0 + vSB + 0 0 ,
where Vt0 is the threshold voltage for vSB = 0, is the body eect coecient (typically,
0.5 V1/2 ), and 0 is the surface potential (typically, 0 0.6 V) [59]. The voltage
drop across resistor REXT is:

2
1
W
vEXT = REXT iD = REXT Cox VGS Vt0 vSB + 0 0 .
2
L
(7.4)
If the substrate noise has a small amplitude, from small signal analysis we obtain:
vext = REXT id = REXT gmb vsb .
(7.5)
In this equation, vext , id and vsb are the small signal components of vEXT , iD and vSB , respectively, and gmb is the bulk transconductance, given by:

gmb = gm /(2 VSB + 0 ),
(7.6)
where VSB is the quiescent source-to-substrate voltage and gm is the transistor transconductance.
118
Chapter 7
Bandgap output voltage [V]
1.26
1.25
1.24
1.23
1.22
0
100
200
300
400
500
Time [ns]
Figure 7.12: Simulated band-gap output voltage when the phase generator within n-isolation
is working (parasitic inductance L = 2 nH).
In test-chip A, MOS transistors have a conductance parameter K = Cox WL = 1.1 mA/V2
and are biased with a drain current ID = 1 mA. From these gures, we obtain a small signal
transconductance gm = 2 KID = 2.1 mA/V, and a bulk transconductance gmb = 0.3 gm =

0.63 mA/V.
Figures 7.10 and 7.11 show the simulated output voltages for MOS transistors labeled
with A (NMOS device) and B (PMOS device) in Figure 7.4, respectively. The output voltages are aected by disturbances with a peak value of 11 mV for the NMOS device and
6 mV for the PMOS device. From Equation (7.5), we can note that the ground bounce
aects the local substrate of the NMOS device more than the local substrate of the PMOS
device. This is due to the shielding eect of the n-well around the PMOS device.
The circuit in Figure 7.6 was simulated with the dedicated C++ algorithm and SPECTRE to analyze digital switching noise due to o-chip inductances. The model for o-chip
parasitics was simplied, neglecting electromagnetic coupling between adjacent bondwires,
since we noted that for this test-chip mounted in the JLCC-24 package, the main contribution to crosstalk is due to the series inductance. Indeed, the pad count is low (20) and the die
size is comparable to the package cavity, which leads to relatively short and widely spaced
bonding wires.
The same model was also used to simulate the test-chip assembled on board. For the
chip-on-board assembly, the series inductance is lower, as does not include the contribution due to the package geometry. Hence, for simulations, we assumed a series inductance
L = 2 nH for the chip-in-package and L = 1 nH for the chip-on-board.
Figures 7.12 and 7.13 show the simulation results for the test-chip, assuming that one
clock phase generator within n-isolation is working. Figure 7.12 illustrates the band-gap
output voltage aected by switching noise when all chip pads are interconnected through a
parasitic inductance L = 2 nH. Figure 7.13 illustrates the band-gap output voltage when the
119
Bandgap output voltage [V]
1.26
1.25
1.24
1.23
1.22
0
100
200
300
400
500
Time [ns]
Figure 7.13: Simulated band-gap output voltage when the phase generator within n-isolation
is working (parasitic inductance L = 1 nH).
parasitic inductance is L = 1 nH. From simulations, the noise peak voltage is about 18 mV
when L = 2 nH, and about 10 mV when L = 1 nH. It is apparent that a reduction in parasitic
inductances leads to better noise immunity.
7.5
Experimental results
The two test-chips were mounted with two dierent mounting techniques: chip-in-package
and chip-on-board.
For the rst technique, chips were assembled into a JLCC-24 package. In this case, the
length of bonding wires is 1 mm, which leads to a parasitic inductance of about 1 nH. Since
the total parasitics inductance for the chip assembled into the JLCC package is 2 nH, we
can conclude that the package itself contributes with a 1 nH inductance. In the case of chipon-board assembly technique, the length of bonding wires is similar to the chip-in-package,
thus leading to similar values for parasitic inductances due to bondwires and board (about
1 nH). This technique avoids additional parasitic elements due to the package. Figure 7.14
shows the rst test-chip mounted into a JLCC-24 package, while Figure 7.15 shows the
test-chip mounted on board.
The test-chips were fed with a 4-MHz clock signal provided through an external clock
generator (shown in Figure 7.16), driving the tapered inverter chain in Figure 7.3. The
output voltages at the drain node of MOS transistors were captured through a digitizing
oscilloscope working on equivalent sampling rate of 2 GS/s.
Figures 7.17, 7.18, 7.19, and 7.20 show the time-domain switching noise at the transistor
outputs. In particular, Figures 7.17 and 7.18 show the output voltages of NMOS transistors
120
Chapter 7
Bonding wire
Package frame
Figure 7.14: Microphotograph of test-chip A mounted in package.
Bonding wire
Board interconnections
Figure 7.15: Microphotograph of test-chip A mounted on board.
121
1.4
1.2
1
Voltage [V]
0.8
0.6
0.4
0.2
0
0.2
Time [50 ns/div]
Figure 7.16: External clock applied to the tapered inverter chain.

Table 7.1: Measured rms values of AC coupled disturbances at transistor outputs.
chip-in-package
output noise voltage
chip-on-board
output noise voltage
layout conguration
peak-to-peak
rms
peak-to-peak
rms
NMOS outside n-iso layer
25.47 mV
2.284 mV
21.51 mV
1.870 mV
NMOS inside n-iso layer
19.26 mV
1.378 mV
18.40 mV
1.618 mV
PMOS outside n-iso layer
9.20 mV
0.641 mV
5.04 mV
0.405 mV
PMOS inside n-iso layer
10.01 mV
0.434 mV
7.12 mV
0.504 mV
outside and inside the n-isolation layer, respectively, while Figures 7.19 and 7.20 show the
output voltages of PMOS transistors outside and inside the n-isolation layer, respectively.
Measured results of peak-to-peak noise in Figures 7.17 and 7.19 are in agreement with
simulated values. We observe that the output noise is lower for PMOS devices, as expected.
Table 7.1 summarizes the measured peak-to-peak and rms noise values for the test-chip
in the two assembly congurations. By comparing the above gures, we can note that the
n-isolation layer improves crosstalk immunity of NMOS devices. On the other hand, PMOS
transistors do not benet by the insertion of the n-isolation layer. Indeed, PMOS devices
are shielded by the n-well, as shown in Figure 7.1: for this reason, the additional n-isolation
layer does not lead to remarkable improvements. Moreover, the chip-on-board has a lower
value of peak-to-peak noise voltage than the chip-in-package, thanks to the reduction of
parasitic inductances.
Figure 7.21 shows the second test-chip mounted into a JLCC-24 package, while Figure 7.22 shows the test-chip mounted on board.
Chapter 7
15
15
10
10
AC coupled voltage [mV]
122
10
15
10
15
Time [50 ns/div]
(a)
Time [50 ns/div]
(b)
15
15
10
10
Figure 7.17: Output of the NMOS transistor outside n-isolation: (a) chip-in-package; (b)
chip-on-board
.
10
15
10
15
Time [50 ns/div]
(a)
Time [50 ns/div]
(b)
15
15
10
10
Figure 7.18: Output of the NMOS transistor inside n-isolation: (a) chip-in-package; (b)
chip-on-board.
10
15
10
Time [50 ns/div]
(a)
15
Time [50 ns/div]
(b)
Figure 7.19: Output of the PMOS transistor outside n-isolation: (a) chip-in-package; (b)
chip-on-board.
123
15
15
10
10
10
15
10
Time [50 ns/div]
(a)
15
Time [50 ns/div]
(b)
Figure 7.20: Output of the PMOS transistor inside n-isolation: (a) chip-in-package; (b)
chip-on-board.
Figure 7.21: Microphotograph of test-chip B mounted in package.
To achieve further reduction of parasitic inductances, one test-chip sample was mounted
on board using double bonding for all pads involved in the analysis. Figure 7.23 shows a
detail of the double bondwires on chip pads. Multiple bonding helps to reduce parasitic
inductances, since two parallel wires have an equivalent inductance equal to half the inductance of the single wire. However, it is worth noting that interconnection parasitics due to
the circuit board remain unchanged.
The test-chips, assembled as described above, were fed with a 4-MHz clock signal provided through an external clock generator (Figure 7.24). Figures 7.25, 7.26, and 7.27 show
the time-domain switching noise at the band-gap reference output of the test-chip in the different assembly congurations, namely, the chip assembled into the package (Figure 7.25),
the chip-on-board with single bondwires (Figure 7.26), and the chip-on-board with double
124
Chapter 7
Figure 7.22: Microphotograph of test-chip B mounted on board.
Figure 7.23: Microphotograph of double bonding on chip pads.

bondwires (Figure 7.27). Signals were measured with a 1-GHz digitizing oscilloscope.
Looking at the three gures, one can notice a very small dierence between peak voltages in the time domain. Indeed, digital switching noise produces transient oscillations in
the frequency range of several gigahertz (10 GHz or above), which cannot be captured by a
1-GHz digitizing oscilloscope. Therefore, peak values are not the best indicator of crosstalk.
A better estimate can be obtained by calculating the rms value of the noise disturbance over
a large number of samples. This measurement has been done for all congurations.
The measurement results are summarized in Table 7.2. First of all, we do not notice any
dierence due to the distance between the digital and the analog blocks. For this reason,
Table 7.2 shows the results for only four congurations: the digital blocks placed on the
left and on the bottom sides of the chip in Figure 7.7 produce the same eects, although the
blocks on the bottom side are farther from the analog sensitive part. This suggests that the
main coupling mechanism is independent of the distance.
Indeed, coupling between digital and analog sections occurs also through the pad rings:
125
1.75
1.5
Input clock voltage [V]
1.25
1
0.75
0.5
0.25
0
0.25
Time [100 ns/div]
Figure 7.24: Digital input clock to phase generator.
AC coupled voltage [mv]
10
10
Time [100 ns/div]
Figure 7.25: Chip-in-package: AC coupled disturbances at the band-gap voltage reference

output.
in our test-chip, this is the main path for crosstalk. For this reason, we observe a limited
dierence in crosstalk immunity between dierent layout congurations.
Nevertheless, we can perform a qualitative analysis on shielding eects of the n-isolation
layer and the p-well guard ring. From Table 7.2, we notice that the layout conguration with
the p-well ring and without the n-isolation displays the worst behavior: the p-well ring,
126
Chapter 7
10
10
Time [100 ns/div]
Figure 7.26: Chip-on-board: AC coupled disturbances at the band-gap voltage reference

output.
10
10
Time [100 ns/div]
Figure 7.27: Chip-on-board with double bonding: AC coupled disturbances at the band-gap
voltage reference output.
biased at the substrate voltage and placed around the digital section, collects the switching
noise of the latter and propagates it to the whole chip through the substrate bias contacts.
An n-isolation layer placed around the digital part reduces the crosstalk. This eect is
due to the shielding eect of the n-isolation, which separates the p-well from the p-doped
127
Table 7.2: Measured rms values of AC coupled disturbances at the band-gap voltage reference output.
layout conguration
rms output noise voltage
n-iso layer
p-well ring
chip-in-package
chip-on-board,
1 bondwire
chip-on-board,
2 bondwires
no
no
1.310 mV
1.285 mV
1.248 mV
yes
no
1.185 mV
1.163 mV
1.087 mV
no
yes
1.400 mV
1.364 mV
1.296 mV
yes
yes
0.965 mV
1.073 mV
1.021 mV
substrate [60]. The n-isolation layer used together with the p-well guard ring displays the
best performance, as the shielding eect of the n-isolation is enhanced by the proper biasing
of the substrate through the p-well ring.
7.6
Conclusion
This chapter has presented an analysis of the eects of digital switching noise on analog
sections in mixed-signal CMOS ICs.
Two CMOS test-chips were designed and mounted with dierent techniques to compare simulated with experimental results. This comparison demonstrates a good agreement
between simulated and measured data.
Experimental evidence indicates that chip-on-board assembly technique has better performance than chip-in-package mounting technique, due to reduction of parasitics. Nevertheless, the improvement is limited, due to the presence of bondwire and board parasitics.
O-chip interconnection inductance causes on-chip supply voltage bounces, which propagate through on-chip interconnections and through the substrate. Careful layout techniques
can also help to reduce crosstalk eects.
Results demonstrate that NMOS transistors in analog subcircuits can be eectively
shielded with an n-isolation layer, to reduce the amount of collected digital switching noise.
Shielding of digital parts with n-isolation layer is benecial; on the other hand, a single
p-well guard ring propagates digital noise, thus worsening the overall performance.
An assembling technology without bondwires (ip-chip mounting) would have even
better noise immunity, due to reduced parasitic inductances. Therefore, it is expected that it
will become more and more popular in the next future for mixed-signal integrated systems.
Chapter 8
Conlusions
This thesis presents the research activity developed in the framework of the Italian National
Program FIRB Enabling technologies for recongurable wireless terminals and devoted
to the realization of a baseband section for a multistandard wireless terminal supporting
the main important protocols for voice (GSM), data (Bluetooth, WLAN) and mixed datavoice (UMTS). In particular the activity of the Integrated Microsystem Laboratory, carried
out with the Department of Innovation Engineering of University of Lecce, is focused on
the realization of a DAC and a reconstruction lter to be embedded in a recongurable
transmitter based on direct conversion architecture.
Several baseband sections have been integrated during the three-years activity. All these
blocks acts as interface between the digital signal processor and the radio-frequency part
which performs the frequency translation of the baseband signal. Four dierent test-chips
have been integrated:
Device #1: baseband section for the WLAN/UMTS standards consisting of a DAC, output transimpedance stage and reconstruction lter, with a total power consumption of
20 mW for WLAN and 16.8 mW for UMTS;
Device #2: baseband section for the WLAN/UMTS standards consisting of DAC, passive
output stage and reconstruction lter, which achieves the same performance of device #1,
but with a reduction in the power consumption, which is equal to 11 mW for WLAN and
8.4 mW for UMTS;
Device #3: baseband section for the WLAN/Bluetooth standards consisting of DAC,
passive output stage and reconstruction lter, with a power consumption of 8 mW for
WLAN and 5.4 mW for Bluetooth;
Device #4: high-frequency baseband section for the WLAN standard, which avoids the
use of an active reconstruction lter achieving a power consumption of 2.4 mW.
The experimental results obtained from the test-chip measurements show that all the
devices fulll the specications imposed by the dierent standards, even with the low 1.2-V
supply voltage adopted for the design. The nal version of the recongurable transceiver
consists of two distinct RX chains, one supporting GSM, UMTS and Bluetooth, the other
supporting WLAN and Bluetooth, and two distinct TX chains, one supporting GSM, UMTS
and Bluetooth, the other supporting WLAN and Bluetooth. The device #3 has been integrated together with the radio-frequency section (Figure 8.1) to implement the WLAN/Bluetooth
recongurable transmitter.
In this thesis the attention is focused on the couple of devices #2 and #4. The implementation of the two blocks have been described in detail: the evaluation of specications
through a Matlab time-domain model, the transistor-level design and, nally, the experimental results obtained with the test-chips realized in a 0.13-m CMOS technology. The
Conlusions
129
Baseband Section
RF Section
Figure 8.1: Microphotograph of the test-chip for the WLAN/Bluetooth recongurable TX

chain.
main aspect of interest of the proposed blocks are the recongurability between the dierent
standards (obtained sharing the same functional blocks), the processing of the signal with
high linearity (even with the low 1.2-V supply voltage) and the minimization of the power
consumption, which have driven all the design choices.
In the last chapter of the thesis, another issue related to the FIRB project is taken into
account. The eect of the crosstalk between the digital and the analog sections of a mixedsignal integrated circuit is studied with the aim of obtaining some design and layout rules.
The obtained results are of primary concern especially if we want integrate a full systemon-chip which comprehends large digital sections and sensitive analog parts (this is the
case of a fully-integrated wireless transceiver). In particular some of the design and layout
choices in implementing the baseband section for the TX chain were taken on the basis of
the experimental results achieved with this activity.
Appendix A
A.1
Crest factor of a signal
Considering a real signal s(t) with mean power P and zero-peak amplitude equal to A0,pk ,
its root mean square (rms) amplitude is dened as:
(A.1)
Arms = P R,
where R is the reference resistance equal to 50 . The crest factor of the signal is dened
as the ratio between the zero-peak amplitude and the rms amplitude:
CR =
A0,pk
.
Arms
(A.2)
The denition of the crest factor relates the power of a signal with its zero-peak amplitude:

2
1
1 A0,pk
2
P = (Arms ) =
.
R
R CR
(A.3)
Considering for example a WLAN signal, its crest factor is equal to 4. A WLAN signal
with a zero-peak amplitude of A0,pk has a power equal to:

2
A0,pk
1
1
.
P = (Arms )2 =
R
R 16
(A.4)
The ratio between the power of a sinusoidal signal with zero-peak amplitude A0,pk and the
power of a WLAN signal with equal
zero-peak amplitude is therefore 8, cosidering that the
crest factor of a sinusoidal signal is 2. The dierence between the two powers expressed
in dB is therefore equal to 9 dB.
A.2
Linearity of a transfer function
Let us consider the transfer function of a real system y = f(x), where x is the input of the
system (bounded between 0 and A) and y the resulting output. We suppose that the ideal
transfer function of the system is linear and we express it as y = id(x) = ax + b. The real
transfer function can be considered as the sum two terms, a linear one lin(x) and a nonlinear one (x). As indicated in Figure A.1, the linear term lin(x) can be obtained joining
the extreme points of the real transfer function, i.e f(0) and f(A). As a consequence, the real
transfer function can be written as:
y = f(x) = lin(x) + (x) = a x + b + (x),
(A.5)
Appendix A
131
1.5
linear part of the
real transfer function
real transfer function
0.5
ideal transfer function
0.2
0.4
0.6
0.8
Figure A.1: Ideal and real transfer functions for a system y = f(x).
with (0) = 0 and (A) = 0. The linear term lin(x), compared with the ideal one id(x)
presents an oset error:
(A.6)
oset = b b,
and a gain error, coming from the dierent slopes of the two lines, i.e a and a . We want
to eliminate from the real transfer function the oset and gain errors and to compare the
resulting transfer function with the ideal one. The gain error can be corrected as follows:
fgain corrected (x) =
!
a
a
b a a
f(x) = a x + b + (x) = ax + + (x).

a
a
a
a
(A.7)
We obtain a transfer function whose linear part (the line joining the two extreme points) has
the same slope a of the ideal transfer function. The oset error can be corrected as follows:
fcorrected (x) = fgain corrected (x) + b
b a
a
= ax + b + (x).
a
a
(A.8)
To pass from the real transfer function f(x) to the corrected one we have to apply the following corrections:
fcorrected (x) =
a
a
f(x) + id(0) f(0) = gain f(x) + id(0) gain f(0),

a
a
(A.9)
indicating as gain the ratio between the two slopes a and a . At this point we can compare the
corrected transfer function with the ideal one. The integral non-linearity INL(x) is dened
as the dierence between the corrected transfer function and the ideal one:
INL(x) = fcorrected (x) id(x) =
a
(x).
a
(A.10)
132
Appendix A
Suppose that the output range of the ideal transfer function can be divided into N intervals.
We dene the ideal least signicant bit (LSB) the amplitude of each interval:
LSB =
id(A) id(0) aA + b b aA
=
=
.
N
N
N
(A.11)
The INL(x), normalized with respect to the ideal LSB is:

INLLSB (x) =
INL(x)
N
= (x).
LSB
aA
(A.12)
The non-linearity of the transfer function can also be calculated making directly the
dierence between f(x) and its linear part lin(x). We indicate the integral non-linearity
evaluated in this way as inl(x). We obtain:
inl(x) = f(x) lin(x) = (x).
(A.13)
The real least signicant bit (lsb) can be dened as:

lsb =
f(A) f(0) a A + b b a A LSB

.
=
=
=
N
N
N
gain
(A.14)
We have that the values of INL(x) and of inl(x) dier for a factor gain . The two quantities
become equal if they are normalized with respect to the LSB and lsb respectively. We have:
INLLSB (x) =
fcorrected (x) (ax + b) gain (x)

N
=
= (x)
LSB
LSB
aA
(A.15)
f(x) (a x + b ) (x)

N
=
= (x).
lsb
lsb
aA
(A.16)
inllsb (x) =
A.3
INL and DNL denition for a DAC
We apply the theory reported in the previous section for the linearity of a generic transfer
function to give the denition of the integral and dierential non-linearity of a digital-to
analog converter.
The static transfer function of a N-bit digital-to-analog converter has 2N digital input codes (indicated as k = 0, 1, ..., 2N 1) and 2N analog output values (indicated as
V(0), V(1), ..., V(2N 1)). In the ideal case these analog values are separated one from
the other of an equal interval, which is indicated as least signicant bit (LSB). There are
2N 1 intervals whose amplitude is 1 LSB. The dierence between the analog output value
corresponding to the 2N 1 code and the analog output value corresponding to the rst code
is indicated as gain. In the ideal case the gain is (2N 1) LSB.
In a real DAC the measured transfer function diers from the ideal one. The oset error
is dened as the dierence between the rst real analog output value and the rst ideal one:
oset = Vreal (0) Vid (0),
(A.17)
while the ratio between the ideal gain and the real one, indicated as gain , is:
gain =
(2N 1)LSB
,
Vreal (2N 1) Vreal (0)
(A.18)
Appendix A
133
The total error in correspondence of the code k is given by:

(k) = Vreal (k) Vid (k).
(A.19)
The linearity errors of a DAC are characterized giving the integral non-linearity for each
code k (INL(k), with k going from 0 to 2N 1) and the dierential non-linearity for each
transition k between code k 1 and the successive one k (DNL(k), with k going from 1 to
2N 1). To calculate these values we have rst to remove from the real transfer function the
oset and gain errors:
Vcorrected (k) = gain Vreal (k) + Vid (0) gain Vreal (0),
(A.20)
then we can compare the corrected transfer function with the ideal one. Note from (A.20)
that the rst and last points of the corrected transfer function and of the ideal one are the
same: Vcorrected (0) = Vid (0) and Vcorrected (2N 1) = Vid (2N 1).
The integral non-linearity in correspondence of the code k is dened as the dierence
between the analog output value at code k of the corrected transfer function and the corresponding one of the ideal transfer function:
INL(k) = Vcorrected (k) Videal (k).
(A.21)
Thanks to the oset and gain error correction we have that INL(0) = INL(2N 1) = 0. The
dierential non-linearity in correspondence of the transition k is dened as:
DNL(k) = Vcorrected (k) Vcorrected (k 1) LSB.
(A.22)
The two quantities are related by the following relationships:

INL(k) INL(k 1) = DNL(k)
INL(k) =
k

i=1
DNL(i).
(A.23)
(A.24)
References
[1] Enabling technologies for wireless recongurable terminals, Italian National Program FIRB, web-site: http://ims.unipv.it/rb.
[2] A. Baschirotto, F. Campi, R. Castello, G. Cesura, R. Guerrieri, L. Lavagno, A. Lodi,
P. Malcovati, and M. Toma, Baseband Analog Front-End and Digital Back-End for
Recongurable Multistandard Terminals, Circuit and Systems (CAS) Magazine, to
be published.
[3] F. Agnelli, G. Albasini, I. Bietti, A. Gnudi, A. Lacaita, D. Manstretta, R. Rovatti,
E. Sacchi, P. Savazzi, F. Svelto, E. Temporiti, S. Vitali, and R. Castello, System
Analysis and Design of a Recongurable RF front-end, Circuit and Systems (CAS)
Magazine, to be published.
[4] A. Vigna, Design of a D/A converter for recongurable mobile terminals, Ph.D.
Thesis, Department of Electronics, University of Pavia, October 2005.
[5] S. DAmico, Low-Power Analog Baseband Blocks for Telecom Transceivers, Ph.D.
Thesis, Department of Innovation Engineering, University of Lecce, 2005.
[6] Wireless Transceivers, Section 5, pp. 90-107, International Solid-State Circuit
Conference (ISSCC) Digest of Technical Papers, February 2005.
[7] Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specications, ANSI/IEEE Std. 802.11, 1999 Edition.
[8] Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specications - High-Speed Physical Layer in the 5-GHz Band, ANSI/IEEE Std. 802.11a,
1999 Edition.
[9] ETSI TS 101.475, Broadband Radio Access Network (BRAN), HiperLAN Type 2,
Physical (PHY) Layer, ver. 1.3.1, 2001.
[10] Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specications - Higher-Speed Physical Layer Extension in the 2.4-GHz Band, ANSI/IEEE
Std. 802.11a, 1999 Edition.
[11] Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specications - Further Higher-Speed Physical Layer Extension in the 2.4-GHz Band,
ANSI/IEEE Std. 802.11g, D1.1, January 2002 Edition.
[12] IEEE Standard for Local and Metropolitan Area Networks Part 16: Air Interface for
Fixed Broadband Wireless Access Systems, IEEE Std. 802.16-2001, Apr. 2002.
[13] ETSI TS 34.121, 3rd Generation Partnership Project, Technical Specication Group
Radio Access Networks, UE Radio Transmission and Reception (FDD), Release
1999, ver. 3.13.0 (2003-03).
References
135
[14] W. Audoglio and S. Marabelli, Model of WLAN 802.11a Transceiver, available at

http://ims.unipv.it/rb.
[15] RadioLab 3G, available at http://www.radioscape.com.
[16] V. Ferragina, A. Frassone, N. Ghittori, P. Malcovati, and A. Vigna, Behavioral study
and design of a digital interpolator lter for wireless recongurable transmitters,
Proceedings of SPIE, VLSI Circuits and Systems II, vol. 5837, pp. 270-277, June
2005.
[17] S. Mehta, D. Weber, M. Terrovitis, K. Onodera, M. Mack, B. Kaczynski, H. Samavati,
S. Jen, W. Si, M. Lee, K. Singh, S. Mendis, P. Husted, N. Zhang, B. McFarland, D.
Su, T. Meng, and B. Wooley, An 802.11g WLAN SoC, International Solid-State
Circuit Conference (ISSCC) Digest of Technical Papers, pp.94-95, February 2005.
[18] H. Darabi, S. Khorram, Z. Zhou, T. Li, B. Marholev, J. Chiu, J. Castaneda, E. Chien,
S. Anand, S. Wu, M. Pan, R. Roufoogaran, H. Kim, P. Lettieri, B. Ibrahim, J. Rael,
L. Tran, E. Geronaga, H. Yeh, T. Frost, J. Trachewsky, and A. Rofougaran, A Fully
Integrated Soc for 802.11b in 0.18 m CMOS, International Solid-State Circuit Conference (ISSCC) Digest of Technical Papers, pp. 96-97, February 2005.
[19] J. Thomson, B. Baas, E. M. Cooper, J. M. Gilbert, G. Hsieh, P. Husted, A. Lokanathan,
J. S. Kuskin, D. McCracken, B. McFarland, T. H. Meng, D. Nakahira, S. Ng, M. Rattehalli, J. L. Smith, R. Subramanian, L. Thon, Y. H. Wang, R. Yu, and X. Zhang, An
Integrated 802.11a Baseband and MAC Processor, International Solid-State Circuit
Conference (ISSCC) Digest of Technical Papers, February 2002.
[20] B. Razavi, RF Microelectronics, Prentice Hall PTR, Upper Saddle River, New Jersey,
1998.
[21] J. B. Shyu, G. C. Temes, and K. Yao, Random errors in MOS capacitors , IEEE
Journal of Solid-State Circuits, vol. sc17, pp. 948-955, December 1982
[22] J. B. Shyu, F. Krummenacher, and G. C. Temes, Random error eects in matched
MOS capacitors and current sources, IEEE Journal of Solid-State Circuits, vol. sc19,
pp. 1070-1076, December 1984
[23] M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, Matching Properties
of MOS Transistors, IEEE Journal of Solid-State Circuits, vol. 24, no. 5, pp. 1433
1440, October 1989.
[24] K. R. Lakshmikumar, R. A. Hadaway, and M. A. Copeland, Characterization and
Modeling of Mismatch in MOS Transistor for Precision Analog Design, IEEE Journal of Solid-State Circuits, vol. sc21, no. 6, pp. 10571066, December 1986.
[25] K. R. Lakshmikumar, R. A. Hadaway, and M. A. Copeland, Reply to A Comment
on Characterization and Modeling of Mismatch in MOS Transistor for Precision
Analog Design , IEEE Journal of Solid-State Circuits, vol. 23, no. 1, p. 296,
February 1988.
[26] C. S. G. Conroy, W. A. Lane, and M. A. Moran, A Comment on Characterization
and Modeling of Mismatch in MOS Transistor for Precision Analog Design, IEEE
Journal of Solid-State Circuits, vol. 23, no. 1, pp. 294296, February 1988.
136
References
[27] A. Van den Bosch, M. Steyaert, and W. Sansen, An accurate Statistical Yield Model
for CMOS Current-Steering D/A Converters, Proceedings of the International Symposium of Circuits and Systems (ISCAS), vol. 4, pp. 105108, May 2000.
[28] J. Wikner and N. Tan, Modeling of CMOS Digital-to-Analog Converters for Telecommunication, IEEE Transaction on Circuits and Systems-II: Analog and Digital Signal
Processing, vol. 46, no. 5, pp. 489499, May 1999.
[29] D. Giotta, P. Pessl, M. Clara, W. Klatzer, and R. Gaggl, Low-Power, 14-bit Current
Steering DAC, for ADSL2+/CO Applications in 0.13 m CMOS, Proceedings of
European Solid-State Circuit Conference (ESSCIRC), pp. 163-166, September 2004.
[30] M. Clara, W. Klatzer, A. Wiesbauer, and D. Straeussnigg, A 350MHz low-OSR
Current-Steering DAC with Active Termination in 0.13 m CMOS, International
Solid-State Circuit Conference (ISSCC) Digest of Technical Papers, pp. 118-119,
February 2005.
[31] N. Ghittori, A. Vigna, P. Malcovati, S. DAmico, A. Baschirotto, A low voltage, low
distortion (1.2 V, 29.5 dBm OIP3) recongurable baseband block for mobile applications, Proceeding of Ph.D. Research in Microelectronics and Electronics (PRIME),
vol. I, pp. 25-28, July 2005.
[32] N. Ghittori, A. Vigna, P. Malcovati, S. DAmico, and A. Baschirotto, A Low-Power,
Low-Voltage (11mW/8.4mW, 1.2V) DAC+Filter for Multistandard (WLAN/UMTS)
Transmitters, Symposium on VLSI Circuits Digest of Technical Papers (VLSI), pp.
334-337, June 2005.
[33] Z. Yu, D. Chen, and R. Geiger, 1-D and 2-D switching strategies achieving near
optimal INL for thermometer-coded current steering DACs, Proceedings of the International Symposium of Circuits and Systems (ISCAS), vol. I, pp. 909-912, May
2003.
[34] Y. Nakamura, T. Miki, A. Maeda, H. Kondoh, and N. Yazawa, A 10-b 70-MS/s
CMOD D/A Converter, IEEE Journal of Solid-State Circuits, vol. 26, no. 4, pp.
637-642, April 1991.
[35] C. Lin, and K. Bult, A 10-b, 500-MSample/s CMOD DAC in 0.6 mm2 , IEEE Journal of Solid-State Circuits, vol. 33, no. 12, pp. 1948-1958, December 1998.
[36] J. Bastos, A. M. Marques, M. S. J. Steyaert, and W. Sansen, A 12-Bit Intrinsic Accuracy High-Speed CMOS DAC, IEEE Journal of Solid-State Circuits, vol. 33, no.
12, pp. 1959-1969, December 1998.
[37] S. Lee, J. Park, J. Yoon, J. Song, and S. Lee, A 3 V 10b 100 MS/s Digital-to-Analog
Converter for Cable Modem Applications, Proceedings of the IEEE Asia Pacifc Conference on ASICs, pp. 203-205, August 2000.
[38] G. A. M. Van Der Plas, J. Vandebbussche, W. Sansen, M. S. J. Steyaert, and G. G. E.
Gielen, A 14-bit Intrinsic Accuracy Q2 Random Walk CMOS DAC, IEEE Journal
of Solid-State Circuits, vol. 34, no. 12, pp. 1708-1718, December 1999.
References
137
[39] N. U. Andersson, and J. J. Wikner, A strategy for implementing dynamic element

matching in current-steering DACs, Proceedings of Southwest Symposium on MixedSignal Design, pp. 51-56, February 2000.
[40] H. T. Jensen, and J. F. Jensen, Dynamic element matching for highly linear digitalto-analog conversion, Advanced A/D and D/A Conversion Techniques and their Application , pp. 5861, July 1999.
[41] K. OSullivan, C. Gorman, M. Hennessy, and V. Callaghan, A 12b 320Msample/s
Current Steering CMOS D/A Converter in 0.44 mm2 , Proceedings of European
Solid-State Circuit Conference (ESSCIRC), pp. 89-92, September 2003.
[42] W. Schoeld, D. Mercer, and L. St. Onge, A 16b 400MS/s DAC with <-80dBc IMD
to 300MHz and <-160dBm/Hz Noise Power Spectral Density, International SolidState Circuit Conference (ISSCC) Digest of Technical Papers, pp. 126-127, February
2003.
[43] V. Ferragina, N. Ghittori, G. Torelli, G. Boselli, G. Trucco,and V. Liberali, Analysis of Crosstalk Eects on Mixed-Signal CMOS ICs with Dierent Mounting Technologies, Proceedings of the IEEE Instrumentation and Measurement Technology
Conference (IMTC), pp. 1979-1984, May 2005.
[44] G. Boselli, V. Ferragina, N. Ghittori, V. Liberali, G. Torelli, and G. Trucco, Impact
of Package Parasitics on Crosstalk in Mixed-Signal ICs, Proceedings of SPIE, VLSI
Circuits and Systems II, vol. 5837, pp. 213-222, June 2005.
[45] K. Y. Lee, S. W. Lee, Y. Koo, H. K. Huh, H. Y. Nam, J. W. Lee, J. Park, K. Lee, D.
K. Jeong, and W. Kim, Full-CMOS 2-GHz WCDMA direct conversion transmitter
and receiver, IEEE Journal of Solid-State Circuits, vol. 38, no. 1, pp. 43-53, January
2003.
[46] R. E. Crochiere and L. R. Rabiner, Interpolation and Decimation of Digital Signal
- A Tutorial Review, Proceedings of the IEEE, vol. 69, no. 3, pp. 300-331, March
1981.
[47] Y. Cong and R. L. Geiger, A 1.5V 14b 100MS/s Self-Calibrated DAC, International
Solid-State Circuit Conference (ISSCC) Digest of Technical Papers, pp. 128-129,
February 2005.
[48] J. Deveugele and M. Steyaert, A 10b 250MS/s Binary-Weighted Current-Steering
DAC, International Solid-State Circuit Conference (ISSCC) Digest of Technical Papers, pp. 362-363, February 2004.
[49] K. Doris, J. Briaire, D. Leenaerts, M. Vertreg, and A. van Roermund, A 12b 500MS/s
DAC with >70dB SFDR up to 120MHz in 0.18 m CMOS, International Solid-State
Circuit Conference (ISSCC) Digest of Technical Papers, pp. 116-117, February 2005.
[50] J. Hyde, T. Humes, C. Diorio, M. Thomas, and M. Figueroa, A 300-MS/s 14-bit
Digital-to-Analog Converter in Logic CMOS, Proceedings of the IEEE, pp. 734740, vol. 38, no. 5, May 2003.
138
References
[51] Q. Huang, P. A. Francese, C. Martelli, and J Nielsen, A 200MS/s 14b 97mW DAC
in 0.18m CMOS, International Solid-State Circuit Conference (ISSCC) Digest of
Technical Papers, pp. 364-365, February 2004.
[52] T. Chen et al., A 14-Bit 130-MHz CMOS Current-Steering DAC with Adjustable
INL, Proceedings of European Solid-State Circuit Conference (ESSCIRC), pp.167170, September 2004.
[53] S. Donnay and G. Gielen, Eds., Substrate Noise Coupling in Mixed-Signal ASICs,
Kluwer Academic Publishers, Boston, MA, USA, 2003.
[54] G. Trucco, G. Boselli, and V. Liberali, An approach to computer simulation of
bonding and package crosstalk in mixed-signal CMOS ICs, Proceedings of Brazilian
Symposium on Integrated Circuit Design (SBCCI), pp. 129-134, September 2004.
[55] V. Liberali, S. Pettazzi, R. Rossi, and G. Torelli, Analysis and simulation of substrate
noise coupling in mixed-signal CMOS ICs, Transworld Research Network Recent
Res. Devel. Electronics, vol. 1, pp. 145163, 2002.
[56] M. van Heijningen, M. Badaroglu, S. Donnay, M. Engels, and I. Bolsens, Highlevel simulation of substrate noise generation including power supply noise coupling,
Proceedings of Design Automation Conference (DAC), pp. 446-451, June 2000.
[57] G. Trucco, G. Boselli, and V. Liberali, An analysis of current waveforms in CMOS
logic cells for RF mixed circuits, Proceedings of IEEE International Conference on
Microelectronics (MIEL), pp. 563-566, May 2004.
[58] V. Ferragina, N. Ghittori, G. Torelli, G. Boselli, G. Trucco, and V. Liberali, A TimeDomain Current Model for Fully CMOS Logic Gates, Proceedings of the 2nd Annual
IEEE Northeast Workshop on Circuits and Systems (NEWCAS), pp. 29-32, June 2004.
[59] R. S. Muller and T. I. Kamins, Device Electronics for Integrated Circuits, John Wiley
& Sons, New York, NY, USA, 1977.
[60] R. Rossi, G. Torelli, and V. Liberali, Model and verication of triple-well shielding
on substrate noise in mixed-signal CMOS ICs, Proceedings of European Solid-State
Circuit Conference (ESSCIRC), pp. 643-646, September 2003.
Acknowledgments
First of all I would like to thank my tutor Prof. Piero Malcovati and my co-tutor Prof.
Andrea Baschirotto for all the support they gave to my work during these years. I have
appreciated not only their incomparable technical competence and practical sense but also
their human qualities. Moreover their help is not going away now that my Ph.D. is nishing.
I am particularly grateful also to my supervisors in the activity of crosstalk study, Prof.
Guido Torelli and Prof. Valentino Liberali.
Then I would like to thank the two guys who worked with me: Andrea and the life is for
you Vincenzo. I hope they can call me a friend.
Then I cannot forget all the fruitful discussions carried out with o rey do triple Edoardo,
er pibe Alessandro, er braciere Davide and ispanico Roberto. Three MaiTais are
always better than one!
Thanks to all the people in the lab that helped me whenever I had a problem. Thanks in
particular to Mac and Fausto, because IMS is an excellence center.
I would like to thank everyone in ST Study and Microlab. Thanks also to Giorgio and
Gabriella from University of Milano.
And in the end, three years later, thanks again to Sabrina...

Analog Baseband Blocks For Multistandard Wireless Transmitters

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Analog Baseband Blocks For Multistandard Wireless Transmitters

Uploaded by

Copyright:

Available Formats

UNIVERSIT DEGLI STUDI DI PAVIA

ANALOG BASEBAND BLOCKS FOR

Anno Accademico 20042005

Multistandard Transmitters for Wireless Applications

High Frequency Baseband Section

Crosstalk Eects in Mixed-Signal CMOS ICs

16-quadrature amplitude modulation

64-quadrature amplitude modulation

bit error rate

binary phase-shift keying

complementary code keying

dierential binary phase-shift keying

Dynamic element matching

discrete Fourier transform

dedicated physical control channel

dedicated physical data channel

dierential quadrature phase-shift keying

direct-sequence code division multiple access

digital signal processor

direct-sequence spread spectrum

error vector magnitude

frequency division multiplexing

fast Fourier transform

frequency-hopping spread spectrum

nite impulse response

Global System for Mobile Communications

third-order harmonic distortion

inverse discrete Fourier transform

inverse fast Fourier transform

input second-order intercept point

input third-order intercept point

innite impulse response

third-order intermodulation distortion

linear amplication with non-linear components

Orthogonal Frequency Division Multiplexing

output third-order intercept point

printed circuit board

quadrature phase-shift keying

spurious-free dynamic range

time-hopping spread spectrum

Universal Mobile Telecommunication System

Universal Networking Information Structure

voltage controlled oscillator

variable gain amplier

Wireless Local Area Network

Wireless Metropolitan Area Network

Recongurable multistandard terminals

The implementation of fully-integrated multistandard transceivers is nowadays driving the

Digital Baseband Phone

Outline of the thesis

This thesis is organized as follows:

Wireless Local Area Networks

Coding rate (R)

Multistandard Transmitters for Wireless Applications

OFDM multicarrier modulation technique

Orthogonal Frequency Division Multiplexing modulation

Considering the symbol dn , the corresponding modulated function is:

while the overall modulated signal can be written as:

Multistandard Transmitters for Wireless Applications

Universal Mobile Telecommunication System

Spread spectrum signals

Figure 2.2: Spreading and despreading process.

Multistandard Transmitters for Wireless Applications