ICA Lab Manual PDF

III year I sem ECE
ICA lab Master manual 2014-15
BASIC INTRODUCTION
THE BREADBOARD
The breadboard consists of two terminal strips and two bus strips (often broken in the
centre). Each bus strip has two rows of contacts. Each of the two rows of contacts are a node. That
is, each contact along a row on a bus strip is connected together (inside the breadboard). Bus
strips are used primarily for power supply connections, but are also used for any node requiring a
large number of connections. Each terminal strip has 60 rows and 5 columns of contacts on each
side of the centre gap. Each row of 5 contacts is a node. You will build your circuits on the
terminal strips by inserting the leads of circuit components into the contact receptacles and
making connections with
Incorrect connection of power to the ICs could result in them exploding or becoming very
hot with the possible serious injury occurring to the people working on the experiment! Ensure
that the power supply polarity and all components and connections are correct before switching
on power .
Fig 1. The breadboard. The lines indicate connected holes.
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BUILDING THE CIRCUIT

The steps for wiring a circuit should be completed in the order described below:
1. Turn the power (Trainer Kit) off before you build anything!
2. Make sure the power is off before you build anything!
3. Connect the supply and ground (GND) leads of the power supply to the power and ground bus
strips on your breadboard.
4. Plug the chips you will be using into the breadboard. Point all the chips in the same direction
with pin 1 at the upper-left corner. (Pin 1 is often identified by a dot or a notch next to it on the
chip package)
5. Connect supply and GND pins of each chip to the power and ground bus
strips on the breadboard.
6. Select a connection on your schematic and place a piece of hook-up wire between
corresponding pins of the chips on your breadboard. It is better to make the short connections
before the longer ones. Mark each connection on your schematic as you go, so as not to try to
make the same connection again at a later stage.
7. Get one of your group members to check the connections, before you turn the power on.
8. If an error is made and is not spotted before you turn the power on. Turn the power off
immediately before you begin to rewire the circuit.
9. At the end of the laboratory session, collect you hook-up wires, chips and all equipment and
return them to the demonstrator.
10. Tidy the area that you were working in and leave it in the same condition as it was before you
started.
Common Causes of Problems:
1. Not connecting the ground and/or power pins for all chips.
2. Not turning on the power supply before checking the operation of the circuit.
3. Leaving out wires.
4. Plugging wires into the wrong holes.
5. Driving a single gate input with the outputs of two or more gates
6. Modifying the circuit with the power on.
In all experiments, you will be expected to obtain all instruments, leads, components at the
start of the experiment and return them to their proper place after you have finished the
experiment. Please inform the demonstrator or technician if you locate faulty equipment. If you
damage a chip, inform a demonstrator, don't put it back in the box of chips for somebody else to
use.
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Functional block diagram
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1.1
INTEGRATED CIRCUITS
An integrated circuit (IC) is a miniature, low cost electronic circuit consisting of active and
passive components fabricated together on a single crystal of silicon. The active components are
transistors and diodes and passive components are resistors and capacitors.
Why silicon is chose as basic material and not Germanium?
The chip is packaged in a plastic holder with pins spaced on a 0.1" (2.54mm) grid which will fit
the holes on strip board and breadboards. Very fine wires inside the package link the chip to the
pins.
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1.2 Advantages of integrated circuits

1. Miniaturization and hence increased equipment density.
2. Cost reduction due to batch processing.
3. Increased system reliability due to the elimination of soldered joints.
4. Improved functional performance.
5. Matched devices.
6. Increased operating speeds.
7. Reduction in power consumption
We introduce the most important of all analog building blocks, the operational amplifier (opamp for short).
1.3 Depending upon the number of active devices per chip, there are different levels of
integration:
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Fig: 1.1 SSI chip
Fig: 1.2 MSI chip
Fig: 1.3 VLSI chip

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1.4 IC Package Types

The op-amp ICs are available in various packages. The IC packages are classified as,
1. Metal Can
2. Dual In Line
3. Flat Pack
Metal Can package:
Fig 1.4 Metal Can
Dual In Line (DIP):
Fig: 1.5 Dual in line package
Flat Pack:
Fig: 1.6 Flat pack
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Table 1.1 Typical package types with typical pin counts and mounting type:
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Table:1.2 Different package types with their abbreviations:
1.5 Basic Information of Op Amp:

Circuit Symbol:
Fig:1.7 symbol of an Op Amp

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The input and output are in anti phase:-
Fig: 1.8 input applied to inverting terminal
Fig:1.9 input applied to non inverting terminal
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The amplifier's differential inputs consist of a input and a input, and ideally the op-amp
amplifies only the difference in voltage between the two, which is called the differential input
voltage.
The output voltage of the op-amp is given by the equation,
where
is the voltage at the non-inverting terminal,
is the voltage at the inverting terminal and
AOL is the open-loop gain of the amplifier (the term "open-loop" refers to the absence of a
feedback loop from the output to the input).
The magnitude of AOL is typically very large10,000 or more for integrated circuit op-amps
and therefore even a quite small difference between and drives the amplifier output nearly to
the supply voltage. This is called saturation of the amplifier.
The magnitude of AOL is not well controlled by the manufacturing process, and so it is impractical
to use an operational amplifier as a stand-alone differential amplifier. If predictable operation is
desired, negative feedback is used, by applying a portion of the output voltage to the inverting
input.
The closed loop feedback greatly reduces the gain of the amplifier. If negative feedback is used,
the circuit's overall gain and other parameters become determined more by the feedback network
than by the op-amp itself.
If the feedback network is made of components with relatively constant, stable values, the
unpredictability and inconstancy of the op-amp's parameters do not seriously affect the circuit's
performance.
If no negative feedback is used, the op-amp functions as a switch or comparator.
Positive feedback may be used to introduce hysteresis or oscillation.
Power supply:
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are as shown below:
Ideal Characteristics of an op-amp:
1.6
Op amp is a differential amplifier.

An ideal op-amp is usually considered to have the following properties, and they are considered to
hold for all input voltages:
Infinite open-loop gain (when doing theoretical analysis, a limit may be taken as open loop
gain AOL goes to infinity).
Infinite voltage range available at the output (vout).

(in practice the voltages available from the output are limited by the supply voltages
and
). The power supply sources are called rails.
Infinite bandwidth (i.e., the frequency magnitude response is considered to be flat

everywhere with zero phase shift).
Infinite input impedance (
Zero input current (i.e., there is assumed to be no leakage or bias current into the device).
Zero input offset voltage (i.e., when the input terminals are shorted so that
, and zero current flows from
to
).
the output is a virtual ground or vout = 0).

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Infinite slew rate (i.e., the rate of change of the output voltage is unbounded) and
power bandwidth (full output voltage and current available at all frequencies).
Zero output impedance (i.e., Rout = 0, so that output voltage does not vary with output
current).
Zero noise.
Infinite Common-mode rejection ratio (CMRR).
Infinite Power supply rejection ratio for both power supply rails.
Fig: 1.10 a. An equivalent circuit of an operational amplifier

An equivalent circuit of an operational amplifier that models some resistive non-ideal parameters.
An exact equivalent of the ideal Op-Amp is called a "nullor" and it is composed of new elements -the nullator and the norator. The input to the op-amp is the nullator (i.e. no voltage or current), while the
output is the norator (i.e. any voltage or current). These two components give the device its ideal
characteristics.
Fig: 1.10 b. Ideal op amp
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Fig: 1.10 c. Open loop circuit
The V+ and V- power supply terminals are connected to two DC voltage sources.
The v+ pin is connected o the positive terminal of one source and v- pin is connected to the
negative terminal of the other source, where two sources are 15 V batteries each.
The power supply voltage may range from 5 to 22 V.
Terms used:
Power Supply:
In general op-amps are designed to be powered from a dual or bipolar voltage supply which is
typically in the range of +5V to +15Vdc with respect to ground, and another supply voltage of 5V to -15Vdc with respect to ground. Although in certain cases an op-amp, like the LM3900 and
called a 'Norton Op-Amp', may be powered from a single supply voltage.
Electrical Ratings:
Electrical characteristics for op-amps are usually specified for a certain (given) supply voltage and
ambient temperature. Also, other factors may play an important role such as certain load and/or
source resistance. In general, all parameters have a typical minimum/maximum value in most
cases.
Definition of 741-pin functions: (Refer to the internal 741 schematic of Fig. 3)
Pin 1 (Offset Null): Offset nulling, see Fig. 11. Since the op-amp is the differential type, input
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offset voltage must be controlled so as to minimize offset. Offset voltage is nulled by application
of a voltage of opposite polarity to the offset. An offset null-adjustment potentiometer may be
used to compensate for offset voltage. The null-offset potentiometer also compensates for
irregularities in the operational amplifier manufacturing process which may cause an offset.
Consequently, the null potentiometer is recommended for critical applications. See 'Offset Null
Adjustment' for method.
Pin 2 (Inverted Input): All input signals at this pin will be inverted at output pin 6. Pins 2 and 3
are very important (obviously) to get the correct input signals or the op amp can not do its work.
Pin 3 (Non-Inverted Input): All input signals at this pin will be processed normally without
inversion. The rest is the same as pin 2.
Pin 4 (-V): The V- pin (also referred to as Vss) is the negative supply voltage terminal. Supplyvoltage operating range for the 741 is -4.5 volts (minimum) to -18 volts (max), and it is specified
for operation between -5 and -15 Vdc. The device will operate essentially the same over this range
of voltages without change in timing period. Sensitivity of time interval to supply voltage change
is low, typically 0.1% per volt. (Note: Do not confuse the -V with ground).
Pin 5 (Offset Null): See pin 1, and Fig. 11.
Pin 6 (Output): Output signal's polarity will be the opposite of the input's when this signal is
applied to the op-amp's inverting input. For example, a sine-wave at the inverting input will
output a square-wave in the case of an inverting comparator circuit.
Pin 7 (posV): The V+ pin (also referred to as Vcc) is the positive supply voltage terminal of the
741 Op-Amp IC. Supply-voltage operating range for the 741 is +4.5 volts (minimum) to +18 volts
(maximum), and it is specified for operation between +5 and +15 Vdc. The device will operate
essentially the same over this range of voltages without change in timing period. Actually, the
most significant operational difference is the output drive capability, which increases for both
current and voltage range as the supply voltage is increased. Sensitivity of time interval to supply
voltage change is low, typically 0.1% per volt.
Pin 8 (N/C): The 'N/C' stands for 'Not Connected'. There is no other explanation. There is
nothing connected to this pin, it is just there to make it a standard 8-pin package.
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8 Pin
16 pin
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Fig: 1.11 Various IC packages of A 741 op amp along with connection diagram
These ideals can be summarized by the two "golden rules":
I. The output attempts to do whatever is necessary to make the voltage difference
between the inputs zero.
II. The inputs draw no current.
The first rule only applies in the usual case where the op-amp is used in a closed-loop design
(negative feedback, where there is a signal path of some sort feeding back from the output to the
inverting input). These rules are commonly used as a good first approximation for analyzing or
designing op-amp circuits.
In practice, none of these ideals can be perfectly realized, and various shortcomings and
compromises have to be accepted. Depending on the parameters of interest, a real op-amp may be
modeled to take account of some of the non-infinite or non-zero parameters using equivalent
resistors and capacitors in the op-amp model. The designer can then include the effects of these
undesirable, but real, effects into the overall performance of the final circuit. Some parameters
may turn out to have negligible effect on the final design while others represent actual limitations
of the final performance that must be evaluated.
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1.7 Classification:
Fig: 1.10 Classifications of ICs.
\
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1.8 Block diagram of op-amp:

The block diagram of IC op-amp is as shown in figure below:
Fig: 1.11 Basic block diagram of an Op Amp
-Dual input balanced

output diff. amp.
-Most of the vg.gain
-Dual input unbalanced

output diff. amp.
-to provide additional vg.
gain.
-chain of multi stage
amplifiers
-DC vg.levels of prev. stage which are applied to next stage

increases above gnd.level.
-high DC level may drive transistor into satn.
-may cause distortion due to clipping.
-may limit the max. ac o/p vg. Swing without distortion.
-buffer is emitter follower whose i/p impedence is
high.prevents loading of high gain stage.
-low o/p
impedence,large ac
o/p vg. Swing and
high ct.sourcing &
sinking capability
reqd.
-push-pull
complementary amp.
Is used.
-here o/p vg. Swing is
increased.
- vg. Swing
symmetrical w.r.t gnd.
-rises the ct. supplying
capability of opamp.
1) Input stage:
2) Intermediate stage:
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3) Level shifting stage:
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4) Output stage:
1.9 Manufacturers for Linear ICs:
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Examples:
1.10
Features of IC-741
i.
No frequency compensation required.
ii.
Short circuit protection provided.
iii.
Offset voltage null capability.
iv.
v.
Excellent temperature stability.

Large common mode and Differential voltage range (high input voltage range).
vi.
No latch up.
1.11 Absolute Maximum Parameters:

Maximum means that the op-amp can safely tolerate the maximum ratings as given in the
data section of such op-amp without the possibility of destroying it. The uA741 is a high
performance operational amplifier with high open loop gain, internal compensation, high
common mode range and exceptional temperature stability. The uA741 is short-circuit
protected and allows for nulling of the offset voltage. The uA741 is manufactured by
Fairchild Semiconductor.
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Supply Voltage (+/-Vs): The maximum voltage (positive and negative) that can be safely used to
feed the op-amp.
Dissipation (Pd): The maximum power the op-amp is able to dissipate, by specified ambient
temperature (500mW @ 80 C).
Differential Input Voltage (Vid): This is the maximum voltage that can be applied across the +
and - inputs.
Input Voltage (Vicm): The maximum input voltage that can be simultaneously applied between
both input and ground also referred to as the common-mode voltage. In general, the maximum
voltage is equal to the supply voltage.
Operating Temperature (Ta): This is the ambient temperature range for which the op-amp will
operate within the manufacturer's specifications. Note that the military grade version (uA741)has
a wider temperature range than the commercial, or hobbyist, grade version (uA741C).
Output Short-Circuit Duration: This is the amount of time that an op-amp's output can be
short-circuited to either supply voltage.
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CYCLE I
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EXPERIMENT- 1
ADDER, SUBTRACTOR AND COMPARATOR USING IC 741 OP-AMP.
AIM: To study the working of op- amp as adder, subtractor and comparator using IC 741.
APPARATUS:
Bread board-1 in no.
Regulated power supply (0V 30V)-1 in no.
CRO (0-20 MHz)-1 in no.
IC 741-1.
Resistors-1K-2 in no., 10K-2 in no3.3K-1 in no.
Multimeter/ voltmeter
Connecting wires.
THEORY:
ADDER:
Let V1 and V2 are two inputs applied to the inverting terminal of op-amp through R1, and
R2 resistors as shown in fig.1. A feedback resistor Rf is connected between o/p and inverting i/p.
Then the o/p will be the summation of i/p voltages.
Vo = - (Rf/R1) (V1+V2)
where Ri = R1 = R2
SUBTRACTOR:
Let V1 and V2 are two inputs applied to the inverting and non-inverting terminals of the
two op -amps through R1and R2 resistors as shown in the subtractor circuit diagram. Feedback
resistor is connected between o/p and inverting i/p. Then the o/p will be the difference of two i/p
voltages.
Vo = + (Rf/R1) (V2-V1)
where Ri = R1 = R2
Here Rf = R1 = R2.
COMPARATOR:
Comparator is a non-linear application of an op-amp in open loop configuration. A
Comparator circuit compares the input signal voltage with a reference voltage at the terminals of
an open loop op amp. An inverting comparator circuit shown in fig 3 with input voltage
applied to terminal and Vref to input terminal.
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The output voltage will be Vsat (= Vcc) and its transfer characteristics as shown in fig.4. The
transfer characteristics for a practical comparator are shown:
When
Vi < Vref ;
Vo= -Vsat
When
Vi>Vref ; Vo= +V sat

When Vi < - Vref
Vo = +Vsat
Vi > - Vref
Vo = - Vsat
CIRCUIT DIAGRAMS:
(i) ADDER:
Rf =10k, R = 10k
Fig 1.1: OP-AMP ADDER

(ii). SUBTRACTOR: Rf & R3 =10k, R1 & R2= 10k.
Fig 1.2: OP-AMP SUBTRACTOR

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(iii) COMPARATOR:
Rf =10k, R=1k.
Fig 1.3: COMPARATOR
PROCEDURE:
ADDER:
1. Connect the circuit as shown in the adder circuit diagram fig.1.3
2. Apply the supply voltages of +12V to pin7 and -12V to pin4 of IC 741 respectively.
3. Apply DC voltage from regulated power supply to inputs V1 and V2 .
4. Increase input voltages from 1V to 5V in steps of 1V for V1,V2
5. Note down the Vo corresponding outputs (CRO in DC mode). Or DMM.
6. Compare theoretical and practical values.
SUBTRACTOR:
1. Connect the circuit as shown in the Subtractor circuit diagram fig:1.2.
3. Apply DC voltage from regulated power supply to inputs V1 and V2.
4. Keep the 6V at V1; slowly decrease V2 from 6V to 3V with five readings
5. Note down the Vo corresponding to different inputs (CRO in DC mode) or DMM.
6. Compare theoretical and practical values.
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COMPARATOR:
1. Connect the circuit as shown in the figure 1.3.
3. Set the reference voltage as 1V DC.
4. Apply a sine wave of 4V p-p with 1 KHz frequency from the function generator.
5. Check the output on CRO. Calculate the amplitude of output wave as shown in fig 4.
6. Plot the waveforms on graph sheets.
7. Compare the output wave amplitude to the theoretical value.
OBSERVATIONS:
ADDER: Input voltages applied to inverting terminal
S.NO
1
2
3
4
5
6
D.C Voltage at
input V1 (V)
0
1
1.5
2
2.5
D.C Voltage
at input V2
(V)
1
1
1
1
1
theoretical
Voltage Vo
(V)
D.C Voltage measured

at Output
Vo (V)
-1
-1.99
-2.5
-3.08
-3.5
-1
-2
-2.5
-3
-3.5
-4
-4
Table 1.1: Adder readings

SUBTRACTOR:
S.NO
D.C Voltage at
input V1 (V)
D.C Voltage at
input V2 (V)
D.C Voltage at
output Vo (V)
theoretical
Voltage Vdc (V)
(practical)
1
2
3
4
6
6
6
6
6
5
4
3
0
1
2
3
0
1.2
2.2
3.2
Table 1.2: Subtractor readings
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COMPARATOR:
S.NO
D.C Voltage at
Input Vref(v)
A.C Voltage at
input V2 (V)
Voltage at output Vo
(V) (CRO)
01
6V peak to peak
sinusoidal
20 Vpp
Table 1.3: Comparator readings
VII. EXPECTED WAVEFORMS:

COMPARATOR: Non- Inverting Comparator.
Fig:1.4 Comparator input and output waveforms for positive reference and negative reference
RESULT:
Hence, the operation of the adder, subtractor and comparator circuits using op-amp 741 is studied
and the output waveforms of the comparator are plotted.
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VIVA QUESTIONS:
Q1. . What are the applications of op-amp?
Ans: application of op-amp are integrator , differentiator, I-V converter , P-V converter etc.
2. Write down output voltage formula for the adder in inverting mode.
Ans: Vo = - Rf/R1(V1+V2)
3. Write down output voltage formula for the adder in non inverting mode.
Ans: Vo = 1+ Rf/R1(V1+V2)
4. Write short notes on inverting and non inverting amplifier.
Ans: inverting amplifier has an output of 180 phase shift for given input, whereas non-inverting
amplifier will delivered the same output for the given input.
5. What are ideal characteristics of an ideal op-amp?
Ans: ideal characteristics of op-amp are
1. the high input impendence order of mega ohms
2.very low output impendence (10 ).
3. very high voltage gain (>10)
4. open loop voltage gain (= )
6. Write down the characteristics of adder and subtractor for sinusoidal input?
Ans: the output will remains same in nature but the magnitude will increase or decrease
depends upon the circuit.
7. What is main difference between BJT amplifier and OP-AMP amplifier in terms of gain?
Ans; the gain of the BJT will be less than the 1 where as the op-amp has 1 .
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8.Mention some of the linear applications of op amps.

Ans:Adder, subtractor, voltage to- current converter, current to- voltage converters,
instrumentation amplifier, analog computation ,power amplifier, etc are some of the
linear op-amp circuits.
9. Mention some of the non linear applications of op-amps:
Ans: Rectifier, peak detector, clipper, clamper, sample and hold circuit, log amplifier, anti
log amplifier, multiplier are some of the non linear op-amp circuits.
10. What are the areas of application of non-linear op- amp circuits:
Industrial instrumentation
Signal processing
11. What does 74LS refers to:

Ans: 74-refers to IC which can be used for commercial purpose.LS-Low Power Schottky.
12. What is Linear IC?
Ans: IC which accepts process and produce analog signal is called linear IC .Eg:IC741,
IC555.
13. Define CMRR
Ans: Common mode rejection ratio-it is defined as the ratio between the differential mode
gain to the common mode gain
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EXPERIMENT 2
INTEGRATOR AND DIFFERENTIATOR USING IC 741 OP-AMP
AIM: -To study the working of op amp as differentiator and integrator using IC 741 and
observe the output waveforms for different input waveforms.
APPARATUS: Bread board -1.
Regulated power supply-1.
CRO - 1.
IC 741-1.
Resistors - 1K , 150 , 1.5 K , 100K , 10K.
Capacitor - 0.01F , 0.1F-2.
Connecting wires.
THEORY
The Op-amp Integrating Amplifier
An OP-Amp circuit for integration is shown in Fig 2.1.
An operational amplifier can be used as part of a positive or negative feedback amplifier
or as an adder or subtractor type circuit using just pure resistances in both the input and the
feedback loop. But what if we were to change the purely resistive ( R ) feedback element of an
inverting amplifier to that of a frequency dependant impedance, ( Z ) type complex element, such
as a Capacitor, C.
By replacing this feedback resistance with a capacitor we now have an RC Network connected
across the operational amplifiers feedback path producing another type of operational amplifier
circuit commonly called an Op-amp Integrator circuit as shown below.
Op-amp Integrator Circuit
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As its name implies, the Op-amp Integrator is an Operational Amplifier circuit that performs the
mathematical operation of Integration that is we can cause the output to respond to changes in
the input voltage over time as the op-amp integrator produces an output voltage which is
proportional to the integral of the input voltage.
The magnitude of the output signal is determined by the length of time a voltage is present at its
input as the current through the feedback loop charges or discharges the capacitor as the required
negative feedback occurs through the capacitor.
When a step voltage, Vin is firstly applied to the input of an integrating amplifier, the uncharged
capacitor C has very little resistance and acts a bit like a short circuit allowing maximum current
to flow via the input resistor, Rin as potential difference exists between the two plates. No current
flows into the amplifiers input and point X is a virtual earth resulting in zero output. As the
impedance of the capacitor at this point is very low, the gain ratio of Xc/Rin is also very small
giving an overall voltage gain of less than one, (voltage follower circuit).
As the feedback capacitor, C begins to charge up due to the influence of the input voltage, its
impedance Xc slowly increase in proportion to its rate of charge. The capacitor charges up at a
rate determined by the RC time constant, ( ) of the series RC network. Negative feedback forces
the op-amp to produce an output voltage that maintains a virtual earth at the op-amps inverting
input.
Since the capacitor is connected between the op-amps inverting input (which is at earth potential)
and the op-amps output (which is negative), the potential voltage, Vc developed across the
capacitor slowly increases causing the charging current to decrease as the impedance of the
capacitor increases. This results in the ratio of Xc/Rin increasing producing a linearly increasing
ramp output voltage that continues to increase until the capacitor is fully charged.
At this point the capacitor acts as an open circuit, blocking any more flow of DC current. The
ratio of feedback capacitor to input resistor ( Xc/Rin ) is now infinite resulting in infinite gain.
The result of this high gain (similar to the op-amps open-loop gain), is that the output of the
amplifier goes into saturation as shown below. (Saturation occurs when the output voltage of the
amplifier swings heavily to one voltage supply rail or the other with little or no control in
between).
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The rate at which the output voltage increases (the rate of change) is determined by the value of
the resistor and the capacitor, RC time constant. By changing this RC time constant value,
either by changing the value of the Capacitor, C or the Resistor, R, the time in which it takes the
output voltage to reach saturation can also be changed for example.
If we apply a constantly changing input signal such as a square wave to the input of an Integrator
Amplifier then the capacitor will charge and discharge in response to changes in the input signal?
This results in the output signal being that of a saw tooth waveform whose frequency is dependent
upon the RC time constant of the resistor/capacitor combination. This type of circuit is also
known as a Ramp Generator and the transfer function is given below.
Op-amp Integrator Ramp Generator
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From the first principals that the voltage on the plates of a capacitor is equal to the charge on the
capacitor divided by its capacitance giving Q/C. Then the voltage across the capacitor is output
Vout therefore: -Vout = Q/C. If the capacitor is charging and discharging, the rate of charge of
voltage across the capacitor is given as:
But dQ/dt is electric current and since the node voltage of the integrating op-amp at its inverting
input terminal is zero, X = 0, the input current I(in) flowing through the input resistor, Rin is
given as:
The current flowing through the feedback capacitor C is given as:
Assuming that the input impedance of the op-amp is infinite (ideal op-amp), no current flows into
the op-amp terminal. Therefore, the nodal equation at the inverting input terminal is given as:
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From which we derive an ideal voltage output for the Op-amp Integrator as:
To simplify the maths a little, this can also be re-written as:
Where = 2 and the output voltage Vout is a constant 1/RC times the integral of the input
voltage Vin with respect to time. The minus sign ( - ) indicates a 180o phase shift because the
input signal is connected directly to the inverting input terminal of the op-amp.
The AC or Continuous Op-amp Integrator
If we changed the above square wave input signal to that of a sine wave of varying frequency the
Op-amp Integrator performs less like an integrator and begins to behave more like an active
Low Pass Filter, passing low frequency signals while attenuating the high frequencies.
At 0Hz or DC, the capacitor acts like an open circuit blocking any feedback voltage resulting in
very little negative feedback from the output back to the input of the amplifier. Then with just the
feedback capacitor, C, the amplifier effectively is connected as a normal open-loop amplifier
which has very high open-loop gain resulting in the output voltage saturating.
This circuit connects a high value resistance in parallel with a continuously charging and
discharging capacitor. The addition of this feedback resistor, R2 across the capacitor, C gives the
circuit the characteristics of an inverting amplifier with finite closed-loop gain of R2/R1. The
result is at very low frequencies the circuit acts as an standard integrator, while at higher
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frequencies the capacitor shorts out the feedback resistor, R2 due to the effects of capacitive
reactance reducing the amplifiers gain.
The AC Op-amp Integrator with DC Gain Control
Unlike the DC integrator amplifier above whose output voltage at any instant will be the integral
of a waveform so that when the input is a square wave, the output waveform will be triangular.
For an AC integrator, a sinusoidal input waveform will produce another sine wave as its output
which will be 90o out-of-phase with the input producing a cosine wave.
Furthermore, when the input is triangular, the output waveform is also sinusoidal. This then forms
the basis of a Active Low Pass Filter as seen before in the filters section tutorials with a corner
frequency given as.
Op-amp Differentiator
As its name implies, the differentiator amplifier produces an output signal which is the
mathematical operation of differentiation that is it produces a voltage output which is proportional
to the input voltages rate-of-change and the current flowing through the input capacitor.
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The basic Op-amp Differentiator circuit is the exact opposite to that of the Integrator Amplifier
circuit that we looked at in the previous tutorial. Here, the position of the capacitor and resistor
have been reversed and now the reactance, Xc is connected to the input terminal of the inverting
amplifier while the resistor, R forms the negative feedback element across the operational
amplifier as normal.
This Operational Amplifier circuit performs the mathematical operation of Differentiation, that is
it produces a voltage output which is directly proportional to the input voltages rate-of-change
with respect to time. In other words the faster or larger the change to the input voltage signal, the
greater the input current, the greater will be the output voltage change in response, becoming
more of a spike in shape.
As with the integrator circuit, we have a resistor and capacitor forming an RC Network across the
operational amplifier and the reactance ( Xc ) of the capacitor plays a major role in the
performance of a Op-amp Differentiator.
Op-amp Differentiator Circuit
The input signal to the differentiator is applied to the capacitor. The capacitor blocks any DC
content so there is no current flow to the amplifier summing point, X resulting in zero output
voltage. The capacitor only allows AC type input voltage changes to pass through and whose
frequency is dependant on the rate of change of the input signal.
At low frequencies the reactance of the capacitor is High resulting in a low gain ( R/Xc ) and
low output voltage from the op-amp. At higher frequencies the reactance of the capacitor is much
lower resulting in a higher gain and higher output voltage from the differentiator amplifier.
However, at high frequencies an op-amp differentiator circuit becomes unstable and will start to
oscillate. This is due mainly to the first-order effect, which determines the frequency response of
the op-amp circuit causing a second-order response which, at high frequencies gives an output
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voltage far higher than what would be expected. To avoid this high frequency gain of the circuit
needs to be reduced by adding an additional small value capacitor across the feedback resistor R.
Ok, some maths to explain whats going on!. Since the node voltage of the operational amplifier
at its inverting input terminal is zero, the current, i flowing through the capacitor will be given as:
The charge on the capacitor equals Capacitance x Voltage across the capacitor
The rate of change of this charge is
but dQ/dt is the capacitor current i
From this we have an ideal voltage output for the op-amp differentiator is given as:
Therefore, the output voltage Vout is a constant -R.C times the derivative of the input voltage
Vin with respect to time. The minus sign indicates a 180o phase shift because the input signal is
connected to the inverting input terminal of the operational amplifier.
One final point to mention, the Op-amp Differentiator circuit in its basic form has two main
disadvantages compared to the previous Operational Amplifier Integrator circuit. One is that it
suffers from instability at high frequencies as mentioned above, and the other is that the capacitive
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input makes it very susceptible to random noise signals and any noise or harmonics present in the
source circuit will be amplified more than the input signal itself. This is because the output is
proportional to the slope of the input voltage so some means of limiting the bandwidth in order to
achieve closed-loop stability is required
Op-amp Differentiator Waveforms
If we apply a constantly changing signal such as a Square-wave, Triangular or Sine-wave type
signal to the input of a differentiator amplifier circuit the resultant output signal will be changed
and whose final shape is dependent upon the RC time constant of the Resistor/Capacitor
combination.
input signal: sinusoidal
output signal
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Improved Op-amp Differentiator Amplifier

The basic single resistor and single capacitor op-amp differentiator circuit is not widely used to
reform the mathematical function of Differentiation because of the two inherent faults mentioned
above, Instability and Noise. So in order to reduce the overall closed-loop gain of the circuit
at high frequencies, an extra resistor, Rin is added to the input as shown below.
Improved Op-amp Differentiator Amplifier
Adding the input resistor Rin limits the differentiators increase in gain at a ratio of R/Rin. The
circuit now acts like a differentiator amplifier at low frequencies and an amplifier with resistive
feedback at high frequencies giving much better noise rejection. Additional attenuation of higher
frequencies is accomplished by connecting a capacitor C in parallel with the differentiator
feedback resistor, R. This then forms the basis of a Active High Pass Filter as we have seen
before in the filters section.
Applications:
1. The DC voltage produced by the differentiator circuit could be used to drive a comparator
which would signal as alarm or active a control if the rate of change exceeded a pre-set level.
2. Waveform Generators.
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Circuit Diagram:
(1) Integrator:
Rf = 100K, R1 = 10K , Cf = 0.1 f
Vo
= -1/R1Cf Vi dt.
Fig: 2.1 Integrator circuit

(2) Differentiator:
Rf = 1.5 K, R1 = 150 , C1 = 0.01f, Cf = 0.1 f
Vo = -RfC1 d/dt [Vi]
Fig: 2.2 Differentiator circuit

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PROCEDURE:INTEGRATOR
1. Connect the circuit as shown in the integrator circuit diagram fig:2.1.
2. Apply a bipolar symmetrical square wave of 5V amplitude peak to peak and 1ms
time period (1 KHz).
3. Connect the input and output of the circuit to channel 1 and channel 2 of the CRO
respectively and observe the waveforms.
4. Draw the waveforms along with the levels on a graph.
5. Compare the practical values with theoretical values.
DIFFERENTIATOR
1. Connect the circuit as shown in the differentiator circuit diagram fig: 2.2.
2. Apply a bipolar symmetrical square wave of 5V amplitude peak to peak and 1ms
time period.
3. Connect the input and output of the circuit to channel 1and channel 2 of the CRO
respectively and observe the waveforms.
4. Draw the waveforms along with the levels on a graph.
5. Compare the practical values with theoretical values.
TABULER FORM
INTEGRATOR:
Sl.No.
input
Waveform
Square wave
Sinusoidal
wave
Amplitude
output Waveform Amplitude
(in volts p-p) &
(in volts p-p)
Frequency
2, 1KHz
Triangular wave
1.89, 1KHz
2, 1KHz
Cosine wave
2, 1KHz
Table: 2.1 Integrator observations

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DIFFERENTIATOR:
Sl.No.
input
Waveform
Square wave
Sinusoidal
wave
Triangular
wave
Amplitude
(in volts p-p) &
Frequency
2, 1KHz
output Waveform
Amplitude
(in volts p-p)
Spikes wave
1.89, 1KHz
2, 1KHz
Cosine wave
2, 1KHz
2, 1KHz
Rectangular wave
1.89, 1KHz
Table: 2.2 Differentiator observations

INTEGRATOR WAVEFORMS:
1) When input signal is a square wave:
Fig: 2.3 Output waveforms of an Integrator when input signal is a square wave
ii) when input is a sine wave:
Fig: 2.4 Output waveforms of an Integrator when input signal is a sine wave
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DIFFERENTIATOR WAVEFORMS:
input signal: sinusoidal
output signal
Fig: 2.5 Input and output waveforms of an differentiator.

Result: Hence,the working of Integrator and Differentiator are studied and the output waveforms
of Integrator and Differentiator for diffetent input waveforms are observed and plotted.
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Viva Questions:
1. Define integrator.
Ans: An integrator is a device to perform the mathematical operation known as integration, a
fundamental operation in calculus. The integration function is often part of engineering and
scientific calculations. Mechanical integrators are used in such applications as metering of water
flow or electric power. Electronic analog integrators were the basis of analog computers
2. Define differentiator.
Ans: A Differentiator is a circuit that is designed such that the output of the circuit is
proportional to the time derivative of the input. There are two types of differentiator circuits,
active and passive.
3.What are the limitations of the basic differentiator circuit?
At high frequency, a differentiator may become unstable and break in to oscillations.
The input impedance decreases with increase in frequency, thereby making the circuit
sensitive to high frequency noise.
4. In practical op-amps, what is the effect of high frequency on its performance?
Ans: The open-loop gain of op -amp decreases at higher frequencies due to the presence of
parasitic capacitance. The closed-loop gain increases at higher frequencies and leads to instability.
5. What happens when the common terminal of V+ and V- sources is not grounded?
Ans: If the common point of the two supplies is not grounded, twice the supply voltage
will get applied and it may damage the op-amp.
6. Write down the condition for good differentiation?
Ans: For good differentiation, the time period of the input signal must be
greater than or equal to Rf C1 ,T > R f C1 Where, Rf is the feedback resistance
7. What is an IC:
Ans: The term IC refers to complex Electronic circuits consisting of a large number of
components on a single substrate.
8 .What are the advantage of IC:
Ans: Cost reduction,Increased operating speed,Reduced power consumption and Improved
functional performance.
9. What are the different IC technologies:
Ans: Monolithic technology and Hybrid technology
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EXPERIMENT: 3
ACTIVE LOW PASS AND HIGH PASS BUTTERWORTH SECOND ORDER FILTERS
AIM: - To design a second order low pass and high pass filters using op-amp 741 IC.
COMPONENTS REQUIRED: Bread board
-1
Regulated power supply
-1
CRO
-1
IC 741
-1
Resistors:
Capacitors:
1K
-2 in no.
5.86 K
-1 in no.
10K
-1 in no.
0.1F
-2 in no.
THEORY:Op-Amp Low Pass Filter:

An Op-Amp Low pass filter is shown in Fig 3.1. The circuit allows the low frequency
signals freely through it and attenuates the signals above a cut off frequency called higher cut
off frequency (fH). The inverting terminal is grounded through a resistor R1. A resistor RF is
connected in feedback path. A Resistor R2 is connected between the input signal source and
the non-inverting terminal of the Op-Amp and a Capacitor C2 is connected between the noninverting terminal and the output. Capacitor C3 is connected between non inverting terminal
and ground. A load resistor RL is connected at the output.
Let Vi = input voltage
Vg = the voltage at the Non-inverting input
Vo = output voltage.
A = Gain of the Op-Amp = 1+RF /R1
Xc = Capacitive Reactance = 1/jC2
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Xc
Vg =
Vi
R2 + Xc
1/ jC2
Vg =
R + 1/ jC2
But V0 = AVg
= 1/jC2
V0 = [1+Rf / Ri] * 1 / jC2
R2+1 /j C2
But = 2f
1 / jC2
V0 = A
R2+1/ jC2
A
V0 =
1+jf / 2 R2 C2
A
V0 =
1+j2 RC
A
V0 =
1+jf / fH
where,
fH is the higher cut off frequency of the Low Pass Filter = 1/2 R2C2.
Transfer function of Low Pass Filter is given as H (s) = Vo / Vi
A
A
H(s) =
H(s)
1+ jf/fH
=
1+ jf/fH
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Magnitude is given by
1
Log A
H(s)
= 20 log 1 +(f / fH)2
Vo = A
jC2 R2 + 1
Similarly for second order filter,
H(s)
= 20 log
A
1 + (f/ fH) 4
Op-Amp High pass filter:

An Op-Amp High pass filter is shown in Fig 3.2. The circuit allows the high frequency
signals freely through it and attenuates the signals below a cut off frequency called Lower cut off
frequency (fL). The inverting terminal is grounded through a resistor R1. A resistor RF is
connected in feedback path. A Capacitor C2 is connected between the input signal source and the
non-inverting terminal of the Op-Amp and a Resistor R2 is connected between the non-inverting
terminal and the output. Resistor R3 is connected between the non inverting terminal and ground.
Let
Vi = input voltage
Vg = Voltage at the Non-inverting input
Vo = output voltage.
A = Gain of the Op-Amp
R2
Vg =
Vi
R 2 + Xc
R2
Vo = A
R2 + 1/ jC2
R2
Vo = A
R2 + j2fR2 C2
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A
Vo =
1- jfL / f
Where fL is the lower cut off frequency of the High Pass Filter = 1/2 R2C2.
Transfer function of High Pass Filter is given as H (s) = Vo / Vi

A
A
H(s) =
H(s)
1- jf L/ f
=
1- jfL/f
H(s)
Log A
= 20 log 1 +(fL / f)2
For second order filter, magnitude is given by,
H(s)
= 20 log
A
1 + (fL/ f) 4
DESIGNING PART:
Gain = 2 and cut off frequency fH =1 .59 KHz
Gain = 1+Rf /R1, then 1+Rf / R1 = 1.586
Rf / R1 = 0.586
Rf = 0.586 R1
Let R1 =27K then Rf = 15.8 K
And higher cutoff frequency fH = 1 / 2R2 C2 R3 C3 = 1.59KHz.
Let C2 = C3= 0.1 F
For design simplifications set R2 =R3, then R2 =R3 =1K,C2 = C3 = 0.1 F
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CIRCUIT DIAGRAM:
Low Pass Filter:
Fig: 3.1 Circuit diagram of a LPF
High Pass Filter:
Fig: 3.2 Circuit diagram of a HPF
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PROCEDURE:LOW PASS FILTER:

1. Connect the circuit as shown in the Low Pass Filter circuit diagram Fig 3.1.
2. Apply 2V p-p sine wave input to the resistor R2.
3. Keep the input constant and take any 10 readings of output voltage with 10 different
frequencies.
4. Observe the theoretical and practical voltage gains.
5. Draw the graph between voltage gain and frequency.
6. The pass band gain of filter is RF /R1 = 1.569.
Observations of Low Pass Filter:

Input Amplitude = 2Vp-p sinusoidal signal
S.No.
Input frequency
(Hz)
1.
200
2.
400
3.
600
4.
800
5.
1K
6.
1.2 K
1.4K
1.5K
1.6K
10
11
12
13
14
15
16
1.8K
2K
2.2K
2.4K
2.6K
2.8K
3K
17
3.2K
Output Amplitude (Vp-p)
Gain
(A=Vo/Vi)
20log (A)
Table: 3.1 Observations of Low Pass Filter

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Calculations of Low Pass Filter:

R2 =R3 = 1K, C2=C3=0.1F
fH =1 / 2 RC =1/ 2*1K*0.1 =1.56 KHz
HIGH PASS FILTER:
1. Connect the circuit as shown in the High pass filter circuit diagram 3.2.
2. Apply 2V p-p sine wave input to the capacitor C2.
3. Keep the input constant and take any 10 readings of output voltage with 10 different
frequencies.
4. Observe the theoretical and practical voltage gains.
5. Draw the graph between voltage gain and frequency.
6. The pass band gain of the filter RF /R1 =1.564.
Observations of High Pass Filter:
S.No.
Input frequency
(KHz)
1.
0.5
2.
3.
4.
5.
6.
10
20
50
10
90
11
100
12
120
Input Amplitude = 2Vp-p sinusoidal signal
Output Amplitude
(Vp-p)
Gain (A=Vo/Vi)
3.9
3.9
3.9
3.9
3.1
20log (A)
2.5
2
1.8
1.4
Table: 3.2 Observations of High Pass Filter

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Calculations of High Pass Filter:

R2 =R3 = 1K, C1=C2=0.1F
fL =1 / 2 RC =1/ 2*1K*0.1*10-3 =1.56 KHz
Output wave forms (LPF):
Gain in db
Frequency in Hz
Fig: 3.3 Frequency response of a second order LPF
Output wave forms (HPF):
Fig: 3.4 Frequency response of a second order HPF

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RESULT:Hence, a second order high pass and low pass filters response for the given specification is
observed and the values are tabulated and the frequency response is plotted.
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Viva Questions:
1. Define an electrical filter.

Ans: Filter is an electrical circuit which separates the two signals.
2. Classify filters.
Ans: Four types of filters
1. low pass filter
2. high pass filter
3. band pass filter
4. band stop filter
3. Discuss the disadvantage of passive filters.
Ans: Very poor frequency response.
4. Why we preferred active filters?
Ans: Accuracy more, high gain, better frequency and with different Q values.
5. Define pass band and stop band of a filter?
Ans: The pass band filter allows only the particular pass band frequency
only. Stop band filter stop only the particular band frequency only.
6. Give some notes on first order filter.
Ans: The first order filter has less frequency response and not proper corner frequency to
the ideal filter.
7. Discuss the differences between Butterworth and Chebyshev filters?
Ans: The Butterworth filter has flat frequency response in pass band where as
Chebyshev filter has ripples in the pass band.
8. Give high cutoff frequency formula for the low pass filter?
Ans: Fh = 1/ 2 RC.
9. What is the difference between analog filter and digital filter?
Ans: The analog filter has less performance whereas digital filters have god
performances.
10. Give low cutoff frequency formula for the high pass filter? Ans: FL = 1/ 2 RC.
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EXPERIMENT: 4
RC PHASE SHIFT AND WIEN BRIDGE OSCILLATORS USING IC 741 OP-AMP
AIM: 1) To design and construct a Wien bridge oscillator and RC Phase shift oscillator using
operational amplifier IC 741.
2) To measure the frequency of oscillation and to compare it to that of theoretical value.
APPARATUS:
RPS (0-30 V) 1 in no.
CRO (20 MHz) 1 in no.
IC 741 1
Resistors :- 470 K - 1 in no., 10K 2 in no., 1 K - 3 in no., 1.5 K- 2 in no.,
20 K - 1 in no.
Capacitors - 0.01F 3 in no.
Connecting wires and probes
THEORY:
RC Phase shift oscillator:The circuit diagram for a Phase shift oscillator using an OP-AMP IC-741 is shown in
fig 4.1. The Barkhausen criteria specifying a required 360o phase shift from input to output and a
total gain of one must be adhered to in the design of a phase shift oscillator. In the inverting Op
Amp provides a phase shift of 1800. The RC network must provide an additional 1800 for a total
phase shift of zero degrees. Each section provides approximately 600 of this requirement. The
filter portion consisting of the RC network introduces an attenuation that the op-amp must match
in gain in order to achieve an overall gain of one.
By using OP-AMP low frequency signals of frequency around 1 KHz can be achieved.
The frequency of oscillations is given by,
R = Ladder network resistor.

C = Ladder network capacitor.
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The minimum gain required of the op-amp so that it sustains oscillations is 29. Keeping the gain
as close to 29 as possible will prevent the peaks of the waveform from being driven into the nonlinear region. This will minimize clipping of the sinusoidal output.
The gain of the OP-AMP when loop gain AV =1 should be at least 29.
i.e., AV 29, for this choose Rf 29 R1 .
Wien bridge oscillator:The circuit diagram for a Wein Bridge oscillator using an OP-AMP IC-741 is shown in
fig 4.2. The feedback signal from circuit is connected to the non-inverting terminal of the OPAMP. A bridge is formed by four arms in which a series RC network in one arm and a parallel
RC network in adjoining arm and the remaining two arms consisting of R1 and RF of the OP-A
MP. The frequency of oscillations is given by,
fo = 1/ (2 RC)
The gain of the Op Amp when loop gain AV = 1 should be atleast 3 i.e., AV 3, (Rf 2 R1).
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R1 = R2 = R and C1= C2 = C, we get it as f = 1/ 2RC
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ADVANTAGES OF WEIN-BRIDGE OSCILLATOR

(1) Overall gain is high seems two stage amplifier is used.
(2) The Circuit is a very good sine wave output.
(3) Frequency stability is good and can be vary over a wide range.
4. DISADVANTAGE OF WEIN-BRIDGE OSCILLATOR
(1) Large number of component required to design 2 stage amplifiers.
(2) Very high frequency cannot be generated.
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CIRCUIT DIAGRAMS:
(1) RC Phase shift oscillator:-
Fig 4. 1. RC phase shift oscillator

Design :
Rf = 470 K, R=1 K, C=0.01f, R1=10 K , Rcomp = 10 k
The frequency of sustained oscillations generated depends on the value of R & C and is given by,
Frequency is measured in Hz.
Therefore, Rf 29 R1
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For oscillations to occur, the gain of the Op Amp must be equal to or greater than 29, which can
be adjusted using the resistances Rf & R1.
Theoritically,
1
2*(1*103) (0.1*10-6) 6
= 649 Hz
Practical Values:
A = 4.2*5V = 21 V
T = 1.6* 1m sec
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F = 625 Hz
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Wien bridge oscillator:R1=R2=1.5K , C1=C2=0.01f, R3=20K , R4=10K
Fig 4.2. Wien bridge oscillator

The above circuit (Fig. 1.2 ) can be redrawn as shown below: (Lead lag circuit)
Fig 4. 3. Equivalent circuit of a Wien bridge oscillator

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Design:
Theoretically:
f = 1/ 2RC
= 1 / ( 2*1.5*103*0.01*10-6)
=10.6 KHz.
Practically:
A = 1.6*10V = 16V
T = 2*50 sec
F = 1/ T = 10 KHz
PROCEDURE:
RC Phase shift oscillator:1. Construct the Phase shift oscillator as shown in the circuit diagram fig 4.1.
2. Also connect the Power supply of +12V & -12 V to Op Amp and CRO at the output.
3. Observe the output waveform on CRO taken at pin no.6 of the OP-AMP.
4. Calculate the frequency and amplitude of the waveform; draw the waveform on graph
sheet.
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Wien bridge oscillator:1. Construct the Wien Bridge oscillator as shown in the circuit diagram fig 4.2.
2. Also connect the Power supply of +12V & -12 V to Op Amp and CRO at the circuit.
3. Observe the output waveform on CRO taken at pin no.6 of the OP-AMP.
4. Calculate the frequency and amplitude of the waveform; draw the waveform on graph
sheet.
EXPECTED WAVEFORM:
Fig: 4.4 Output waveform of the oscillator
RESULT:Hence, the design of RC phase shift and Wien bridge oscillator is studied and the output
waveforms are observed and plotted.
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Viva Questions:
1. Classify the oscillators.
Ans:Oscillator are two types 1) RC oscillator 2) LC oscillator
2.
In what way is IC 741S better than IC 741?
Ans: IC741S is a military grade of amplifier and has higher slew rate and lower temperature
than IC 741.
3. In phase shift oscillator what phase shift does the op - amp provide?
Ans: 180
4. What phase shift is provided by the feedback network in phase shift oscillator?
Ans: 180
5. Write down the frequency oscillations formula for the phase shift
oscillator. Ans:
6. What is the relation between RF and R1 in op -amp phase shift oscillator?
Ans: RF provides positive feedback path and R1 provides the high input impedances hence
both the resistor are important to sustained oscillations.
7. Define oscillator?
Ans: An electronic circuit that converts energy from a direct-current source to a periodically
varying electric output.
8. In what mode op - amp is used in phase shift oscillator?
Ans: non-inverting mode.
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9. What is the purpose of Phase Shift Network in a Wein Bridge Oscillator?
Ans : A Wien bridge oscillator produces sine waves. In order for the sine waves to maintain
steady amplitude, a positive feedback system is used with some sort of control to limit gain. In
order for the positive feedback system to work, the waves being "fed back" to the amplifier
have to be in phase with the waves being generated. Thus, you need a phase shift network to
ensure that the phases of the waves match, which in the case of a positive feedback system
means that the generated waves need to go through a 360o phase shift during the feedback
process.
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EXPERIMENT 5
IC 555 TIMER IN MONOSTABLE OPERATION
AIM: To design and study the operation of a Monostable Multivibrator using 555 timer.
APPARATUS: Bread board
CRO (20 MHz) 1 in No .
IC 555 -1 in No.
Resistors - 100K - 1 in No., 1.8K -in No., 1 K - 2 in No.
Capacitors - 0.1F -1 in No., 0.01F 1 in No.
RPS
THEORY:IC 555 Timer
IC-555 Timer is an integrated circuit used in a multitude of precise timing and
waveform generation applications. An IC-555 Timer is a versatile Monolithic timing circuit
that can produce accurate and highly stable time delays or oscillations. It can be used as an
Astable and Monostable multivibrators or one shot. It is available as an 8- pin mini DIPpackage. The one shot receives an appropriate trigger signal and outputs a single pulse
whose duration is set by the selection of an external resistor and capacitor.
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Fig: 5. 2 pin diagram of 555 Timer
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Fig: 5.3 Functional diagram of 555 Timer
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Monostable multivibrator operation:Monostable Multivibrator has only one stable state. We can change the stable state by applying
a trigger pulse.
Fig 5.4: Monostable Multivibrator Functional Circuit diagram

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Summary:
Widely used as a monostable or astable multivibrator.
Output voltage is approximately 2 V < VCC.

Output can typically sink or source 200 mA.
Max. output frequency is about 10 kHz. fo varies somewhat with VCC.
Threshold input (pin 6) and trigger input (pin 2) are normally tied together to external
timing RC.
The 555 Timer is a highly stable & inexpensive device for generating accurate time delay
or oscillation.
It can provide time delays ranging from microseconds to hours.
It can be used with power supply voltage ranging from +5V to +18V.
It is compatible with both TTL & CMOS logic circuits.
It has very high temperature stability & it is designed to operate in the temperature
range -55o to +125oC(SE 555), whereas NE555 is a commercial grade IC (0 - 70 oC).
Uses /Applications of Monostable Multivibrator:

1. The falling part of the output pulse from MMV is often used to trigger another pulse
generator circuit thus producing a pulse delayed by a time T with respect to the input
pulse.
2. MMV is used for regenerating old and worn out pulses. Various pulses used in
computers and telecommunication systems become somewhat distorted during use. An
MMV can be used to generate new, clean and sharp pulses from these distorted and
used ones.
3. 3. Frequency divider.
4. Pulse width Modulation (PWM).
5. Pulse Position Modulation (PPM)
6. Linear Ramp Generator
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Circuit Diagram:
Fig:5. 5 Triggering Circuit
Fig 5.6 Monostable multivibrators
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Designing part:Theoritical:
Here, T=1ms,
Let C1=0.1 F, R1=100K then
T = 1.1R1C1=1.1*(100 *103*0.01 *10-6) = 1ms
Practically:
T = 2.2*0.5 at 0.95 KHz
= 1.1 msec
A = 3.8 V at triggering circuit
= 2.6 V
T =2*0.5 msec = 1 msec
PROCEDURE:Monostable multivibrator:1. Design the Monostable multivibrator circuit with the pulse width of T1= 1.1R1C1.
2. Connect the circuit as shown in the circuit diagram fig 5.5 and observe a square
waveform on the CRO as shown in fig 5.7
3. Apply the trigger to pin 2 i.e., output of circuit 5.5 to Fig 5.6
4. Observe the output waveform on the CRO as shown in fig 5.8.
5. Note down the time period and compare the theoretical and practical time periods.
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MODEL WAVEFORMS:Monostable multivibrator:-
Fig 5.7 Trigger input
Fig 5.8 Capacitor and monostable output
RESULT:Hence, the monostable multivibrator using 555 Timer is studied and the output
waveforms are plotted.
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Viva Questions:1. Draw the functional block diagram of a 555 timer.
2. What are the modes of operation of timer?

Ans: three modes of operations of timer:
1) Mono Stable Multivibrator
2) Astable Multivibrator
3) Bistable Multivibrator.
3. Define duty cycle.
Ans: A duty cycle is the time that an entity spends in an active state as a fraction of the
total time under consideration
4.What are the applications of 555 timers in astable mode?
Ans: symmetrical wave generator.
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5. Draw the pin diagram of 555 timers?

Ans:
6. Explain the function of reset?

Ans: This pin is used to make the OUTPUT PIN (Pin 3) LOW. The reset pin must go below 0.7
volt and it needs 0.1mA to reset the chip. The RESET PIN is an overriding function. It will force
the OUTPUT PIN to go LOW regardless of the state of the TRIGGER PIN (Pin 2). It can be used
to terminate an output pulse prematurely, to gate oscillations from "on" to "off." The pin is active
when a voltage level between 0v and 0.4 volt is applied to it. When not used, it is recommended
that the RESET PIN be tied to the positive rail to avoid the possibility of false resetting.
7. What are the applications of 555 timers in monostable mode?

Ans: Missing pulse detector, frequency divider, pulse width modulation.
8. What is the expression of %duty cycle in monostable
mode?
Ans:
9. Explain capacitor output waveform in monostable mode?

Ans: the capacitor gets charged upto maximum value of in given signal whenever the input
changes suddenly from high to low level the capacitor slowly decrease, again for second
pulse input the capacitor charges from that value to the maximum value i.e 2/3 Vcc.
10. Write down the expression for output pulse width in monostable mode?
Ans: T = 1.1R1C1
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Experiment: 6
SCHMITT TRIGGER CIRCUIT USING IC 741 & IC 555
AIM: 1. To Design and construct a Schmitt trigger circuit using IC 741 and IC 555.
2. Verify the output wave forms.
3. Measure the UTP and LTP values.
APPARATUS:
Regulated power supply - 1 in No.
Function generator 1 in No.
CRO - 1 in No.
IC 741 1 in No.
IC 555 1 in No.
Resistors: 1K 2 in No., 10K - 1 No., 100K - 2 in No.
Capacitor 0.01F 2 in No.
THEORY:
Inverting Schmitt Trigger:
Fig 6.1 Schmitt Trigger using op amp 741

When a positive feedback is added to an ideal comparator then the circuit acts as
a Schmitt Trigger. The input voltage is applied at the inverting (-ve ) terminal. The inverting
mode produces opposite polarity output. This is feedback to the non-inverting (+ ve) terminal of
op-amp which is of same polarity as that of the output.
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When Vin is slightly positive than Vref, the output gets driven into negative
saturation at Vsat level.
The output voltage remains in a given state until the input voltage exceeds the
threshold voltage level either positive or negative.
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Fig 6.2 Transfer characteristics showing Hysteresis

The graph indicates that once the output changes its state, it remains there
indefinitely until the input voltage crosses any of the threshold voltage levels. This is called
hysteresis of Schmitt Trigger. The hysteresis is also called dead band or dead zone.
If input applied is purely sinusoidal, the input and output waveforms for inverting
Schmitt Trigger is as shown below:
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Fig: 6.3 Input and output waveforms (Inverting Schmitt Trigger)
Non Inverting Schmitt Trigger:
Fig: 6.4 Non inverting Schmitt Trigger
positive feedback.
Though Vin is decreased, the output continues its positive saturation level unless and until
the input becomes more negative than VLT. At lower threshold, the output changes its state from
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positive saturation +Vsat to negative saturation -Vsat . It remains in negative saturation till Vin
increases beyond its upper threshold level VUT.
The transfer characteristics are as shown below:
Fig: 6.5 Transfer characteristics showing hysteresis
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Fig: 6.6 Input and output waveforms (Non inverting Schmitt Trigger)
Applications of Schmitt trigger:

1. Used as trigger for eliminating comparator Chatter.
2. Used in ON/OFF controllers.
3. The creation of a timer (simple clock signal creation), or the debouncing of a switch.
( The timer can be made by adding an RC to the output and feeding that signal back
to the input. Simple debouncing can be done by sending the input of the switch to the input of the
Schmitt Trigger and taking the output.)
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CIRCUIT DIAGRAM:(1) SCHMITT TRIGGER USING IC 741 (inverting mode)
Fig 6.7 Schmitt trigger using IC 741
PROCEDURE:USING IC 741:1.
Connect the circuit as shown in the Schmitt trigger using IC 741 (fig: 6.7).
2.
Apply an input of a 2V p-p sine wave of 1 KHz.
3.
4.
Observe the output on the CROas shown in fig 6.9

From the rectangular wave displays on CRO measure UTP and LTP.
5.
Use x-y mode in CRO and observe hysteresis curve on CRO.
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(2) SCHMITT TRIGGER USING IC 555.
Fig 6.8 Schmitt trigger using IC 555
PROCEDURE:USING IC 555:1. Connect the circuit as shown in the Schmitt trigger using IC 555 (fig: 6.8).
2. Apply a sine wave of 2 V peak to peak and 1 KHz frequency.
3. The output changes from - Vsat to +Vsat when the input crosses 2/3 Vcc. It is the Upper
Trigger Point (UTP).
4. The output changes from +Vsat to -Vsat when the input crosses 1/3 Vcc. It is the Lower
Trigger Point (LTP).
5. Observe the output waveform on CRO and draw the observed waveforms on graph
Sheet and note down the UTP and LTP values as shown in fig 6.10
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MODEL WAVEFORMS:Using IC 741:-
Fig 6.9 Input and output waveforms of Schmitt trigger using IC 741
Using IC 555.
Fig 6.10 Input and output waveforms of Schmitt trigger using IC 555
RESULT:
Hence, Schmitt trigger circuit using IC 741 and IC 555 are studied and the output
waveforms are observed on the CRO and plotted. The values of UTP and LTP are noted.
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VIVA QUESTIONS:1. What type of feedback we use in Schmitt trigger circuit?

Ans: +Ve feedback
2. What is UTP?
Ans: It is the upper threshold voltage or + Ve voltage where the input signal gets
compared with it and output signal changes its logic.
3. What is LTP?
Ans: It is the lower threshold voltage or negative voltage where the input signal gets
compared with it and output signal changes its logic.
4. What are the circuits we used to generate square?
Ans: Schmitt trigger, monostable multivibrator, astable multivibrator, bistable
multivibrator.
5. What is a zero crossing detectors?
Ans: The zero-crossing is the instantaneous point at which there is no voltage present. In
a sine wave or other simple waveform, this normally occurs twice during each cycle.
6. Define hysteresis width?

Ans: when the input is higher than a certain chosen threshold, the output is high; when
the input is below a different (lower) chosen threshold, the output is low; when the
input is between the two, the output retains its value. This dual threshold action is
called hysteresis and implies that the Schmitt trigger possesses memory and can act as
a bistable circuit (latch). There is a close relation between the two kinds of circuits: a
Schmitt trigger can be converted into a latch and a latch can be converted into a Schmitt
trigger.
7. Write pin diagram of IC 741?
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Ans: 7.
8. Write pin diagram of 555 IC?
Ans:
9. What is the supply voltage rang for IC 741?
Ans: 4.5 V to 18 V
10. What is the supply voltage range for IC 555?
Ans: 4.5V to 15V.
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Experiment 7
IC 743 Voltage regulator
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Experiment 08
PLL
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Expected Graph:
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CYCLE II
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EXPERIMENT: 9
D FLIP-FLOP (74LS74) AND JK MASTER SLAVE FLIP-FLOP (74LS73)
AIM:- To study & verify the truth table of D flip- flop and J K Master Slave flip-flop.
APPARATUS:
1. IC 74LS74, IC 74LS73.
2. Bread board IC trainer kit.
3. Patch cords.
THEORY:
IC 74LS74
One of the main disadvantages of the basic SR NAND Gate bistable circuit is that the
indeterminate input condition of SET = logic 0 and RESET = logic 0 is forbidden. This
state will force both outputs to be at logic 1, over-riding the feedback latching action and
whichever input goes to logic level 1 first will lose control, while the other input still at logic
0 controls the resulting state of the latch.
But in order to prevent this from happening an inverter can be connected between the SET and
the RESET inputs to produce another type of flip flop circuit known as a Data Latch, Delay
flip flop, D-type Bistable, D-type Flip Flop or just simply a D Flip Flop as it is more generally
called.
The D Flip Flop is by far the most important of the Clocked Flip-flops as it ensures that ensures
that inputs S and R are never equal to one at the same time. The D-type flip flop is constructed
from a gated SR flip-flop with an inverter added between the S and the R inputs to allow for a
single D (data) input. Then this single data input, labeled D, is used in place of the set signal,
and the inverter is used to generate the complementary reset input thereby making a levelsensitive D-type flip-flop from a level-sensitive RS-latch as now S = D and R = not D as shown.
Fig: 9.1 Symbol and circuit of a D flip flop.

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A simple SR flip-flop requires two inputs, one to SET the output and one to RESET the
output. By connecting an inverter (NOT gate) to the SR flip-flop we can SET and RESET
the flip-flop using just one input as now the two input signals are complements of each other.
This complement avoids the ambiguity inherent in the SR latch when both inputs are LOW, since
that state is no longer possible.
Thus this single input is called the DATA input. If this data input is held HIGH the flip flop
would be SET and when it is LOW the flip flop would change and become RESET.
However, this would be rather pointless since the flip flops output would always change on
every pulse applied to this data input.
To avoid this an additional input called the CLOCK or ENABLE input is used to isolate the
data input from the flip flops latching circuitry after the desired data has been stored. The effect
is that D input condition is only copied to the output Q when the clock input is active. This then
forms the basis of another sequential device called a D Flip Flop.
The D flip flop will store and output whatever logic level is applied to its data terminal so long
as the clock input is HIGH. Once the clock input goes LOW the set and reset inputs of the
flip-flop are both held at logic level 1 so it will not change state and store whatever data was
present on its output before the clock transition occurred. In other words the output is latched
at either logic 0 or logic 1.
If a 0 is given at Din, then S is 0 and R will be 1. This resets the flip-flop. If a 1 is given at
Din, and then S is 1 and R 0. This sets the flip-flop. Thus we find that D out is always equal to
Din. Hence this flip-flop can be used to store a binary digit. So it is known as the Data flip-flop. The
D flip-flop can also be clocked similar to the RS flip-flop. In the clocked D flip-flop Dout will be
made equal to D in only when the clock arrives. Thus the data bit is sent to the output after a delay.
Therefore, the D flip-flop is also known as the Delay flip-flop.
TRUTH TABLE (74LS74):
Table: 9.1 Truth table of D flip flop
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Fig: 9.2 Pin Diagram of IC 74LS74A
Fig 9.3 Logic diagram of IC 74LS74A
The Master-Slave D Flip Flop

The basic D-type flip flop can be improved further by adding a second SR flip-flop to its output
that is activated on the complementary clock signal to produce a Master-Slave D-type flip flop.
On the leading edge of the clock signal (LOW-to-HIGH) the first stage, the master latches the
input condition at D, while the output stage is deactivated.
On the trailing edge of the clock signal (HIGH-to-LOW) the second slave stage is now
activated, latching on to the output from the first master circuit. Then the output stage appears to
be triggered on the negative edge of the clock pulse. Master-Slave D-type flip flops can be
constructed by the cascading together of two latches with opposite clock phases as shown.
On the leading edge of the clock pulse the master flip-flop will be loading data from the data D
input, therefore the master is ON. With the trailing edge of the clock pulse the slave flip-flop is
loading data, i.e. the slave is ON. Then there will always be one flip-flop ON and the other
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OFF but never both the master and slave ON at the same time. Therefore, the output Q
acquires the value of D, only when one complete pulse, ie, 0-1-0 is applied to the clock input.
There are many different D flip-flop ICs available in both TTL and CMOS packages with the
more common being the 74LS74 which is a Dual D flip-flop IC, which contains two individual
D type bistables within a single chip enabling single or master-slave toggle flip-flops to be
made. Other D flip-flop ICs include the 74LS174 HEX D flip-flop with direct clear input, the
74LS175 Quad D flip-flop with complementary outputs and the 74LS273 Octal D-type flip flop
containing eight D-type flip flops with a clear input in one single package.
Applications of the D-type Flip Flop:

1) For Frequency Division
One main use of a D-type flip flop is as a Frequency Divider. If the Q output on a D-type flipflop is connected directly to the D input giving the device closed loop feedback, successive
clock pulses will make the bistable toggle once every two clock cycles.
In the counters tutorials we saw how the Data Latch can be used as a Binary Divider, or a
Frequency Divider to produce a divide-by-2 counter circuit, that is, the output has half the
frequency of the clock pulses. By placing a feedback loop around the D-type flip flop another
type of flip-flop circuit can be constructed called a T-type flip-flop or more commonly a T-type
bistable, that can be used as a divide-by-two circuit in binary counters as shown below.
Divide-by-2 Counter
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It can be seen from the frequency waveforms above, that by feeding back the output from Q to
the input terminal D, the output pulses at Q have a frequency that are exactly one half ( /2 ) that
of the input clock frequency, ( IN ). In other words the circuit produces frequency division as it
now divides the input frequency by a factor of two (an octave) as Q = 1 once every two clock
cycles.
2) As Data Latches
As well as frequency division, another useful application of the D flip flop is as a Data Latch. A
data latch can be used as a device to hold or remember the data present on its data input, thereby
acting a bit like a single bit memory device and ICs such as the TTL 74LS74 or the CMOS 4042
are available in Quad format exactly for this purpose. By connecting together four, 1-bit data
latches so that all their clock inputs are connected together and are clocked at the same time, a
simple 4-bit Data latch can be made as shown below.
4-bit Data Latch
74LS73:
This simple JK flip Flop is the most widely used of all the flip-flop designs and is considered to be a
universal flip-flop circuit. The sequential operation of the JK flip flop is exactly the same as for the
previous SR flip-flop with the same Set and Reset inputs. The difference this time is that the JK flip
flop has no invalid or forbidden input states of the SR Latch even when S and R are both at logic 1.
The JK flip flop is basically a gated SR Flip-flop with the addition of a clock input circuitry that prevents
the illegal or invalid output condition that can occur when both inputs S and R are equal to logic level
1. Due to this additional clocked input, a JK flip-flop has four possible input combinations, logic 1,
and logic 0, no change and toggle The symbol for a JK flip flop is similar to that of an SR Bistable
Latch as seen in the previous tutorial except for the addition of a clock input.
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Fig: 9.4 Symbol and internal circuit of JK flip flop

The two 2-input AND gates of the gated SR bistable have now been replaced by two 3-input NAND gates
with the third input of each gate connected to the outputs at Q and Q. This cross coupling of the SR flipflop allows the previously invalid condition of S = 1 and R = 1 state to be used to produce a toggle
action as the two inputs are now interlocked.
If the circuit is now SET the J input is inhibited by the 0 status of Q through the lower NAND gate. If
the circuit is RESET the K input is inhibited by the 0 status of Q through the upper NAND gate.
As Q and Q_bar are always different we can use them to control the input. When both inputs J and K are
equal to logic 1, the JK flip flop toggles as shown in the following truth table.
Inputs
CLR
L
H
H
J
X
L
H
K
X
L
L
Outputs
Q
L
Q0
H
CLK
X
Q_bar
H
Qo_bar
L
H
Toggle
Table: 9.2 Truth table of JK flip flop

Then the JK flip-flop is basically an SR flip flop with feedback which enables only one of its two
input terminals, either SET or RESET to be active at any one time thereby eliminating the
invalid condition seen previously in the SR flip flop circuit. Also when both the J and
the K inputs are at logic level 1 at the same time, and the clock input is pulsed either HIGH,
the circuit will toggle from its SET state to a RESET state, or visa-versa. These results in the
JK flip flop acting more like a T-type toggle flip-flop when both terminals are HIGH.
Although this circuit is an improvement on the clocked SR flip-flop it still suffers from timing
problems called race if the output Q changes state before the timing pulse of the clock input
has time to go OFF. To avoid this the timing pulse period (T) must be kept as short as possible
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(high frequency). As this is sometimes not possible with modern TTL ICs the much
improved Master-Slave JK Flip-flop was developed.
The master-slave flip-flop eliminates all the timing problems by using two SR flip-flops
connected together in a series configuration. One flip-flop acts as the Master circuit, which
triggers on the leading edge of the clock pulse while the other acts as the Slave circuit, which
triggers on the falling edge of the clock pulse. This results in the two sections, the master section
and the slave section being enabled during opposite half-cycles of the clock signal.
The TTL 74LS73 is a Dual JK flip-flop IC, which contains two individual JK type bistables
within a single chip enabling single or master-slave toggle flip-flops to be made. Other JK flip
flop ICs include the 74LS107 Dual JK flip-flop with clear, the 74LS109 Dual positive-edge
triggered JK flip flop and the 74LS112 Dual negative-edge triggered flip-flop with both preset and clear inputs.
Fig: 9.5 Dual JK Flip-flop 74LS73

The Master-Slave JK Flip-flop
The Master-Slave Flip-Flop is basically two gated SR flip-flops connected together in a series
configuration with the slave having an inverted clock pulse. The outputs from Q and Q from the
Slave flip-flop are fed back to the inputs of the Master with the outputs of the Master flip
flop being connected to the two inputs of the Slave flip flop. This feedback configuration from
the slaves output to the masters input gives the characteristic toggle of the JK flip flop as
shown below.
The input signals J and K are connected to the gated master SR flip flop which locks the
input condition while the clock (Clk) input is HIGH at logic level 1. As the clock input of
the slave flip flop is the inverse (complement) of the master clock input, the slave SR flip
flop does not toggle. The outputs from the master flip flop are only seen by the gated slave
flip flop when the clock input goes LOW to logic level 0.
When the clock is LOW, the outputs from the master flip flop are latched and any additional
changes to its inputs are ignored. The gated slave flip flop now responds to the state of its inputs
passed over by the master section.
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The Master-Slave JK Flip Flop
Then on the Low-to-High transition of the clock pulse the inputs of the master flip flop are
fed through to the gated inputs of the slave flip flop and on the High-to-Low transition the
same inputs are reflected on the output of the slave making this type of flip flop edge or pulsetriggered.
Then, the circuit accepts input data when the clock signal is HIGH, and passes the data to the
output on the falling-edge of the clock signal. In other words, the Master-Slave JK Flip flop is a
Synchronous device as it only passes data with the timing of the clock signal.
Applications:
Automotive and Transportation
Amplifiers amplifier.ti.com Communications and Telecom
Data Converters & Computers and Peripherals
Clocks and Timers
Circuit diagram:
Fig: 9.6 Circuit diagram to verify the truth table of D flip flop (IC 74LS74A)
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PROCEDURE:
For IC 74LS74 (D flip flop)
1. Connect the circuit as per the internal circuit diagram as shown in fig 9.6.
2. Connect the Q & Q_ bar to the LED on digital trainer kit.
3. Connect the preset terminal to logic 1 and then clear terminal to logic 0. Observe Q
and Q_bar.
4. Connect the preset terminal to logic 0 and then clear terminal to logic 1.
3. Connect the DIP switch to data input terminal at pin 2.
4. Observe Q and Q-bar.
5. Now apply positive edge triggered circuit clock and change the values of D to 0 and 1.
6. Now verify the values of Q and Q_bar from the truth table.
For IC 74LS73 (JK flip flop)
1.
2.
3.
4.
5.
6.
Connect the circuit as per the internal circuit diagram 9.5.

Connect the pin 1, 5 to the clock pulse.
Connect the pin 3, 7, 10, 14 to the DIP switch for input.
Connect the pin 8, 9, 12, 13 to the LED for output.
Connect the pin 2, 6 to the switch to clear the flip- flop.
Verify the values of Q & Q_bar by connecting various connections as given in the truth
table.
PRECAUTIONS:
1. Avoid loose connections.
2. Identify the pin numbers correctly.
3. Care should be taken while applying the power supply to the IC.
RESULT: Hence the truth table of D-flip-flop and J-K master slave flip-flop is verified.
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VIVA QUESTIONS:
1. What is D-FF?
Ans: Delay flip-flop, which has delayed output to the input.
2. Define a latch?
Ans: A latch is an electronic switch using digital logic that will hold the logic level at
its output (1 or 0) that was last applied to its input.
3. Define a FF?
Ans: flip-flop is one bit storage element
4. What is the difference b/w latch & FF?
Ans: Flip-flop is a one bit storage element where as latch is memory less element.
5. In flip-flop how many stable states are there?
Ans: two stable state.
6. What is edge triggering?
Ans: Flip-flop or latch that produced output for given clock signal of falling edge or
rising edge is known as edge triggering.
7. What is level triggering?
Ans: The output of a latch takes its value as soon as inputs are present is knoen as
level triggered
8. I/P of D-F/F =1, then what is the O/P value
Q= Ans: 1.
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EXPERIMENT: 10
DECADE COUNTER (74LS90) AND UP-DOWN COUNTER (74LS192)
AIM: To study the operation of decade counter, using IC7490 and UP-Down Counter using
74LS192.
APPARATUS:
1.
2.
3.
4.
IC 74LS90, 74LS73.
Bread board IC trainer kit.
Connecting wires.
Patch cords.
THEORY:
The decade counter (mod-10 counter) is used most often. In order to count from 0
through 9, a counter with 3 flip-flops is not sufficient. With 4 flip-flops one can count from
0 to15 (16 states). In the decade counter, when the output is 1010 (for the 10th clock pulse),
all the flip-flops should be reset. Thus the outputs QD and QB are given directly to the
inputs of the AND gate and the outputs QC and QA are given through inverters. Therefore,
for the 10th clock pulse, the counter output would be 1010 for a moment. This sends the
output of the AND gate to HIGH clearing all the flip-flops. Thus a decade counter has been
developed.
PIN DIAGRAM ( IC 74LS90):
Fig: 10.1 pin diagram of IC 74LS90 (Decade counter)

IC 7490 is a decade counter which drives input by 10 and provides BCD outputs 0 to 9;
this is also called as decimal counter. These counters comprise of a divide-by 2 and divide-by 5
counters. To use as decade counter we have to cascade divide-by 2 and divide-by 5. Outputs QA
to QD are BCD outputs, inputs A and B are clock inputs to the, divide-by 2 and divide-by 5
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counters respectively. R01 and R02 are the reset inputs, when these are activated counter output
go to 0000. S91 and S92 are the set inputs to the counter, when these inputs are activated
counter output go to 1001.
IC 74LS192:
Fig: 10.2 pin diagram of IC 74LS90( Up down counter)

The IC74192 is an Up/Down modulo -10 decade counter -separate count up and count down
clocks are used in either counting node the circuits, operate synchronously. The outputs change
state synchronous with the low-to- high transitions on the clock inputs. Separate terminal count
up and terminal countdown outputs are provided, which are used as the clocks for subsequent
stages without extra logic, thus simplifying multi-stage counter designs. Individual preset inputs
allow the circuits to be used as programmable counters.
Both the parallel load and the master reset inputs synchronously over ride the clocks.
The description of various pins is as follows:
CPu Count up clock input (active rising edge)

CPd Count down clock input (active rising edge)
MR Asynchronous master reset input (active high)
PL Asynchronous parallel load input (active low)
P0 - P3 Parallel data inputs.
T CD Terminal count down (borrow) output (Active low)
T CU Terminal count up (carry) output (active low)
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CIRCUIT DIAGRAM:
Fig:10.3 (a) Pin details of IC 74192
Fig: 10.3 (b) Circuit for verification of truth table of IC 74192
(counts up from 3 to 8)
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CLK B
Fig:10.4 Circuit for verification of truth table of IC 7490

TRUTH TABLE:-
Table: 10.1 Truth table of IC 74193
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Sl.No. Master reset

R01
1
0
0
0
0
0
0
0
0
0
0
1
2
3
4
5
6
7
8
9
10
11
R02
1
0
0
0
0
0
0
0
0
0
0
Master set
QD
QC
QB
QA
Decimal
equivalent output
Ra1
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
1
0
1
0
1
0
1
0
1
0
9
1
2
3
4
5
6
7
8
9
Ra2
0
1
0
0
0
0
0
0
0
0
0
Table: 10.2 Truth table of IC 7490
PROCEDURE:
1) For verification of truth table of IC 74192 (counts up from 3 to 8)
1. Connect the circuit as shown in the circuit diagram fig:10.3 (b).
2. Observe the ON-OFF of the LEDs (variations in the output).
2) For verification of truth table of IC 7490:
1. Connect the circuit as shown in the circuit diagram fig:10.4.
2. The clock pulse is given to pin-14 and Vcc supply is given to pin-5 of IC 7490.
3. Pin-12 and pin-1 to be shorted.
4. Pins-2, 3 are Master Reset (MR) inputs and pins-6, 7 are Master Set (MS) inputs. Pins-13, 14
has no connections.
5. Pins-2, 3, 6, 7 are inputs and is always 0, to be connected through the DIP switches on
trainer kit.
6. Pins-12, 9,8,11 are outputs, should be connected to the LED on digital trainer kit.
7. Observe the display when feed to MR terminal with 1 and MS terminals with 0 which
displays 0.
8. Observe the display when feed to MR terminal with 0 and MS terminals with 1 which
displays 9.
9. Feed MR terminal with 0 and MS terminals with 0, now apply clock then observe that the
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output varies between the values0 and 9.

PRECAUTIONS:
1.
Avoid loose connections on the bread board/ digital trainer kit.
2.
No connections are to be given to pins-13and 14.
3.
Supply voltage (Vcc) should not exceed +5v.
RESULT:
Hence, the operation of decade counter using IC7490 and UP-Down Counter using 74LS192
is studied and the truth tables are verified.
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VIVA QUESTIONS:
1.
What is a counter?
Ans: It is digital or analog circuits which counts the number of inputs logic given.
2.
what are the asynchronous inputs

Ans: the inputs which doesnt have a sequence of input applied.
3.
Define mod -up counter.
Ans: An up counter is simply a digital counter which counts up at some

predefined increment
4.
Define mod -down counter.
Ans: A down counter is simply a digital counter which counts down at

some predefined decrement.
5.
Difference b/w mod-up counter and mod-down counter.
Ans: mode-up counter will counts increment value to some predefine and
mode- down counter will counts value to some predefine decrement value.
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EXPERIMENT 11
IC 74195 UNIVERSAL SHIFT REGISTER
Aim : To study and verify the following operations of shift register using IC7495 :
Clearing the register

Serial input / parallel output
Parallel input / parallel output
Parallel input / Serial output
Apparatus:
1. IC 7495
2. Patch cords
3. Bread Board
4. Connecting wires.
Theory:
The shift register is an n-bit shift register with a provision for shifting its stored data by
one bit position at each tick of the clock. The series inputs- SERIN, specifies a new bit to be
shifted into one end at each clock tick. This bit appears at the serial output- SEROUT, after n
clock ticks, and is lost one tick later. Thus, an n-bit serial out shift register can be used to delay a
signal by n clock ticks. A serial in, parallel out shift register has outputs for all of its stored bits,
making them available to the other circuits. Such a shift register can be used to perform serial
to-parallel conversion. Conversely it is possible to build a parallel in, serial out shift register. At
the each clock tick the register either loads new data from inputs ID_ND, or it shifts its current
contents, depending on the value of the load / shift control input. The device uses a 2 input
multiplexer on each flip-flops D input to select between the two cases. A parallel in, serial out
shift register can be used to perform parallel-to-serial conversion. By providing outputs for all of
the stored bits in a parallel- in shift register, we obtain the parallel-in parallel-out shift register.
Such a device is general enough to be used in any of the application of the previous shift register.
SN54/74LS195A is a high speed 4-Bit Shift Register offering typical shift frequencies of
39 MHz. It is useful for a wide variety of register and counting applications. It utilizes the
Schottky diode clamped process to achieve high speeds and is fully compatible with all Motorola
TTL products.
These 4 bit registers feature parallel inputs, parallel outputs, J-K serial inputs, shift / load
(SH/LD) control input, and a direct overriding clear. All inputs are buffered to lower the input
drive requirements. The register has two modes of operation:
Parallel (broadside) load
Shift (in the direction QA towards QD)

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Parallel loading is accomplished by applying the four bits of data and taking SH/LD low.
The data is loaded into the associated flip-flop and appears at the outputs after the positive
transition of the clock input. During loading, serial data flow is inhibited.
Shifting is accomplished synchronously when SH/LD is high. Serial data for this mode is
entered at the J-K inputs. Theses inputs permit the first stage to perform as a J-K, D or T type flip
flop.The high performance S195 with a 105 megahertz typical maximum shift- frequency, is
particularly attractive for very high speed data processing systems. In most cases existing
systems can be upgraded merely by using this Schottky- clamped shift register.
Features:
Typical Shift Right Frequency of 39 MHz
Asynchronous Master Reset
J, K Inputs to First Stage
Fully Synchronous Serial or Parallel Data Transfers
Input Clamp Diodes Limit High Speed Termination Effects
Pin diagram:
Fig: 11.1 Pin diagram of 74195
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Fig: 11.2 Logic diagram of IC 74195
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Table 11.1 Function table of IC 74195
PROCEDURE:
1. Mount the IC 74195 on the logic trainer board and connect a 4 bit left shift register as
shown in fig 11.1.
2. Connect pins 2,3,4,5 of the IC to the logic switch SW1, SW2, SW3 and SW4 for
applying low and high logic levels at the input.
3. The serial inputs are given to pin 1 & mode control to pin 6.
4. Pins 8 & 9 are shorted and connected to clock pulse.
5. Apply a supply voltage of +5V to pin 14 and pin 7 to be grounded.
6. Connect the outputs i.e., pin 10, 11, 12 & 13 to LEDs.
Clearing Function:
1. Set the mode control switch to low.
2. Set the serial input switch SW3 to low.
3. Set parallel inputs A, B, C & D to logic 0.
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4. To clear the register apply clock pulses till the output is 0000.
Serial input and parallel output:
1. After the register has been cleared, any 4 bit serial number can be loaded into the register.
2. Set mode control switch to low.
3. Set the serial input to high.
4. Apply a clock pulse which will shift the serial input 1 into the register, in this case Qn
is 1.
5. Return serial input switch SW3 to low and apply 3 clock pulses. The register will show
an output of 00001. Any 4 bit number can be loaded into the register in this way.
Parallel input and parallel output:
1. Set the mode control to high.
2. Apply the following inputs at A,B, C & D.
Eg: A B C D
1
0
1
1
3. When a clock pulse is applied, the word is loaded into the register.
Parallel input and Serial output:
1. If the loaded input is 1011, set the mode control to low.
2. Set the serial input pin 1 to low.
3. As the clock is applied, the word is shifted out serially from Qn and after 4 clock pulses
the register will be cleared.
PRECAUTIONS:
1. All the pins should be identified properly.
2. Supply voltage should not exceed +5v.
3. Avoid loose connections on the bread board.
RESULT: Hence, the various functions of the Universal shift register are verified using IC 7495.
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VIVA QUESTIONS:
1. What is a register?
Ans: Register is a small amount of storage available as part of a digital processor, such as a CPU. Such
registers are (typically) addressed by mechanisms other than main memory and can be accessed faster.
2. What is a shift register?
Ans: a shift register is a cascade of flip flops, sharing the same clock, in which the output
of each flip-flop is connected to the "data" input of the next flip-flop in the chain, resulting in
a circuit that shifts by one position the "bit array" stored in it, shifting in the data present at its
input and shifting out the last bit in the array, at each transition of the clock input.
3. What are the operations performed by a shift register?
Ans: Shift registers operate in one of four different modes with the basic movement of data
through a shift register being:
Serial-in to Parallel-out (SIPO) - the register is loaded with serial data, one bit at a
time, with the stored data being available in parallel form.
Serial-in to Serial-out (SISO) - the data is shifted serially IN and OUT of the
register, one bit at a time in either a left or right direction under clock control.
Parallel-in to Serial-out (PISO) - the parallel data is loaded into the register
simultaneously and is shifted out of the register serially one bit at a time under clock
control.
Parallel-in to Parallel-out (PIPO) - the parallel data is loaded simultaneously into
the register, and transferred together to their respective outputs by the same clock pulse.
4. What is a Universal Shift register?
Ans: A universal shift register is an integrated logic circuit that can transfer data in three
different modes. Like a parallel register it can load and transmit data in parallel.
5. All the operations in a digital system are performed on --------------.
Ans: All the operations in a digital system are performed on registers.
6. What is the purpose of the parallel-in/ parallel-out shift register?

Ans: The purpose of the parallel-in/ parallel-out shift register is to take in parallel
data, shift it, and then output it as shown below. A universal shift register is a doeverything device in addition to the parallel-in/ parallel-out function.
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7. Shift left / right register left action.
8.
Mention any practical application of Universal shift register.

Ans:
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09. Applications of SISO universal shift register?

Ans: In medical industries for filling liquids in bottles.
10. Applications of SIPO universal shift register?
Ans: USB to I/O interface.
11.Applications of PIPO universal shift register?
Ans: DMA interface.
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EXPERIMENT: 12
3 - 8 DECODER- 74138
AIM: To study and verify the truth table for 3 - 8 decoder using IC 74138.
APPARATUS:
1.
2.
3.
4.
IC 74138.
Bread board trainer kit
Patch cords
Connecting wires
PIN DIAGRAM:
Pin s: 1, 2 & 3 are input pins

Pins; 4, 5 &6 are enable inputs
Pins: 7, 9,10,11, 12,13,14,15 are output pins
Fig: 12.1 Pin configuration of IC 74138
THEORY:
n
Decoder is the combinational circuit which contains n input lines to 2 output
lines. The decoder is used for converting the binary code into the octal code. The IC74138
is the 3*8 decoder which contains three inputs and eight outputs and also three enables out
of them two are active low and one is active high. Decoders are used in the circuit where
required to get more outputs than that of the inputs which also used in the chip designing
process for reducing the IC chip area.
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LOGIC SYMBOL:
Select lines
Fig: 12.2 Logic symbol of IC 74138

LOGIC DIAGRAM:
Select lines
Fig: 12.3 Logic diagram of IC 74138

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TRUTH TABLE:
Fig: 12.4 Truth table of IC 74138

PROCEDURE:
1. Mount the IC74138 on the bread board and connect the input and output lines using a trainer
kit as mentioned in the truth table 12.4.
2. Apply Vcc=+5v to the Pin-16 and ground pin 8 of IC 74138.
3. Connect the DIP switches to input lines i.e., Pins-1, 2 & 3.
4. Connect the DIP switches to pins 4, 5, 6 which are the enable inputs.
5. When E1 is high and E2, E3 are low then all the outputs are high irrespective of inputs A0, A1
and A2.
6. Similarly when E2 is high, all the outputs are high irrespective of the inputs.
7. When E3 is low all the outputs are high irrespective of the inputs i.e., E1 and E2 and high.
8. If E1 and E2 are low and E3 are high, the inputs are low, the outputs Qo will be low
with all the other outputs are high.
This indicates selection of output 0 based on input code 000.
9. Similarly by changing the inputs we get (one) 1 output as low and all other outputs as high.
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10. When all inputs are high O71 will be low and all other will be high based on the code.
11. When all the inputs are high O7 will be low indicating the selection output 7 as the input code
is 111.
PRECAUTIONS:
RESULT: Hence, the working of the 3 to 8 decoder is verified using IC 74138.
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VIVA QUESTIONS:
1. What is decoder?
Ans: A decoder is a device which does the reverse operation of an encoder, undoing the
encoding so that the original information can be retrieved. The same method used to
encode is usually just reversed in order to decode. It is a combinational circuit that
n
converts binary information from n input lines to a maximum of 2 unique output lines
2. What is a encoder?
Ans: An encoder is a device, circuit, transducer, software program, algorithm or
person that converts information from one format or code to another, for the purposes of
standardization, speed, secrecy, security, or saving space by shrinking size
3. For a 2- I/P decoder how much Outputs are produced?
Ans: 4.
4. A decoder with n input produces max. of number of minterms.
n
Ans: 2
5. The general representation of an encoder is?
Ans: The general representation of an encoder is for economical realization,
decoder is used to realize a function which contain (Less no. of dont cares)
6. Difference between demultiplexer and decoder.
Ans: Decoder is one to many outputs.
7. Can more than one decoder O/P be activated at

one time?
Ans: No.
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EXPERIMENT: 13
4-BIT COMPARATOR- 74LS85

AIM: To verify the operation of 4-bit magnitude comparator using IC 7485.
APPARATUS:
1. IC 74LS85.
2. Bread board IC trainer kit.
3. Patch cords.
PIN DIAGRAM:
Circuit diagram:
Fig:13.1 Pin configuration of IC 74LS 85
Fig 13.2: Circuit diagram of IC 74LS 85
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LOGIC DIAGRAM
Fig: 13.3 Logic diagram of IC 74LS 85
TRUTH TABLE:
Table 13.1 Truth table of IC 74LS85

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THEORY:
Comparing two binary words for equality is a commonly used operation in
computer systems and device interfaces. A circuit that compares two binary words and
indicates whether they are equal is called a comparator. Some comparators interpret their
input words as signed or unsigned numbers and also indicate an arithmetic relationship
(greater or less than) between the words. These devices are often called magnitude
comparators. A 1-bit Comparator is designed using Ex-OR and Ex-NOR gates. The
outputs of 4 XOR gates are ORed to create a 4-bit comparator. The IC 7485 is 4-bit
magnitude comparator. With respect to the 8 inputs 3 inputs are cascaded inputs. After the
8 input operations are performed further the outputs are based on the cascaded inputs.
Features:
Typical power dissipation 52 mW
Typical delay (4-bit words) 24 ns
PROCEDURE:
1. Connect the circuit as shown in circuit diagram fig 13.2.
2. Give the input pins A [A3, A2, A1, A0] and B [B3, B2, B1, B0] according to each case
mentioned in the function table 13.1.
3. Connect the pin 5, 6, 7 to the LED to verify the output.

4. Connect the pin 2, 3, 4 to the DIP switches.
5. Give the cascaded inputs IA>B, IA=B, IA<B and verify the outputs.
6. Tabulate the inputs and outputs according to function table.
PRECAUTIONS:
RESULT: Hence, the operation of 4-bit magnitude comparator is verified using IC74LS85.
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VIVA QUESTIONS:
1. What is Magnitude Comparator?
Ans: A digital comparator or magnitude comparator is a hardware electronic device
that takes two numbers as input in binary form and determines whether one number is
greater than, less than or equal to the other number.
2. To form a 12 - bit comparator how many 4-bit comparators are connected in cascaded
form.
Ans: 3
3. The IC 7485 is a package and is a ____ comparator.
Ans: 4
4. How many cascaded input are there for a 4-bit comparator.
Ans: 3
5. Which gate is best used as a basic comparator?
Ans: Exclusive OR gate.
6. How many Exclusive NOR gates would be required for a 8 bit comparator circuit?
Ans: 8
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EXPERIMENT 14
8 x 1 MULTIPLEXER-74151 & 2X4 DEMULTIPLEXER - 74155

AIM: To verify the operation of 8x1 multiplexer using IC 74151 and 2X4 Demultiplexer -74155.
APPARATUS:
1.
2.
3.
4.
IC 74151, IC 74155.
IC trainer kit.
Patch cords.
Connecting wires.
PIN DIAGRAM
Fig:14.1 Pin diagram of IC 74151
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Fig: 14.2 Details of inputs applied to pin s of IC 74155
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TRUTH TABLE
Table 14.1 Truth table of IC 74151
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Table 142 Truth table of 8:1 multiplexer
Table:14.3 For IC 74155

LOGIC DIAGRAM ( IC 74151)
Fig 14.3 Logic diagram of IC 74155

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THEORY:
A multiplexer is a digital switch- it connects data from one of n sources to its output. An
8x1 is multiplexer consists of 3 input lines as select lines and 8 input lines and 1 output line. A
multiplexer is a unidirectional device which follows the data from input lines to output lines.
Multiplexers are obviously useful device in any application in which data must be multiple
source to destination. A common application in computers is the mux between the processors
registers and its ALU.
PROCEDURE:
1. Connections are made as per logic diagram shown in fig 14.3
2. Connect the inputs D0 to D7.
3. Apply inputs / data to select inputs and verify outputs according to truth table.
PRECAUTIONS:
RESULT: Hence, a 8x1 multiplexer operation is verified using IC74151.

VIVA QUESTIONS:
1. Mux is an implementation of?
Ans: Any n-variable logic function can be implemented using a smaller 2
n-1
-to-1
multiplexer and a single inverter (e.g 4-to-1 mux to implement 3 variable functions) as
follows.
2. Multiplexer is represented by?
Ans: Multiplexer is represented by number of inputs x number of outputs as 2" x 1
MUX, l-of-2n MUX (or) 4-to-l-line MUX.
3. De multiplexer is represented by?
Ans: A multiplexer (or MUX) is a device that selects one of several
analog or digital input signals and forwards the selected input into a single line. A
n
multiplexer of 2 inputs has n select lines, which are used to select which input line
to send to the output
4. Could you design 3-variable functions with one 74151 MUX IC? How?
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Ans: Yes, Implement the function F(X,Y,Z) = (1,3,5,6) using

an 8-to-1 mux. Connect the input variables X, Y, Z to mux select lines. Mux data input
lines 1, 3, 5, 6 that correspond to function minterms are connected to 1. The remaining
mux data input lines 0, 2, 4, 7 are connected to 0.
Ans: YES. 4-variable Function Using 8-to-1 mux
Implement the function
F(x1,x2,x3,x4) = (0,1,2,3,4,9,13,14,15)
74151A 8-to-1 mux and an
inverter. We choose the three most
using a single
significant inputs x1,x2,x3 as mux select
lines.Construct truth table. Determine multiplexer Data input line Di values.

7. Could you design 4-variable functions with one 74155 DECODER IC? How?
8. In this experiment you have realized 3-variable function by using one 74155 DECODER,
What else could you design, in general, by using one 74155 DECODER? (See data sheet)
9. Could you state a rule when you prefer MUX or DECODER realizations?
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Experiment 15
STUDY OF RAM IC 74189
AIM: - To study the operation of the RAM IC 74189.
APPARATUS: - 1. RAM IC 74189 Trainer kit.
PIN DIAGRAM:
OPERATION: RAM IC 7489 is 16 words x 4-bit Read/Write Memory.

The Truth Table for the RAM IC 74189 is given below.
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The memory Enable pin is used to select 1- of-n ICs i.e. like a Chip Select
signal.
For simply city, the memory enable pin is permanently held low.
The address lines are given through an up /down counter with preset capability.
The set address switch is held high to allow the user choose any location in the
RAM, using the address bits.
The address and data bits are used to set an address and enter the data.
The Read/Write switch is used to write data on to the RAM.
WRITE OPERATION: 1. Assume that the following data has to be written on to the RAM. The address and data are
given in the hexadecimal format.
2. Position the Stack/Queue switch in the Queueposition.
3. Position the Read/Write switch in the Write position to enable the entry of data in to
the RAM.
4. Position the Set Address switch in the 1 position to allow random access of memory.
5. Set the desired address (any address at random) using the address bit switches.
6. Set the desired data (refer table for the data to be entered in each location) using the data bit
switches.
7. Observe that the data is indicated by the LEDs (D3 toD0). This is because the data is written
on to the RAM.
8. Also observe that the data is indicated by the data outputs is the compliment of the data input
(refer truth table condition ME =L and WE=L) .
9. After each data entry, make a note of the location where data is entered. This is to make sure
that we are not re entering data in the same location.
10. Repeat steps 4 and 5 until data has been entered in all the addresses listed in the above table
11. Position the Read/Write switch in the Read position, to disable data entry.
12. This completes data entry.
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READ OPERATION: 1. Position the Stack/Queue switch in the Queue position.

2. Position the Set Address switch in the 0 position to allow random access of memory.
3. Position Read/Write switch in the Read position, to disable unauthorized entry of data.
4. Set the desired address (any address at random).
5. Observe that the data entered in the location is indicated by the LEDs (D3 toD0). This is
because the data was written during the data entry procedure.
6. Also observe that the data indicated by the data out puts is the compliment of the data input
(refer truth table condition ME=L and WE=H).
RESULT: Hence, the operation of the RAM Ic7489 has been verified.
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Viva Questions:
1. What is RAM?
Ans: RAM (pronounced ramm) is an acronym for random access memory, a type of
computer memory that can be accessed randomly; that is, any byte of memory can be
accessed without touching the preceding bytes. RAM is the most common type of
memory found in computers and other devices, such as printers.
2. Give the applications of the RAM?
Ans:
There are main types of RAM: SDRAM, DDR and Rambus DRAM.
SDRAM (Synchronous DRAM)

Almost all systems used to ship with 3.3 volt, 168-pin SDRAM DIMMs. SDRAM is not an
extension of older EDO DRAM but a new type of DRAM altogether. SDRAM started out
running at 66 MHz, while older fast page mode DRAM and EDO max out at 50 MHz. SDRAM
is able to scale to 133 MHz (PC133) officially, and unofficially up to 180MHz or higher. As
processors get faster, new generations of memory such as DDR and RDRAM are required to get
proper performance.
DDR (Double Data Rate SDRAM)
DDR basically doubles the rate of data transfer of standard SDRAM by transferring data on the
up and down tick of a clock cycle. DDR memory operating at 333MHz actually operates at
166MHz * 2 (aka PC333 / PC2700) or 133MHz*2 (PC266 / PC2100). DDR is a 2.5 volt
technology that uses 184 pins in its DIMMs. It is incompatible with SDRAM physically, but uses
a similar parallel bus, making it easier to implement than RDRAM, which is a different
technology..
Rambus DRAM (RDRAM)
Despite it's higher price, Intel has given RDRAM it's blessing for the consumer MARKET and
it will be the sole choice of memory for Intel's Pentium 4. RDRAM is a serial memory
technology that arrived in three flavors, PC600, PC700, and PC800. PC800 RDRAM has double
the maximum throughput of old PC100 SDRAM, but a higher latency. RDRAM designs with
multiple channels, such as those in Pentium 4 motherboards, are currently at the top of the heap
in memory throughput, especially when paired with PC1066 RDRAM memory.
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3. What is the difference between RAM &ROM?

Ans:
4. What is the difference between static RAM &dynamic RAM?

Ans: Even though both SRAMs and DRAMs are volatile memories, they have some
important differences. Since the DRAM requires a single capacitor and a transistor for
each memory cell, it is much simpler in the structure than the SRAM, which uses six
transistors for each memory cell. On the other hand, due to the use of capacitors, DRAM
requires to be refreshed periodically as opposed to the SRAM. DRAMs are less
expensive and slower than SRAMs. Therefore they are used for the large main memory
of personal computers, workstations, etc., while SRAM are used for the smaller and
faster cache memory.
5. Which can be used as 1-bit memory?
Ans: Flip-flop.
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Experiment 16
Stack and Queue implementation using RAM 74189
AIM: - To study the operation of the RAM IC 74189.
APPARATUS: - 1. RAM IC 74189 Trainer kit.
PIN DIAGRAM:
PROCEDURE:
This experiment has 3 stages Clearing the memory, data entry (Write operation) and
data verification (Read operation).
CLEARING THE MEMORY:
The RAM IC 7489 is a volatile memory. This means that it will lose the data stored in it, on loss
of power. However, this does not mean that the content of the memory becomes 0h, but not
always. The RAM IC 7489 does not come with a Clear Memory signal. The memory has to be
cleared manually.
1. Position the Stack/Queue switch in the Queue position.

2. Position the Set Address switch in the 1 position.
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3. Set the address bits to 0h (first byte in the memory)

4. Position the Set Address switch in the 0 position to disable random access and enable the
counter.
5. Position the Read/Write switch in the Write position to write data on to the memory.
6. Set the data bits to 0h (clearing the content)
7. Observe that the LEDs (D3 to D0) glow. This is to indicate that the content is 0h. Refer
the truth table above and observe that the data outputs of the RAM will be compliments of the
data inputs.
8. Position the Increment/Decrement switch in the Increment position.
9. Press the Clock to increment the counter to the next address. As the Read /Write switch is
already in the Write position, and the data bits are set to the 0h, the content in the new location
is also replaced with 0h.
10. Repeat step 8 until the data in all the memory locations has been cleared.
Result: Hence the Stack and Queue is implemented using RAM 74189
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Additional
Experiments
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Design
Experiments
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Equations:
Q =fo/BW
But BW = (fH-fL)
Q = fo/(fH-fL)
Fo = fHfL
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Filter Response:
Q factor at resonance is Qo = WoL / R = WoRc
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Open
Experiments
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References
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QUESTION
BANK
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1. Mention the advantages of integrated circuits.
Miniaturization and hence increased equipment density.
Cost reduction due to batch processing.
Increased system reliability due to the elimination of soldered joints.

Improved functional performance.
Matched devices.
Increased operating speeds.
Reduction in power consumption.
2.Write down the various processes used to fabricate ICs using silicon planar
technology.
Silicon wafer preparation.
Epitaxial growth
Oxidation.
Photolithography.
Diffusion.
Ion implantation.
Isolation.
Metallization.
Assembly processing and packaging.

3. What is the purpose of oxidation?
SiO2is an extremely hard protective coating and is unaffected by almost all reagents. By
selective etching of SiO2, diffusion of impurities through carefully defined windows can be
accomplished to fabricate various components.
4.Why aluminum is preferred for metallization?
It is a good conductor.
It is easy to deposit aluminium films using vacuum deposition.
It makes good mechanical bonds with silicon.
It forms a low resistance contact.
5. What are the popular IC packages available?
Metal can package.
Dual-in-line package.
Ceramic flat package.

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6. Define an operational amplifier.

An operational amplifier is a direct-coupled, high gain amplifier consisting of one or more
differential amplifier. By properly selecting the external components, it can be used to perform a
variety of mathematical operations.
7. Mention the characteristics of an ideal op-amp.
Open loop voltage gain is infinity.
Input impedance is infinity.
Output impedance is zero.
Bandwidth is infinity.
Zero offset.
8. Define input offset voltage.

A small voltage applied to the input terminals to make the output voltages zero when
the two input terminals are grounded is called input offset voltage.
9. Define input offset current. State the reasons for the offset currents at the input of
the op-amp.
The difference between the bias currents at the input terminals of the op-amp is
called as input offset current. The input terminals conduct a small value of DC current to
bias the input transistors. Since the input transistors cannot be made identical, there exists a
difference in bias currents.
10. Define CMRR of an op-amp.
The relative sensitivity of an op-amp to a difference signal as compared to a
common mode signal is called the common mode rejection ratio. It is expressed in
decibels. CMRR= Ad/Ac.
11. What are the applications of current sources?
Transistor current sources are widely used in analog ICs both as biasing elements and
as load devices for amplifier stages.
12. Justify the reasons for using current sources in integrated circuits.
Superior insensitivity of circuit performance to power supply variations and

temperature.
More economical than resistors in terms of die area required to provide bias
currents of small value.
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When used as load element, the high incremental resistance of current source results in
high voltage gains at low supply voltages.
13. What is the advantage of widlar current source over constant current
source?
Using constant current source output current of small magnitude (micro amp range)
is not attainable due to the limitations in chip area. Widlar current source is useful for
obtaining small output currents. Sensitivity of widlar current source is less compared to
constant current source.
14. Mention the advantages of Wilson current source.
Provides high output resistance.
Offers low sensitivity to transistor base currents.
15.
Define sensitivity.
Sensitivity is defined as the percentage or fractional change in output current per
percentage or fractional change in power-supply voltage.
16. What are the limitations in a temperature compensated zener-reference source?

A power supply voltage of at least 7 to 10 V is required to place the diode in the
breakdown region and that substantial noise is introduced in the circuit by the avalanching
diode.
17. What do you mean by a band-gap referenced biasing circuit?
The biasing sources referenced to VBE have a negative temperature co-efficient and VT
has a positive temperature co-efficient. Band gap reference circuit is one in which the output
current is referenced to a composite voltage that is a weighted sum of VBE a n d V T so that by
proper weighting, zero temperature co-efficient can be achieved.
18. In practical op-amps, what is the effect of high frequency on its performance?
The open-loop gain of op -amp decreases at higher frequencies due to the presence of
parasitic capacitance.
The closed-loop gain increases at higher frequencies and leads to instability.
19. What is the advantage of widlar current source over constant current
source?
Using constant current source output current of small magnitude (micro amp range)
is not attainable due to the limitations in chip area. Widlar current source is useful for
obtaining small output currents. Sensitivity of widlar current source is less compared to
constant current source.
20. Mention the advantages of Wilson current source.
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Provides high output resistance.
Offers low sensitivity to transistor base currents.
21.
Define sensitivity.
Sensitivity is defined as the percentage or fractional change in output current per
percentage or fractional change in power-supply voltage.
22. Difference between open loop gain and closed loop gain in practical op-amps,
what is the effect of high frequency on its performance?
The open-loop gain of op -amp decreases at higher frequencies due to the presence of
parasitic capacitance. The closed-loop gain increases at higher frequencies and leads to
instability.
23. What is the need for frequency compensation in practical op-amps?
Frequency compensation is needed when large bandwidth and lower closed loop gain is
desired. Compensating networks are used to control the phase shift and hence to improve the
stability.
24. Mention the frequency compensation methods.
Dominant-pole compensation
Pole-zero compensation.
26. What are the merits and demerits of Dominant-pole compensation?
Noise immunity of the system is improved.
Open-loop bandwidth is reduced.
27. Define slew rate.

The slew rate is defined as the maximum rate of change of output voltage caused by a
step input voltage. An ideal slew rate is infinite which means that op-amps output voltage
should change instantaneously in response to input step voltage.
28. Why IC 741 is not used for high frequency applications?
IC741 has a low slew rate because of the predominance of capacitance present in the
circuit at higher frequencies. As frequency increases the output gets distorted due to limited
slew rate.
29. What causes slew rate?
There is a capacitor with-in or outside of an op-amp to prevent oscillation. It is this
capacitor which prevents the output voltage from responding immediately to a fast changing
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input.
30. What is monolithic IC?

A monolithic IC is a type of "integrated circuit" electronic device that contains active and
passive devices that are made in and on the surface of a single piece of a single crystal
semiconductor, such as a Silicon (Si) wafer. A process called "planar technology" must be used
in the single block (monolith), and be interconnected to the insulating layer over the same body
of the semiconductor to produce a solid integral monolithic-IC. In monolithic-ICs, the devices
(transistors, diodes, resistors and capacitors) are fabricated on the same single chip of a single
Silicon crystal by PLANAR technology, and have ISOLATED p-n junctions, and have
interconnections adherent to the insulator layers without shorting to the adjacent areas and each
other.
31. What is hybrid IC?
If the devices are interconnected by bonding wires dangling above the chip, it is a
hybrid-IC.
32. What is Photolithography?
Photolithography is a process used in micro fabrication to selectively remove parts o f a
thin film or the bulk of a substrate. It uses light to transfer a geometric pattern from a photo mask
to a light-sensitive chemical "photo resist", or simply "resist," on the substrate. A series of
chemical treatments then engraves the exposure pattern in to the material underneath the photo
resist. In complex integrated circuits, for example a modern CMOS, a wafer will go through the
photolithographic cycle up to 50 times.
33. What is the principle of Photolithography?
Photolithography shares some fundamental principles with photography in that the
pattern in the resist is created by exposing it to light, either using a projected image or an optical
mask.
It is used because it affords exact control over the shape and size of the objects it creates, and
because it can create patterns over an entire surface simultaneously
34. Mention some of the linear applications of op amps.
Adder, Subtractor, voltage to- current converter, current to-voltage converters,
instrumentation amplifier, analog computation, power amplifier, etc are some of the linear
op-amp circuits.
35. Mention some of the non linear applications of op-amps.
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Rectifier, peak detector, clipper, clamper, sample and hold circuit, log amplifier, anti
log amplifier, multiplier are some of the non linear op-amp circuits.
36. What are the areas of application of non-linear op- amp circuits?
Industrial instrumentation
Communication
Signal processing
37. What is the need for an instrumentation amplifier?

In a number of industrial and consumer applications, the measurement of physical
quantities is usually done with the help of transducers. The output of transducer has to be
amplified So that it can drive the indicator or display system. This function is performed by an
instrumentation amplifier.
38. List the features of instrumentation amplifier.
High Gain Accuracy
High CMRR
High Gain Stability With Low Temperature Co-Efficient
Low DC Offset
Low Output Impedance
39. List the applications of Log amplifiers.
Analog computation may require functions such as lnx, log x, sin hx etc. These
functions can be performed by log amplifiers
Log amplifier can perform direct dB display on digital voltmeter and spectrum
analyzer
Log amplifier can be used to compress the dynamic range of a signal
40. What are the limitations of the basic differentiator circuit?
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At high frequency, a differentiator may become unstable and break in to oscillations
The input impedance decreases with increase in frequency, thereby making the circuit
sensitive to high frequency noise.
42. What is a comparator?

A comparator is a circuit which compares a signal voltage applied at one input of an
op-amp with a known reference voltage at the other input. It is an open loop op -amp with
output +Vsat .
43. What are the applications of comparator?
Zero crossing detector

Window detector
Time marker generator
Phase detector
44. What is a Schmitt trigger?
Schmitt trigger is a regenerative comparator. It converts sinusoidal input into a square
wave output. The output of Schmitt trigger swings between upper and lower threshold voltages,
which are the reference voltages of the input waveform.
45. What is a multivibrator?
Multivibrators are a group of regenerative circuits that are used extensively in timing
applications. It is a wave shaping circuit which gives symmetric or asymmetric square output. It
has two states either stable or quasi- stable depending on the type of multivibrato.
46.What is an astable multivibrator?
Astable multivibrator is a free running oscillator having two quasi-stable states. Thus,
there is oscillations between these two states and no external signal are required to produce the
change in state.
47.What is a bistable multivibrator?
Bistable multivibrator is one that maintains a given output voltage level unless an
external trigger is applied. Application of an external trigger signal causes a change of state,
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and this output level is maintained indefinitely until a second trigger is applied. Thus, it
requires two external triggers before it returns to its initial state.
48. What are the characteristics of a comparator?
Speed of operation
Accuracy
Compatibility of the output
49 .What is a filter?
Filter is a frequency selective circuit that passes signal of specified band of frequencies
and attenuates the signals of frequencies outside the band.
50. What are the demerits of passive filters?
Passive filters works well for high frequencies. But at audio frequencies, the inductors
become problematic, as they become large, heavy and expensive. For low frequency more
number of turns of wire must be used which in turn adds to the series resistance degrading
inductors performance ie, low Q, resulting in high power dissipation.
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51. What are the advantages of active filters?
Active filters used op - amp as the active element and resistors

and capacitors as passive elements.
By enclosing a capacitor in the feedback loop , inductor less active
filters can be obtained
Op-amp used in non inverting configuration offers high input
impedance and low output impedance, thus improving the load drive
capacity.
52. Mention some commonly used active filters.
Low pass filter

High pass filter
Band pass filter
Band reject filter.
53. Mention some areas where PLL is widely used.
Radar synchronization
Satellite communication systems
air borne navigational systems
FM communication systems
Computers.
54. List the basic building blocks of PLL
Phase detector/comparator
Low pass filter
Error amplifier
Voltage controlled oscillator
55. What are the three stages through which PLL operates?
Free running
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Capture
Locked/ tracking
56. Define lock-in range of a PLL.

The range of frequencies over which the PLL can maintain lock with
the incoming signal is called the lock-in range or tracking range. It is
expressed as a percentage of the VCO free running frequency.
57. Define capture range of PLL.
The range of frequencies over which the PLL can acquire lock
with an input signal is called the capture range. It is expressed as a
percentage of the VCO free running frequency.
58. Define Pull-in time.
The total time taken by the PLL to establish lock is called pull-in
time. It depends on the initial phase and frequency difference between the
two signals as well as on the overall loop gain and loop filter
characteristics.
59. For perfect lock, what should be the phase relation between
the incoming signal and VCO output signal?
The VCO output should be 90 degrees out of
phase with respect to the input signal.
60. Give the classification of phase detector:
Analog phase detector
Digital phase detector
61. What is a switch type phase detector?

An electronic switch is opened and closed by signal coming from
VCO and the input signal is chopped at a repetition rate determined by the
VCO frequency. This type of phase detector is called a half wave detector
since the phase information for only one-half of the input signal is detected
and averaged.
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62. What are the problems associated with switch type phase detector?
The output voltage Ve is proportional to the input signal
amplitude. This is undesirable because it makes phase detector gain and
loop gain dependent on the input signal amplitude. The output is
proportional to cos making it non linear.
63.What is a voltage controlled oscillator?
Voltage controlled oscillator is a free running multivibrator
operating at a set frequency called the free running frequency. This
frequency can be shifted to either side by applying a dc control voltage and
the frequency deviation is proportional to the dc control voltage.
64. On what parameters does the free running frequency of VCO depend
on?
External timing resistor, R T
External timing capacitor, CT
The dc control voltage Vc.
65. What is the purpose of having a low pass filter in PLL?

It removes the high frequency components and noise.
Controls the dynamic characteristics of the PLL such as capture
range, lock -in range, band-width and transient response.
The charge on the filter capacitor gives a short- time memory to
the PLL.
66. Discuss the effect of having large capture range.
The PLL cannot acquire a signal outside the capture range, but once
captured, it will hold on till the frequency goes beyond the lock-in range.
Thus, to increase the ability of lock range, large capture range is required.
But, a large capture range will make the PLL more susceptible to noise and
undesirable signal.
67. Mention some typical applications of PLL:
Frequency multiplication/division
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Frequency translation
AM detection
FM demodulation
FSK demodulation.
68.What is a compander IC? Give some examples.

The term companding means compressing and expanding. In
acommun ication system, the audio signal is compressed in the transmitter
and expanded in the receiver. Examples : LM 2704- LM 2707 ; NE 570/571.
69. What are the merits of companding?
The compression process reduces the dynamic range of the
signal before it is transmitted. Companding preserves the signal to
noise ratio of the original signal and avoids non linear distortion of
the signal when the input amplitude is large. It also reduces buzz,
bias and low level audio tones caused by mild interference.
70. List the applications of OTA
`OTA can be used in:
programmable gain voltage amplifier

sample and hold circuits
voltage controlled state variable filter
Current controlled relaxation oscillator.
71. List the broad classification of ADCs.
Direct type ADC.
Integrating type ADC.
72. List out the direct type ADCs.

i. Flash (comparator) type converter
ii. Counter type converter
iii. Tracking or servo converter
iv. Successive approximation type converter
73. List out some integrating type converters.
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Charge balancing ADC

Dual slope ADC
74. What is integrating type converter?

An ADC converter that perform conversion in an indirect manner
by firstchanging the analog I/P signal to a linear function of time or
frequency and then to adigital code is known as integrating type A/D
converter.
75. Explain in brief the principle of operation of successive
Approximation
ADC.
The circuit of successive approximation ADC consists of a successive
approximation register (SAR), to find the required value of each bit by trial &
error. With the arrival of START command, SAR sets the MSB bit to 1. The
O/P is converted into an analog signal & it is compared with I/P signal. This
O/P is low or high. This process continues until all bits are checked.
76. What are the main advantages of integrating type ADCs?
The integrating type of ADCs do not need a sample/Hold circuit at

the input.
It is possible to transmit frequency even in noisy environment or in an
isolated form.
77. Where are the successive approximation type ADC used?

The Successive approximation ADCs are used in applications such as
data loggers & instrumentation where conversion speed is important.
78. What is the main drawback of a dual-slop ADC?
The dual slope ADC has long conversion time. This is the
main drawback of dual slope ADC.
79. State the advantages of dual slope ADC:
It provides excellent noise rejection of a signal whose periods are
integral multiples of the integration time T.
80.Define conversion time.
It is defined as the total time required to convert an analog signal into
its digital output. It depends on the conversion technique used & the
propagation delay of circuit components. The conversion time of a
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successive approximation type ADC is given by

T(n+1)
where T---clock period Tc---conversion time n----no.of bits
81. Define resolution of a data converter.
The resolution of a converter is the smallest change in voltage
which may be produced at the output or input of the converter.
Resolution (in volts) = VFS/2n-1=1 LSB increment
. The resolution of an ADC is defined as the smallest change in
analog input for a one bit change at the output.
82. Define accuracy of converter.
Absolute accuracy:
It is the maximum deviation between the actual converter output &
the ideal converter output.
Relative accuracy:
It is the maximum deviation after gain & offset errors have been
removed. The accuracy of a converter is also specified in form of LSB
increments or % of full-scale voltage.
83. What is settling time?
It represents the time it takes for the output to settle within a
specified bandLSB of its final value following a code change at the
input (usually a full scale change). It depends upon the switching time
of the logic circuitry due to internal parasitic capacitance &
inductances. Settling time ranges from 100ns. 10 Depending on word
length & type circuit used.
84. Explain in brief stability of a converter:
The performance of converter changes with temperature age &
power supply variation. So all the relevant parameters such as offset,
gain, linearity error & monotonicity must be specified over the full
temperature & power supply ranges to have better stability
performances.
85. What is meant by linearity?
The linearity of an ADC/DAC is an important measure of its
accuracy & tells us how close the converter output is to its ideal transfer
characteristics. The linearity error is usually expressed as a fraction of LSB
increment or percentage of full-scale voltage. A good converter exhibits a
linearity error of less thanLSB.
86. What is monotonic DAC?
A monotonic DAC is one whose analog output increases for an
increase in digital input.
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87.What is multiplying DAC?

A digital to analog converter which uses a varying reference
voltage VR is called a multiplying DAC (MDAC). If the reference
voltage of a DAC, VR is a sine wave give by V(t)=Vin Cos 2f t
Then, Vo(t)=Vo m Cos(2 ft + 180)
88. What is a sample and hold circuit? Where it is used?
A sample and hold circuit is one which samples an input signal and
holds onto its last sampled value until the input is sampled again. This circuit
is mainly used in digital interfacing, analog to digital systems, and pulse code
modulation systems.
89. Define sample period and hold period.
The time during which the voltage across the capacitor in sample and
hold circuit is equal to the input voltage is called sample period. The time
period during which the voltage across the capacitor is held constant is called
hold period.
90. What is meant by delta modulation?
Delta modulation is a technique capable of performing analog signal
quantization with smaller bandwidth requirements. Here, the binary output
representing the most recent sampled amplitude will be determined on the
basis of previous sampled amplitude levels.
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91. Draw the Pin digram of IC 555.
92. Mention some applications of 555 timer.
Oscillator
pulse generator
ramp and square wave generator
mono-shot multivibrator
burglar alarm
Traffic light control.
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93. List the applications of 555 timer in monostable mode of

operation:
Missing pulse detector
Linear ramp generator

Frequency divider
Pulse width modulation.
94. List the applications of 555 timer in Astable mode of operation:

a.
FSK generator
b.
Pulse-position modulator
95. List the applications of 555 timer in monostable mode of

operation:
Missing pulse detector
Linear ramp generator
Frequency divider
Pulse width modulation.

96. List the applications of 555 timer in astable mode of operation:
FSK generator
Pulse-position modulator
97. What is a voltage regulator?

A voltage regulator is an electronic circuit that provides a stable DC
voltage independent of the load current, temperature, and ac line voltage
variations.
98. Give the classification of voltage regulators:
Series / Linear regulators
Switching regulators.
99. What is opto coupler

An opto-isolator, also called an optocoupler, photocoupler, or
optical isolator, is "an electronic device designed to transfer electrical
signals by utilizing light waves to provide coupling with electrical
isolation between its input and output. The main purpose of an optoisolator is "to prevent voltages or rapidly changing voltages on one side of
the circuit from damaging components or distorting transmissions on the
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other side.
100.What is a linear voltage regulator?
Series or linear regulator uses a power transistor connected in
series between the unregulated dc input and the load and it conducts in
the linear region .The output voltage is controlled by the continuous
voltage drop taking place across the series pass transistor.
101.What is a switching regulator?
Switching regulators are those which operate the power transistor as
a high frequency on/off switch, so that the power transistor does not
conduct current continuously. This gives improved efficiency over series
regulators.
102. What are the advantages of IC voltage regulators?
Low cost
High reliability
Reduction in size
Excellent performance
103.Give some examples of monolithic IC voltage regulators:

78XX series fixed output, positive voltage regulators
79XX series fixed output, negative voltage regulators
723 general purpose regulator.
104.
What is the purpose of having input and output
capacitors in three terminal IC regulators?
A capacitor connected between the input terminal and ground
cancels the inductive effects due to long distribution leads. The output
capacitor improves the transient response.
105. Define line regulation.
Line regulation is defined as the percentage change in the output
voltage for a change in the input voltage. It is expressed in milli volts or as
a percentage of the output voltage.
106.Define load regulation.
Load regulation is defined as the change in output voltage for
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change in load current. It is expressed in millivolts or as a percentage of

the output voltage.
107.What is meant by current limiting?
Current limiting refers to the ability of a regulator to prevent the
load currentfrom increasing above a preset value.
108.Give the drawbacks of linear regulators:
The input step down transformer is bulky and expensive

because of low line frequency.
Because of low line frequency, large values of filter capacitors are

required to decrease the ripple.
Efficiency is reduced due to the continuous power dissipation

by the transistor as it operates in the linear region.
109.What is the advantage of switching regulators?
Greater efficiency is achieved as the power transistor is made to operate as low
impedance switch. Power transmitted across the transistor is in discrete pulses rather than
as a steady current flow. By using suitable switching loss reduction technique, the
switching frequency can be increased so as to reduce the size and weight of the inductors
and capacitors.
110.What is an opto-coupler IC? Give examples.
Opto-coupler IC is a combined package of a photo-emitting device and aphotosensing device. Examples for opto-coupler circuit: LED and a photo diode, LED and photo
transistor, LED and Darlington.
Examples for opto-coupler IC: MCT 2F , MCT 2E .
111.Mention the advantages of opto-couplers:
Better isolation between the two stages.
Impedance problem between the stages is eliminated.

Wide frequency response.
Easily interfaced with digital circuit.
Compact and light weight.
Problems such as noise, transients, contact bounce, are eliminated.
112. What is an isolation amplifier?

An isolation amplifier is an amplifier that offers electrical isolation between its
input and output terminals.
113. What is the need for a tuned amplifier?
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In radio or TV receivers, it is necessary to select a particular channel among all

other available channels. Hence some sort of frequency selective circuit is needed that will
allow us to amplify the frequency band required and reject all the other unwanted signals
and this function is provided by a tuned amplifier.
114.Give the classification of tuned amplifier:
+
Small signal tuned amplifier

Single tuned
Double tuned
Stagger tuned
Large signal tuned amplifier.
115 .What happens when the common terminal of V+ and V- sources is

not grounded?
If the common point of the two supplies is not grounded, twice the
supply voltage will get applied and it may damage the op-amp.
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Data
Sheets
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III year I sem ECE

ICA lab Master manual 2014-15

Fig 1. The breadboard. The lines indicate connected holes.

III year I sem ECE

ICA lab Master manual 2014-15

BUILDING THE CIRCUIT

III year I sem ECE

ICA lab Master manual 2014-15

III year I sem ECE

ICA lab Master manual 2014-15

Functional block diagram

III year I sem ECE

ICA lab Master manual 2014-15

Why silicon is chose as basic material and not Germanium?

III year I sem ECE

ICA lab Master manual 2014-15

1.2 Advantages of integrated circuits

III year I sem ECE

ICA lab Master manual 2014-15

Fig: 1.1 SSI chip

Fig: 1.2 MSI chip

Fig: 1.3 VLSI chip

III year I sem ECE

ICA lab Master manual 2014-15

1.4 IC Package Types

Metal Can package:

Fig 1.4 Metal Can

Dual In Line (DIP):

Fig: 1.5 Dual in line package

Fig: 1.6 Flat pack

III year I sem ECE

ICA lab Master manual 2014-15

III year I sem ECE

ICA lab Master manual 2014-15

Table:1.2 Different package types with their abbreviations:

1.5 Basic Information of Op Amp:

Fig:1.7 symbol of an Op Amp

III year I sem ECE

ICA lab Master manual 2014-15

The input and output are in anti phase:-

Fig: 1.8 input applied to inverting terminal

Fig:1.9 input applied to non inverting terminal

III year I sem ECE

ICA lab Master manual 2014-15

III year I sem ECE

ICA lab Master manual 2014-15

are as shown below:

Ideal Characteristics of an op-amp:

Op amp is a differential amplifier.

Infinite voltage range available at the output (vout).

Infinite bandwidth (i.e., the frequency magnitude response is considered to be flat

Infinite input impedance (

, and zero current flows from

the output is a virtual ground or vout = 0).

III year I sem ECE

ICA lab Master manual 2014-15

Infinite Common-mode rejection ratio (CMRR).

Fig: 1.10 a. An equivalent circuit of an operational amplifier

Fig: 1.10 b. Ideal op amp

III year I sem ECE

ICA lab Master manual 2014-15

Fig: 1.10 c. Open loop circuit