DNSK1

DNSK2

DNSK3

DNSK4

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DNSK6
VLSI subject
can anyone help me out to answer this question
extract the thickness of each layer and spacing between each layer from the substrate's surface
for poly1, poly2, and all metal layers. (the "stackup"). Use the C5N process measurements text
file includes sufficient measurements to extract this information. Hand in a drawing showing the
dimensions (thickness, distance to substrate, layer separation).

This is C5N.text File

* File .included automatically each time Electric writes a spice netlist

* Includes default power supplies and current transistor models
* Default this technology to 5 V supply
*VVdd Vdd 0 5
*VGnd gnd 0 0
* Latest transistor models
* DATE: Oct 17/13
* LOT: v37p
WAF:
* Temperature_parameters=Default
.MODEL N NMOS (
+VERSION = 3.1
TNOM
+XJ
= 1.5E-7
NCH
+K1
= 0.9137986
K2
+K3B
= -9.7485086
W0
+DVT0W
= 0
DVT1W
+DVT0
= 0.8309419
DVT1
+U0
= 460.0124125
UA
+UC
= 3.089014E-12
VSAT
+AGS
= 0.1204319
B0
+KETA
= -2.797385E-3
A1
+RDSW
= 1.115544E3
PRWG
+WR
= 1
WINT
+XL
= 1E-7
XW
+DWB
= 1.914595E-8
VOFF
+CIT
= 0
CDSC
+CDSCB
= 0
ETA0
+DSUB
= 0.0833302
PCLM
+PDIBLC2 = 1.863456E-3
PDIBLCB
+PSCBE1 = 3.853855E8
PSCBE2
+DELTA
= 0.01
RSH
+PRT
= 0
UTE
+KT1L
= 0
KT2
+UB1
= -7.61E-18
UC1
+WL
= 0
WLN
+WWN
= 1
WWL
+LLN
= 1
LW
+LWL
= 0
CAPMOD
+CGDO
= 1.91E-10
CGSO
+CJ
= 4.131634E-4
PB
+CJSW
= 3.400072E-10
PBSW
+CJSWG
= 1.64E-10
PBSWG
+CF
= 0
PVTH0
+PK2
= -0.0768747
WKETA
*
.MODEL P PMOS (
+VERSION = 3.1
TNOM
+XJ
= 1.5E-7
NCH
+K1
= 0.553472
K2
+K3B
= 0.5506188
W0
+DVT0W
= 0
DVT1W
+DVT0
= 0.4716221
DVT1
+U0
= 201.3603195
UA
+UC
= -1E-10
VSAT

1003
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=

LEVEL
= 8
27
TOX
1.7E17
VTH0
-0.1071877
K3
2.658488E-8
NLX
0
DVT2W
0.3317542
DVT2
2.759471E-13
UB
1.840576E5
A0
1.941274E-6
B1
2.420581E-5
A2
0.0828351
PRWB
2.526685E-7
LINT
0
DWG
-6.986376E-5
NFACTOR
2.4E-4
CDSCD
2.045973E-3
ETAB
2.3615569
PDIBLC1
0.0644698
DROUT
4.115782E-6
PVAG
82.4
MOBMOD
-1.5
KT1
0.022
UA1
-5.6E-11
AT
1
WW
0
LL
0
LWN
2
XPART
1.91E-10
CGBO
0.8399766
MJ
0.809471
MJSW
0.8
MJSWG
-0.028514
PRDSW
-0.0138828
LKETA

=
=
=
=
=
=
=
=

27
1.7E17
7.871921E-3
1E-8
0
0.1854949
2.48572E-9
1.578444E5

=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=

1.41E-8
0.6176544
22.288867
1E-9
0
-0.5
1.603084E-18
0.5615191
5E-6
0.3164714
0.0311852
7.469087E-8
-1.032244E-8
0.8533219
0
-3.21453E-4
9.500103E-5
1.39184E-3
0
1
-0.11
4.31E-9
3.3E4
0
0
1
0.5
1E-9
0.4305505
0.1977865
0.2019414
114.6437024
1.62687E-3

LEVEL
= 8
TOX
= 1.41E-8
VTH0
= -0.9152268
K3
= 8.5645893
NLX
= 1.006451E-9
DVT2W
= 0
DVT2
= -0.3
UB
= 1.005454E-21
A0
= 0.8192884

+AGS
+KETA
+RDSW
+WR
+XL
+DWB
+CIT

=
=
=
=
=
=
=

0.1111278
-4.865785E-3
3E3
1.01
1E-7
-1.38669E-8
0

B0
A1
PRWG
WINT
XW
VOFF
CDSC

=
=
=
=
=
=
=

5.743519E-7
5.800723E-4
-0.0219603
2.247043E-7
0
-0.0295318
2.4E-4

B1
A2
PRWB
LINT
DWG
NFACTOR
CDSCD

=
=
=
=
=
=
=

6.088988E-8
0.3229711
-0.0910566
9.979797E-8
2.080226E-9
0.5872216
0

DNSK7
Please design the following gate level circuit by only using the following gates: and, or, not.
A 16-bit 2s compliment ALU that supports addition, subtraction, logical and, logical or, logical
not on left input, pass left, and pass right. Please be specific and complete in explaining the
circuit and how you designed it.
DNSK8
Consider an AC motor with an inductive input operating from a 208V single phase
60 Hz powerline(the voltage on the load terminal). The real power delivered by the
motor (including efficiency losses) is 350W. The input power factor is 0.6 lagging
(inductive), and there is no distortion of the input current waveform (linear load).
The equivalent circuit of the input to the motor, as seen by the powerline, is shown
in Figure. Assume the cable resistance (connection between the source and the
load) is 1 .
DNSK9