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D E S I G N S T R AT E G I E S A N D M E T H O D O L O G I E S

Real-Time Embedded Multithreading:


Using ARM Cores and the ThreadX RTOS

Author:
I ntroduction
Multithreading is a common approach to
add complexity and difficulty. Thus, sim-
plicity is an asset, or feature, of the RTOS.
By Dr. Ed Lamie, Express Logic the software design of a real-time embed- In particular, the ThreadX RTOS is simple
ded application. In multithreading, sever- and easy to use because of its following
Synopsis: characteristics:
al program segments (threads) share
This article contains a discussion of
access to the CPU based on priority or 1. Simple API. The Application
embedded multithreading used in
event-association. This enables real-world Programming Interface (API) should
the ARM® processor family, and
events to dictate the actual flow of opera- be intuitive, readable, and consistent,
Express Logic’s popular ThreadX®
real-time operating system (RTOS). tions performed by the system, and to and there should be a manageably
avoid system idle time by letting other small number of services that are easy
The ARM architecture is arguably threads execute while one thread waits for to find when needed.
today’s most popular embedded an external event. 2. Full Source Code. This is important
platform. Because of its inherent Programs Time >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
simplicity, it can be found in a wide
Thread-1
variety of devices — from cell phones
to laser printers. Express Logic's Thread-2
ThreadX RTOS is also simple and Thread-3
addresses the same target markets
Idle Thread
as the ARM processor family. ThreadX
is one of the most popular RTOSs Scheduler
for the ARM processor, thus this article ISR
has relevance for many embedded
Event-1
developers, both those familiar with
ThreadX and ARM, and those who Event-2
have an interest in learning more Timeline >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
about them.
Idle
Running
Event

Diagram 1

A commercial RTOS is often used to man- not so every user can modify the RTOS
age the execution of a multithreaded real- for special needs, but so a developer
time system. The RTOS is software that can look at exactly what the RTOS is
performs thread scheduling, interrupt doing at any point, and thereby use
servicing, message passing, and other the RTOS most effectively.
services for the application threads. If a 3. Good Documentation. This is often
commercial RTOS is not used, something an overlooked feature, but good doc-
functionally similar might have to be cre- umentation can be a project lifesaver.
ated by the developer. This article will A well organized and clearly written
focus on the use of a commercial RTOS, User Guide with relevant examples,
which is rapidly becoming the approach make a developer’s job easier.
of choice in embedded development. 4. Less Is More. An application that has
less RTOS code is easier to debug and
Simplicity is a Feature to understand. The more complex a
When approaching the design of a real- RTOS is, the more difficult it is to learn
time system, focus should be given to the and use. A small footprint RTOS not
application. The RTOS, if any, is there to only saves memory, but also probably
make the application’s job easier, not to executes faster.

Information Quarterly [48] Volume 3, Number 2, 2004


D E S I G N S T R AT E G I E S A N D M E T H O D O L O G I E S

ThreadX has a reputation for simplicity in make up a complete system. Threads are at the beginning of an Interrupt Service
its user programming interface, making it executed in response to real world events Routine (ISR) is called the Interrupt Latency.
an ideal reference for a discussion of mul- (interrupts) or are scheduled to execute at Interrupt service routines can mark
tithreading. To illustrate the simplicity of certain intervals, such as every N millisec- threads as ready to run, triggering a con-
ThreadX service calls, consider the exam- onds. ThreadX provides services that text switch if those threads are of higher
ple in Figure 1, which sends a message to enable threads to schedule themselves, priority than the thread that was inter-
a message queue. communicate with other threads, allocate rupted. The ARM architecture provides a
memory, and easily perform other com- facility for efficient interrupt processing
mon operations. Threads contain several called FIQ mode. ThreadX enables zero-
tx_queue_send (&my_queue,
attributes that may be used to control latency processing of FIQ interrupts.
my_message,
their execution or characteristics. Figure 3
TX_NO_WAIT);
shows some thread attributes. Context Switch
Figure 1: Send a Message When one thread is executing and an
Control Block interrupt occurs, triggering the execution
In this example, the message called of a higher priority thread, the previously
Stack
my_message is sent to the rear of the mes- executing thread is interrupted, its context
sage queue called my_queue. The Priority Entry Function saved, and the processor is directed to start
TX_NO_WAIT option means that if the mes- or resume execution of the instructions of
sage queue is full, the thread will not wait
Preemption Threshold the new thread. This context switch must
or suspend, and the thread will not send a Time Slice be performed quickly, because real-time
message to the queue. All ThreadX service systems can require many context switch-
calls follow this pattern of simplicity and Figure 3: Some Thread Attributes es in a short period of time. On the front
readability. end of interrupt service routines, only the
For example, a thread may adjust its compiler’s scratch registers are saved ini-
RTOS Building Blocks “Priority” to enable it to “catch up” on tially. If it turns out that thread preemp-
for System Development processing if it detects that it is falling tion is required, then the remaining regis-
The basic building blocks of an embedded behind. Similarly, a thread can adjust its ters in the set are also saved. ThreadX opti-
application, used by the developer in var- “Preemption Threshold” (a feature unique mizes context switching on the ARM
ious ways to manage application code, to ThreadX) to prevent preemption by cer- processor. Only those registers preserved
are threads, mutexes, memory pools, tain threads, which in turn helps prevent across function calls are saved (registers
counting semaphores, event flags groups, problems such as priority inversion. v1-v4, fp, and lr). As a result, ThreadX per-
message queues, and application timers. forms context switch on the ARM proces-
Figure 2 contains a complete list of these Thread Execution sor in only about 100 cycles, which is one
building blocks, as provided by the If the developer wishes to have a certain microsecond on a 100MHz processor.
ThreadX RTOS. Using these building thread executed at a particular time, or
blocks, the developer can structure a real- upon occurrence of some external event, Thread Communication
time application quickly, and avoid much he or she must somehow connect that with Message Queues
of the programming effort often required thread to an interrupt that corresponds to Often, it is necessary for one thread to
to create and manage an embedded sys- that particular time. The developer might exchange information with another
tem. designate one thread to be executed to thread. Message queues provide the pri-
process data when it arrives via Ethernet, mary means of inter-thread communica-
The Thread – The Essential as indicated by an interrupt from the tion.
Component Ethernet controller, for example. Another rear front
A thread is a semi-independent program thread might need to execute every 20
segment that performs some function milliseconds, as indicated by an interrupt msg_n || • • • || msg_3 || msg_2 || msg_1
required by the application. Typically, upon the expiration of a timer. The RTOS
there are multiple threads that combine to makes it easy to assure that the appropri-
Figure 4: A Message Queue
ate thread is executed upon the occur-
Threads Message Counting rence of a particular event. ThreadX pro-
Queues Semaphores vides interrupt services and optimized Threads can send or receive messages
application timers for this purpose. to/from a message queue, which can store
Mutexes Event Flags Memory a number of messages (a queue that can
Block Pools Interrupt Servicing store only a single message is commonly
Interrupts are important elements of a called a “mailbox”). Figure 4 contains an
Memory System real-time system. Efficient processing of illustration of a message queue. Threads
Byte Clock and Interrupt interrupts enables the system to keep up can suspend themselves while attempting
with more demanding applications where to send or receive a message from a queue.
Pools Application Control
interrupts occur with great frequency. The Typically, thread suspension involves
Timers
time it takes for a system to respond to an waiting for a message from an empty
Figure 2: Building Blocks
interrupt and begin executing instructions queue, or waiting for room in a full queue.

Information Quarterly [49] Volume 3, Number 2, 2004


D E S I G N S T R AT E G I E S A N D M E T H O D O L O G I E S

Each message queue can contain a num- order to protect its critical section, a thread
ber of fixed-size messages, each limited to first “gets” a mutex (tx_mutex_get),enters fixed-size block
16 words in length. Messages larger than its critical section, and then gives up the fixed-size block
16 words can be sent using pointers. mutex upon completion of the section.
Only one thread can own a mutex, thus fixed-size block
Mutual Exclusion Challenges providing the necessary protection. :
and Considerations :
Since any thread can be interrupted at Memory Allocation: fixed-size block
any time, and a different thread might be Byte Pools and Block Pools
Figure 5: Memory Block Pool
allowed to execute, the developer must not Throughout the execution of an embed-
assume that a processing sequence will ded real-time application, it is often neces- Application Timers
run to completion. For example, decre- sary for the application to require more Application timers are maintained by
menting a counter, or adding an element memory than it was allocated upon its ThreadX to provide “count-down” services
to a queue. Code sequences that must be start. This is to avoid wasting memory, to provide a variety of time-related duties.
executed in their entirety in order to pre- and to allow real-world events to dictate Timers can be set up to operate once (an
vent the possibility of corruption from a where memory resources should be allo- one-shot timer), or for recurring operation
new thread are called “Critical Sections.” cated. When a thread encounters the need (a periodic timer). When a timer expires, it
This is analogous to a “Test and Set” atom- for more memory, it asks the RTOS, which generates an interrupt and a timer func-
ic instruction found in most processors. manages available memory, to allocate tion (similar to an Interrupt Service
Real-time systems almost always require a some for use by the thread. ThreadX pro- Routine or “ISR”) is executed. The timer
way to deal with issues such as protecting vides two methods of memory allocation function can affect the processing or even
a critical section, or else the wrong and management: the Byte Pool and the the scheduling of application threads,
sequence of events could destroy the valid- Block Pool. Byte Pools contain memory depending on which threads have been set
ity of application data. ThreadX contains that can be allocated to threads in sizes of up to execute when this timer expires.
an object that handles this issue, the any number of bytes, similar to malloc().
“mutual exclusion” semaphore, or mutex. Block Pools enable allocation of memory Conclusion
A mutex is the only ThreadX object that in fixed-size blocks, user-defined. There ThreadX is an easy-to-use RTOS, and is
can be owned by a thread. It is also the can be multiple byte pools and/or block well suited to applications using the ARM
only object with a priority inheritance fea- pools each one with a different size. In this architecture. The RTOS services are power-
ture. These properties make the mutex an way, thread demands for various sizes of ful, concise, easy to learn and use, and
ideal object with which to provide mutual memory regions can be managed most are optimized for the ARM environ-
exclusion protection for critical sections. In efficiently. ment.

Everything you need for designing advanced digital products



The most commonly
used embedded
processor core will be
the ARM architecture,
which, product October 19-21, 2004
Santa Clara Convention Center
shipment wise, will
account for almost Call for papers
Don’t miss your chance to be an integral part of this inaugural event!
two out of every three
For proposal submission and registration go to www.arm.com/developersconference
dollars. For sponsorship opportunities go to www.convergencepromotions.com


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Information Quarterly [50] Volume 3, Number 2, 2004

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