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What is CAP7?
JTAG
Main
OSC
PLL
PMC
WDT
AIC
PIT
32K OSC
RTT
RC OSC
POR
ICE
PLL
EBI
ARM7TDMI
MPLIB
250K/450K ASIC gates
SHWDC GPBREG
Static Mem.
CF
NAND Flash
SDRAM
SRAM SRAM
96KB 64KB
POR
AMBA Bridge
Peripheral DMA
Controller
APB
USB
FS
Device
SPI
PIO
x64
Timer
x3
Confidential
CAP7 Features
Processor:
Memory:
Peripherals:
Debug Unit
Confidential
Confidential
Design Requirements
Low Cost ARM7TDMI CPU
Fast on chip memory for execution of GUI OS / Application code
Display Support:
Passive LCDs
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ARM7 CPU
Application Code
And Data
Display Frame
Buffer
LCD Controller
640x480 =
1,228,800 Bytes
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ARM7 CPU
And Data
External Memory
Frame Buffer
LCD Controller
640x480 =
1,228,800 Bytes
Confidential
ARM7TDMI
PIXEL Formatter
Color Pallete
(DualPort)
LineBuffer
(DualPort)
AHB MASTER 2
AHB MASTER 1
EBI
Control
Registers
External
RAM
Static Mem.
SRAM
(64KB)
SDRAM
Frame Buffer
APB
ROM
(256KB)
Peripheral DMA
Controller
SRAM
(96KB)
USB
FS
Device
SPI
PIO
x64
Timer
x3
Confidential
Components:
routing is fixed
Hard Macro
Timing is fixed,
STA on internal
paths not needed
ARM7
HMATRIX
System
RAM/ROM
PDC
AHB/APB Bridge
EBI
APB Peripherals
ASCs
DPRs
Confidential
Delivered a pre-
Battery Backup
synthesized gates
JTAG logic
Design Centers
will need to place,
route, and extract
timing
MP Macro
Interface
DPR BIST
Gives freedom to
customize* (within
restrictions)
In most cases,
customer can
used as delivered
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Components:
Custom MP
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Components:
be used directly by
the customer
Atmel IP
Delivered as
protected RTL,
gates*
Design centers
will need to assist
customers for
integration
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Components:
fixed
Digital I/O
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MP Block
4x4 AHB
Slaves
4 AHB
Masters
15 APB
Slaves
...
MP Interface Scan W rapper
...
ChipID
USB
PHY
Ext ChipID
BIST
Clock (42)
DPR
2kx16
BIST
MPBlock Custom
AREA
DPR
2kx16
ITs (19)
13 PDC
channels
Resets (4)
450K Gates
90 MPIO I/OS
MPIOs
(90)
MPBlock scan chain wrapper for Chip and MPBlock scan test
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10~12
WEEKS
Prototype Fabrication
Production Volume
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Custom
IP Blocks
FPGA
Emulation Platform
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PostLayout
Sims *
01001110
01110010
10101111
00101011
11000...
H/W
Flow
Verilog/VHDL
MP Logic RTL
Bitstream
.mpm
.edf
Synthesis
Netlist
P&R
JT AG ICE
He ad er
Header
JT AG
He ade r
Xilinx Virtex 4
LX60
Header
LED's
Produ ct #
C/C++
Source
.Hex
Header
S/W
Flow
Xi l in x
Pl atform Fla sh
Header
SRAM
CAP7L
em u la ti o n
pe rsona li ty
Rev. A
ICE
Compile/Link/Debug
Download/ICE
* Simulators Supported
NC Verilog/ Modelsim
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USB
UART 0
UART 1
Ethe rn et
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Modelsim
Atmel Provides:
ARM7TDMI Solaris/Linux compatible model
Encrypted Verilog model of CAP7 platform logic
Scripts to support simulation environment (e.g.
makefiles, Perl, etc.)
Verilog testbench
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Modelsim
Atmel Provides:
ARM7TDMI Solaris/Linux compatible model
FPGA netlist for CAP7 Platform Logic
Scripts to support simulation environment (e.g.
makefiles, Perl, etc.)
Verilog testbench (same as for RTL simulations)
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Vendors :
ARM ADS
GNU GCC + Eclipse
IAR Embedded Workbench
Green Hills Multi IDE
Keil RealView MDK
Rowley CrossWorks
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