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International Journal of Science and Applied Information Technology (IJSAIT), Vol.5 , No.1, Pages : 14-19 (2016)
Special Issue of ICECT 2016 - Held on February 27, 2016 in Hyderabad Marriot Hotel & Convention Centre, Hyderabad
http://warse.org/IJSAIT/static/pdf/Issue/icect2016sp04.pdf
1.1 Router
INTRODUCTION
ISSN 2278-3083
International Journal of Science and Applied Information Technology (IJSAIT), Vol.5 , No.1, Pages : 14-19 (2016)
Special Issue of ICECT 2016 - Held on February 27, 2016 in Hyderabad Marriot Hotel & Convention Centre, Hyderabad
http://warse.org/IJSAIT/static/pdf/Issue/icect2016sp04.pdf
The communication on network on chip is
carried out by means of router, so for implementing
better NOC, the router should be efficiently design.
This router supports four parallel connections at the
same time. It uses store and forward type of flow
control and Fsm Controller deterministic routing which
improves the performance of router. The switching
mechanism used here is packet switching which is
generally used on network on chip.
A router is a device that forwards data packets across
computer networks. Routers perform the data "traffic
direction" functions on the Internet. A router is a
microprocessor-controlled device that is connected to
two or more data lines from different networks. When a
data packet comes in on one of the lines. the router
reads the address information in the packet to determine
its ultimate destination. Then, using information in its
routing table, it directs the packet to the next network
on its journey
2.
15
ISSN 2278-3083
International Journal of Science and Applied Information Technology (IJSAIT), Vol.5 , No.1, Pages : 14-19 (2016)
Special Issue of ICECT 2016 - Held on February 27, 2016 in Hyderabad Marriot Hotel & Convention Centre, Hyderabad
http://warse.org/IJSAIT/static/pdf/Issue/icect2016sp04.pdf
OVM Factory
The factory method is a classic software
design pattern that is used to create generic code,
deferring to run time the exact specification of the
object that will be created. In functional verification,
introducing class variations is frequently needed. For
example, in many tests you might want to derive from
the generic data item definition and add more
constraints or fields to it; or you might want to use the
new derived class in the entire environment or only in a
single interface; or perhaps you must modify the way
data is sent to the DUT by deriving a new driver. The
factory allows you to substitute the verification
component without having to provide a derived version
of the parent component as well.
ISSN 2278-3083
International Journal of Science and Applied Information Technology (IJSAIT), Vol.5 , No.1, Pages : 14-19 (2016)
Special Issue of ICECT 2016 - Held on February 27, 2016 in Hyderabad Marriot Hotel & Convention Centre, Hyderabad
http://warse.org/IJSAIT/static/pdf/Issue/icect2016sp04.pdf
output ports based on the address contained in the
packet.The router has a one input port from which the
packet enters. It has three output ports where the packet
is driven out. The router has an active low synchronous
input reset which resets the router.
Packet Format
Packet contains 7 parts. They are Header, payload
and parity.
Packet width is 8 bits and the length of the packet can
be between 1 bytes to 67 bytes.
17
ISSN 2278-3083
International Journal of Science and Applied Information Technology (IJSAIT), Vol.5 , No.1, Pages : 14-19 (2016)
Special Issue of ICECT 2016 - Held on February 27, 2016 in Hyderabad Marriot Hotel & Convention Centre, Hyderabad
http://warse.org/IJSAIT/static/pdf/Issue/icect2016sp04.pdf
ii.
iii.
iv.
Read operation
Read and
Write Operation
SIMULATION RESULTS
The below figures shows the simulation results
of test cases applied to the DUT. Figure 4.3 shows the
response of the device for the control test case at the
usb interface. Figure 4.2 shows the master transmitter
sending random data to the external slave device.
ISSN 2278-3083
International Journal of Science and Applied Information Technology (IJSAIT), Vol.5 , No.1, Pages : 14-19 (2016)
Special Issue of ICECT 2016 - Held on February 27, 2016 in Hyderabad Marriot Hotel & Convention Centre, Hyderabad
http://warse.org/IJSAIT/static/pdf/Issue/icect2016sp04.pdf
coverage of Router. In this project used one master and
eight slaves to monitor the Router. Thus the functional
coverage of Router was improved.
The results shows that System Verilog
methodology can be used to make reusable test benches
successfully. Large part of the test bench is made
reusable over multiple projects.even though
this
reusablity is limited to the interfaces. A large class of
devices that are build on these inerfaces can be verified
successfully. Once these components are made the
amount of time required to build test benches for other
projects can be reduced a lot.
REFERENCES
[1] Verilog HDL- Digital Design and Synthesis, by
Samir Palnitkar.
[2] M. K. Papamichael, J. C. Hoe, and O. Mutlu, FIST:
A Fast, Lightweight, FPGA-Friendly Packet Latency
Estimator for NoC Modeling in Full-System
Simulations, NOCS, 2011.
[3] Xilinx, LogiCORE IP Processor Local
Bus(PLB)v4.6,http://www.xilinx.com/support/docume
ntation/i pdocumentation/plb v46.pdf .
[4] P. Wolkotte, P. Holzenspies, and G. Smit, Fast,
Accurate and Detailed NoC Simulations, NOCS, 2007.
[5] System Verilog Manuals by Mentor.
[6] LRM, IEEE Standard Hardware Description
Language Based on the Verilog Hardware Description
Language IEEE STD 1364-1995.
[7]
Chris
Spears
SYSTEMVERILOG
FOR
VERIFICATION, Publisher: Springer
[8] Cisco Router OSPF: Design& Implementation
Guide, Publisher: McGraw-Hill