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Xcell Journal
Summer 2004
Bypass Capacitor
Power Planes
Active Device
Test Point 1
PCB
Test Point 2
ESR
ESL
You cannot assume electrical symmetry, however, so Z11 and Z22 are, in general, different. You can calculate the noise
voltages at test points 1 and 2 generated
by the noise currents of I1(t) and I2(t) of
the two active devices with the following
formula:
V 1(t) = Z 11I 1(t) + Z MI 2(t)
V 2(t) = Z MI 1(t) + Z 22I 2(t)
Although in a general case all three elements in the equivalent circuit are frequency-dependent [3], for the sake of simplicity,
and because it would not change the conclusions of this article, well use frequencyindependent constant parameters.
Figure 3 shows the impedance magnitudes of three different capacitors you
1.E-01
100 uF
1 uF
0.1 uF
0.1 Ohm
0.02 Ohm
0.05 Ohm
10 nH
3 nH
0.8 nH
Q = 0.1
Q = 2.7
Q = 1.8
1.E-02
1.E-02
1.E-01
1.E+00
1.E+01
1.E+02
Frequency [MHz]
00
1.E+00
Max: 0.22
Typ: 0.11
Min: 0.079
1.E-01
1.E-02
1.E-02
1.E-01
1.E+00
1.E+01
Frequency [MHz]
Figure 4 Typical, highest, and lowest impedance curves of the three parallel
connected capacitors shown in Figure 3
1.E+02
Xcell Journal
Summer 2004
Self-impedance
at
0.5
MHz
on
a
2
x
2
impedance magnitude doubles. At
plane
pair
with
50
mils
dielectric
separation,
with
a
100
uF,
Packaging 22(3): 284-290.
the corners of the 2 x 2 plane pair,
0.001 Ohm, 1 nH capacitor located in the middle
the impedance magnitude is almost
[3] Novak, I., and J. R. Miller. FrequencyDependent Characterization of Bulk and
10 milliohms.
Self-Impedance
Magnitude
[Ohm]
Ceramic Bypass Capacitors in Proceedings of
When changing either the plane
EPEP, October 2003, Princeton, NJ.
impedance or the ESR of capacitor
so that their values are closer, the
[4] Brooks, Douglas. 2003. Signal Integrity
Issues and Printed Circuit Board Design.
variation of impedance over the
Upper Saddle River: Prentice Hall.
plane shape gets smaller. Figure 6 1.E-02
shows the impedance surface of the
[5] Ritchey, Lee W. 2003. Right the First Time,
same plane shape and same capaciA Practical Handbook on High Speed PCB
tor in the middle, except we
and System Design, Volume 1. Glen Ellen:
Speeding Edge.
increased ESR from 1 to 7 milliohms and decreased the plane sep[6] Download Microsoft Excel spreadsheet
aration from 50 to 20 mils. Now
at http://home.att.net/~istvan.novak/tools/
the impedance surface at SRF varies
bypass49.xls
only about 10% over the plane area.
[7] Novak, I., L. Noujeim, V. St. Cyr, N.
For Figures 5 and 6, you can see
Biunno, A. Patel, G. Korony, and A. Ritter.
1.E-03
the same characteristic behavior if
2002. Distributed Matched Bypasssing for
you sweep the frequency over a wider
Board-Level Power Distribution Networks.
IEEE Transactions on Advanced Packaging
frequency range in the spreadsheet.
25(2):230-243.
The impedance surface of Figure 5
changes and fluctuates significantly,
[8] Download Microsoft Excel spreadsheet at
Figure 6 Self-impedance at 0.5 MHz on a 2 x 2
while the impedance surface of
http://home.att.net/~istvan.novak/tools/
plane pair with 20 mils dielectric separation, and a 100 uF,
0.007
Ohm,
1
nH
capacitor
located
in
the
middle
Caprange_rev10.xls
Figure 6 changes less with frequency.
Summer 2004
Xcell Journal
00