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GD32F103xx
ARM Cortex-M3 32-bit MCU
Datasheet
www.realsense.com.cn
GD32F103xx
Table of Contents
List of Figures ............................................................................................................................. 3
List of Tables ............................................................................................................................... 4
1
2.2
2.3
2.4
2.5
2.6
3.1
3.2
On-chip memory................................................................................................................................ 25
3.3
3.4
3.5
3.6
3.7
3.8
DMA .................................................................................................................................................... 28
3.9
3.10
3.11
3.12
3.13
3.14
3.15
3.16
3.17
3.18
3.19
3.20
3.21
4
4.1
4.2
4.3
4.4
4.5
4.6
Electrical sensitivity........................................................................................................................... 37
1 / 48
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GD32F103xx
4.7
4.8
4.9
4.10
4.11
GPIO characteristics......................................................................................................................... 39
4.12
4.13
4.14
4.15
5
5.1
5.2
Revision History............................................................................................................. 47
2 / 48
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GD32F103xx
List of Figures
Figure 1. GD32F103x4/6/8/B block diagram ........................................................................................................... 9
Figure 2. GD32F103xC/D/E/F/G/I/K block diagram.............................................................................................. 10
Figure 3. GD32F103Zx LQFP144 pinouts ............................................................................................................. 11
Figure 4. GD32F103Vx LQFP100 pinouts ............................................................................................................. 12
Figure 5. GD32F103Rx LQFP64 pinouts ............................................................................................................... 13
Figure 6. GD32F103Cx LQFP48 pinouts ............................................................................................................... 13
Figure 7. GD32F103Tx QFN36 pinouts ................................................................................................................. 14
Figure 8. GD32F103xx memory map ..................................................................................................................... 15
Figure 9. GD32F103xx clock tree............................................................................................................................ 16
Figure 10. QFN package outline.............................................................................................................................. 42
Figure 11. LQFP package outline ............................................................................................................................ 43
3 / 48
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GD32F103xx
List of Tables
Table 1. GD32F103xx devices features and peripheral list ................................................................................... 6
Table 2. GD32F103xx pin definitions ...................................................................................................................... 17
Table 3. Absolute maximum ratings ........................................................................................................................ 34
Table 4. DC operating conditions ............................................................................................................................ 34
Table 5. Power consumption characteristics ......................................................................................................... 35
Table 6. EMS characteristics ................................................................................................................................... 36
Table 7. EMI characteristics ..................................................................................................................................... 36
Table 8 Power supply supervisor characteristics .................................................................................................. 36
Table 9. ESD characteristics .................................................................................................................................... 37
Table 10. Static latch-up characteristics ................................................................................................................ 37
Table 11. High speed external clock (HSE) generated from a crystal/ceramic characteristics ...................... 37
Table 12. Low speed external clock (LSE) generated from a crystal/ceramic characteristics ....................... 38
Table 13. High speed internal clock (HSI) characteristics ................................................................................... 38
Table 14. Low speed internal clock (LSI) characteristics ..................................................................................... 38
Table 15. PLL characteristics ................................................................................................................................... 39
Table 16. Flash memory characteristics ................................................................................................................. 39
Table 17. I/O port characteristics ............................................................................................................................. 39
Table 18. ADC characteristics .................................................................................................................................. 40
Table 19. DAC characteristics ................................................................................................................................. 40
Table 20. I2C characteristics .................................................................................................................................... 40
Table 21. SPI characteristics .................................................................................................................................... 41
Table 22. QFN package dimensions ....................................................................................................................... 42
Table 23. LQFP package dimensions ..................................................................................................................... 44
Table 24. Part ordering code for GD32F103xx devices ....................................................................................... 45
Table 25. Revision history......................................................................................................................................... 47
4 / 48
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GD32F103xx
General description
Cortex-M3 RISC core with best ratio in terms of processing power, reduced power
consumption and peripheral set. The Cortex-M3 is a next generation processor core which
is tightly coupled with a Nested Vectored Interrupt Controller (NVIC), SysTick timer and
advanced debug support.
operating at 108 MHz frequency with Flash accesses zero wait states to obtain maximum
efficiency. It provides up to 3 MB on-chip Flash memory and up to 96 KB SRAM memory. An
extensive range of enhanced I/Os and peripherals connected to two APB buses. The
devices offer up to three 12-bit ADCs, up to two 12-bit DACs, up to ten general-purpose
16-bit timers, two basic timers plus two PWM advanced-control timer, as well as standard
2
and advanced communication interfaces: up to three SPIs, two I Cs, three USARTs, two
2
5 / 48
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GD32F103xx
Device overview
2.1
Device information
T8
TB
C4
C6
C8
CB
R4
R6
R8
RB
V8
VB
Flash (KB)
16
32
64
128
16
32
64
128
16
32
64
128
64
128
SRAM (KB)
10
20
20
10
20
20
10
20
20
20
20
GPTM
Advanced TM
SysTick
Watchdog
RTC
USART
I2C
SPI
CAN 2.0B
USB 2.0 FS
GPIO
26
26
26
26
37
37
37
37
51
51
51
51
80
80
EXMC
EXTI
16
16
16
16
16
16
16
16
16
16
16
16
16
16
Units
Channels
10
10
10
10
10
10
10
10
16
16
16
16
16
16
ADC
Connectivity
Timers
T4
Package
QFN36
LQFP48
LQFP64
LQFP100
6 / 48
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GD32F103xx
Table 1. GD32F103xx devices features and peripheral list (continued)
GD32F103xx
Part Number
RC
RD
RE
RF
RG
RI
RK
VC
VD
VE
VF
VG
VI
VK
SRAM (KB)
48
64
64
96
96
96
96
48
64
64
96
96
96
96
GPTM
10
10
10
10
10
10
10
10
Advanced TM
SysTick
Basic TM
Watchdog
RTC
U(S)ART
I2C
SPI
CAN 2.0B
USB 2.0 FS
I2S
SDIO
GPIO
51
51
51
51
51
51
51
80
80
80
80
80
80
80
EXMC
EXTI
16
16
16
16
16
16
16
16
16
16
16
16
16
16
Units
Channels
16
16
16
16
16
16
16
16
16
16
16
16
16
16
DAC
ADC
Connectivity
Timers
Flash (KB)
Package
LQFP64
LQFP100
7 / 48
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GD32F103xx
Table 1. GD32F103xx devices features and peripheral list (continued)
GD32F103xx
Part Number
ZD
ZE
ZF
ZG
ZI
ZK
Flash (KB)
256
384
512
768
1024
2048
3072
SRAM (KB)
48
64
64
96
96
96
96
GPTM
10
10
10
10
Advanced TM
SysTick
Basic TM
Watchdog
RTC
U(S)ART
I2C
SPI
CAN 2.0B
USB 2.0 FS
I2S
SDIO
GPIO
112
112
112
112
112
112
112
EXMC
EXTI
16
16
16
16
16
16
16
Units
Channels
21
21
21
21
21
21
21
ADC
Connectivity
Timers
ZC
DAC
Package
LQFP144
8 / 48
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GD32F103xx
2.2
Block diagram
Figure 1. GD32F103x4/6/8/B block diagram
TPIU
SW/JTAG
NVIC
ARM Cortex-M3
Processor
Fmax: 108MHz
Flash
Memory
Controller
Ibus
Flash
Memory
PLL
Fmax: 144MHz
Dbus
FMC Control
Registers
Master
Master
Slave
EXMC
Slave
Slave
LDO
1.2V
RST/CLK Control
Registers
AHB Peripherals
Slave
AHB Matrix
GP DMA
7chs
POR/PDR
SRAM
Controller
AHB to APB
Bridge 2
HSI
8MHz
SRAM
HSE
4-16MHz
AHB to APB
Bridge 1
LVD
Interrput request
CAN
USART1
Slave
12-bit
SAR ADC
Slave
WDG
ADC1
TM2
ADC2
TM3
GPIOA
TM4
GPIOB
GPIOC
GPIOD
SPI1
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Powered By V DDA
SPI2
USART2
USART3
GPIOE
I2C1
TM1
I2C2
EXTI
USB FS
9 / 48
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GD32F103xx
Figure 2. GD32F103xC/D/E/F/G/I/K block diagram
POR/PDR
TPIU
SW/JTAG
GP DMA 1
7chs
PLL
Ibus
Dbus
Flash Memory
Controller 1
Flash
Memory
Flash Memory
Controller 2
Flash
Memory
FMC Control
Registers
Master
AHB Matrix
NVIC
ARM Cortex-M3
Processor
Fmax: 108MHz
Fmax: 144MHz
LDO
1.2V
RST/CLK Control
Registers
HSI
8MHz
AHB Peripherals
Slave
EXMC
HSE
4-16MHz
Slave
Slave
SRAM
Controller
SRAM
SDIO
Master
LVD
Slave
GP DMA 2
5chs
Master
Slave
AHB to APB
Bridge 2
AHB to APB
Bridge 1
Powered By V DDA
Interrput request
CAN
USART1
Slave
SPI1
Slave
WDG
GP TM2
ADC1
12-bit
SAR ADC
GPIOB
GPIOC
GPIOA
GP TM4
APB2: Fmax = 108MHz
ADC3
Powered By V DDA
GP TM3
ADC2
GP TM5
GP TM12
GP TM13
GP TM14
GPIOD
SPI2/I2S2
GPIOE
SPI3/I2S3
GPIOF
USART2
GPIOG
USART3
ADV TM1
UART4
ADV TM8
UART5
GP TM9
I2C1
GP TM10
BSC TM6
I2C2
GP TM11
BSC TM7
USB 2.0 FS
DAC1
EXTI
DAC2
10 / 48
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GD32F103xx
2.3
PA14
PA15
PC10
PC11
PC12
PD0
PD1
PD2
PD3
PD4
PD5
VSS_10
VDD_10
PD6
PD7
PG9
PG10
PG11
PG12
PG13
PG14
VSS_11
VDD_11
PG15
PB4
PB3
PB5
PB6
PB7
BOOT0
PB8
PB9
PE0
PE1
VSS_3
VDD_3
PE2
PE3
PE4
107
VSS_2
NC
PE5
PE6
106
105
104
VBAT
103
PA12
PA11
PC13-TAMPER-RTC
PC14-OSC32_IN
102
PA10
PA9
PC15-OSC32_OUT
101
100
10
99
PC9
PF1
11
98
PC8
PF2
12
97
PC7
PF3
PF4
PF5
13
96
PC6
14
95
VDD_9
15
94
VSS_9
93
PG8
VDD_5
16
17
PF6
18
PF7
19
PF8
PF9
20
21
PF10
22
PF0
VSS_5
GigaDevice GD32F103Zx
LQFP144
VDD_2
PA13
PA8
92
PG7
91
90
PG6
89
PG4
PG5
88
PG3
87
PG2
OSC_IN
23
86
PD15
OSC_OUT
24
85
PD14
NRST
25
84
VDD_8
PC0
26
83
VSS_8
PC1
27
28
82
PD13
PD12
PC3
VSSA
29
80
79
PD11
VREFVREF+
31
32
78
PD9
77
PD8
VDDA
33
76
PB15
PA0_WKUP
34
75
PB14
PA1
35
74
PB13
PA2
36
73
PB12
PC2
81
30
PD10
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
VDD_1
VSS_1
PB11
PB10
PE15
PE13
PE14
PE12
PE11
VDD_7
PE10
VSS_7
PE8
PE9
PE7
PG1
PG0
PF15
PF14
VDD_6
PF13
VSS_6
PF12
PB2
PF11
PB1
PC5
PB0
PA7
PC4
PA6
PA5
VDD_4
PA4
VSS_4
PA3
11 / 48
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GD32F103xx
Figure 4. GD32F103Vx LQFP100 pinouts
PA14
PA15
PC10
PC11
PC12
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PB4
PB3
PB5
PB6
PB7
BOOT0
PB8
PB9
PE0
PE1
VSS_3
VDD_3
PE2
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
PE3
PE4
74
VSS_2
NC
PE5
PE6
73
72
71
VBAT
PC13-TAMPER-RTC
PC14-OSC32_IN
70
69
PC15-OSC32_OUT
VSS_5
PA13
PA12
PA11
PA10
PA9
68
67
10
66
PC9
PA8
65
PC8
64
PC7
63
PC6
14
62
PD15
15
61
PD14
16
17
60
PD13
59
PD12
18
58
57
PD11
56
PD9
VDD_5
11
OSC_IN
12
OSC_OUT
NRST
PC0
13
PC1
PC2
PC3
VDD_2
GigaDevice GD32F103Vx
LQFP100
VSSA
19
VREFVREF+
20
21
55
PD8
VDDA
22
54
PB15
PD10
PA0-WKUP
23
53
PA1
24
52
PB14
PB13
PA2
25
51
PB12
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
VSS_1
VDD_1
PB11
PB10
PE15
PE14
PE13
PE11
PE12
PE10
PE9
PE8
PE7
PB2
PB1
PC5
PB0
PA7
PC4
PA6
PA5
PA4
VDD_4
PA3
VSS_4
12 / 48
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GD32F103xx
Figure 5. GD32F103Rx LQFP64 pinouts
PA14
PA15
PC10
PC11
PC12
PB3
PD2
PB4
PB5
PB6
PB7
BOOT0
PB9
PB8
VSS_3
VDD_3
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VBAT
48
VDD_2
PC13-TAMPER-RTC
47
VSS_2
PC14-OSC32_IN
46
PA13
PC15-OSC32_OUT
PD0-OSC_IN
45
PA12
44
PA11
43
PA10
NRST
PC0
7
8
42
PA9
PC1
PC2
PC3
VSSA
10
PD1 OSC_OUT
GigaDevice GD32F103Rx
LQFP64
41
PA8
40
39
PC9
11
12
38
PC7
37
PC6
VDDA
13
36
PB15
PA0-WKUP
14
35
PA1
15
34
PB14
PB13
PA2
16
33
PB12
PC8
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PB11
VSS_1
PB3
PA15
PA14
VDD_1
PB10
PB2
PB0
PB1
PC5
PC4
PA7
PA6
PA5
PA4
VDD_4
PA3
VSS_4
PB4
PB5
PB6
PB7
PB8
BOOT0
PB9
VSS_3
VDD_3
48 47 46 45 44 43 42 41 40 39 38 37
VBAT
36
VDD_2
PC13-TAMPER-RTC
35
VSS_2
PC14-OSC32_IN
34
PA13
PC15-OSC32_OUT
PD0-OSC_IN
33
PA12
GigaDevice GD32F103Cx
LQFP48
32
PA11
31
PA10
30
PA9
29
PA8
PB15
PD1-OSC_OUT
NRST
VSSA
7
8
VDDA
PA0-WKUP
10
28
27
PA1
PA2
11
12
26
PB14
PB13
25
PB12
13 14 15 16 17 18 19 20 21 22 23 24
VDD_1
VSS_1
PB11
PB10
PB2
PB0
PB1
PA7
PA6
PA5
PA4
PA3
13 / 48
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GD32F103xx
Figure 7. GD32F103Tx QFN36 pinouts
PA0-WKUP
PA1
PA2
PA14
VDDA
PA15
OSC_OUT/PD1
NRST
VSSA
PB3
PB4
OSC_IN/PD0
PB5
PB6
PB7
BOOT0
VSS_3
VDD_3
36 35 34 33 32 31 30 29 28
1
27
2
26
3
4
VDD_2
VSS_2
25
PA13
24
5 GigaDevice GD32F103Tx 23
QFN36
6
22
7
21
PA12
PA9
PA8
20
9
19
10 11 12 13 14 15 16 17 18
PA11
PA10
VDD_1
VSS_1
PB2
PB1
PB0
PA7
PA6
PA5
PA4
PA3
14 / 48
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GD32F103xx
2.4
Memory map
Figure 8. GD32F103xx memory map
0x 4002 4400
0x 4002 3000
0x 4002 2400
0x 4002 2000
0x 4002 1400
RCC
reserved
0x 4002 0400
DMA2
0x 4002 0000
DMA1
0x 4001 8400
reserved
0x 4001 8000
SDIO
reserved
0x 4001 5800
0x 4001 5400
0x 4001 5000
0x 4001 4C00
0x 4001 4000
0x 4001 3C00
0x 4001 3800
0x 4001 3400
0x 4001 3000
0x 4001 2C00
0x 4001 2800
0x 4001 2400
0x 4001 2000
0x 4001 1C00
0x 4001 1800
0x 4001 1400
0x 4001 1000
Cortex-M3 Internal
Peripherals
0xE010 0000
0x1FFF FFFF
0x1FFF F80F
reserved
Option
Bytes
0x 4001 0C00
0x 4001 0800
0x 4001 0400
0x 4001 0000
0xE000 0000
0x 4000 7800
0x1FFF F800
reserved
0x 4000 7400
0x 4000 7000
0x 4000 6C00
0xC000 0000
System
memory
0x1FFF F000
0x 4000 6800
EXMC register
0x 4000 6400
0xA000 1000
0x 4000 6000
0xA000 0000
0x 4000 5C00
0x 4000 5800
reserved
reserved
0x8000 0000
EXMC bank
reserved
0x 4000 5400
0x 4000 5000
0x 4000 4C00
0x 4000 4800
0x 4000 4400
0x 4000 4000
0x 4000 3C00
0x6000 0000
0x 4000 3800
reserved
0x 4000 3400
0x 4000 3000
0x 4000 2C00
0x4000 0000
0x0830 0000
0x0808 0000
0x0802 0000
0x0800 0000
0x0010 0000
0x0000 0000
Flash memory
bank 2 (2560KB)
Flash memory
bank 1 (512KB)
Flash Memory
reserved
Aliased to Flash or
system memory
according to BOOT
pins configuration
Peripherals
reserved
0x 4000 2800
0x 4000 2400
0x 4000 2000
0x 4000 1C00
0x2001 8000
0x2000 0000
SRAM (96KB)
reserved
0x0000 0000
Flash Interface
reserved
0x 4002 0800
0x 4002 1000
0xFFFF FFFF
CRC
reserved
0x 4000 1800
0x 4000 1400
0x 4000 1000
0x 4000 0C00
0x 4000 0800
0x 4000 0400
0x 4000 0000
TM11
TM10
TM9
reserved
ADC3
USART1
TM8
SPI1
TM1
ADC2
ADC1
Port G
Port F
Port E
Port D
Port C
Port B
Port A
EXTI
AFIO
reserved
DAC
PWR
BKP
reserved
bxCAN
shared 512 byte
USB/CAN SRAM
USB Registers
I2C2
I2C1
UART5
UART4
USART3
USART2
reserved
SPI3/I2S3
SPI2/I2S2
reserved
IWDG
WWDG
RTC
reserved
TM14
TM13
TM12
TM7
TM6
TM5
TM4
TM3
TM2
15 / 48
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GD32F103xx
2.5
Clock tree
Figure 9. GD32F103xx clock tree
USB
Prescaler
(1,1.5,2)
CK_USB
(to USB)
I2S2CLK
(to I2S2)
enable
I2S3CLK
enable
(to I2S3)
enable
(to SDIO)
HCLK/2
CK_FMCU
SCS[1:0]
FMCU enable
(by hardware)
(to FMCU)
CK_EXMC
CK_HSI
EXMC
enable
00
8 MHz
HSI RC
/2
PLLPREDV
PLL
2...32
PLLSEL
PLLEN
CK_PLL
10
CK_SYS
108 MHz max
AHB
Prescaler
(1,2...512)
(to EXMC)
CK_AHB
108 MHz max
HCLK
AHB enable
01
CK_CST
8
(to Cortex-M3 SysTick)
/2
4-16 MHz
HSE XTAL
Clock
Monitor
FCLK
(free running clock)
CK_HSE
TM2,3,4
1 or 2
to TM2,3,4
11
/128
32.768 KHz
LSE OSC
01
(to RTC)
APB1
Prescaler
(1,2,4,8,16)
CK_IWDG
TM1
1 or 2
CK_RTC
RTCSRC[1:0]
CK_APB1
PCLK1
54 MHz max
Peripheral enable
10
40 KHz
LSI RC
CK_TMX
TMX enable
CK_TM1
TM1 enable
to TM1
(to IWDG)
APB2
Prescaler
(1,2,4,8,16)
CK_SYS
CK_HSI
CK_APB2
PCLK2
108 MHz max
Peripheral enable
CK_OUT
to APB1
peripherals
to APB2
peripherals
CK_HSE
ADC
Prescaler
(2,4,8,12,16)
CK_PLL/2
CK_ADCX to ADC1,ADC2
14 MHz max
Legend:
HSE = High speed external clock
HSI = High speed internal clock
LSE = Low speed external clock
LSI = Low speed internal clock
16 / 48
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GD32F103xx
2.6
Pin definitions
LQFP100
LQFP64
LQFP48
QFN36
Pin Type
PE2
I/O
5VT
PE3
I/O
5VT
PE4
I/O
5VT
Functions description
I/O
Pin Name
(2)
LQFP144
(1)
Pins
Level
Default: PE2
Alternate: TRACECK, EXMC_A23
Default: PE3
Alternate: TRACED0, EXMC_A19
Default: PE4
Alternate:TRACED1, EXMC_A20
Default: PE5
PE5
I/O
(4)
Default: PE6
PE6
I/O
VBAT
PC13-TAMPE
R-RTC
PC14-OSC32
_IN
PC15OSC32_OUT
PF0
PF1
I/O
I/O
I/O
10
I/O
11
I/O
Default: VBAT
Default: PC13
Alternate: TAMPER-RTC
Default: PC14
Alternate: OSC32_IN
Default: PC15
Alternate: OSC32_OUT
5VT
5VT
Default: PF0
(3)
Alternate: EXMC_A0
Default: PF1
Alternate: EXMC_A1
Default: PF2
I/O
5VT
PF3
13
I/O
5VT
PF4
14
I/O
5VT
PF5
15
I/O
5VT
VSS_5
16
10
Default: VSS_5
VDD_5
17
11
Default: VDD_5
Alternate: EXMC_A2
18
I/O
19
I/O
(3)
(3)
(3)
(3)
PF7
(3)
(3)
Alternate: EXMC_A5
Default: PF6
(3)
(3)
Alternate: EXMC_A4
Default: PF5
(3)
(3)
Alternate: EXMC_A3
Default: PF4
(3)
(3)
12
Default: PF3
(3)
(3)
PF2
PF6
(4)
Default: PF7
(4)
(3)
(3)
(3)
17 / 48
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(2)
Functions description
I/O
(1)
Pin Type
QFN36
LQFP48
LQFP64
LQFP100
Pin Name
LQFP144
Pins
Level
GD32F103xx
Remap: TM11_CH1
Default: PF8
PF8
20
I/O
(3)
Default: PF9
21
I/O
(3)
PF9
(4)
(3)
(4)
(3)
(3)
(3)
(4)
(3)
I/O
Default: PF10
PF10
22
OSC_IN
23
12
OSC_OUT
24
13
NRST
25
14
I/O
PC0
26
15
I/O
PC1
27
16
I/O
PC2
28
17
10
I/O
PC3
29
18
11
I/O
VSSA
30
19
12
Default: VSSA
VREF-
31
20
Default: VREF-
VREF+
32
21
Default: VREF+
VDDA
33
22
13
Default: VDDA
(3)
(3)
(4)
Default: OSC_OUT
Remap: PD1
(4)
Default: NRST
Default: PC0
Alternate: ADC_IN10
Default: PC1
Alternate: ADC_IN11
Default: PC2
Alternate: ADC_IN12
Default: PC3
Alternate: ADC_IN13
Default: PA0
PA0-WKUP
34
23
14
10
I/O
(3)
TM5_CH1 , TM8_ETR
PA1
35
24
15
11
I/O
PA2
36
25
16
12
I/O
Default: PA1
Alternate: USART2_RTS, ADC_IN1, TM2_CH2, TM5_CH2
(3)
Default: PA2
Alternate: USART2_TX, ADC_IN2, TM2_CH3, TM5_CH3
TM9_CH1
(3)
(3)
(4)
Default: PA3
PA3
37
26
17
13
10
I/O
(4)
VSS_4
38
27
18
Default: VSS_4
VDD_4
39
28
19
Default: VDD_4
PA4
40
29
20
14
11
I/O
Default: PA4
Alternate: SPI1_NSS, USART2_CK, ADC12_IN4;
DAC_OUT1
(3)
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LQFP48
QFN36
Pin Type
30
21
15
12
I/O
(2)
LQFP64
41
Functions description
I/O
LQFP100
PA5
LQFP144
Pin Name
(1)
Pins
Level
GD32F103xx
Default: PA5
Alternate: SPI1_SCK, ADC12_IN5, DAC_OUT2
(3)
Default: PA6
(3)
PA6
42
31
22
16
13
I/O
TM13_CH1
(4)
Remap: TM1_BKIN
Default: PA7
PA7
43
32
23
17
14
I/O
(3)
TM8_CH1N , TM14_CH1
(4)
Remap: TM1_CH1N
PC4
44
33
24
I/O
PC5
45
34
25
I/O
PB0
46
35
26
18
15
I/O
Default: PC4
Alternate: ADC12_IN14
Default: PC5
Alternate: ADC12_IN15
Default: PB0
(3)
PB1
47
36
27
19
16
(3)
I/O
Remap: TM1_CH3N
I/O
49
I/O
5VT
PF12
50
I/O
5VT
VSS_6
51
Default: VSS_6
VDD_6
52
Default: VDD_6
PF13
53
I/O
5VT
PF14
54
I/O
5VT
PF15
55
I/O
5VT
PG0
56
I/O
5VT
PB2
48
PF11
37
28
20
17
(3)
Default: PF11
Alternate: EXMC_NIOS16
(3)
(3)
Default: PF12
Alternate: EXMC_A6
(3)
(3)
Default: PF13
Alternate: EXMC_A7
(3)
(3)
Default: PF14
Alternate: EXMC_A8
(3)
(3)
PG1
57
I/O
5VT
Default: PF15
Alternate: EXMC_A9
Default: PG0
(3)
(3)
Alternate: EXMC_A10
Default: PG1
(3)
(3)
Alternate: EXMC_A11
(3)
Default: PE7
PE7
58
38
I/O
PE8
59
39
I/O
www.realsense.com.cn
(2)
Functions description
I/O
(1)
Pin Type
QFN36
LQFP48
LQFP64
LQFP100
Pin Name
LQFP144
Pins
Level
GD32F103xx
Default: PE9
PE9
60
40
I/O
VSS_7
61
Default: VSS_7
VDD_7
62
Default: VDD_7
Default: PE10
PE10
63
41
I/O
PE11
64
42
I/O
PE12
65
43
I/O
PE13
66
44
I/O
PE14
67
45
I/O
PE15
68
46
I/O
PB10
69
47
29
21
I/O
PB11
70
48
30
22
I/O
VSS_1
71
49
31
23
18
Default: VSS_1
VDD_1
72
50
32
24
19
Default: VDD_1
Default: PB12
PB12
73
51
33
25
I/O
TM1_BKIN, I2S2_WS
Default: PB13
PB13
74
52
34
26
I/O
I2S2_CK
Default: PB14
PB14
75
53
35
27
I/O
(4)
Default: PB15
PB15
76
54
36
28
I/O
(3)
(4)
20 / 48
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(2)
Functions description
I/O
(1)
Pin Type
QFN36
LQFP48
LQFP64
LQFP100
Pin Name
LQFP144
Pins
Level
GD32F103xx
Default: PD8
PD8
77
55
I/O
PD9
78
56
I/O
PD10
79
57
I/O
PD11
80
58
I/O
PD12
81
59
I/O
PD13
82
60
I/O
VSS_8
83
Default: VSS_8
VDD_8
84
Default: VDD_8
PD14
85
Default: PD14
61
I/O
PD15
86
62
I/O
PG2
87
I/O
5VT
PG3
88
I/O
5VT
PG4
89
I/O
5VT
PG5
90
I/O
5VT
PG6
91
I/O
5VT
PG7
92
I/O
PG8
93
I/O
5VT
Default: PG2
(3)
Alternate: EXMC_A12
Default: PG3
(3)
Alternate: EXMC_A13
Default: PG4
Alternate: EXMC_INT2
Default: PG7
Alternate: EXMC_INT3
Default: VSS_9
95
Default: VDD_9
PC6
96
I/O
5VT
(3)
(3)
94
(3)
(3)
VSS_9
37
(3)
(3)
VDD_9
63
(3)
(3)
Alternate: EXMC_A15
Default: PG6
(3)
(3)
Alternate: EXMC_A14
Default: PG5
(3)
Default: PC6
(3)
(3)
(3)
21 / 48
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(2)
Functions description
I/O
(1)
Pin Type
QFN36
LQFP48
LQFP64
LQFP100
Pin Name
LQFP144
Pins
Level
GD32F103xx
Remap: TM3_CH1
Default: PC7
PC7
97
64
38
I/O
(3)
(3)
(3)
PC8
98
65
39
I/O
(3)
(3)
(3)
(3)
PC9
99
66
40
I/O
PA8
100 67
41
29
20
I/O
5VT
PA9
101 68
42
30
21
I/O
5VT
PA10
102 69
43
31
22
I/O
5VT
PA11
103 70
44
32
23
I/O
5VT
PA12
104 71
45
33
24
I/O
5VT
PA13
105 72
46
34
25
I/O
5VT
NC
106 73
VSS_2
107 74
47
35
26
Default: VSS_2
VDD_2
108 75
48
36
27
Default: VDD_2
PA14
109 76
49
37
28
I/O
5VT
PA15
110 77
50
38
29
I/O
(3)
(3)
111 78
51
I/O
(3)
(3)
(3)
(3)
(3)
(3)
PC11
112 79
52
I/O
PC12
113 80
53
I/O
PD0
114 81
I/O
www.realsense.com.cn
(2)
Functions description
I/O
(1)
Pin Type
QFN36
LQFP48
LQFP64
LQFP100
Pin Name
LQFP144
Pins
Level
GD32F103xx
Default: PD1
PD1
115 82
I/O
PD2
116 83
54
PD3
117 84
Default: PD2
I/O
5VT
I/O
(3)
(3)
Remap: USART2_CTS
Default: PD4
PD4
118 85
I/O
PD5
119 86
I/O
VSS_10
120
Default: VSS_10
VDD_10
121
Default: VDD_10
Default: PD6
PD6
122 87
I/O
PD7
123 88
I/O
PG9
124
I/O
5VT
PG10
125
I/O
5VT
PG11
126
I/O
5VT
PG12
127
I/O
5VT
PG13
128
I/O
5VT
PG14
129
I/O
5VT
Default: PG9
(3)
(3)
(3)
(3)
(3)
(3)
Alternate: EXMC_NCE4_2
Default: PG12
(3)
(3)
Alternate: EXMC_A24
Default: PG14
(3)
(3)
Alternate: EXMC_NE4
Default: PG13
(3)
(3)
(3)
Alternate: EXMC_A25
VSS_11
130
Default: VSS_10
VDD_11
131
Default: VDD_10
PG15
132
I/O
(3)
PB3
133 89
55
39
30
I/O
(3)
(3)
134 90
56
40
31
I/O
(3)
www.realsense.com.cn
(1)
Functions description
I/O
(2)
Pin Type
QFN36
LQFP48
LQFP64
LQFP100
Pin Name
LQFP144
Pins
Level
GD32F103xx
Default: PB5
PB5
135 91
57
41
32
(3)
(3)
I/O
136 92
58
42
33
I/O
Remap: USART1_TX
Default: PB7
PB7
137 93
59
43
34
(3)
I/O
Remap: USART1_RX
BOOT0
138 94
60
44
35
PB8
139 95
61
45
I/O
Default: BOOT0
Default: PB8
(3)
(4)
(3)
(4)
PB9
140 96
62
46
I/O
PE0
141 97
I/O
5VT
PE1
142 98
I/O
5VT
VSS_3
143 99
63
47
36
Default: VSS_3
VDD_3
144 100 64
48
Default: VDD_3
Notes:
1.
2.
3.
4.
24 / 48
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GD32F103xx
Functional description
3.1
The Cortex-M3 processor is the latest generation of ARM processors for embedded
systems. It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
The Cortex-M3 processor is based on the ARMv7 architecture and supports both Thumb
and Thumb-2 instruction sets. Some system peripherals listed below are also provided by
Cortex-M3:
Internal Bus Matrix connected with ICode bus, DCode bus, system bus, Private
Peripheral Bus (PPB) and debug accesses (AHB-AP)
3.2
On-chip memory
Up to 96 Kbytes of SRAM
The ARM
separate buses to fetch instructions and load/store data. 3072 Kbytes of inner Flash and 96
Kbytes of inner SRAM at most is available for storing programs and data, both accessed
(R/W) at CPU clock speed with zero wait states. The Figure 6. GD32F103xx memory map
shows the memory map of the GD32F103xx series of devices, including code, SRAM,
peripheral, and other pre-defined regions.
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GD32F103xx
3.3
Internal 40 KHz RC calibrated oscillator and external 32.768 KHz crystal oscillator
Supply Supervisor: POR (Power On Reset), PDR (Power Down Reset), and low voltage
detector (LVD)
The Clock Control Unit (CCU) provides a range of oscillator and clock functions. These
include speed internal RC oscillator and external crystal oscillator, high speed and low speed
two types. Several prescalers allow the configuration of the AHB frequency, the high-speed
APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB
and the high-speed APB domains is 108 MHz. The maximum allowed frequency of the
low-speed APB domain is 54 MHz. See Figure 7 for details on the clock tree.
The Reset Control Unit (RCU) controls three kinds of reset: system reset resets the
processor core and peripheral IP components. Power-on reset (POR) and power-down reset
(PDR) are always active, and ensures proper operation starting from/down to 2.6 V. The
device remains in reset mode when VDD is below a specified threshold. The embedded low
voltage detector (LVD) monitors the power supply, compares it to the voltage threshold and
generates an interrupt as a warning message for leading the MCU into security.
Power supply schemes:
VDD range: 2.6 to 3.6 V, external power supply for I/Os and the internal regulator.
Provided externally through VDD pins.
VSSA, VDDA range: 2.6 to 3.6 V, external analog power supplies for ADC, reset blocks,
RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.
VBAT range: 1.8 to 3.6 V, power supply for RTC, external clock 32 kHz oscillator and
backup registers (through power switch) when VDD is not present.
3.4
Boot modes
At startup, boot pins are used to select one of three boot options:
The boot loader is located in the internal boot ROM memory (system memory). It is used to
reprogram the Flash memory by using USART1 in device mode. It also can be used to
transfer and update the Flash memory code, the data and the vector table sections. In
default condition, boot from bank 1 of Flash memory is selected. It also supports to boot from
bank 2 of Flash memory by setting a bit in option bytes.
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GD32F103xx
3.5
Sleep mode
In sleep mode, only the clock of CPU core is off. All peripherals continue to operate and
any interrupt/event can wake up the system.
Deep-sleep mode
In Deep-sleep mode, all clocks in the 1.2V domain are off, and all of the high speed
crystal oscillator (HSI, HSE) and PLL are disabled. Only the contents of SRAM and
registers are retained. Any interrupt or wakeup event from EXTI lines can wake up the
system from the Deep-sleep mode including the 16 external lines, the RTC alarm, the
LVD output, and USB wakeup. When exiting the Deep-sleep mode, the HSI is selected
as the system clock.
Standby mode
In Standby mode, the whole 1.2V domain is power off, the LDO is shut down, and all of
HSI, HSE and PLL are disabled. The contents of SRAM and registers (except Backup
Registers) are lost. There are four wakeup sources for the Standby mode, including the
external reset from NRST pin, the RTC alarm, the IWDG reset, and the rising edge on
WKUP pin.
3.6
Temperature sensor
Up to three 12-bit 1 s multi-channel ADCs are integrated in the device. Each is a total of up
to 21 multiplexed external channels. An analog watchdog block can be used to detect the
channels, which are required to remain within a specific threshold window. A configurable
channel management block of analog inputs also can be used to perform conversions in
single, continuous, scan or discontinuous mode to support more advanced usages.
The ADCs can be triggered from the events generated by the general-purpose timers (TMx)
and the advanced-control timers (TM1 and TM8) with internal connection. The temperature
sensor has to generate a voltage that varies linearly with temperature. The conversion range
is between 2.6 V < VDDA < 3.6 V. The temperature sensor is internally connected to the
ADC_IN16 input channel which is used to convert the sensor output voltage into a digital
value.
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GD32F103xx
3.7
The two 12-bit buffered DAC channels are used to generate variable analog outputs. The
DACs are designed with integrated resistor strings structure. The DAC channels can be
triggered by the timer update outputs or EXTI with DMA support. In dual DAC channel
operation, conversions could be done independently or simultaneously. The maximum
output value of the DAC is VREF+.
3.8
DMA
Peripherals supported: Timers, ADC, SPIs, I Cs, USARTs, DAC, I S and SDIO
3.9
There are up to 112 general purpose I/O pins (GPIO) in GD32F103xx, named PA0 ~ PA15
and PB0 ~ PB15, PC0 ~ PC15, PD0 ~ PD15, PE0 ~ PE15, PF0-PF15, PG0-PG15 to
implement logic input/output functions. Each of the GPIO ports has related control and
configuration registers to satisfy the requirements of specific applications. The external
interrupts on the GPIO pins of the device have related control and configuration registers in
the External Interrupt Control Unit (EXTI). The GPIO ports are pin-shared with other
alternative functions (AFs) to obtain maximum flexibility on the package pins. Each of the
GPIO pins can be configured by software as output (push-pull or open-drain), as input (with
or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are
shared with digital or analog alternate functions. All GPIOs are high-current capable except
for analog inputs.
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GD32F103xx
3.10
Up to two 16-bit advanced-control timer (TM1 & TM8), ten 16-bit general-purpose timers
(GPTM), and two 16-bit basic timer (TM6 & TM7)
Up to 4 independent channels of PWM, output compare or input capture for each GPTM
and external trigger input
The advanced-control timer (TM1 & TM8) can be seen as a three-phase PWM multiplexed
on 6 channels. It has complementary PWM outputs with programmable dead-time
generation. It can also be used as a complete general-purpose timer. The 6 independent
channels can be used for
Input capture
Output compare
If configured as a general-purpose 16-bit timer, it has the same functions as the TMx timer. It
can be synchronized with external signals or to interconnect with other GPTMs together
which have the same architecture and features.
The general-purpose timer (GPTM), known as TM2 ~ TM5, TM9 ~ TM11, TM12 ~ TM14 can
be used for a variety of purposes including general time, input signal pulse width
measurement or output waveform generation such as a single pulse generation or PWM
output, up to 4 independent channels for input capture/output compare. The GPTM also
supports an encoder interface with two inputs using quadrature decoder.
The basic timer, known as TM6 and TM7 are mainly used for DAC trigger generation. They
can also be used as a simple 16-bit time base.
The GD32F103xx have two watchdog peripherals, Independent watchdog and window
watchdog. They offer a combination of high safety level, flexibility of use and timing accuracy.
The independent watchdog timer includes a 12-bit down-counting counter and a 8-bit
prescaler, It is clocked from an independent 40 kHz internal RC and as it operates
independently of the main clock, it can operate in stop and standby modes. It can be used
either as a watchdog to reset the device when a problem occurs, or as a free-running timer
for application timeout management.
The window watchdog is based on a 7-bit down counter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from the
main clock. It has an early warning interrupt capability and the counter can be frozen in
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GD32F103xx
debug mode.
The SysTick timer is dedicated for OS, but could also be used as a standard down counter. It
features:
3.11
Alarm function
The real time clock is an independent timer which provides a set of continuously running
counters which can be used with suitable software to provide a clock calendar function, and
provides an alarm interrupt and an expected interrupt. The RTC features a 32-bit
programmable counter for long-term measurement using the compare register to generate
an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to
generate a time base of 1 second from a clock at 32.768 kHz from external crystal oscillator.
3.12
Up to two I2C bus interfaces can support both master and slave mode with a frequency
up to 400 kHz
Provide arbitration function, optional PEC (packet error checking) generation and
checking
Supports 7-bit and 10-bit addressing mode and general call addressing mode
The I2C interface is an internal circuit allowing communication with an external I2C interface
which is an industry standard two line serial interface used for connection to external
hardware. These two serial lines are known as a serial data line (SDA) and a serial clock line
(SCL). The I2C module provides two data transfer rates: 100 kHz of standard mode or 400
kHz of the fast mode. The I2C module also has an arbitration detect function to prevent the
situation where more than one master attempts to transmit data to the I2C bus at the same
time. A CRC-8 calculator is also provided in I2C interface to perform packet error checking
for I2C data.
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GD32F103xx
3.13
The SPI interface uses 4 pins, among which are the serial data input and output lines (MISO
& MOSI), the clock line (SCK) and the slave select line (NSS). Both SPIs can be served by
the DMA controller. The SPI interface may be used for a variety of purposes, including
simplex synchronous transfers on two lines with a possible bidirectional data line or reliable
communication using CRC checking.
3.14
Up to three USARTs and two UARTs with operating frequency up to 4.5 MHz
The USART (USART1, USART2 and USART3) and UART (UART4 & UART5) are used to
translate data between parallel and serial interfaces, provides a flexible full duplex data
exchange using synchronous or asynchronous transfer. It is also commonly used for RS-232
standard communication. The USART includes a programmable baud rate generator which
is capable of dividing the system clock to produce a dedicated clock for the USART
transmitter and receiver. The USART also supports DMA function for high speed data
communication except UART5.
3.15
Two I2S bus Interfaces with sampling frequency from 8 kHz to 192 kHz
The Inter-IC sound (I2S) bus provides a standard communication interface for digital audio
applications by 3-wire serial lines. GD32F103xx contain two I2S-bus interfaces that can be
operated with 16/32 bit resolution in master or slave mode, pin multiplexed with SPI2 and
SPI3. The audio sampling frequency from 8 kHz to 192 kHz is supported with less than 0.5%
accuracy error.
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GD32F103xx
3.16
The Secure Digital Input and Output Card Interface (SDIO) provides access to external SD
memory cards specifications version 2.0, SDIO card specification version 2.0 and
multi-media card system specification version 4.2 with DMA supported. In addition, this
interface is also compliant with CE-ATA digital protocol rev1.1.
3.17
The Universal Serial Bus (USB) is a 4-wire bus that supports communication between one or
more devices. Full-speed peripheral is compliant with the USB 2.0 specification. The device
controller enables 12 Mbit/s data exchange with a USB Host controller. Transaction
formatting is performed by the hardware, including CRC generation and checking. The status
of a completed USB transfer or error condition is indicated by status registers. An interrupt is
also generated if enabled. The dedicated 48 MHz clock is generated from the internal main
PLL (the clock source must use a HSE crystal oscillator) and the operating frequency divided
from APB1 should be 12 MHz above.
3.18
Controller area network (CAN) is a method for enabling serial communication in field bus.
The CAN protocol has been used extensively in industrial automation and automotive
applications. It can receive and transmit standard frames with 11-bit identifiers as well as
extended frames with 29-bit identifiers. It has three mailboxes for transmission and two
FIFOs of three message deep for reception. It also provides 14 scalable/configurable
identifier filter banks for selecting the incoming messages needed and discarding the others.
3.19
Supported external memory: SRAM, PSRAM, ROM and NOR-Flash, NAND Flash and
CF card
Support to interface with Motorola 6800 and Intel 8080 type LCD directly
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GD32F103xx
divided in to several sub-banks for external device support, each sub-bank has its own chip
selection signal but at one time, only one bank can be accessed. The EXMC support code
execution from external memory except NAND Flash and CF card. The EXMC also can be
configured to interface with the most common LCD module of Motorola 6800 and Intel 8080
series and reduce the system cost and complexity.
3.20
Debug mode
The ARM SWJ-DP Interface is embedded and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
3.21
33 / 48
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GD32F103xx
Electrical characteristics
4.1
Min
Max
Unit
VDD
VSS - 0.3
VSS + 3.6
VDDA
VSSA - 0.3
VSSA + 3.6
VBAT
VSS - 0.3
VSS + 3.6
VSS - 0.3
VSS + 4.0
VSS - 0.3
4.0
VIN
IIO
25
mA
TA
-40
+85
-55
+150
125
TSTG
TJ
4.2
Parameter
Recommended DC characteristics
Table 4. DC operating conditions
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDD
Supply voltage
2.6
3.3
3.6
VDDA
Same as VDD
2.6
3.3
3.6
VBAT
1.8
3.6
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GD32F103xx
4.3
Power consumption
The power measurements specified in the tables represent that code with data executing
from on-chip Flash with the following specifications.
Table 5. Power consumption characteristics
Symbol
Parameter
Conditions
VDD=VBAT=3.3V, HSE=8MHz, System
Min
Typ
Max
Unit
45.2
mA
36.0
mA
32.4
mA
26.1
mA
23.2
mA
12.4
mA
0.61
1.4
mA
10.5
7.3
4.3
(Run mode)
IDD
Supply current
(Sleep mode)
Supply current
(Deep-Sleep
mode)
Supply current
current
(Standby mode)
35 / 48
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GD32F103xx
4.4
EMC characteristics
EMS (electromagnetic susceptibility) includes ESD (Electrostatic discharge, positive and
negative) and FTB (Burst of Fast Transient voltage, positive and negative) testing result is
given in the following table, based on the EMS levels and classes compliant with IEC 61000
series standard.
Table 6. EMS characteristics
Symbol
VESD
Parameter
Conditions
Level/Class
3B
4A
EMI (Electromagnetic Interference) emission testing result is given in the following table,
compliant with IEC 61967-2 standard which specifies the test board and the pin loading.
Table 7. EMI characteristics
Symbol
Parameter
Conditions
VDD = 3.3 V,
SEMI
Peak level
TA = +25 C,
compliant with IEC
61967-2
4.5
Conditions
Tested
frequency band
Unit
56M
72M
108M
0.1 to 2 MHz
<0
<0
<0
2 to 30 MHz
-3.7
-2.8
-1.6
30 to 130 MHz
-6.5
-8
-5.5
-7
-7
-5
dBV
Parameter
Conditions
Min
Typ
Max
Unit
VPOR
2.32
2.40
2.48
VPDR
2.27
2.35
2.43
VHYST
PDR hysteresis
0.05
Reset temporization
TRSTTEMP
36 / 48
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GD32F103xx
4.6
Electrical sensitivity
The device is strained in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharges (ESD) are applied directly to the pins of the sample. Static latch-up
(LU) test is based on the two measurement methods.
Table 9. ESD characteristics
Symbol
VESD(HBM)
VESD(CDM)
Parameter
Conditions
Electrostatic discharge
TA=25 C;
JESD22-A114
Electrostatic discharge
TA=25 C;
JESD22-C101
Min
Typ
Max
Unit
4000
1000
Min
Typ
Max
Unit
100
mA
5.4
Parameter
Conditions
I-test
LU
TA=25 C; JESD78
Vsupply over voltage
4.7
CHSE
Parameter
High Speed External oscillator
(HSE) frequency
Recommended load capacitance
on OSC_IN and OSC_OUT
Conditions
Min
Typ
Max
Unit
VDD=3.3V
16
MHz
20
30
pF
DHSE
48
50
52
IDDHSE
VDD=3.3V, TA=25C
1.4
tSUHSE
VDD=3.3V, TA=25C
ms
37 / 48
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GD32F103xx
Table 12. Low speed external clock (LSE) generated from a crystal/ceramic
characteristics
Symbol
fLSE
Parameter
Low Speed External oscillator
(LSE) frequency
Conditions
Min
Typ
Max
Unit
32.768
1000
KHz
15
pF
48
50
52
VDD=VBAT=3.3V
1.4
VDD=VBAT=3.3V
VDD=VBAT=3.3V
Recommended load
CLSE
RFLSE
DLSE
IDDLSE
tSULSE
4.8
ACCHSI
DHSI
IDDHSI
tSUHSI
Parameter
High Speed Internal
Oscillator (HSI) frequency
Conditions
VDD=3.3V, TA=-40C ~+85C
Min
Typ
Max
Unit
MHz
-1
+1
Factory-trimmed
accuracy
VDD=3.3V, TA=25C
VDD=3.3V, fHSI=8MHz
48
50
52
VDD=3.3V, fHSI=8MHz
80
100
VDD=3.3V, fHSI=8MHz
us
Min
Typ
Max
Unit
30
40
60
KHz
VDD=VBAT=3.3V, TA=25C
VDD=VBAT=3.3V, TA=25C
80
IDDLSI
tSULSI
Parameter
Conditions
VDD=VBAT=3.3V,
TA=-40C ~ +85C
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GD32F103xx
4.9
PLL characteristics
Table 15. PLL characteristics
Symbol
4.10
Parameter
Conditions
Min
Typ
Max
Unit
fPLLIN
25
MHz
fPLL
16
108
MHz
tLOCK
100
Memory characteristics
Table 16. Flash memory characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
TA=-40C ~ +85C
100
kcycles
TA=125C
20
years
Number of guaranteed
PECYC
tRET
4.11
tPROG
TA=-40C ~ +85C
200
400
us
tERASE
TA=-40C ~ +85C
60
100
450
ms
tMERASE
TA=-40C ~ +85C
3.2
9.6
GPIO characteristics
Table 17. I/O port characteristics
Symbol
Parameter
Standard IO Low level
VIL
input voltage
5V-tolerant IO Low level
input voltage
Standard IO High level
VIH
input voltage
5V-tolerant IO High level
input voltage
Conditions
Min
Typ
Max
Unit
VDD=2.6V
-0.3
0.95
VDD=2.6V
-0.3
0.9
VDD=2.6V
1.2
4.0
VDD=2.6V
1.5
5.5
VOL
VDD=2.6V
0.2
VOH
VDD=2.6V
2.3
RPU
VIN=VSS
30
40
50
RPD
VIN=VDD
30
40
50
39 / 48
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GD32F103xx
4.12
ADC characteristics
Table 18. ADC characteristics
Symbol
Min
Typ
Max
Unit
2.6
3.3
3.6
VREF+
ADC clock
0.6
14
MHz
Sampling rate
MHz
18
0.2
32
pF
Min
Typ
Max
Unit
2.6
3.3
3.6
VREF+
50
pF
DAC in 12-bit
LSB
Integral non-linearity
DAC in 12-bit
LSB
Offset
Offset error
12
LSB
GE
Gain error
DAC in 12-bit
0.5
VDDA
VADCIN
fADC
fS
fADCCONV
RADC
CADC
tSU
4.13
Parameter
Conditions
Operating voltage
ADC input voltage range
fADC=14MHz
No pin/pad capacitance
included
Startup time
DAC characteristics
Table 19. DAC characteristics
Symbol
VDDA
RLOAD
Load resistance
CLOAD
Load capacitance
INL
Conditions
Operating voltage
VDACIN
DNE
4.14
Parameter
Differential non-linearity
error
No pin/pad capacitance
included
I2C characteristics
Table 20. I2C characteristics
Symbol
Parameter
Conditions
Standard mode
Fast mode
Min
Max
Min
Max
Unit
fSCL
100
400
KHz
tSCL(H)
4.0
0.6
ns
tSCL(L)
4.7
1.3
ns
40 / 48
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GD32F103xx
4.15
SPI characteristics
Table 21. SPI characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fSCK
18
MHz
tSCK(H)
19
ns
tSCK(L)
19
ns
25
ns
tH(MO)
ns
tSU(MI)
ns
tH(MI)
ns
fPCLK=54MHz
74
ns
tH(NSS)
fPCLK=54MHz
37
ns
tA(SO)
fPCLK=54MHz
55
ns
tDIS(SO)
10
ns
tV(SO)
25
ns
tH(SO)
15
ns
tSU(SI)
ns
tH(SI)
ns
41 / 48
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GD32F103xx
Package information
5.1
Dimensions (mm)
min
max
Symbol
Dimensions (mm)
min
max
6.0 0.1
D1
3.90 Typ
6.0 0.1
D2
3.90 Typ
0.210 0.025
0.85
0.95
C1
00.050
E1
0.500 Typ
C2
0.203 Typ
0.550 Typ
Note:
1. Formed lead shall be planar with respect to one another within 0.004 inches.
2. Both package length and width do not include mold flash and metal burr.
42 / 48
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GD32F103xx
5.2
43 / 48
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GD32F103xx
Table 23. LQFP package dimensions
Symbol
LQFP48
LQFP64
LQFP100
LQFP144
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
1.20
1.60
1.60
1.60
A1
0.05
0.15
0.05
0.15
0.05
0.15
0.05
0.15
A2
0.95
1.00
1.05
1.35
1.40
1.45
1.35
1.40
1.45
1.35
1.40
1.45
9.00
12.00
16.00
22.00
D1
7.00
10.00
14.00
20.00
9.00
12.00
16.00
22.00
E1
7.00
10.00
14.00
20.00
R1
0.08
0.08
0.08
0.08
R2
0.08
0.20
0.08
0.20
0.08
0.20
0.08
0.20
3.5
3.5
3.5
3.5
11
12
13
11
12
13
11
12
13
11
12
13
11
12
13
11
12
13
11
12
13
11
12
13
0.09
0.20
0.09
0.20
0.09
0.20
0.09
0.20
0.45
0.60
0.75
0.45
0.60
0.75
0.45
0.60
0.75
0.45
0.60
0.75
L1
1.00
1.00
1.00
1.00
0.20
0.20
0.20
0.20
0.17
0.22
0.27
0.17
0.20
0.27
0.17
0.20
0.27
0.17
0.20
0.27
0.50
0.50
0.50
0.50
D2
5.50
7.50
12.00
17.50
E2
5.50
7.50
12.00
17.50
aaa
0.20
0.20
0.20
0.20
bbb
0.20
0.20
0.20
0.20
ccc
0.08
0.08
0.08
0.08
44 / 48
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GD32F103xx
Ordering Information
Flash (KB)
Package
Package type
GD32F103T4U6
16
QFN36
Green
GD32F103T6U6
32
QFN36
Green
GD32F103T8U6
64
QFN36
Green
GD32F103TBU6
128
QFN36
Green
GD32F103C4T6
16
LQFP48
Green
GD32F103C6T6
32
LQFP48
Green
GD32F103C8T6
64
LQFP48
Green
GD32F103CBT6
128
LQFP48
Green
GD32F103R4T6
16
LQFP64
Green
GD32F103R6T6
32
LQFP64
Green
GD32F103R8T6
64
LQFP64
Green
GD32F103RBT6
128
LQFP64
Green
GD32F103RCT6
256
LQFP64
Green
GD32F103RDT6
384
LQFP64
Green
GD32F103RET6
512
LQFP64
Green
GD32F103RFT6
768
LQFP64
Green
GD32F103RGT6
1024
LQFP64
Green
GD32F103RIT6
2048
LQFP64
Green
GD32F103RKT6
3072
LQFP64
Green
GD32F103V8T6
64
LQFP100
Green
GD32F103VBT6
128
LQFP100
Green
GD32F103VCT6
256
LQFP100
Green
GD32F103VDT6
384
LQFP100
Green
GD32F103VET6
512
LQFP100
Green
Temperature
operating range
Industrial
-40C to +85C
Industrial
-40C to +85C
Industrial
-40C to +85C
Industrial
-40C to +85C
Industrial
-40C to +85C
Industrial
-40C to +85C
Industrial
-40C to +85C
Industrial
-40C to +85C
Industrial
-40C to +85C
Industrial
-40C to +85C
Industrial
-40C to +85C
Industrial
-40C to +85C
Industrial
-40C to +85C
Industrial
-40C to +85C
Industrial
-40C to +85C
Industrial
-40C to +85C
Industrial
-40C to +85C
Industrial
-40C to +85C
Industrial
-40C to +85C
Industrial
-40C to +85C
Industrial
-40C to +85C
Industrial
-40C to +85C
Industrial
-40C to +85C
Industrial
-40C to +85C
45 / 48
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GD32F103xx
Ordering code
Flash (KB)
Package
Package type
GD32F103VFT6
768
LQFP100
Green
GD32F103VGT6
1024
LQFP100
Green
GD32F103VIT6
2048
LQFP100
Green
GD32F103VKT6
3072
LQFP100
Green
GD32F103ZCT6
256
LQFP144
Green
GD32F103ZDT6
384
LQFP144
Green
GD32F103ZET6
512
LQFP144
Green
GD32F103ZFT6
768
LQFP144
Green
GD32F103ZGT6
1024
LQFP144
Green
GD32F103ZIT6
2048
LQFP144
Green
GD32F103ZKT6
3072
LQFP144
Green
Temperature
operating range
Industrial
-40C to +85C
Industrial
-40C to +85C
Industrial
-40C to +85C
Industrial
-40C to +85C
Industrial
-40C to +85C
Industrial
-40C to +85C
Industrial
-40C to +85C
Industrial
-40C to +85C
Industrial
-40C to +85C
Industrial
-40C to +85C
Industrial
-40C to +85C
46 / 48
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GD32F103xx
Revision History
Description
Date
1.0
Initial Release
Mar.8, 2013
2.2
Oct.10, 2013
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