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A. Yazdian
H. Mokhtari
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DN S
Vi , 0 D 1
N1
(1)
VLoad = VS + Vi
(2)
DN S
Vi
VLoad = 1 +
N 1
(3)
DN S
Vi , 0 D 1
N1
(4)
(5)
VLoad = VS Vi
DN S
VLoad = 1
N1
Vi
(6)
(bb)
(cc)
(dd)
Fig. 6. Current path for
f an inductive load
(a)
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SIMULATION PARAM
METERS
Value
500 H
5 F
IRFP460
BYV08-900
2.67
Half Cycle RM
MS
18 KHz
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V. EXPERIMENTAL RESULTS
In Fig. 12 and Fig. 13, the steady state operation of the
system for compensating a low voltage is presented. The
parameters are presented in Table II.
Input
Green
50.068 Hz
161 V
0.2 %
1.5 %
0.036 %
1.23 %
2%
Output
Blue
50.068 Hz
220 V
0.5%
1.4 %
0.04 %
1.17 %
1.9%
Fig. 16. 20% Voltage drop during 150 mSec; Green: Input,
Blue: Output. V/div= 100V, Time/div= 10mSec
Fig. 17. CBEMA Curve, the operation point is denoted by a red square
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ACKNOWLEDGMENT
The authors thank to RMS Electronics for its support in
producing the prototype.
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